nkeynes@10: /** nkeynes@586: * $Id$ nkeynes@10: * nkeynes@945: * This file defines the internal functions used by the SH4 core, nkeynes@10: * nkeynes@945: * Copyright (c) 2005-2008 Nathan Keynes. nkeynes@10: * nkeynes@10: * This program is free software; you can redistribute it and/or modify nkeynes@10: * it under the terms of the GNU General Public License as published by nkeynes@10: * the Free Software Foundation; either version 2 of the License, or nkeynes@10: * (at your option) any later version. nkeynes@10: * nkeynes@10: * This program is distributed in the hope that it will be useful, nkeynes@10: * but WITHOUT ANY WARRANTY; without even the implied warranty of nkeynes@10: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the nkeynes@10: * GNU General Public License for more details. nkeynes@1: */ nkeynes@30: nkeynes@736: #ifndef lxdream_sh4core_H nkeynes@736: #define lxdream_sh4core_H 1 nkeynes@1: nkeynes@27: #include nkeynes@1: #include nkeynes@23: #include nkeynes@378: #include "mem.h" nkeynes@586: #include "sh4/sh4.h" nkeynes@1: nkeynes@1: #ifdef __cplusplus nkeynes@1: extern "C" { nkeynes@1: #endif nkeynes@1: nkeynes@586: /* Breakpoint data structure */ nkeynes@586: extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; nkeynes@586: extern int sh4_breakpoint_count; nkeynes@591: extern gboolean sh4_starting; nkeynes@27: nkeynes@27: /** nkeynes@586: * Cached direct pointer to the current instruction page. If AT is on, this nkeynes@586: * is derived from the ITLB, otherwise this will be the entire memory region. nkeynes@586: * This is actually a fairly useful optimization, as we can make a lot of nkeynes@586: * assumptions about the "current page" that we can't make in general for nkeynes@586: * arbitrary virtual addresses. nkeynes@27: */ nkeynes@586: struct sh4_icache_struct { nkeynes@586: sh4ptr_t page; // Page pointer (NULL if no page) nkeynes@586: sh4vma_t page_vma; // virtual address of the page. nkeynes@586: sh4addr_t page_ppa; // physical address of the page nkeynes@586: uint32_t mask; // page mask nkeynes@586: }; nkeynes@586: extern struct sh4_icache_struct sh4_icache; nkeynes@586: nkeynes@27: /** nkeynes@586: * Test if a given address is contained in the current icache entry nkeynes@27: */ nkeynes@586: #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask)) nkeynes@27: /** nkeynes@586: * Return a pointer for the given vma, under the assumption that it is nkeynes@586: * actually contained in the current icache entry. nkeynes@27: */ nkeynes@586: #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma)) nkeynes@27: /** nkeynes@586: * Return the physical (external) address for the given vma, assuming that it is nkeynes@586: * actually contained in the current icache entry. nkeynes@27: */ nkeynes@586: #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma)) nkeynes@27: nkeynes@589: /** nkeynes@589: * Return the virtual (vma) address for the first address past the end of the nkeynes@589: * cache entry. Assumes that there is in fact a current icache entry. nkeynes@589: */ nkeynes@589: #define GET_ICACHE_END() (sh4_icache.page_vma + (~sh4_icache.mask) + 1) nkeynes@589: nkeynes@740: nkeynes@740: /** nkeynes@948: * SH4 vm-exit flag - exit the current block but continue normally nkeynes@740: */ nkeynes@740: #define CORE_EXIT_CONTINUE 1 nkeynes@740: nkeynes@740: /** nkeynes@740: * SH4 vm-exit flag - exit the current block and halt immediately (eg fatal error) nkeynes@740: */ nkeynes@740: #define CORE_EXIT_HALT 2 nkeynes@740: nkeynes@740: /** nkeynes@740: * SH4 vm-exit flag - exit the current block and halt immediately for a system nkeynes@740: * breakpoint. nkeynes@740: */ nkeynes@740: #define CORE_EXIT_BREAKPOINT 3 nkeynes@740: nkeynes@740: /** nkeynes@740: * SH4 vm-exit flag - exit the current block and continue after performing a full nkeynes@740: * system reset (dreamcast_reset()) nkeynes@740: */ nkeynes@740: #define CORE_EXIT_SYSRESET 4 nkeynes@740: nkeynes@740: /** nkeynes@740: * SH4 vm-exit flag - exit the current block and continue after the next IRQ. nkeynes@740: */ nkeynes@740: #define CORE_EXIT_SLEEP 5 nkeynes@740: nkeynes@740: /** nkeynes@939: * SH4 vm-exit flag - exit the current block and flush all instruction caches (ie nkeynes@740: * if address translation has changed) nkeynes@740: */ nkeynes@740: #define CORE_EXIT_FLUSH_ICACHE 6 nkeynes@740: nkeynes@939: /** nkeynes@939: * SH4 vm-exit flag - exit the current block following a taken exception. sh4r.spc nkeynes@939: * is fixed up by recovery rather than sh4r.pc. nkeynes@939: */ nkeynes@939: #define CORE_EXIT_EXCEPTION 7 nkeynes@939: nkeynes@740: typedef uint32_t (*sh4_run_slice_fn)(uint32_t); nkeynes@740: nkeynes@586: /* SH4 module functions */ nkeynes@1: void sh4_init( void ); nkeynes@1: void sh4_reset( void ); nkeynes@1: void sh4_run( void ); nkeynes@1: void sh4_stop( void ); nkeynes@617: uint32_t sh4_run_slice( uint32_t nanos ); // Run single timeslice using emulator nkeynes@617: uint32_t sh4_xlat_run_slice( uint32_t nanos ); // Run single timeslice using translator nkeynes@617: uint32_t sh4_sleep_run_slice( uint32_t nanos ); // Run single timeslice while the CPU is asleep nkeynes@586: nkeynes@740: /** nkeynes@740: * Immediately exit from the currently executing instruction with the given nkeynes@740: * exit code. This method does not return. nkeynes@740: */ nkeynes@740: void sh4_core_exit( int exit_code ); nkeynes@740: nkeynes@740: /** nkeynes@740: * Exit the current block at the end of the current instruction, flush the nkeynes@740: * translation cache (completely) and return control to sh4_xlat_run_slice. nkeynes@740: * nkeynes@740: * As a special case, if the current instruction is actually the last nkeynes@740: * instruction in the block (ie it's in a delay slot), this function nkeynes@740: * returns to allow normal completion of the translation block. Otherwise nkeynes@740: * this function never returns. nkeynes@740: * nkeynes@740: * Must only be invoked (indirectly) from within translated code. nkeynes@740: */ nkeynes@740: void sh4_flush_icache(); nkeynes@740: nkeynes@586: /* SH4 peripheral module functions */ nkeynes@586: void CPG_reset( void ); nkeynes@586: void DMAC_reset( void ); nkeynes@586: void DMAC_run_slice( uint32_t ); nkeynes@586: void DMAC_save_state( FILE * ); nkeynes@586: int DMAC_load_state( FILE * ); nkeynes@586: void INTC_reset( void ); nkeynes@586: void INTC_save_state( FILE *f ); nkeynes@586: int INTC_load_state( FILE *f ); nkeynes@564: void MMU_init( void ); nkeynes@586: void MMU_reset( void ); nkeynes@586: void MMU_save_state( FILE *f ); nkeynes@586: int MMU_load_state( FILE *f ); nkeynes@586: void MMU_ldtlb(); nkeynes@986: void CCN_reset(); nkeynes@968: void CCN_set_cache_control( int reg ); nkeynes@931: void CCN_save_state( FILE *f ); nkeynes@931: int CCN_load_state( FILE *f ); nkeynes@586: void SCIF_reset( void ); nkeynes@586: void SCIF_run_slice( uint32_t ); nkeynes@586: void SCIF_save_state( FILE *f ); nkeynes@586: int SCIF_load_state( FILE *f ); nkeynes@586: void SCIF_update_line_speed(void); nkeynes@669: void TMU_init( void ); nkeynes@586: void TMU_reset( void ); nkeynes@586: void TMU_run_slice( uint32_t ); nkeynes@586: void TMU_save_state( FILE * ); nkeynes@586: int TMU_load_state( FILE * ); nkeynes@586: void TMU_update_clocks( void ); nkeynes@841: void PMM_reset( void ); nkeynes@841: void PMM_write_control( int, uint32_t ); nkeynes@841: void PMM_save_state( FILE * ); nkeynes@841: int PMM_load_state( FILE * ); nkeynes@841: uint32_t PMM_run_slice( uint32_t ); nkeynes@759: uint32_t sh4_translate_run_slice(uint32_t); nkeynes@759: uint32_t sh4_emulate_run_slice(uint32_t); nkeynes@586: nkeynes@586: /* SH4 instruction support methods */ nkeynes@929: mem_region_fn_t FASTCALL sh7750_decode_address( sh4addr_t address ); nkeynes@929: void FASTCALL sh7750_decode_address_copy( sh4addr_t address, mem_region_fn_t result ); nkeynes@905: void FASTCALL sh4_sleep( void ); nkeynes@905: void FASTCALL sh4_fsca( uint32_t angle, float *fr ); nkeynes@905: void FASTCALL sh4_ftrv( float *fv ); nkeynes@905: uint32_t FASTCALL sh4_read_sr(void); nkeynes@905: void FASTCALL sh4_write_sr(uint32_t val); nkeynes@905: void FASTCALL sh4_write_fpscr(uint32_t val); nkeynes@905: void FASTCALL sh4_switch_fr_banks(void); nkeynes@905: void FASTCALL signsat48(void); nkeynes@597: gboolean sh4_has_page( sh4vma_t vma ); nkeynes@378: nkeynes@586: /* SH4 Memory */ nkeynes@603: #define MMU_VMA_ERROR 0x80000000 nkeynes@586: /** nkeynes@586: * Update the sh4_icache structure to contain the specified vma. If the vma nkeynes@586: * cannot be resolved, an MMU exception is raised and the function returns nkeynes@586: * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly. nkeynes@586: * Note: If the vma resolves to a non-memory area, sh4_icache will be nkeynes@586: * invalidated, but the function will still return TRUE. nkeynes@586: * @return FALSE if an MMU exception was raised, otherwise TRUE. nkeynes@586: */ nkeynes@905: gboolean FASTCALL mmu_update_icache( sh4vma_t addr ); nkeynes@23: nkeynes@905: int64_t FASTCALL sh4_read_quad( sh4addr_t addr ); nkeynes@905: int32_t FASTCALL sh4_read_long( sh4addr_t addr ); nkeynes@905: int32_t FASTCALL sh4_read_word( sh4addr_t addr ); nkeynes@905: int32_t FASTCALL sh4_read_byte( sh4addr_t addr ); nkeynes@905: void FASTCALL sh4_write_quad( sh4addr_t addr, uint64_t val ); nkeynes@905: void FASTCALL sh4_write_long( sh4addr_t addr, uint32_t val ); nkeynes@905: void FASTCALL sh4_write_word( sh4addr_t addr, uint32_t val ); nkeynes@905: void FASTCALL sh4_write_byte( sh4addr_t addr, uint32_t val ); nkeynes@527: int32_t sh4_read_phys_word( sh4addr_t addr ); nkeynes@911: void FASTCALL sh4_flush_store_queue( sh4addr_t addr ); nkeynes@939: void FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr, void *exc ); nkeynes@10: nkeynes@586: /* SH4 Exceptions */ nkeynes@586: #define EXC_POWER_RESET 0x000 /* reset vector */ nkeynes@586: #define EXC_MANUAL_RESET 0x020 /* reset vector */ nkeynes@586: #define EXC_TLB_MISS_READ 0x040 /* TLB vector */ nkeynes@586: #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */ nkeynes@586: #define EXC_INIT_PAGE_WRITE 0x080 nkeynes@586: #define EXC_TLB_PROT_READ 0x0A0 nkeynes@586: #define EXC_TLB_PROT_WRITE 0x0C0 nkeynes@586: #define EXC_DATA_ADDR_READ 0x0E0 nkeynes@586: #define EXC_DATA_ADDR_WRITE 0x100 nkeynes@586: #define EXC_TLB_MULTI_HIT 0x140 nkeynes@586: #define EXC_SLOT_ILLEGAL 0x1A0 nkeynes@586: #define EXC_ILLEGAL 0x180 nkeynes@586: #define EXC_TRAP 0x160 nkeynes@586: #define EXC_FPU_DISABLED 0x800 nkeynes@586: #define EXC_SLOT_FPU_DISABLED 0x820 nkeynes@374: nkeynes@586: #define EXV_EXCEPTION 0x100 /* General exception vector */ nkeynes@586: #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */ nkeynes@586: #define EXV_INTERRUPT 0x600 /* External interrupt vector */ nkeynes@586: nkeynes@951: void FASTCALL sh4_raise_exception( int ); nkeynes@951: void FASTCALL sh4_raise_reset( int ); nkeynes@951: void FASTCALL sh4_raise_trap( int ); nkeynes@951: void FASTCALL sh4_raise_tlb_exception( int, sh4vma_t ); nkeynes@951: void FASTCALL sh4_raise_tlb_multihit( sh4vma_t ); nkeynes@905: void FASTCALL sh4_accept_interrupt( void ); nkeynes@1: nkeynes@948: /** nkeynes@948: * Complete the current instruction as part of a core exit. Prevents the nkeynes@948: * system from being left in an inconsistent state when an exit is nkeynes@948: * triggered during a memory write. nkeynes@948: */ nkeynes@948: void sh4_finalize_instruction( void ); nkeynes@948: nkeynes@1: /* Status Register (SR) bits */ nkeynes@1: #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ nkeynes@1: #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */ nkeynes@1: #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */ nkeynes@1: #define SR_FD 0x00008000 /* FPU disable */ nkeynes@1: #define SR_M 0x00000200 nkeynes@1: #define SR_Q 0x00000100 nkeynes@1: #define SR_IMASK 0x000000F0 /* Interrupt mask level */ nkeynes@1: #define SR_S 0x00000002 /* Saturation operation for MAC instructions */ nkeynes@1: #define SR_T 0x00000001 /* True/false or carry/borrow */ nkeynes@1: #define SR_MASK 0x700083F3 nkeynes@1: #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */ nkeynes@586: #define SR_MDRB 0x60000000 /* MD+RB mask for convenience */ nkeynes@1: nkeynes@1: #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD) nkeynes@1: #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4) nkeynes@265: #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot) nkeynes@1: nkeynes@1: #define FPSCR_FR 0x00200000 /* FPU register bank */ nkeynes@1: #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */ nkeynes@1: #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */ nkeynes@1: #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */ nkeynes@1: #define FPSCR_CAUSE 0x0003F000 nkeynes@1: #define FPSCR_ENABLE 0x00000F80 nkeynes@1: #define FPSCR_FLAG 0x0000007C nkeynes@1: #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */ nkeynes@823: #define FPSCR_MASK 0x003FFFFF nkeynes@1: nkeynes@1: #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR) nkeynes@1: #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ) nkeynes@1: #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0) nkeynes@1: nkeynes@669: #define FR(x) sh4r.fr[0][(x)^1] nkeynes@669: #define DRF(x) *((double *)&sh4r.fr[0][(x)<<1]) nkeynes@669: #define XF(x) sh4r.fr[1][(x)^1] nkeynes@669: #define XDR(x) *((double *)&sh4r.fr[1][(x)<<1]) nkeynes@669: #define DRb(x,b) *((double *)&sh4r.fr[b][(x)<<1]) nkeynes@669: #define DR(x) *((double *)&sh4r.fr[x&1][x&0x0E]) nkeynes@669: #define FPULf (sh4r.fpul.f) nkeynes@669: #define FPULi (sh4r.fpul.i) nkeynes@359: nkeynes@939: /**************** SH4 internal memory regions *****************/ nkeynes@939: extern struct mem_region_fn p4_region_itlb_addr; nkeynes@939: extern struct mem_region_fn p4_region_itlb_data; nkeynes@939: extern struct mem_region_fn p4_region_utlb_addr; nkeynes@939: extern struct mem_region_fn p4_region_utlb_data; nkeynes@939: extern struct mem_region_fn p4_region_icache_addr; nkeynes@939: extern struct mem_region_fn p4_region_icache_data; nkeynes@939: extern struct mem_region_fn p4_region_ocache_addr; nkeynes@939: extern struct mem_region_fn p4_region_ocache_data; nkeynes@946: nkeynes@971: #define OC_ENABLED 1 nkeynes@1: nkeynes@1: #ifdef __cplusplus nkeynes@1: } nkeynes@1: #endif nkeynes@359: nkeynes@736: #endif /* !lxdream_sh4core_H */ nkeynes@736: