nkeynes@23: /**
nkeynes@561:  * $Id$
nkeynes@23:  * 
nkeynes@23:  * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
nkeynes@23:  * keep things simple (they intertwine a bit).
nkeynes@23:  *
nkeynes@23:  * Copyright (c) 2005 Nathan Keynes.
nkeynes@23:  *
nkeynes@23:  * This program is free software; you can redistribute it and/or modify
nkeynes@23:  * it under the terms of the GNU General Public License as published by
nkeynes@23:  * the Free Software Foundation; either version 2 of the License, or
nkeynes@23:  * (at your option) any later version.
nkeynes@23:  *
nkeynes@23:  * This program is distributed in the hope that it will be useful,
nkeynes@23:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@23:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@23:  * GNU General Public License for more details.
nkeynes@23:  */
nkeynes@23: 
nkeynes@619: #include <assert.h>
nkeynes@619: #include "lxdream.h"
nkeynes@23: #include "mem.h"
nkeynes@23: #include "clock.h"
nkeynes@619: #include "eventq.h"
nkeynes@619: #include "sh4/sh4core.h"
nkeynes@619: #include "sh4/sh4mmio.h"
nkeynes@619: #include "sh4/intc.h"
nkeynes@23: 
nkeynes@23: /********************************* CPG *************************************/
nkeynes@859: /* This is the base clock from which all other clocks are derived. 
nkeynes@859:  * Note: The real clock runs at 33Mhz, which is multiplied by the PLL to
nkeynes@859:  * run the instruction clock at 200Mhz. For sake of simplicity/precision,
nkeynes@859:  * we instead use 200Mhz as the base rate and divide everything down instead.
nkeynes@859:  **/
nkeynes@53: uint32_t sh4_input_freq = SH4_BASE_RATE;
nkeynes@53: 
nkeynes@414: uint32_t sh4_cpu_multiplier = 2000; /* = 0.5 * frequency */
nkeynes@414: 
nkeynes@53: uint32_t sh4_cpu_freq = SH4_BASE_RATE;
nkeynes@859: uint32_t sh4_bus_freq = SH4_BASE_RATE / 2;
nkeynes@859: uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 4;
nkeynes@53: 
nkeynes@53: uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */
nkeynes@859: uint32_t sh4_bus_period = 2* 1000 / SH4_BASE_RATE;
nkeynes@859: uint32_t sh4_peripheral_period = 4 * 2000 / SH4_BASE_RATE;
nkeynes@23: 
nkeynes@23: int32_t mmio_region_CPG_read( uint32_t reg )
nkeynes@23: {
nkeynes@23:     return MMIO_READ( CPG, reg );
nkeynes@23: }
nkeynes@23: 
nkeynes@53: /* CPU + bus dividers (note officially only the first 6 values are valid) */
nkeynes@53: int ifc_divider[8] = { 1, 2, 3, 4, 5, 8, 8, 8 };
nkeynes@53: /* Peripheral clock dividers (only first 5 are officially valid) */
nkeynes@53: int pfc_divider[8] = { 2, 3, 4, 6, 8, 8, 8, 8 };
nkeynes@53: 
nkeynes@23: void mmio_region_CPG_write( uint32_t reg, uint32_t val )
nkeynes@23: {
nkeynes@53:     uint32_t div;
nkeynes@859:     uint32_t primary_clock = sh4_input_freq;
nkeynes@859:     
nkeynes@53:     switch( reg ) {
nkeynes@53:     case FRQCR: /* Frequency control */
nkeynes@859:         if( (val & FRQCR_PLL1EN) == 0 )
nkeynes@859:             primary_clock /= 6;
nkeynes@736:         div = ifc_divider[(val >> 6) & 0x07];
nkeynes@859:         sh4_cpu_freq = primary_clock / div;
nkeynes@736:         sh4_cpu_period = sh4_cpu_multiplier * div / sh4_input_freq;
nkeynes@736:         div = ifc_divider[(val >> 3) & 0x07];
nkeynes@859:         sh4_bus_freq = primary_clock / div;
nkeynes@736:         sh4_bus_period = 1000 * div / sh4_input_freq;
nkeynes@736:         div = pfc_divider[val & 0x07];
nkeynes@859:         sh4_peripheral_freq = primary_clock / div;
nkeynes@736:         sh4_peripheral_period = 1000 * div / sh4_input_freq;
nkeynes@53: 
nkeynes@736:         /* Update everything that depends on the peripheral frequency */
nkeynes@736:         SCIF_update_line_speed();
nkeynes@736:         break;
nkeynes@53:     case WTCSR: /* Watchdog timer */
nkeynes@736:         break;
nkeynes@53:     }
nkeynes@736: 
nkeynes@23:     MMIO_WRITE( CPG, reg, val );
nkeynes@23: }
nkeynes@23: 
nkeynes@260: /**
nkeynes@260:  * We don't really know what the default reset value is as it's determined
nkeynes@260:  * by the mode select pins. This is the standard value that the BIOS sets,
nkeynes@260:  * however, so it works for now.
nkeynes@260:  */
nkeynes@260: void CPG_reset( )
nkeynes@260: {
nkeynes@260:     mmio_region_CPG_write( FRQCR, 0x0E0A );
nkeynes@260: }
nkeynes@260: 
nkeynes@260: 
nkeynes@23: /********************************** RTC *************************************/
nkeynes@23: 
nkeynes@53: uint32_t rtc_output_period;
nkeynes@53: 
nkeynes@23: int32_t mmio_region_RTC_read( uint32_t reg )
nkeynes@23: {
nkeynes@23:     return MMIO_READ( RTC, reg );
nkeynes@23: }
nkeynes@23: 
nkeynes@23: void mmio_region_RTC_write( uint32_t reg, uint32_t val )
nkeynes@23: {
nkeynes@23:     MMIO_WRITE( RTC, reg, val );
nkeynes@23: }
nkeynes@23: 
nkeynes@23: /********************************** TMU *************************************/
nkeynes@23: 
nkeynes@619: #define TMU_IS_RUNNING(timer)  (MMIO_READ(TMU,TSTR) & (1<<timer))
nkeynes@619: 
nkeynes@260: uint32_t TMU_count( int timer, uint32_t nanosecs );
nkeynes@260: 
nkeynes@619: void TMU_event_callback( int eventid )
nkeynes@619: {
nkeynes@619:     TMU_count( eventid - EVENT_TMU0, sh4r.slice_cycle );
nkeynes@619: }
nkeynes@619: 
nkeynes@619: void TMU_init(void)
nkeynes@619: {
nkeynes@619:     register_event_callback( EVENT_TMU0, TMU_event_callback );
nkeynes@619:     register_event_callback( EVENT_TMU1, TMU_event_callback );
nkeynes@619:     register_event_callback( EVENT_TMU2, TMU_event_callback );
nkeynes@619: }    
nkeynes@260: 
nkeynes@53: #define TCR_ICPF 0x0200
nkeynes@53: #define TCR_UNF  0x0100
nkeynes@53: #define TCR_UNIE 0x0020
nkeynes@53: 
nkeynes@115: #define TCR_IRQ_ACTIVE (TCR_UNF|TCR_UNIE)
nkeynes@115: 
nkeynes@53: struct TMU_timer {
nkeynes@53:     uint32_t timer_period;
nkeynes@53:     uint32_t timer_remainder; /* left-over cycles from last count */
nkeynes@53:     uint32_t timer_run; /* cycles already run from this slice */
nkeynes@53: };
nkeynes@53: 
nkeynes@619: static struct TMU_timer TMU_timers[3];
nkeynes@23: 
nkeynes@23: int32_t mmio_region_TMU_read( uint32_t reg )
nkeynes@23: {
nkeynes@260:     switch( reg ) {
nkeynes@260:     case TCNT0:
nkeynes@736:         TMU_count( 0, sh4r.slice_cycle );
nkeynes@736:         break;
nkeynes@260:     case TCNT1:
nkeynes@736:         TMU_count( 1, sh4r.slice_cycle );
nkeynes@736:         break;
nkeynes@260:     case TCNT2:
nkeynes@736:         TMU_count( 2, sh4r.slice_cycle );
nkeynes@736:         break;
nkeynes@260:     }
nkeynes@23:     return MMIO_READ( TMU, reg );
nkeynes@23: }
nkeynes@23: 
nkeynes@115: void TMU_set_timer_control( int timer,  int tcr )
nkeynes@53: {
nkeynes@53:     uint32_t period = 1;
nkeynes@115:     uint32_t oldtcr = MMIO_READ( TMU, TCR0 + (12*timer) );
nkeynes@115: 
nkeynes@115:     if( (oldtcr & TCR_UNF) == 0 ) {
nkeynes@736:         tcr = tcr & (~TCR_UNF);
nkeynes@115:     } else {
nkeynes@736:         if( ((oldtcr & TCR_UNIE) == 0) && 
nkeynes@736:                 (tcr & TCR_IRQ_ACTIVE) == TCR_IRQ_ACTIVE ) {
nkeynes@736:             intc_raise_interrupt( INT_TMU_TUNI0 + timer );
nkeynes@736:         } else if( (oldtcr & TCR_UNIE) != 0 && 
nkeynes@736:                 (tcr & TCR_IRQ_ACTIVE) != TCR_IRQ_ACTIVE ) {
nkeynes@736:             intc_clear_interrupt( INT_TMU_TUNI0 + timer );
nkeynes@736:         }
nkeynes@115:     }
nkeynes@115: 
nkeynes@53:     switch( tcr & 0x07 ) {
nkeynes@53:     case 0:
nkeynes@736:         period = sh4_peripheral_period << 2 ;
nkeynes@736:         break;
nkeynes@53:     case 1: 
nkeynes@736:         period = sh4_peripheral_period << 4;
nkeynes@736:         break;
nkeynes@53:     case 2:
nkeynes@736:         period = sh4_peripheral_period << 6;
nkeynes@736:         break;
nkeynes@53:     case 3: 
nkeynes@736:         period = sh4_peripheral_period << 8;
nkeynes@736:         break;
nkeynes@53:     case 4:
nkeynes@736:         period = sh4_peripheral_period << 10;
nkeynes@736:         break;
nkeynes@53:     case 5:
nkeynes@736:         /* Illegal value. */
nkeynes@736:         ERROR( "TMU %d period set to illegal value (5)", timer );
nkeynes@736:         period = sh4_peripheral_period << 12; /* for something to do */
nkeynes@736:         break;
nkeynes@53:     case 6:
nkeynes@736:         period = rtc_output_period;
nkeynes@736:         break;
nkeynes@53:     case 7:
nkeynes@736:         /* External clock... Hrm? */
nkeynes@736:         period = sh4_peripheral_period; /* I dunno... */
nkeynes@736:         break;
nkeynes@53:     }
nkeynes@53:     TMU_timers[timer].timer_period = period;
nkeynes@115: 
nkeynes@115:     MMIO_WRITE( TMU, TCR0 + (12*timer), tcr );
nkeynes@53: }
nkeynes@23: 
nkeynes@619: void TMU_schedule_timer( int timer )
nkeynes@619: {
nkeynes@619:     uint64_t duration = (uint64_t)((uint32_t)(MMIO_READ( TMU, TCNT0 + 12*timer )+1)) * 
nkeynes@736:     (uint64_t)TMU_timers[timer].timer_period - TMU_timers[timer].timer_remainder;
nkeynes@619:     event_schedule_long( EVENT_TMU0+timer, (uint32_t)(duration / 1000000000), 
nkeynes@736:                          (uint32_t)(duration % 1000000000) );
nkeynes@619: }
nkeynes@619: 
nkeynes@53: void TMU_start( int timer )
nkeynes@23: {
nkeynes@260:     TMU_timers[timer].timer_run = sh4r.slice_cycle;
nkeynes@53:     TMU_timers[timer].timer_remainder = 0;
nkeynes@619:     TMU_schedule_timer( timer );
nkeynes@53: }
nkeynes@53: 
nkeynes@264: /**
nkeynes@264:  * Stop the given timer. Run it up to the current time and leave it there.
nkeynes@264:  */
nkeynes@53: void TMU_stop( int timer )
nkeynes@53: {
nkeynes@264:     TMU_count( timer, sh4r.slice_cycle );
nkeynes@619:     event_cancel( EVENT_TMU0+timer );
nkeynes@53: }
nkeynes@53: 
nkeynes@53: /**
nkeynes@53:  * Count the specified timer for a given number of nanoseconds.
nkeynes@53:  */
nkeynes@53: uint32_t TMU_count( int timer, uint32_t nanosecs ) 
nkeynes@53: {
nkeynes@619:     uint32_t run_ns = nanosecs + TMU_timers[timer].timer_remainder -
nkeynes@736:     TMU_timers[timer].timer_run;
nkeynes@53:     TMU_timers[timer].timer_remainder = 
nkeynes@736:         run_ns % TMU_timers[timer].timer_period;
nkeynes@619:     TMU_timers[timer].timer_run = nanosecs;
nkeynes@619:     uint32_t count = run_ns / TMU_timers[timer].timer_period;
nkeynes@53:     uint32_t value = MMIO_READ( TMU, TCNT0 + 12*timer );
nkeynes@53:     uint32_t reset = MMIO_READ( TMU, TCOR0 + 12*timer );
nkeynes@53:     if( count > value ) {
nkeynes@736:         uint32_t tcr = MMIO_READ( TMU, TCR0 + 12*timer );
nkeynes@736:         tcr |= TCR_UNF;
nkeynes@736:         count -= value;
nkeynes@619:         value = reset - (count % reset) + 1;
nkeynes@736:         MMIO_WRITE( TMU, TCR0 + 12*timer, tcr );
nkeynes@736:         if( tcr & TCR_UNIE ) 
nkeynes@736:             intc_raise_interrupt( INT_TMU_TUNI0 + timer );
nkeynes@736:         MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
nkeynes@736:         TMU_schedule_timer(timer);
nkeynes@53:     } else {
nkeynes@736:         value -= count;
nkeynes@736:         MMIO_WRITE( TMU, TCNT0 + 12*timer, value );
nkeynes@23:     }
nkeynes@53:     return value;
nkeynes@23: }
nkeynes@23: 
nkeynes@23: void mmio_region_TMU_write( uint32_t reg, uint32_t val )
nkeynes@23: {
nkeynes@53:     uint32_t oldval;
nkeynes@53:     int i;
nkeynes@23:     switch( reg ) {
nkeynes@53:     case TSTR:
nkeynes@736:         oldval = MMIO_READ( TMU, TSTR );
nkeynes@736:         for( i=0; i<3; i++ ) {
nkeynes@736:             uint32_t tmp = 1<<i;
nkeynes@736:             if( (oldval & tmp) != 0 && (val&tmp) == 0  )
nkeynes@736:                 TMU_stop(i);
nkeynes@736:             else if( (oldval&tmp) == 0 && (val&tmp) != 0 )
nkeynes@736:                 TMU_start(i);
nkeynes@736:         }
nkeynes@736:         break;
nkeynes@53:     case TCR0:
nkeynes@736:         TMU_set_timer_control( 0, val );
nkeynes@736:         return;
nkeynes@53:     case TCR1:
nkeynes@736:         TMU_set_timer_control( 1, val );
nkeynes@736:         return;
nkeynes@53:     case TCR2:
nkeynes@736:         TMU_set_timer_control( 2, val );
nkeynes@736:         return;
nkeynes@619:     case TCNT0:
nkeynes@736:         MMIO_WRITE( TMU, reg, val );
nkeynes@736:         if( TMU_IS_RUNNING(0) ) { // reschedule
nkeynes@736:             TMU_timers[0].timer_run = sh4r.slice_cycle;
nkeynes@736:             TMU_schedule_timer( 0 );
nkeynes@736:         }
nkeynes@736:         return;
nkeynes@619:     case TCNT1:
nkeynes@736:         MMIO_WRITE( TMU, reg, val );
nkeynes@736:         if( TMU_IS_RUNNING(1) ) { // reschedule
nkeynes@736:             TMU_timers[1].timer_run = sh4r.slice_cycle;
nkeynes@736:             TMU_schedule_timer( 1 );
nkeynes@736:         }
nkeynes@736:         return;
nkeynes@619:     case TCNT2:
nkeynes@736:         MMIO_WRITE( TMU, reg, val );
nkeynes@736:         if( TMU_IS_RUNNING(2) ) { // reschedule
nkeynes@736:             TMU_timers[2].timer_run = sh4r.slice_cycle;
nkeynes@736:             TMU_schedule_timer( 2 );
nkeynes@736:         }
nkeynes@736:         return;
nkeynes@23:     }
nkeynes@23:     MMIO_WRITE( TMU, reg, val );
nkeynes@23: }
nkeynes@23: 
nkeynes@619: void TMU_count_all( uint32_t nanosecs )
nkeynes@23: {
nkeynes@23:     int tcr = MMIO_READ( TMU, TSTR );
nkeynes@23:     if( tcr & 0x01 ) {
nkeynes@736:         TMU_count( 0, nanosecs );
nkeynes@23:     }
nkeynes@23:     if( tcr & 0x02 ) {
nkeynes@736:         TMU_count( 1, nanosecs );
nkeynes@23:     }
nkeynes@23:     if( tcr & 0x04 ) {
nkeynes@736:         TMU_count( 2, nanosecs );
nkeynes@23:     }
nkeynes@23: }
nkeynes@53: 
nkeynes@619: void TMU_run_slice( uint32_t nanosecs )
nkeynes@619: {
nkeynes@619:     TMU_count_all( nanosecs );
nkeynes@619:     TMU_timers[0].timer_run = 0;
nkeynes@619:     TMU_timers[1].timer_run = 0;
nkeynes@619:     TMU_timers[2].timer_run = 0;
nkeynes@619: }
nkeynes@619: 
nkeynes@53: void TMU_update_clocks()
nkeynes@53: {
nkeynes@115:     TMU_set_timer_control( 0, MMIO_READ( TMU, TCR0 ) );
nkeynes@115:     TMU_set_timer_control( 1, MMIO_READ( TMU, TCR1 ) );
nkeynes@115:     TMU_set_timer_control( 2, MMIO_READ( TMU, TCR2 ) );
nkeynes@53: }
nkeynes@53: 
nkeynes@53: void TMU_reset( )
nkeynes@53: {
nkeynes@53:     TMU_timers[0].timer_remainder = 0;
nkeynes@53:     TMU_timers[0].timer_run = 0;
nkeynes@53:     TMU_timers[1].timer_remainder = 0;
nkeynes@53:     TMU_timers[1].timer_run = 0;
nkeynes@53:     TMU_timers[2].timer_remainder = 0;
nkeynes@53:     TMU_timers[2].timer_run = 0;
nkeynes@53:     TMU_update_clocks();
nkeynes@53: }
nkeynes@53: 
nkeynes@53: void TMU_save_state( FILE *f ) {
nkeynes@53:     fwrite( &TMU_timers, sizeof(TMU_timers), 1, f );
nkeynes@53: }
nkeynes@53: 
nkeynes@53: int TMU_load_state( FILE *f ) 
nkeynes@53: {
nkeynes@53:     fread( &TMU_timers, sizeof(TMU_timers), 1, f );
nkeynes@53:     return 0;
nkeynes@53: }