nkeynes@359: /**
nkeynes@561:  * $Id$
nkeynes@359:  * 
nkeynes@359:  * SH4 => x86 translation. This version does no real optimization, it just
nkeynes@359:  * outputs straight-line x86 code - it mainly exists to provide a baseline
nkeynes@359:  * to test the optimizing versions against.
nkeynes@359:  *
nkeynes@359:  * Copyright (c) 2007 Nathan Keynes.
nkeynes@359:  *
nkeynes@359:  * This program is free software; you can redistribute it and/or modify
nkeynes@359:  * it under the terms of the GNU General Public License as published by
nkeynes@359:  * the Free Software Foundation; either version 2 of the License, or
nkeynes@359:  * (at your option) any later version.
nkeynes@359:  *
nkeynes@359:  * This program is distributed in the hope that it will be useful,
nkeynes@359:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@359:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@359:  * GNU General Public License for more details.
nkeynes@359:  */
nkeynes@359: 
nkeynes@368: #include <assert.h>
nkeynes@388: #include <math.h>
nkeynes@368: 
nkeynes@380: #ifndef NDEBUG
nkeynes@380: #define DEBUG_JUMPS 1
nkeynes@380: #endif
nkeynes@380: 
nkeynes@905: #include "lxdream.h"
nkeynes@368: #include "sh4/sh4core.h"
nkeynes@368: #include "sh4/sh4trans.h"
nkeynes@671: #include "sh4/sh4stat.h"
nkeynes@388: #include "sh4/sh4mmio.h"
nkeynes@953: #include "sh4/mmu.h"
nkeynes@991: #include "xlat/xltcache.h"
nkeynes@991: #include "xlat/x86/x86op.h"
nkeynes@368: #include "clock.h"
nkeynes@368: 
nkeynes@368: #define DEFAULT_BACKPATCH_SIZE 4096
nkeynes@368: 
nkeynes@991: /* Offset of a reg relative to the sh4r structure */
nkeynes@991: #define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
nkeynes@991: 
nkeynes@995: #define R_T      REG_OFFSET(t)
nkeynes@995: #define R_Q      REG_OFFSET(q)
nkeynes@995: #define R_S      REG_OFFSET(s)
nkeynes@995: #define R_M      REG_OFFSET(m)
nkeynes@995: #define R_SR     REG_OFFSET(sr)
nkeynes@995: #define R_GBR    REG_OFFSET(gbr)
nkeynes@995: #define R_SSR    REG_OFFSET(ssr)
nkeynes@995: #define R_SPC    REG_OFFSET(spc)
nkeynes@995: #define R_VBR    REG_OFFSET(vbr)
nkeynes@995: #define R_MACH   REG_OFFSET(mac)+4
nkeynes@995: #define R_MACL   REG_OFFSET(mac)
nkeynes@995: #define R_PC     REG_OFFSET(pc)
nkeynes@991: #define R_NEW_PC REG_OFFSET(new_pc)
nkeynes@995: #define R_PR     REG_OFFSET(pr)
nkeynes@995: #define R_SGR    REG_OFFSET(sgr)
nkeynes@995: #define R_FPUL   REG_OFFSET(fpul)
nkeynes@995: #define R_FPSCR  REG_OFFSET(fpscr)
nkeynes@995: #define R_DBR    REG_OFFSET(dbr)
nkeynes@995: #define R_R(rn)  REG_OFFSET(r[rn])
nkeynes@995: #define R_FR(f)  REG_OFFSET(fr[0][(f)^1])
nkeynes@995: #define R_XF(f)  REG_OFFSET(fr[1][(f)^1])
nkeynes@995: #define R_DR(f)  REG_OFFSET(fr[(f)&1][(f)&0x0E])
nkeynes@995: #define R_DRL(f) REG_OFFSET(fr[(f)&1][(f)|0x01])
nkeynes@995: #define R_DRH(f) REG_OFFSET(fr[(f)&1][(f)&0x0E])
nkeynes@995: 
nkeynes@995: #define DELAY_NONE 0
nkeynes@995: #define DELAY_PC 1
nkeynes@995: #define DELAY_PC_PR 2
nkeynes@991: 
nkeynes@559: struct backpatch_record {
nkeynes@604:     uint32_t fixup_offset;
nkeynes@559:     uint32_t fixup_icount;
nkeynes@596:     int32_t exc_code;
nkeynes@559: };
nkeynes@559: 
nkeynes@368: /** 
nkeynes@368:  * Struct to manage internal translation state. This state is not saved -
nkeynes@368:  * it is only valid between calls to sh4_translate_begin_block() and
nkeynes@368:  * sh4_translate_end_block()
nkeynes@368:  */
nkeynes@368: struct sh4_x86_state {
nkeynes@590:     int in_delay_slot;
nkeynes@368:     gboolean fpuen_checked; /* true if we've already checked fpu enabled. */
nkeynes@409:     gboolean branch_taken; /* true if we branched unconditionally */
nkeynes@901:     gboolean double_prec; /* true if FPU is in double-precision mode */
nkeynes@903:     gboolean double_size; /* true if FPU is in double-size mode */
nkeynes@903:     gboolean sse3_enabled; /* true if host supports SSE3 instructions */
nkeynes@408:     uint32_t block_start_pc;
nkeynes@547:     uint32_t stack_posn;   /* Trace stack height for alignment purposes */
nkeynes@417:     int tstate;
nkeynes@368: 
nkeynes@570:     /* mode flags */
nkeynes@570:     gboolean tlb_on; /* True if tlb translation is active */
nkeynes@570: 
nkeynes@368:     /* Allocated memory for the (block-wide) back-patch list */
nkeynes@559:     struct backpatch_record *backpatch_list;
nkeynes@368:     uint32_t backpatch_posn;
nkeynes@368:     uint32_t backpatch_size;
nkeynes@368: };
nkeynes@368: 
nkeynes@368: static struct sh4_x86_state sh4_x86;
nkeynes@368: 
nkeynes@388: static uint32_t max_int = 0x7FFFFFFF;
nkeynes@388: static uint32_t min_int = 0x80000000;
nkeynes@394: static uint32_t save_fcw; /* save value for fpu control word */
nkeynes@394: static uint32_t trunc_fcw = 0x0F7F; /* fcw value for truncation mode */
nkeynes@386: 
nkeynes@903: gboolean is_sse3_supported()
nkeynes@903: {
nkeynes@903:     uint32_t features;
nkeynes@903:     
nkeynes@903:     __asm__ __volatile__(
nkeynes@903:         "mov $0x01, %%eax\n\t"
nkeynes@908:         "cpuid\n\t" : "=c" (features) : : "eax", "edx", "ebx");
nkeynes@903:     return (features & 1) ? TRUE : FALSE;
nkeynes@903: }
nkeynes@903: 
nkeynes@669: void sh4_translate_init(void)
nkeynes@368: {
nkeynes@368:     sh4_x86.backpatch_list = malloc(DEFAULT_BACKPATCH_SIZE);
nkeynes@559:     sh4_x86.backpatch_size = DEFAULT_BACKPATCH_SIZE / sizeof(struct backpatch_record);
nkeynes@903:     sh4_x86.sse3_enabled = is_sse3_supported();
nkeynes@368: }
nkeynes@368: 
nkeynes@368: 
nkeynes@559: static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
nkeynes@368: {
nkeynes@991:     int reloc_size = 4;
nkeynes@991:     
nkeynes@991:     if( exc_code == -2 ) {
nkeynes@991:         reloc_size = sizeof(void *);
nkeynes@991:     }
nkeynes@991:     
nkeynes@368:     if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
nkeynes@368: 	sh4_x86.backpatch_size <<= 1;
nkeynes@559: 	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
nkeynes@559: 					  sh4_x86.backpatch_size * sizeof(struct backpatch_record));
nkeynes@368: 	assert( sh4_x86.backpatch_list != NULL );
nkeynes@368:     }
nkeynes@559:     if( sh4_x86.in_delay_slot ) {
nkeynes@559: 	fixup_pc -= 2;
nkeynes@368:     }
nkeynes@991: 
nkeynes@604:     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
nkeynes@991: 	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
nkeynes@559:     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
nkeynes@559:     sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
nkeynes@559:     sh4_x86.backpatch_posn++;
nkeynes@368: }
nkeynes@368: 
nkeynes@991: #define TSTATE_NONE -1
nkeynes@995: #define TSTATE_O    X86_COND_O
nkeynes@995: #define TSTATE_C    X86_COND_C
nkeynes@995: #define TSTATE_E    X86_COND_E
nkeynes@995: #define TSTATE_NE   X86_COND_NE
nkeynes@995: #define TSTATE_G    X86_COND_G
nkeynes@995: #define TSTATE_GE   X86_COND_GE
nkeynes@995: #define TSTATE_A    X86_COND_A
nkeynes@995: #define TSTATE_AE   X86_COND_AE
nkeynes@577: 
nkeynes@991: #define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
nkeynes@991: #define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
nkeynes@359: 
nkeynes@991: /* Convenience instructions */
nkeynes@991: #define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
nkeynes@991: #define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
nkeynes@991: #define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
nkeynes@991: #define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
nkeynes@991: #define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
nkeynes@991: #define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
nkeynes@991: #define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
nkeynes@991: #define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
nkeynes@991: #define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
nkeynes@991: #define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
nkeynes@991: #define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
nkeynes@991: #define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
nkeynes@991: #define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
nkeynes@991: #define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
nkeynes@991: #define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
nkeynes@991: #define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
nkeynes@991: #define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
nkeynes@991: #define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
nkeynes@991: #define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
nkeynes@368: 
nkeynes@991: /** Branch if T is set (either in the current cflags, or in sh4r.t) */
nkeynes@991: #define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@991: 	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@991:     JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
nkeynes@374: 
nkeynes@991: /** Branch if T is clear (either in the current cflags or in sh4r.t) */
nkeynes@991: #define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
nkeynes@991: 	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
nkeynes@991:     JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
nkeynes@368: 
nkeynes@359: 
nkeynes@991: #define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
nkeynes@991: #define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
nkeynes@374: 
nkeynes@375: /**
nkeynes@375:  * Load an FR register (single-precision floating point) into an integer x86
nkeynes@375:  * register (eg for register-to-register moves)
nkeynes@375:  */
nkeynes@991: #define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
nkeynes@991: #define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
nkeynes@375: 
nkeynes@375: /**
nkeynes@669:  * Load the low half of a DR register (DR or XD) into an integer x86 register 
nkeynes@669:  */
nkeynes@991: #define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
nkeynes@991: #define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
nkeynes@669: 
nkeynes@669: /**
nkeynes@669:  * Store an FR register (single-precision floating point) from an integer x86+
nkeynes@375:  * register (eg for register-to-register moves)
nkeynes@375:  */
nkeynes@991: #define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991: #define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@375: 
nkeynes@991: #define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
nkeynes@991: #define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
nkeynes@375: 
nkeynes@374: 
nkeynes@991: #define push_fpul()  FLDF_rbpdisp(R_FPUL)
nkeynes@991: #define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
nkeynes@991: #define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991: #define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
nkeynes@991: #define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991: #define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
nkeynes@991: #define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991: #define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
nkeynes@991: #define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@991: #define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
nkeynes@377: 
nkeynes@991: #ifdef ENABLE_SH4STATS
nkeynes@995: #define COUNT_INST(id) MOVL_imm32_r32( id, REG_EAX ); CALL1_ptr_r32(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
nkeynes@991: #else
nkeynes@991: #define COUNT_INST(id)
nkeynes@991: #endif
nkeynes@377: 
nkeynes@374: 
nkeynes@368: /* Exception checks - Note that all exception checks will clobber EAX */
nkeynes@416: 
nkeynes@416: #define check_priv( ) \
nkeynes@953:     if( (sh4r.xlat_sh4_mode & SR_MD) == 0 ) { \
nkeynes@953:         if( sh4_x86.in_delay_slot ) { \
nkeynes@956:             exit_block_exc(EXC_SLOT_ILLEGAL, (pc-2) ); \
nkeynes@953:         } else { \
nkeynes@956:             exit_block_exc(EXC_ILLEGAL, pc); \
nkeynes@953:         } \
nkeynes@956:         sh4_x86.branch_taken = TRUE; \
nkeynes@953:         sh4_x86.in_delay_slot = DELAY_NONE; \
nkeynes@953:         return 2; \
nkeynes@953:     }
nkeynes@416: 
nkeynes@416: #define check_fpuen( ) \
nkeynes@416:     if( !sh4_x86.fpuen_checked ) {\
nkeynes@416: 	sh4_x86.fpuen_checked = TRUE;\
nkeynes@995: 	MOVL_rbpdisp_r32( R_SR, REG_EAX );\
nkeynes@991: 	ANDL_imms_r32( SR_FD, REG_EAX );\
nkeynes@416: 	if( sh4_x86.in_delay_slot ) {\
nkeynes@559: 	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
nkeynes@416: 	} else {\
nkeynes@559: 	    JNE_exc(EXC_FPU_DISABLED);\
nkeynes@416: 	}\
nkeynes@875: 	sh4_x86.tstate = TSTATE_NONE; \
nkeynes@416:     }
nkeynes@416: 
nkeynes@559: #define check_ralign16( x86reg ) \
nkeynes@991:     TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@559:     JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@416: 
nkeynes@559: #define check_walign16( x86reg ) \
nkeynes@991:     TESTL_imms_r32( 0x00000001, x86reg ); \
nkeynes@559:     JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368: 
nkeynes@559: #define check_ralign32( x86reg ) \
nkeynes@991:     TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@559:     JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@368: 
nkeynes@559: #define check_walign32( x86reg ) \
nkeynes@991:     TESTL_imms_r32( 0x00000003, x86reg ); \
nkeynes@559:     JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@368: 
nkeynes@732: #define check_ralign64( x86reg ) \
nkeynes@991:     TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732:     JNE_exc(EXC_DATA_ADDR_READ)
nkeynes@732: 
nkeynes@732: #define check_walign64( x86reg ) \
nkeynes@991:     TESTL_imms_r32( 0x00000007, x86reg ); \
nkeynes@732:     JNE_exc(EXC_DATA_ADDR_WRITE);
nkeynes@732: 
nkeynes@1004: #define address_space() ((sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space)
nkeynes@1004: 
nkeynes@824: #define UNDEF(ir)
nkeynes@953: /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
nkeynes@953:  * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
nkeynes@953:  */
nkeynes@953: #ifdef HAVE_FRAME_ADDRESS
nkeynes@995: static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995: {
nkeynes@1004:     decode_address(address_space(), addr_reg);
nkeynes@995:     if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
nkeynes@995:         CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995:     } else {
nkeynes@995:         if( addr_reg != REG_ARG1 ) {
nkeynes@995:             MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995:         }
nkeynes@995:         MOVP_immptr_rptr( 0, REG_ARG2 );
nkeynes@995:         sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995:         CALL2_r32disp_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2);
nkeynes@995:     }
nkeynes@995:     if( value_reg != REG_RESULT1 ) { 
nkeynes@995:         MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995:     }
nkeynes@995: }
nkeynes@995: 
nkeynes@995: static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995: {
nkeynes@1004:     decode_address(address_space(), addr_reg);
nkeynes@995:     if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { 
nkeynes@995:         CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995:     } else {
nkeynes@995:         if( value_reg != REG_ARG2 ) {
nkeynes@995:             MOVL_r32_r32( value_reg, REG_ARG2 );
nkeynes@995: 	}        
nkeynes@995:         if( addr_reg != REG_ARG1 ) {
nkeynes@995:             MOVL_r32_r32( addr_reg, REG_ARG1 );
nkeynes@995:         }
nkeynes@995: #if MAX_REG_ARG > 2        
nkeynes@995:         MOVP_immptr_rptr( 0, REG_ARG3 );
nkeynes@995:         sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995:         CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, REG_ARG3);
nkeynes@995: #else
nkeynes@995:         MOVL_imm32_rspdisp( 0, 0 );
nkeynes@995:         sh4_x86_add_backpatch( xlat_output, pc, -2 );
nkeynes@995:         CALL3_r32disp_r32_r32_r32(REG_ECX, offset, REG_ARG1, REG_ARG2, 0);
nkeynes@995: #endif
nkeynes@995:     }
nkeynes@995: }
nkeynes@995: #else
nkeynes@995: static void call_read_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995: {
nkeynes@1004:     decode_address(address_space(), addr_reg);
nkeynes@995:     CALL1_r32disp_r32(REG_ECX, offset, addr_reg);
nkeynes@995:     if( value_reg != REG_RESULT1 ) {
nkeynes@995:         MOVL_r32_r32( REG_RESULT1, value_reg );
nkeynes@995:     }
nkeynes@995: }     
nkeynes@995: 
nkeynes@996: static void call_write_func(int addr_reg, int value_reg, int offset, int pc)
nkeynes@995: {
nkeynes@1004:     decode_address(address_space(), addr_reg);
nkeynes@995:     CALL2_r32disp_r32_r32(REG_ECX, offset, addr_reg, value_reg);
nkeynes@995: }
nkeynes@953: #endif
nkeynes@953:                 
nkeynes@995: #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
nkeynes@995: #define MEM_READ_BYTE( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_byte), pc)
nkeynes@995: #define MEM_READ_BYTE_FOR_WRITE( addr_reg, value_reg ) call_read_func( addr_reg, value_reg, MEM_REGION_PTR(read_byte_for_write), pc) 
nkeynes@995: #define MEM_READ_WORD( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_word), pc)
nkeynes@995: #define MEM_READ_LONG( addr_reg, value_reg ) call_read_func(addr_reg, value_reg, MEM_REGION_PTR(read_long), pc)
nkeynes@995: #define MEM_WRITE_BYTE( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_byte), pc)
nkeynes@995: #define MEM_WRITE_WORD( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_word), pc)
nkeynes@995: #define MEM_WRITE_LONG( addr_reg, value_reg ) call_write_func(addr_reg, value_reg, MEM_REGION_PTR(write_long), pc)
nkeynes@995: #define MEM_PREFETCH( addr_reg ) call_read_func(addr_reg, REG_RESULT1, MEM_REGION_PTR(prefetch), pc)
nkeynes@361: 
nkeynes@956: #define SLOTILLEGAL() exit_block_exc(EXC_SLOT_ILLEGAL, pc-2); sh4_x86.in_delay_slot = DELAY_NONE; return 2;
nkeynes@388: 
nkeynes@901: void sh4_translate_begin_block( sh4addr_t pc ) 
nkeynes@901: {
nkeynes@927:     enter_block();
nkeynes@1004:     MOVP_immptr_rptr( ((uint8_t *)&sh4r) + 128, REG_EBP );
nkeynes@901:     sh4_x86.in_delay_slot = FALSE;
nkeynes@901:     sh4_x86.fpuen_checked = FALSE;
nkeynes@901:     sh4_x86.branch_taken = FALSE;
nkeynes@901:     sh4_x86.backpatch_posn = 0;
nkeynes@901:     sh4_x86.block_start_pc = pc;
nkeynes@953:     sh4_x86.tlb_on = IS_TLB_ENABLED();
nkeynes@901:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@901:     sh4_x86.double_prec = sh4r.fpscr & FPSCR_PR;
nkeynes@903:     sh4_x86.double_size = sh4r.fpscr & FPSCR_SZ;
nkeynes@901: }
nkeynes@901: 
nkeynes@901: 
nkeynes@593: uint32_t sh4_translate_end_block_size()
nkeynes@593: {
nkeynes@596:     if( sh4_x86.backpatch_posn <= 3 ) {
nkeynes@1008:         return EPILOGUE_SIZE + (sh4_x86.backpatch_posn*24);
nkeynes@596:     } else {
nkeynes@1008:         return EPILOGUE_SIZE + 72 + (sh4_x86.backpatch_posn-3)*27;
nkeynes@596:     }
nkeynes@593: }
nkeynes@593: 
nkeynes@361: 
nkeynes@571: /**
nkeynes@590:  * Embed a breakpoint into the generated code
nkeynes@571:  */
nkeynes@577: void sh4_translate_emit_breakpoint( sh4vma_t pc )
nkeynes@577: {
nkeynes@995:     MOVL_imm32_r32( pc, REG_EAX );
nkeynes@995:     CALL1_ptr_r32( sh4_translate_breakpoint_hit, REG_EAX );
nkeynes@875:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@577: }
nkeynes@590: 
nkeynes@601: 
nkeynes@601: #define UNTRANSLATABLE(pc) !IS_IN_ICACHE(pc)
nkeynes@601: 
nkeynes@590: /**
nkeynes@995:  * Exit the block with sh4r.pc already written
nkeynes@995:  */
nkeynes@995: void exit_block_pcset( sh4addr_t pc )
nkeynes@995: {
nkeynes@995:     MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995:     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995:     MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995:     if( sh4_x86.tlb_on ) {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995:     } else {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995:     }
nkeynes@995:     exit_block();
nkeynes@995: }
nkeynes@995: 
nkeynes@995: /**
nkeynes@995:  * Exit the block with sh4r.new_pc written with the target pc
nkeynes@995:  */
nkeynes@995: void exit_block_newpcset( sh4addr_t pc )
nkeynes@995: {
nkeynes@995:     MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995:     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995:     MOVL_rbpdisp_r32( R_NEW_PC, REG_ARG1 );
nkeynes@995:     MOVL_r32_rbpdisp( REG_ARG1, R_PC );
nkeynes@995:     if( sh4_x86.tlb_on ) {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995:     } else {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995:     }
nkeynes@995:     exit_block();
nkeynes@995: }
nkeynes@995: 
nkeynes@995: 
nkeynes@995: /**
nkeynes@995:  * Exit the block to an absolute PC
nkeynes@995:  */
nkeynes@995: void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995: {
nkeynes@995:     MOVL_imm32_r32( pc, REG_ECX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995:     if( IS_IN_ICACHE(pc) ) {
nkeynes@995:         MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@995:         ANDP_imms_rptr( -4, REG_EAX );
nkeynes@995:     } else if( sh4_x86.tlb_on ) {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
nkeynes@995:     } else {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code, REG_ECX);
nkeynes@995:     }
nkeynes@995:     MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995:     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995:     exit_block();
nkeynes@995: }
nkeynes@995: 
nkeynes@995: /**
nkeynes@995:  * Exit the block to a relative PC
nkeynes@995:  */
nkeynes@995: void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
nkeynes@995: {
nkeynes@995:     MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995:     ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995:     if( IS_IN_ICACHE(pc) ) {
nkeynes@995:         MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) );
nkeynes@995:         ANDP_imms_rptr( -4, REG_EAX );
nkeynes@995:     } else if( sh4_x86.tlb_on ) {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code_by_vma, REG_ECX);
nkeynes@995:     } else {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code, REG_ECX);
nkeynes@995:     }
nkeynes@995:     MOVL_imm32_r32( ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995:     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995:     exit_block();
nkeynes@995: }
nkeynes@995: 
nkeynes@995: /**
nkeynes@995:  * Exit unconditionally with a general exception
nkeynes@995:  */
nkeynes@995: void exit_block_exc( int code, sh4addr_t pc )
nkeynes@995: {
nkeynes@995:     MOVL_imm32_r32( pc - sh4_x86.block_start_pc, REG_ECX );
nkeynes@995:     ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995:     MOVL_imm32_r32( ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period, REG_ECX );
nkeynes@995:     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );
nkeynes@995:     MOVL_imm32_r32( code, REG_ARG1 );
nkeynes@995:     CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995:     MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995:     if( sh4_x86.tlb_on ) {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code_by_vma,REG_ARG1);
nkeynes@995:     } else {
nkeynes@995:         CALL1_ptr_r32(xlat_get_code,REG_ARG1);
nkeynes@995:     }
nkeynes@995: 
nkeynes@995:     exit_block();
nkeynes@995: }    
nkeynes@995: 
nkeynes@995: /**
nkeynes@590:  * Embed a call to sh4_execute_instruction for situations that we
nkeynes@601:  * can't translate (just page-crossing delay slots at the moment).
nkeynes@601:  * Caller is responsible for setting new_pc before calling this function.
nkeynes@601:  *
nkeynes@601:  * Performs:
nkeynes@601:  *   Set PC = endpc
nkeynes@601:  *   Set sh4r.in_delay_slot = sh4_x86.in_delay_slot
nkeynes@601:  *   Update slice_cycle for endpc+2 (single step doesn't update slice_cycle)
nkeynes@601:  *   Call sh4_execute_instruction
nkeynes@601:  *   Call xlat_get_code_by_vma / xlat_get_code as for normal exit
nkeynes@590:  */
nkeynes@601: void exit_block_emu( sh4vma_t endpc )
nkeynes@590: {
nkeynes@995:     MOVL_imm32_r32( endpc - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991:     ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@577:     
nkeynes@995:     MOVL_imm32_r32( (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period, REG_ECX ); // 5
nkeynes@991:     ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
nkeynes@995:     MOVL_imm32_r32( sh4_x86.in_delay_slot ? 1 : 0, REG_ECX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_ECX, REG_OFFSET(in_delay_slot) );
nkeynes@590: 
nkeynes@995:     CALL_ptr( sh4_execute_instruction );    
nkeynes@995:     MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@590:     if( sh4_x86.tlb_on ) {
nkeynes@995: 	CALL1_ptr_r32(xlat_get_code_by_vma,REG_EAX);
nkeynes@590:     } else {
nkeynes@995: 	CALL1_ptr_r32(xlat_get_code,REG_EAX);
nkeynes@590:     }
nkeynes@926:     exit_block();
nkeynes@590: } 
nkeynes@539: 
nkeynes@359: /**
nkeynes@995:  * Write the block trailer (exception handling block)
nkeynes@995:  */
nkeynes@995: void sh4_translate_end_block( sh4addr_t pc ) {
nkeynes@995:     if( sh4_x86.branch_taken == FALSE ) {
nkeynes@995:         // Didn't exit unconditionally already, so write the termination here
nkeynes@995:         exit_block_rel( pc, pc );
nkeynes@995:     }
nkeynes@995:     if( sh4_x86.backpatch_posn != 0 ) {
nkeynes@995:         unsigned int i;
nkeynes@995:         // Exception raised - cleanup and exit
nkeynes@995:         uint8_t *end_ptr = xlat_output;
nkeynes@995:         MOVL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995:         ADDL_r32_r32( REG_EDX, REG_ECX );
nkeynes@995:         ADDL_r32_rbpdisp( REG_ECX, R_SPC );
nkeynes@995:         MOVL_moffptr_eax( &sh4_cpu_period );
nkeynes@995:         MULL_r32( REG_EDX );
nkeynes@995:         ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
nkeynes@995:         MOVL_rbpdisp_r32( R_PC, REG_ARG1 );
nkeynes@995:         if( sh4_x86.tlb_on ) {
nkeynes@995:             CALL1_ptr_r32(xlat_get_code_by_vma, REG_ARG1);
nkeynes@995:         } else {
nkeynes@995:             CALL1_ptr_r32(xlat_get_code, REG_ARG1);
nkeynes@995:         }
nkeynes@995:         exit_block();
nkeynes@995: 
nkeynes@995:         for( i=0; i< sh4_x86.backpatch_posn; i++ ) {
nkeynes@995:             uint32_t *fixup_addr = (uint32_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset];
nkeynes@995:             if( sh4_x86.backpatch_list[i].exc_code < 0 ) {
nkeynes@995:                 if( sh4_x86.backpatch_list[i].exc_code == -2 ) {
nkeynes@995:                     *((uintptr_t *)fixup_addr) = (uintptr_t)xlat_output; 
nkeynes@995:                 } else {
nkeynes@995:                     *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995:                 }
nkeynes@995:                 MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995:                 int rel = end_ptr - xlat_output;
nkeynes@995:                 JMP_prerel(rel);
nkeynes@995:             } else {
nkeynes@995:                 *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
nkeynes@995:                 MOVL_imm32_r32( sh4_x86.backpatch_list[i].exc_code, REG_ARG1 );
nkeynes@995:                 CALL1_ptr_r32( sh4_raise_exception, REG_ARG1 );
nkeynes@995:                 MOVL_imm32_r32( sh4_x86.backpatch_list[i].fixup_icount, REG_EDX );
nkeynes@995:                 int rel = end_ptr - xlat_output;
nkeynes@995:                 JMP_prerel(rel);
nkeynes@995:             }
nkeynes@995:         }
nkeynes@995:     }
nkeynes@995: }
nkeynes@539: 
nkeynes@359: /**
nkeynes@359:  * Translate a single instruction. Delayed branches are handled specially
nkeynes@359:  * by translating both branch and delayed instruction as a single unit (as
nkeynes@359:  * 
nkeynes@577:  * The instruction MUST be in the icache (assert check)
nkeynes@359:  *
nkeynes@359:  * @return true if the instruction marks the end of a basic block
nkeynes@359:  * (eg a branch or 
nkeynes@359:  */
nkeynes@590: uint32_t sh4_translate_instruction( sh4vma_t pc )
nkeynes@359: {
nkeynes@388:     uint32_t ir;
nkeynes@577:     /* Read instruction from icache */
nkeynes@577:     assert( IS_IN_ICACHE(pc) );
nkeynes@577:     ir = *(uint16_t *)GET_ICACHE_PTR(pc);
nkeynes@577:     
nkeynes@571:     if( !sh4_x86.in_delay_slot ) {
nkeynes@596: 	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
nkeynes@388:     }
nkeynes@1003:     
nkeynes@1003:     /* check for breakpoints at this pc */
nkeynes@1003:     for( int i=0; i<sh4_breakpoint_count; i++ ) {
nkeynes@1003:         if( sh4_breakpoints[i].address == pc ) {
nkeynes@1003:             sh4_translate_emit_breakpoint(pc);
nkeynes@1003:             break;
nkeynes@1003:         }
nkeynes@571:     }
nkeynes@359: %%
nkeynes@359: /* ALU operations */
nkeynes@359: ADD Rm, Rn {:
nkeynes@671:     COUNT_INST(I_ADD);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: ADD #imm, Rn {:  
nkeynes@671:     COUNT_INST(I_ADDI);
nkeynes@991:     ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: ADDC Rm, Rn {:
nkeynes@671:     COUNT_INST(I_ADDC);
nkeynes@417:     if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@911:         LDC_t();
nkeynes@417:     }
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     ADCL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@359:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: ADDV Rm, Rn {:
nkeynes@671:     COUNT_INST(I_ADDV);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     ADDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@359:     SETO_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_O;
nkeynes@359: :}
nkeynes@359: AND Rm, Rn {:
nkeynes@671:     COUNT_INST(I_AND);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     ANDL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: AND #imm, R0 {:  
nkeynes@671:     COUNT_INST(I_ANDI);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ANDL_imms_r32(imm, REG_EAX); 
nkeynes@991:     store_reg( REG_EAX, 0 );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: AND.B #imm, @(R0, GBR) {: 
nkeynes@671:     COUNT_INST(I_ANDB);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991:     MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991:     MOVL_rspdisp_r32(0, REG_EAX);
nkeynes@991:     ANDL_imms_r32(imm, REG_EDX );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: CMP/EQ Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_CMPEQ);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359:     SETE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_E;
nkeynes@359: :}
nkeynes@359: CMP/EQ #imm, R0 {:  
nkeynes@671:     COUNT_INST(I_CMPEQI);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     CMPL_imms_r32(imm, REG_EAX);
nkeynes@359:     SETE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_E;
nkeynes@359: :}
nkeynes@359: CMP/GE Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_CMPGE);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359:     SETGE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_GE;
nkeynes@359: :}
nkeynes@359: CMP/GT Rm, Rn {: 
nkeynes@671:     COUNT_INST(I_CMPGT);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359:     SETG_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_G;
nkeynes@359: :}
nkeynes@359: CMP/HI Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_CMPHI);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359:     SETA_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_A;
nkeynes@359: :}
nkeynes@359: CMP/HS Rm, Rn {: 
nkeynes@671:     COUNT_INST(I_CMPHS);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@359:     SETAE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_AE;
nkeynes@359:  :}
nkeynes@359: CMP/PL Rn {: 
nkeynes@671:     COUNT_INST(I_CMPPL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     CMPL_imms_r32( 0, REG_EAX );
nkeynes@359:     SETG_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_G;
nkeynes@359: :}
nkeynes@359: CMP/PZ Rn {:  
nkeynes@671:     COUNT_INST(I_CMPPZ);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     CMPL_imms_r32( 0, REG_EAX );
nkeynes@359:     SETGE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_GE;
nkeynes@359: :}
nkeynes@361: CMP/STR Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_CMPSTR);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     XORL_r32_r32( REG_ECX, REG_EAX );
nkeynes@991:     TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991:     JE_label(target1);
nkeynes@991:     TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@991:     JE_label(target2);
nkeynes@991:     SHRL_imm_r32( 16, REG_EAX );
nkeynes@991:     TESTB_r8_r8( REG_AL, REG_AL );
nkeynes@991:     JE_label(target3);
nkeynes@991:     TESTB_r8_r8( REG_AH, REG_AH );
nkeynes@380:     JMP_TARGET(target1);
nkeynes@380:     JMP_TARGET(target2);
nkeynes@380:     JMP_TARGET(target3);
nkeynes@368:     SETE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_E;
nkeynes@361: :}
nkeynes@361: DIV0S Rm, Rn {:
nkeynes@671:     COUNT_INST(I_DIV0S);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     SHRL_imm_r32( 31, REG_EAX );
nkeynes@991:     SHRL_imm_r32( 31, REG_ECX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995:     MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991:     CMPL_r32_r32( REG_EAX, REG_ECX );
nkeynes@386:     SETNE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_NE;
nkeynes@361: :}
nkeynes@361: DIV0U {:  
nkeynes@671:     COUNT_INST(I_DIV0U);
nkeynes@991:     XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_Q );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_M );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417:     sh4_x86.tstate = TSTATE_C; // works for DIV1
nkeynes@361: :}
nkeynes@386: DIV1 Rm, Rn {:
nkeynes@671:     COUNT_INST(I_DIV1);
nkeynes@995:     MOVL_rbpdisp_r32( R_M, REG_ECX );
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@417:     if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417: 	LDC_t();
nkeynes@417:     }
nkeynes@991:     RCLL_imm_r32( 1, REG_EAX );
nkeynes@991:     SETC_r8( REG_DL ); // Q'
nkeynes@991:     CMPL_rbpdisp_r32( R_Q, REG_ECX );
nkeynes@991:     JE_label(mqequal);
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991:     JMP_label(end);
nkeynes@380:     JMP_TARGET(mqequal);
nkeynes@991:     SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@386:     JMP_TARGET(end);
nkeynes@991:     store_reg( REG_EAX, Rn ); // Done with Rn now
nkeynes@991:     SETC_r8(REG_AL); // tmp1
nkeynes@991:     XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
nkeynes@991:     XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
nkeynes@995:     MOVL_r32_rbpdisp( REG_ECX, R_Q );
nkeynes@991:     XORL_imms_r32( 1, REG_AL );   // T = !Q'
nkeynes@991:     MOVZXL_r8_r32( REG_AL, REG_EAX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_T );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@374: :}
nkeynes@361: DMULS.L Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_DMULS);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     IMULL_r32(REG_ECX);
nkeynes@995:     MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: DMULU.L Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_DMULU);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     MULL_r32(REG_ECX);
nkeynes@995:     MOVL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );    
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@359: DT Rn {:  
nkeynes@671:     COUNT_INST(I_DT);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     ADDL_imms_r32( -1, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359:     SETE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_E;
nkeynes@359: :}
nkeynes@359: EXTS.B Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_EXTSB);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     MOVSXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@361: EXTS.W Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_EXTSW);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@361: :}
nkeynes@361: EXTU.B Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_EXTUB);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     MOVZXL_r8_r32( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@361: :}
nkeynes@361: EXTU.W Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_EXTUW);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     MOVZXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@361: :}
nkeynes@571: MAC.L @Rm+, @Rn+ {:
nkeynes@671:     COUNT_INST(I_MACL);
nkeynes@571:     if( Rm == Rn ) {
nkeynes@991: 	load_reg( REG_EAX, Rm );
nkeynes@991: 	check_ralign32( REG_EAX );
nkeynes@991: 	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991: 	MOVL_r32_rspdisp(REG_EAX, 0);
nkeynes@991: 	load_reg( REG_EAX, Rm );
nkeynes@991: 	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991: 	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
nkeynes@571:     } else {
nkeynes@991: 	load_reg( REG_EAX, Rm );
nkeynes@991: 	check_ralign32( REG_EAX );
nkeynes@991: 	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991: 	MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991: 	load_reg( REG_EAX, Rn );
nkeynes@991: 	check_ralign32( REG_EAX );
nkeynes@991: 	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991: 	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@991: 	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@571:     }
nkeynes@953:     
nkeynes@991:     IMULL_rspdisp( 0 );
nkeynes@991:     ADDL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@991:     ADCL_r32_rbpdisp( REG_EDX, R_MACH );
nkeynes@571: 
nkeynes@995:     MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991:     TESTL_r32_r32(REG_ECX, REG_ECX);
nkeynes@991:     JE_label( nosat );
nkeynes@995:     CALL_ptr( signsat48 );
nkeynes@386:     JMP_TARGET( nosat );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@386: :}
nkeynes@386: MAC.W @Rm+, @Rn+ {:  
nkeynes@671:     COUNT_INST(I_MACW);
nkeynes@571:     if( Rm == Rn ) {
nkeynes@991: 	load_reg( REG_EAX, Rm );
nkeynes@991: 	check_ralign16( REG_EAX );
nkeynes@991: 	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991:         MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991: 	load_reg( REG_EAX, Rm );
nkeynes@991: 	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
nkeynes@991: 	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991: 	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
nkeynes@571: 	// Note translate twice in case of page boundaries. Maybe worth
nkeynes@571: 	// adding a page-boundary check to skip the second translation
nkeynes@571:     } else {
nkeynes@991: 	load_reg( REG_EAX, Rm );
nkeynes@991: 	check_ralign16( REG_EAX );
nkeynes@991: 	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991:         MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991: 	load_reg( REG_EAX, Rn );
nkeynes@991: 	check_ralign16( REG_EAX );
nkeynes@991: 	MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991: 	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
nkeynes@991: 	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@571:     }
nkeynes@991:     IMULL_rspdisp( 0 );
nkeynes@995:     MOVL_rbpdisp_r32( R_S, REG_ECX );
nkeynes@991:     TESTL_r32_r32( REG_ECX, REG_ECX );
nkeynes@991:     JE_label( nosat );
nkeynes@386: 
nkeynes@991:     ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991:     JNO_label( end );            // 2
nkeynes@995:     MOVL_imm32_r32( 1, REG_EDX );         // 5
nkeynes@995:     MOVL_r32_rbpdisp( REG_EDX, R_MACH );   // 6
nkeynes@991:     JS_label( positive );        // 2
nkeynes@995:     MOVL_imm32_r32( 0x80000000, REG_EAX );// 5
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991:     JMP_label(end2);           // 2
nkeynes@386: 
nkeynes@386:     JMP_TARGET(positive);
nkeynes@995:     MOVL_imm32_r32( 0x7FFFFFFF, REG_EAX );// 5
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );   // 6
nkeynes@991:     JMP_label(end3);            // 2
nkeynes@386: 
nkeynes@386:     JMP_TARGET(nosat);
nkeynes@991:     ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
nkeynes@991:     ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
nkeynes@386:     JMP_TARGET(end);
nkeynes@386:     JMP_TARGET(end2);
nkeynes@386:     JMP_TARGET(end3);
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@386: :}
nkeynes@359: MOVT Rn {:  
nkeynes@671:     COUNT_INST(I_MOVT);
nkeynes@995:     MOVL_rbpdisp_r32( R_T, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@361: MUL.L Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_MULL);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     MULL_r32( REG_ECX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@374: MULS.W Rm, Rn {:
nkeynes@671:     COUNT_INST(I_MULSW);
nkeynes@995:     MOVSXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995:     MOVSXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991:     MULL_r32( REG_ECX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@374: MULU.W Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_MULUW);
nkeynes@995:     MOVZXL_rbpdisp16_r32( R_R(Rm), REG_EAX );
nkeynes@995:     MOVZXL_rbpdisp16_r32( R_R(Rn), REG_ECX );
nkeynes@991:     MULL_r32( REG_ECX );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@374: :}
nkeynes@359: NEG Rm, Rn {:
nkeynes@671:     COUNT_INST(I_NEG);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     NEGL_r32( REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: NEGC Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_NEGC);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     XORL_r32_r32( REG_ECX, REG_ECX );
nkeynes@359:     LDC_t();
nkeynes@991:     SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@359:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: NOT Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_NOT);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     NOTL_r32( REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: OR Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_OR);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: OR #imm, R0 {:
nkeynes@671:     COUNT_INST(I_ORI);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ORL_imms_r32(imm, REG_EAX);
nkeynes@991:     store_reg( REG_EAX, 0 );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@374: OR.B #imm, @(R0, GBR) {:  
nkeynes@671:     COUNT_INST(I_ORB);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991:     MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991:     MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991:     ORL_imms_r32(imm, REG_EDX );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@374: :}
nkeynes@359: ROTCL Rn {:
nkeynes@671:     COUNT_INST(I_ROTCL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@417:     if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417: 	LDC_t();
nkeynes@417:     }
nkeynes@991:     RCLL_imm_r32( 1, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: ROTCR Rn {:  
nkeynes@671:     COUNT_INST(I_ROTCR);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@417:     if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417: 	LDC_t();
nkeynes@417:     }
nkeynes@991:     RCRL_imm_r32( 1, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: ROTL Rn {:  
nkeynes@671:     COUNT_INST(I_ROTL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     ROLL_imm_r32( 1, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: ROTR Rn {:  
nkeynes@671:     COUNT_INST(I_ROTR);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     RORL_imm_r32( 1, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: SHAD Rm, Rn {:
nkeynes@671:     COUNT_INST(I_SHAD);
nkeynes@359:     /* Annoyingly enough, not directly convertible */
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     load_reg( REG_ECX, Rm );
nkeynes@991:     CMPL_imms_r32( 0, REG_ECX );
nkeynes@991:     JGE_label(doshl);
nkeynes@361:                     
nkeynes@991:     NEGL_r32( REG_ECX );      // 2
nkeynes@991:     ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991:     JE_label(emptysar);     // 2
nkeynes@991:     SARL_cl_r32( REG_EAX );       // 2
nkeynes@991:     JMP_label(end);          // 2
nkeynes@386: 
nkeynes@386:     JMP_TARGET(emptysar);
nkeynes@991:     SARL_imm_r32(31, REG_EAX );  // 3
nkeynes@991:     JMP_label(end2);
nkeynes@382: 
nkeynes@380:     JMP_TARGET(doshl);
nkeynes@991:     ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991:     SHLL_cl_r32( REG_EAX );       // 2
nkeynes@380:     JMP_TARGET(end);
nkeynes@386:     JMP_TARGET(end2);
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SHLD Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_SHLD);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     load_reg( REG_ECX, Rm );
nkeynes@991:     CMPL_imms_r32( 0, REG_ECX );
nkeynes@991:     JGE_label(doshl);
nkeynes@368: 
nkeynes@991:     NEGL_r32( REG_ECX );      // 2
nkeynes@991:     ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991:     JE_label(emptyshr );
nkeynes@991:     SHRL_cl_r32( REG_EAX );       // 2
nkeynes@991:     JMP_label(end);          // 2
nkeynes@386: 
nkeynes@386:     JMP_TARGET(emptyshr);
nkeynes@991:     XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991:     JMP_label(end2);
nkeynes@382: 
nkeynes@382:     JMP_TARGET(doshl);
nkeynes@991:     ANDB_imms_r8( 0x1F, REG_CL ); // 3
nkeynes@991:     SHLL_cl_r32( REG_EAX );       // 2
nkeynes@382:     JMP_TARGET(end);
nkeynes@386:     JMP_TARGET(end2);
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SHAL Rn {: 
nkeynes@671:     COUNT_INST(I_SHAL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHLL_imm_r32( 1, REG_EAX );
nkeynes@397:     SETC_t();
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: SHAR Rn {:  
nkeynes@671:     COUNT_INST(I_SHAR);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SARL_imm_r32( 1, REG_EAX );
nkeynes@397:     SETC_t();
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: SHLL Rn {:  
nkeynes@671:     COUNT_INST(I_SHLL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHLL_imm_r32( 1, REG_EAX );
nkeynes@397:     SETC_t();
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: SHLL2 Rn {:
nkeynes@671:     COUNT_INST(I_SHLL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHLL_imm_r32( 2, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SHLL8 Rn {:  
nkeynes@671:     COUNT_INST(I_SHLL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHLL_imm_r32( 8, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SHLL16 Rn {:  
nkeynes@671:     COUNT_INST(I_SHLL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHLL_imm_r32( 16, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SHLR Rn {:  
nkeynes@671:     COUNT_INST(I_SHLR);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHRL_imm_r32( 1, REG_EAX );
nkeynes@397:     SETC_t();
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: SHLR2 Rn {:  
nkeynes@671:     COUNT_INST(I_SHLR);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHRL_imm_r32( 2, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SHLR8 Rn {:  
nkeynes@671:     COUNT_INST(I_SHLR);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHRL_imm_r32( 8, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SHLR16 Rn {:  
nkeynes@671:     COUNT_INST(I_SHLR);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     SHRL_imm_r32( 16, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SUB Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_SUB);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: SUBC Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_SUBC);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@417:     if( sh4_x86.tstate != TSTATE_C ) {
nkeynes@417: 	LDC_t();
nkeynes@417:     }
nkeynes@991:     SBBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@394:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@359: SUBV Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_SUBV);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     SUBL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@359:     SETO_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_O;
nkeynes@359: :}
nkeynes@359: SWAP.B Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_SWAPB);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: SWAP.W Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_SWAPB);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     SHLL_imm_r32( 16, REG_ECX );
nkeynes@991:     SHRL_imm_r32( 16, REG_EAX );
nkeynes@991:     ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@361: TAS.B @Rn {:  
nkeynes@671:     COUNT_INST(I_TASB);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991:     MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
nkeynes@991:     TESTB_r8_r8( REG_DL, REG_DL );
nkeynes@361:     SETE_t();
nkeynes@991:     ORB_imms_r8( 0x80, REG_DL );
nkeynes@991:     MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: TST Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_TST);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     TESTL_r32_r32( REG_EAX, REG_ECX );
nkeynes@361:     SETE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_E;
nkeynes@361: :}
nkeynes@368: TST #imm, R0 {:  
nkeynes@671:     COUNT_INST(I_TSTI);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     TESTL_imms_r32( imm, REG_EAX );
nkeynes@368:     SETE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_E;
nkeynes@368: :}
nkeynes@368: TST.B #imm, @(R0, GBR) {:  
nkeynes@671:     COUNT_INST(I_TSTB);
nkeynes@991:     load_reg( REG_EAX, 0);
nkeynes@991:     ADDL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991:     TESTB_imms_r8( imm, REG_AL );
nkeynes@368:     SETE_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_E;
nkeynes@368: :}
nkeynes@359: XOR Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_XOR);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     XORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: XOR #imm, R0 {:  
nkeynes@671:     COUNT_INST(I_XORI);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     XORL_imms_r32( imm, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, 0 );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: XOR.B #imm, @(R0, GBR) {:  
nkeynes@671:     COUNT_INST(I_XORB);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
nkeynes@991:     MOVL_r32_rspdisp( REG_EAX, 0 );
nkeynes@991:     MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
nkeynes@991:     MOVL_rspdisp_r32( 0, REG_EAX );
nkeynes@991:     XORL_imms_r32( imm, REG_EDX );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@361: XTRCT Rm, Rn {:
nkeynes@671:     COUNT_INST(I_XTRCT);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     load_reg( REG_ECX, Rn );
nkeynes@991:     SHLL_imm_r32( 16, REG_EAX );
nkeynes@991:     SHRL_imm_r32( 16, REG_ECX );
nkeynes@991:     ORL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     store_reg( REG_ECX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: 
nkeynes@359: /* Data move instructions */
nkeynes@359: MOV Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_MOV);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: MOV #imm, Rn {:  
nkeynes@671:     COUNT_INST(I_MOVI);
nkeynes@995:     MOVL_imm32_r32( imm, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: MOV.B Rm, @Rn {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B Rm, @-Rn {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B Rm, @(R0, Rn) {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B R0, @(disp, GBR) {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@995:     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     load_reg( REG_EDX, 0 );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B R0, @(disp, Rn) {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     load_reg( REG_EDX, 0 );
nkeynes@991:     MEM_WRITE_BYTE( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B @Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B @Rm+, Rn {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@953:     if( Rm != Rn ) {
nkeynes@991:     	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
nkeynes@953:     }
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B @(R0, Rm), Rn {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991:     MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B @(disp, GBR), R0 {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@995:     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, 0 );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: MOV.B @(disp, Rm), R0 {:  
nkeynes@671:     COUNT_INST(I_MOVB);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     MEM_READ_BYTE( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, 0 );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@374: MOV.L Rm, @Rn {:
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32(REG_EAX);
nkeynes@991:     MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991:     CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991:     JNE_label( notsq );
nkeynes@991:     ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991:     JMP_label(end);
nkeynes@953:     JMP_TARGET(notsq);
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@953:     JMP_TARGET(end);
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L Rm, @-Rn {:  
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L Rm, @(R0, Rn) {:  
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L R0, @(disp, GBR) {:  
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@995:     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     load_reg( REG_EDX, 0 );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L Rm, @(disp, Rn) {:  
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     MOVL_r32_r32( REG_EAX, REG_ECX );
nkeynes@991:     ANDL_imms_r32( 0xFC000000, REG_ECX );
nkeynes@991:     CMPL_imms_r32( 0xE0000000, REG_ECX );
nkeynes@991:     JNE_label( notsq );
nkeynes@991:     ANDL_imms_r32( 0x3C, REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
nkeynes@991:     JMP_label(end);
nkeynes@953:     JMP_TARGET(notsq);
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@953:     JMP_TARGET(end);
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L @Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L @Rm+, Rn {:  
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@953:     if( Rm != Rn ) {
nkeynes@991:     	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@953:     }
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L @(R0, Rm), Rn {:  
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L @(disp, GBR), R0 {:
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@995:     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, 0 );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.L @(disp, PC), Rn {:  
nkeynes@671:     COUNT_INST(I_MOVLPC);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@388: 	uint32_t target = (pc & 0xFFFFFFFC) + disp + 4;
nkeynes@569: 	if( IS_IN_ICACHE(target) ) {
nkeynes@569: 	    // If the target address is in the same page as the code, it's
nkeynes@569: 	    // pretty safe to just ref it directly and circumvent the whole
nkeynes@569: 	    // memory subsystem. (this is a big performance win)
nkeynes@569: 
nkeynes@569: 	    // FIXME: There's a corner-case that's not handled here when
nkeynes@569: 	    // the current code-page is in the ITLB but not in the UTLB.
nkeynes@569: 	    // (should generate a TLB miss although need to test SH4 
nkeynes@569: 	    // behaviour to confirm) Unlikely to be anyone depending on this
nkeynes@569: 	    // behaviour though.
nkeynes@569: 	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991: 	    MOVL_moffptr_eax( ptr );
nkeynes@388: 	} else {
nkeynes@569: 	    // Note: we use sh4r.pc for the calc as we could be running at a
nkeynes@569: 	    // different virtual address than the translation was done with,
nkeynes@569: 	    // but we can safely assume that the low bits are the same.
nkeynes@995: 	    MOVL_imm32_r32( (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_EAX );
nkeynes@991: 	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991: 	    MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@569: 	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@388: 	}
nkeynes@991: 	store_reg( REG_EAX, Rn );
nkeynes@374:     }
nkeynes@361: :}
nkeynes@361: MOV.L @(disp, Rm), Rn {:  
nkeynes@671:     COUNT_INST(I_MOVL);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W Rm, @Rn {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign16( REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W Rm, @-Rn {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign16( REG_EAX );
nkeynes@991:     LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W Rm, @(R0, Rn) {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@991:     check_walign16( REG_EAX );
nkeynes@991:     load_reg( REG_EDX, Rm );
nkeynes@991:     MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W R0, @(disp, GBR) {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@995:     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     check_walign16( REG_EAX );
nkeynes@991:     load_reg( REG_EDX, 0 );
nkeynes@991:     MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W R0, @(disp, Rn) {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     check_walign16( REG_EAX );
nkeynes@991:     load_reg( REG_EDX, 0 );
nkeynes@991:     MEM_WRITE_WORD( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W @Rm, Rn {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign16( REG_EAX );
nkeynes@991:     MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W @Rm+, Rn {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign16( REG_EAX );
nkeynes@991:     MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@953:     if( Rm != Rn ) {
nkeynes@991:         ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
nkeynes@953:     }
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W @(R0, Rm), Rn {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@991:     load_reg( REG_EAX, 0 );
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
nkeynes@991:     check_ralign16( REG_EAX );
nkeynes@991:     MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W @(disp, GBR), R0 {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@995:     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     check_ralign16( REG_EAX );
nkeynes@991:     MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, 0 );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOV.W @(disp, PC), Rn {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@569: 	// See comments for MOV.L @(disp, PC), Rn
nkeynes@569: 	uint32_t target = pc + disp + 4;
nkeynes@569: 	if( IS_IN_ICACHE(target) ) {
nkeynes@569: 	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
nkeynes@991: 	    MOVL_moffptr_eax( ptr );
nkeynes@991: 	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
nkeynes@569: 	} else {
nkeynes@995: 	    MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4, REG_EAX );
nkeynes@991: 	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991: 	    MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@569: 	    sh4_x86.tstate = TSTATE_NONE;
nkeynes@569: 	}
nkeynes@991: 	store_reg( REG_EAX, Rn );
nkeynes@374:     }
nkeynes@361: :}
nkeynes@361: MOV.W @(disp, Rm), R0 {:  
nkeynes@671:     COUNT_INST(I_MOVW);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     ADDL_imms_r32( disp, REG_EAX );
nkeynes@991:     check_ralign16( REG_EAX );
nkeynes@991:     MEM_READ_WORD( REG_EAX, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, 0 );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@361: MOVA @(disp, PC), R0 {:  
nkeynes@671:     COUNT_INST(I_MOVA);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@995: 	MOVL_imm32_r32( (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03), REG_ECX );
nkeynes@991: 	ADDL_rbpdisp_r32( R_PC, REG_ECX );
nkeynes@991: 	store_reg( REG_ECX, 0 );
nkeynes@571: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@374:     }
nkeynes@361: :}
nkeynes@361: MOVCA.L R0, @Rn {:  
nkeynes@671:     COUNT_INST(I_MOVCA);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     load_reg( REG_EDX, 0 );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@361: :}
nkeynes@359: 
nkeynes@359: /* Control transfer instructions */
nkeynes@374: BF disp {:
nkeynes@671:     COUNT_INST(I_BF);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@571: 	sh4vma_t target = disp + pc + 4;
nkeynes@991: 	JT_label( nottaken );
nkeynes@571: 	exit_block_rel(target, pc+2 );
nkeynes@380: 	JMP_TARGET(nottaken);
nkeynes@408: 	return 2;
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: BF/S disp {:
nkeynes@671:     COUNT_INST(I_BFS);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@590: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995: 	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991: 	    JT_label(nottaken);
nkeynes@991: 	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601: 	    JMP_TARGET(nottaken);
nkeynes@991: 	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995: 	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    sh4_x86.branch_taken = TRUE;
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991: 		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601: 		sh4_x86.tstate = TSTATE_E;
nkeynes@601: 	    }
nkeynes@601: 	    sh4vma_t target = disp + pc + 4;
nkeynes@991: 	    JCC_cc_rel32(sh4_x86.tstate,0);
nkeynes@991: 	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@879: 	    int save_tstate = sh4_x86.tstate;
nkeynes@601: 	    sh4_translate_instruction(pc+2);
nkeynes@601: 	    exit_block_rel( target, pc+4 );
nkeynes@601: 	    
nkeynes@601: 	    // not taken
nkeynes@601: 	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879: 	    sh4_x86.tstate = save_tstate;
nkeynes@601: 	    sh4_translate_instruction(pc+2);
nkeynes@601: 	    return 4;
nkeynes@417: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: BRA disp {:  
nkeynes@671:     COUNT_INST(I_BRA);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@590: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995: 	    MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991: 	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995: 	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    sh4_translate_instruction( pc + 2 );
nkeynes@601: 	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601: 	    return 4;
nkeynes@601: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: BRAF Rn {:  
nkeynes@671:     COUNT_INST(I_BRAF);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@995: 	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991: 	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991: 	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    sh4_translate_instruction( pc + 2 );
nkeynes@974: 	    exit_block_newpcset(pc+4);
nkeynes@601: 	    return 4;
nkeynes@601: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: BSR disp {:  
nkeynes@671:     COUNT_INST(I_BSR);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@995: 	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991: 	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@590: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@601: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@991: 	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@995: 	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    sh4_translate_instruction( pc + 2 );
nkeynes@601: 	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601: 	    return 4;
nkeynes@601: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: BSRF Rn {:  
nkeynes@671:     COUNT_INST(I_BSRF);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@995: 	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991: 	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991: 	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@590: 
nkeynes@601: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@417: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    sh4_translate_instruction( pc + 2 );
nkeynes@974: 	    exit_block_newpcset(pc+4);
nkeynes@601: 	    return 4;
nkeynes@601: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: BT disp {:
nkeynes@671:     COUNT_INST(I_BT);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@571: 	sh4vma_t target = disp + pc + 4;
nkeynes@991: 	JF_label( nottaken );
nkeynes@571: 	exit_block_rel(target, pc+2 );
nkeynes@380: 	JMP_TARGET(nottaken);
nkeynes@408: 	return 2;
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: BT/S disp {:
nkeynes@671:     COUNT_INST(I_BTS);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@590: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@995: 	    MOVL_imm32_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@991: 	    JF_label(nottaken);
nkeynes@991: 	    ADDL_imms_r32( disp, REG_EAX );
nkeynes@601: 	    JMP_TARGET(nottaken);
nkeynes@991: 	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@995: 	    MOVL_r32_rbpdisp( REG_EAX, R_NEW_PC );
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    sh4_x86.branch_taken = TRUE;
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    if( sh4_x86.tstate == TSTATE_NONE ) {
nkeynes@991: 		CMPL_imms_rbpdisp( 1, R_T );
nkeynes@601: 		sh4_x86.tstate = TSTATE_E;
nkeynes@601: 	    }
nkeynes@991: 	    JCC_cc_rel32(sh4_x86.tstate^1,0);
nkeynes@991: 	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
nkeynes@991: 
nkeynes@879: 	    int save_tstate = sh4_x86.tstate;
nkeynes@601: 	    sh4_translate_instruction(pc+2);
nkeynes@601: 	    exit_block_rel( disp + pc + 4, pc+4 );
nkeynes@601: 	    // not taken
nkeynes@601: 	    *patch = (xlat_output - ((uint8_t *)patch)) - 4;
nkeynes@879: 	    sh4_x86.tstate = save_tstate;
nkeynes@601: 	    sh4_translate_instruction(pc+2);
nkeynes@601: 	    return 4;
nkeynes@417: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: JMP @Rn {:  
nkeynes@671:     COUNT_INST(I_JMP);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@991: 	load_reg( REG_ECX, Rn );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    sh4_translate_instruction(pc+2);
nkeynes@974: 	    exit_block_newpcset(pc+4);
nkeynes@601: 	    return 4;
nkeynes@601: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: JSR @Rn {:  
nkeynes@671:     COUNT_INST(I_JSR);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@995: 	MOVL_rbpdisp_r32( R_PC, REG_EAX );
nkeynes@991: 	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@991: 	load_reg( REG_ECX, Rn );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@601: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@601: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    sh4_translate_instruction(pc+2);
nkeynes@974: 	    exit_block_newpcset(pc+4);
nkeynes@601: 	    return 4;
nkeynes@601: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: RTE {:  
nkeynes@671:     COUNT_INST(I_RTE);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@408: 	check_priv();
nkeynes@995: 	MOVL_rbpdisp_r32( R_SPC, REG_ECX );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@995: 	MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@995: 	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@590: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@377: 	sh4_x86.fpuen_checked = FALSE;
nkeynes@417: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    sh4_translate_instruction(pc+2);
nkeynes@974: 	    exit_block_newpcset(pc+4);
nkeynes@601: 	    return 4;
nkeynes@601: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: RTS {:  
nkeynes@671:     COUNT_INST(I_RTS);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@995: 	MOVL_rbpdisp_r32( R_PR, REG_ECX );
nkeynes@995: 	MOVL_r32_rbpdisp( REG_ECX, R_NEW_PC );
nkeynes@590: 	sh4_x86.in_delay_slot = DELAY_PC;
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@601: 	if( UNTRANSLATABLE(pc+2) ) {
nkeynes@601: 	    exit_block_emu(pc+2);
nkeynes@601: 	    return 2;
nkeynes@601: 	} else {
nkeynes@601: 	    sh4_translate_instruction(pc+2);
nkeynes@974: 	    exit_block_newpcset(pc+4);
nkeynes@601: 	    return 4;
nkeynes@601: 	}
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: TRAPA #imm {:  
nkeynes@671:     COUNT_INST(I_TRAPA);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@374: 	SLOTILLEGAL();
nkeynes@374:     } else {
nkeynes@995: 	MOVL_imm32_r32( pc+2 - sh4_x86.block_start_pc, REG_ECX );   // 5
nkeynes@991: 	ADDL_r32_rbpdisp( REG_ECX, R_PC );
nkeynes@995: 	MOVL_imm32_r32( imm, REG_EAX );
nkeynes@995: 	CALL1_ptr_r32( sh4_raise_trap, REG_EAX );
nkeynes@417: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@974: 	exit_block_pcset(pc+2);
nkeynes@409: 	sh4_x86.branch_taken = TRUE;
nkeynes@408: 	return 2;
nkeynes@374:     }
nkeynes@374: :}
nkeynes@374: UNDEF {:  
nkeynes@671:     COUNT_INST(I_UNDEF);
nkeynes@374:     if( sh4_x86.in_delay_slot ) {
nkeynes@956: 	exit_block_exc(EXC_SLOT_ILLEGAL, pc-2);    
nkeynes@374:     } else {
nkeynes@956: 	exit_block_exc(EXC_ILLEGAL, pc);    
nkeynes@408: 	return 2;
nkeynes@374:     }
nkeynes@368: :}
nkeynes@374: 
nkeynes@374: CLRMAC {:  
nkeynes@671:     COUNT_INST(I_CLRMAC);
nkeynes@991:     XORL_r32_r32(REG_EAX, REG_EAX);
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@368: :}
nkeynes@374: CLRS {:
nkeynes@671:     COUNT_INST(I_CLRS);
nkeynes@374:     CLC();
nkeynes@991:     SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@368: :}
nkeynes@374: CLRT {:  
nkeynes@671:     COUNT_INST(I_CLRT);
nkeynes@374:     CLC();
nkeynes@374:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@359: :}
nkeynes@374: SETS {:  
nkeynes@671:     COUNT_INST(I_SETS);
nkeynes@374:     STC();
nkeynes@991:     SETCCB_cc_rbpdisp(X86_COND_C, R_S);
nkeynes@872:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@374: SETT {:  
nkeynes@671:     COUNT_INST(I_SETT);
nkeynes@374:     STC();
nkeynes@374:     SETC_t();
nkeynes@417:     sh4_x86.tstate = TSTATE_C;
nkeynes@374: :}
nkeynes@359: 
nkeynes@375: /* Floating point moves */
nkeynes@375: FMOV FRm, FRn {:  
nkeynes@671:     COUNT_INST(I_FMOV1);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_size ) {
nkeynes@991:         load_dr0( REG_EAX, FRm );
nkeynes@991:         load_dr1( REG_ECX, FRm );
nkeynes@991:         store_dr0( REG_EAX, FRn );
nkeynes@991:         store_dr1( REG_ECX, FRn );
nkeynes@901:     } else {
nkeynes@991:         load_fr( REG_EAX, FRm ); // SZ=0 branch
nkeynes@991:         store_fr( REG_EAX, FRn );
nkeynes@375:     }
nkeynes@375: :}
nkeynes@416: FMOV FRm, @Rn {: 
nkeynes@671:     COUNT_INST(I_FMOV2);
nkeynes@559:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@901:     if( sh4_x86.double_size ) {
nkeynes@991:         check_walign64( REG_EAX );
nkeynes@991:         load_dr0( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:         load_reg( REG_EAX, Rn );
nkeynes@991:         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991:         load_dr1( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@375:     } else {
nkeynes@991:         check_walign32( REG_EAX );
nkeynes@991:         load_fr( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@375:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@375: :}
nkeynes@375: FMOV @Rm, FRn {:  
nkeynes@671:     COUNT_INST(I_FMOV5);
nkeynes@559:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@901:     if( sh4_x86.double_size ) {
nkeynes@991:         check_ralign64( REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_dr0( REG_EAX, FRn );
nkeynes@991:         load_reg( REG_EAX, Rm );
nkeynes@991:         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_dr1( REG_EAX, FRn );
nkeynes@375:     } else {
nkeynes@991:         check_ralign32( REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_fr( REG_EAX, FRn );
nkeynes@375:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@375: :}
nkeynes@377: FMOV FRm, @-Rn {:  
nkeynes@671:     COUNT_INST(I_FMOV3);
nkeynes@559:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@901:     if( sh4_x86.double_size ) {
nkeynes@991:         check_walign64( REG_EAX );
nkeynes@991:         LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
nkeynes@991:         load_dr0( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:         load_reg( REG_EAX, Rn );
nkeynes@991:         LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991:         load_dr1( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:         ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
nkeynes@377:     } else {
nkeynes@991:         check_walign32( REG_EAX );
nkeynes@991:         LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991:         load_fr( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:         ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
nkeynes@377:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@416: FMOV @Rm+, FRn {:
nkeynes@671:     COUNT_INST(I_FMOV6);
nkeynes@559:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@901:     if( sh4_x86.double_size ) {
nkeynes@991:         check_ralign64( REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_dr0( REG_EAX, FRn );
nkeynes@991:         load_reg( REG_EAX, Rm );
nkeynes@991:         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_dr1( REG_EAX, FRn );
nkeynes@991:         ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
nkeynes@377:     } else {
nkeynes@991:         check_ralign32( REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_fr( REG_EAX, FRn );
nkeynes@991:         ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@377:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@377: FMOV FRm, @(R0, Rn) {:  
nkeynes@671:     COUNT_INST(I_FMOV4);
nkeynes@559:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901:     if( sh4_x86.double_size ) {
nkeynes@991:         check_walign64( REG_EAX );
nkeynes@991:         load_dr0( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:         load_reg( REG_EAX, Rn );
nkeynes@991:         ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991:         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991:         load_dr1( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@377:     } else {
nkeynes@991:         check_walign32( REG_EAX );
nkeynes@991:         load_fr( REG_EDX, FRm );
nkeynes@991:         MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
nkeynes@377:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@377: FMOV @(R0, Rm), FRn {:  
nkeynes@671:     COUNT_INST(I_FMOV7);
nkeynes@559:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@901:     if( sh4_x86.double_size ) {
nkeynes@991:         check_ralign64( REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_dr0( REG_EAX, FRn );
nkeynes@991:         load_reg( REG_EAX, Rm );
nkeynes@991:         ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
nkeynes@991:         LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_dr1( REG_EAX, FRn );
nkeynes@377:     } else {
nkeynes@991:         check_ralign32( REG_EAX );
nkeynes@991:         MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:         store_fr( REG_EAX, FRn );
nkeynes@377:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@377: FLDI0 FRn {:  /* IFF PR=0 */
nkeynes@671:     COUNT_INST(I_FLDI0);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec == 0 ) {
nkeynes@991:         XORL_r32_r32( REG_EAX, REG_EAX );
nkeynes@991:         store_fr( REG_EAX, FRn );
nkeynes@901:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@377: FLDI1 FRn {:  /* IFF PR=0 */
nkeynes@671:     COUNT_INST(I_FLDI1);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec == 0 ) {
nkeynes@995:         MOVL_imm32_r32( 0x3F800000, REG_EAX );
nkeynes@991:         store_fr( REG_EAX, FRn );
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: 
nkeynes@377: FLOAT FPUL, FRn {:  
nkeynes@671:     COUNT_INST(I_FLOAT);
nkeynes@377:     check_fpuen();
nkeynes@991:     FILD_rbpdisp(R_FPUL);
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         pop_dr( FRn );
nkeynes@901:     } else {
nkeynes@901:         pop_fr( FRn );
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: FTRC FRm, FPUL {:  
nkeynes@671:     COUNT_INST(I_FTRC);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr( FRm );
nkeynes@901:     } else {
nkeynes@901:         push_fr( FRm );
nkeynes@901:     }
nkeynes@995:     MOVP_immptr_rptr( &max_int, REG_ECX );
nkeynes@991:     FILD_r32disp( REG_ECX, 0 );
nkeynes@388:     FCOMIP_st(1);
nkeynes@991:     JNA_label( sat );
nkeynes@995:     MOVP_immptr_rptr( &min_int, REG_ECX );
nkeynes@995:     FILD_r32disp( REG_ECX, 0 );
nkeynes@995:     FCOMIP_st(1);              
nkeynes@995:     JAE_label( sat2 );            
nkeynes@995:     MOVP_immptr_rptr( &save_fcw, REG_EAX );
nkeynes@991:     FNSTCW_r32disp( REG_EAX, 0 );
nkeynes@995:     MOVP_immptr_rptr( &trunc_fcw, REG_EDX );
nkeynes@991:     FLDCW_r32disp( REG_EDX, 0 );
nkeynes@995:     FISTP_rbpdisp(R_FPUL);             
nkeynes@991:     FLDCW_r32disp( REG_EAX, 0 );
nkeynes@995:     JMP_label(end);             
nkeynes@388: 
nkeynes@388:     JMP_TARGET(sat);
nkeynes@388:     JMP_TARGET(sat2);
nkeynes@991:     MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
nkeynes@995:     MOVL_r32_rbpdisp( REG_ECX, R_FPUL );
nkeynes@388:     FPOP_st();
nkeynes@388:     JMP_TARGET(end);
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@377: FLDS FRm, FPUL {:  
nkeynes@671:     COUNT_INST(I_FLDS);
nkeynes@377:     check_fpuen();
nkeynes@991:     load_fr( REG_EAX, FRm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@377: :}
nkeynes@377: FSTS FPUL, FRn {:  
nkeynes@671:     COUNT_INST(I_FSTS);
nkeynes@377:     check_fpuen();
nkeynes@995:     MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991:     store_fr( REG_EAX, FRn );
nkeynes@377: :}
nkeynes@377: FCNVDS FRm, FPUL {:  
nkeynes@671:     COUNT_INST(I_FCNVDS);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr( FRm );
nkeynes@901:         pop_fpul();
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: FCNVSD FPUL, FRn {:  
nkeynes@671:     COUNT_INST(I_FCNVSD);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_fpul();
nkeynes@901:         pop_dr( FRn );
nkeynes@901:     }
nkeynes@377: :}
nkeynes@375: 
nkeynes@359: /* Floating point instructions */
nkeynes@374: FABS FRn {:  
nkeynes@671:     COUNT_INST(I_FABS);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRn);
nkeynes@901:         FABS_st0();
nkeynes@901:         pop_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRn);
nkeynes@901:         FABS_st0();
nkeynes@901:         pop_fr(FRn);
nkeynes@901:     }
nkeynes@374: :}
nkeynes@377: FADD FRm, FRn {:  
nkeynes@671:     COUNT_INST(I_FADD);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRm);
nkeynes@901:         push_dr(FRn);
nkeynes@901:         FADDP_st(1);
nkeynes@901:         pop_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRm);
nkeynes@901:         push_fr(FRn);
nkeynes@901:         FADDP_st(1);
nkeynes@901:         pop_fr(FRn);
nkeynes@901:     }
nkeynes@375: :}
nkeynes@377: FDIV FRm, FRn {:  
nkeynes@671:     COUNT_INST(I_FDIV);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRn);
nkeynes@901:         push_dr(FRm);
nkeynes@901:         FDIVP_st(1);
nkeynes@901:         pop_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRn);
nkeynes@901:         push_fr(FRm);
nkeynes@901:         FDIVP_st(1);
nkeynes@901:         pop_fr(FRn);
nkeynes@901:     }
nkeynes@375: :}
nkeynes@375: FMAC FR0, FRm, FRn {:  
nkeynes@671:     COUNT_INST(I_FMAC);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr( 0 );
nkeynes@901:         push_dr( FRm );
nkeynes@901:         FMULP_st(1);
nkeynes@901:         push_dr( FRn );
nkeynes@901:         FADDP_st(1);
nkeynes@901:         pop_dr( FRn );
nkeynes@901:     } else {
nkeynes@901:         push_fr( 0 );
nkeynes@901:         push_fr( FRm );
nkeynes@901:         FMULP_st(1);
nkeynes@901:         push_fr( FRn );
nkeynes@901:         FADDP_st(1);
nkeynes@901:         pop_fr( FRn );
nkeynes@901:     }
nkeynes@375: :}
nkeynes@375: 
nkeynes@377: FMUL FRm, FRn {:  
nkeynes@671:     COUNT_INST(I_FMUL);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRm);
nkeynes@901:         push_dr(FRn);
nkeynes@901:         FMULP_st(1);
nkeynes@901:         pop_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRm);
nkeynes@901:         push_fr(FRn);
nkeynes@901:         FMULP_st(1);
nkeynes@901:         pop_fr(FRn);
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: FNEG FRn {:  
nkeynes@671:     COUNT_INST(I_FNEG);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRn);
nkeynes@901:         FCHS_st0();
nkeynes@901:         pop_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRn);
nkeynes@901:         FCHS_st0();
nkeynes@901:         pop_fr(FRn);
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: FSRRA FRn {:  
nkeynes@671:     COUNT_INST(I_FSRRA);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec == 0 ) {
nkeynes@901:         FLD1_st0();
nkeynes@901:         push_fr(FRn);
nkeynes@901:         FSQRT_st0();
nkeynes@901:         FDIVP_st(1);
nkeynes@901:         pop_fr(FRn);
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: FSQRT FRn {:  
nkeynes@671:     COUNT_INST(I_FSQRT);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRn);
nkeynes@901:         FSQRT_st0();
nkeynes@901:         pop_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRn);
nkeynes@901:         FSQRT_st0();
nkeynes@901:         pop_fr(FRn);
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: FSUB FRm, FRn {:  
nkeynes@671:     COUNT_INST(I_FSUB);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRn);
nkeynes@901:         push_dr(FRm);
nkeynes@901:         FSUBP_st(1);
nkeynes@901:         pop_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRn);
nkeynes@901:         push_fr(FRm);
nkeynes@901:         FSUBP_st(1);
nkeynes@901:         pop_fr(FRn);
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: 
nkeynes@377: FCMP/EQ FRm, FRn {:  
nkeynes@671:     COUNT_INST(I_FCMPEQ);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRm);
nkeynes@901:         push_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRm);
nkeynes@901:         push_fr(FRn);
nkeynes@901:     }
nkeynes@377:     FCOMIP_st(1);
nkeynes@377:     SETE_t();
nkeynes@377:     FPOP_st();
nkeynes@901:     sh4_x86.tstate = TSTATE_E;
nkeynes@377: :}
nkeynes@377: FCMP/GT FRm, FRn {:  
nkeynes@671:     COUNT_INST(I_FCMPGT);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec ) {
nkeynes@901:         push_dr(FRm);
nkeynes@901:         push_dr(FRn);
nkeynes@901:     } else {
nkeynes@901:         push_fr(FRm);
nkeynes@901:         push_fr(FRn);
nkeynes@901:     }
nkeynes@377:     FCOMIP_st(1);
nkeynes@377:     SETA_t();
nkeynes@377:     FPOP_st();
nkeynes@901:     sh4_x86.tstate = TSTATE_A;
nkeynes@377: :}
nkeynes@377: 
nkeynes@377: FSCA FPUL, FRn {:  
nkeynes@671:     COUNT_INST(I_FSCA);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec == 0 ) {
nkeynes@991:         LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
nkeynes@995:         MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@995:         CALL2_ptr_r32_r32( sh4_fsca, REG_EAX, REG_EDX );
nkeynes@901:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@377: FIPR FVm, FVn {:  
nkeynes@671:     COUNT_INST(I_FIPR);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec == 0 ) {
nkeynes@904:         if( sh4_x86.sse3_enabled ) {
nkeynes@991:             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
nkeynes@991:             MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
nkeynes@903:             HADDPS_xmm_xmm( 4, 4 ); 
nkeynes@903:             HADDPS_xmm_xmm( 4, 4 );
nkeynes@991:             MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
nkeynes@903:         } else {
nkeynes@904:             push_fr( FVm<<2 );
nkeynes@903:             push_fr( FVn<<2 );
nkeynes@903:             FMULP_st(1);
nkeynes@903:             push_fr( (FVm<<2)+1);
nkeynes@903:             push_fr( (FVn<<2)+1);
nkeynes@903:             FMULP_st(1);
nkeynes@903:             FADDP_st(1);
nkeynes@903:             push_fr( (FVm<<2)+2);
nkeynes@903:             push_fr( (FVn<<2)+2);
nkeynes@903:             FMULP_st(1);
nkeynes@903:             FADDP_st(1);
nkeynes@903:             push_fr( (FVm<<2)+3);
nkeynes@903:             push_fr( (FVn<<2)+3);
nkeynes@903:             FMULP_st(1);
nkeynes@903:             FADDP_st(1);
nkeynes@903:             pop_fr( (FVn<<2)+3);
nkeynes@904:         }
nkeynes@901:     }
nkeynes@377: :}
nkeynes@377: FTRV XMTRX, FVn {:  
nkeynes@671:     COUNT_INST(I_FTRV);
nkeynes@377:     check_fpuen();
nkeynes@901:     if( sh4_x86.double_prec == 0 ) {
nkeynes@903:         if( sh4_x86.sse3_enabled ) {
nkeynes@991:             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
nkeynes@991:             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
nkeynes@991:             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
nkeynes@991:             MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
nkeynes@903: 
nkeynes@991:             MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
nkeynes@991:             MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
nkeynes@991:             MOV_xmm_xmm( 4, 6 );
nkeynes@991:             MOV_xmm_xmm( 5, 7 );
nkeynes@903:             MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
nkeynes@903:             MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
nkeynes@903:             MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
nkeynes@903:             MOVHLPS_xmm_xmm( 7, 7 );  // V2 V2 V2 V2
nkeynes@903:             MULPS_xmm_xmm( 0, 4 );
nkeynes@903:             MULPS_xmm_xmm( 1, 5 );
nkeynes@903:             MULPS_xmm_xmm( 2, 6 );
nkeynes@903:             MULPS_xmm_xmm( 3, 7 );
nkeynes@903:             ADDPS_xmm_xmm( 5, 4 );
nkeynes@903:             ADDPS_xmm_xmm( 7, 6 );
nkeynes@903:             ADDPS_xmm_xmm( 6, 4 );
nkeynes@991:             MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
nkeynes@903:         } else {
nkeynes@991:             LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
nkeynes@995:             CALL1_ptr_r32( sh4_ftrv, REG_EAX );
nkeynes@903:         }
nkeynes@901:     }
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@377: 
nkeynes@377: FRCHG {:  
nkeynes@671:     COUNT_INST(I_FRCHG);
nkeynes@377:     check_fpuen();
nkeynes@991:     XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );
nkeynes@995:     CALL_ptr( sh4_switch_fr_banks );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@377: :}
nkeynes@377: FSCHG {:  
nkeynes@671:     COUNT_INST(I_FSCHG);
nkeynes@377:     check_fpuen();
nkeynes@991:     XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);
nkeynes@991:     XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@901:     sh4_x86.double_size = !sh4_x86.double_size;
nkeynes@377: :}
nkeynes@359: 
nkeynes@359: /* Processor control instructions */
nkeynes@368: LDC Rm, SR {:
nkeynes@671:     COUNT_INST(I_LDCSR);
nkeynes@386:     if( sh4_x86.in_delay_slot ) {
nkeynes@386: 	SLOTILLEGAL();
nkeynes@386:     } else {
nkeynes@386: 	check_priv();
nkeynes@991: 	load_reg( REG_EAX, Rm );
nkeynes@995: 	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@386: 	sh4_x86.fpuen_checked = FALSE;
nkeynes@417: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953: 	return 2;
nkeynes@386:     }
nkeynes@368: :}
nkeynes@359: LDC Rm, GBR {: 
nkeynes@671:     COUNT_INST(I_LDC);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_GBR );
nkeynes@359: :}
nkeynes@359: LDC Rm, VBR {:  
nkeynes@671:     COUNT_INST(I_LDC);
nkeynes@386:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_VBR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC Rm, SSR {:  
nkeynes@671:     COUNT_INST(I_LDC);
nkeynes@386:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_SSR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC Rm, SGR {:  
nkeynes@671:     COUNT_INST(I_LDC);
nkeynes@386:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_SGR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC Rm, SPC {:  
nkeynes@671:     COUNT_INST(I_LDC);
nkeynes@386:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_SPC );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC Rm, DBR {:  
nkeynes@671:     COUNT_INST(I_LDC);
nkeynes@386:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_DBR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@374: LDC Rm, Rn_BANK {:  
nkeynes@671:     COUNT_INST(I_LDC);
nkeynes@386:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@374: :}
nkeynes@359: LDC.L @Rm+, GBR {:  
nkeynes@671:     COUNT_INST(I_LDCM);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_GBR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@368: LDC.L @Rm+, SR {:
nkeynes@671:     COUNT_INST(I_LDCSRM);
nkeynes@386:     if( sh4_x86.in_delay_slot ) {
nkeynes@386: 	SLOTILLEGAL();
nkeynes@386:     } else {
nkeynes@559: 	check_priv();
nkeynes@991: 	load_reg( REG_EAX, Rm );
nkeynes@991: 	check_ralign32( REG_EAX );
nkeynes@991: 	MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991: 	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995: 	CALL1_ptr_r32( sh4_write_sr, REG_EAX );
nkeynes@386: 	sh4_x86.fpuen_checked = FALSE;
nkeynes@417: 	sh4_x86.tstate = TSTATE_NONE;
nkeynes@953: 	return 2;
nkeynes@386:     }
nkeynes@359: :}
nkeynes@359: LDC.L @Rm+, VBR {:  
nkeynes@671:     COUNT_INST(I_LDCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_VBR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC.L @Rm+, SSR {:
nkeynes@671:     COUNT_INST(I_LDCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_SSR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC.L @Rm+, SGR {:  
nkeynes@671:     COUNT_INST(I_LDCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_SGR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC.L @Rm+, SPC {:  
nkeynes@671:     COUNT_INST(I_LDCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_SPC );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC.L @Rm+, DBR {:  
nkeynes@671:     COUNT_INST(I_LDCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_DBR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDC.L @Rm+, Rn_BANK {:  
nkeynes@671:     COUNT_INST(I_LDCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@626: LDS Rm, FPSCR {:
nkeynes@673:     COUNT_INST(I_LDSFPSCR);
nkeynes@626:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     CALL1_ptr_r32( sh4_write_fpscr, REG_EAX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@901:     return 2;
nkeynes@359: :}
nkeynes@359: LDS.L @Rm+, FPSCR {:  
nkeynes@673:     COUNT_INST(I_LDSFPSCRM);
nkeynes@626:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     CALL1_ptr_r32( sh4_write_fpscr, REG_EAX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@901:     return 2;
nkeynes@359: :}
nkeynes@359: LDS Rm, FPUL {:  
nkeynes@671:     COUNT_INST(I_LDS);
nkeynes@626:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@359: :}
nkeynes@359: LDS.L @Rm+, FPUL {:  
nkeynes@671:     COUNT_INST(I_LDSM);
nkeynes@626:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_FPUL );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDS Rm, MACH {: 
nkeynes@671:     COUNT_INST(I_LDS);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@359: :}
nkeynes@359: LDS.L @Rm+, MACH {:  
nkeynes@671:     COUNT_INST(I_LDSM);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACH );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDS Rm, MACL {:  
nkeynes@671:     COUNT_INST(I_LDS);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@359: :}
nkeynes@359: LDS.L @Rm+, MACL {:  
nkeynes@671:     COUNT_INST(I_LDSM);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_MACL );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: LDS Rm, PR {:  
nkeynes@671:     COUNT_INST(I_LDS);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@359: :}
nkeynes@359: LDS.L @Rm+, PR {:  
nkeynes@671:     COUNT_INST(I_LDSM);
nkeynes@991:     load_reg( REG_EAX, Rm );
nkeynes@991:     check_ralign32( REG_EAX );
nkeynes@991:     MEM_READ_LONG( REG_EAX, REG_EAX );
nkeynes@991:     ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
nkeynes@995:     MOVL_r32_rbpdisp( REG_EAX, R_PR );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@550: LDTLB {:  
nkeynes@671:     COUNT_INST(I_LDTLB);
nkeynes@995:     CALL_ptr( MMU_ldtlb );
nkeynes@875:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@550: :}
nkeynes@671: OCBI @Rn {:
nkeynes@671:     COUNT_INST(I_OCBI);
nkeynes@671: :}
nkeynes@671: OCBP @Rn {:
nkeynes@671:     COUNT_INST(I_OCBP);
nkeynes@671: :}
nkeynes@671: OCBWB @Rn {:
nkeynes@671:     COUNT_INST(I_OCBWB);
nkeynes@671: :}
nkeynes@374: PREF @Rn {:
nkeynes@671:     COUNT_INST(I_PREF);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     MEM_PREFETCH( REG_EAX );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@374: :}
nkeynes@388: SLEEP {: 
nkeynes@671:     COUNT_INST(I_SLEEP);
nkeynes@388:     check_priv();
nkeynes@995:     CALL_ptr( sh4_sleep );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@590:     sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@408:     return 2;
nkeynes@388: :}
nkeynes@386: STC SR, Rn {:
nkeynes@671:     COUNT_INST(I_STCSR);
nkeynes@386:     check_priv();
nkeynes@995:     CALL_ptr(sh4_read_sr);
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC GBR, Rn {:  
nkeynes@671:     COUNT_INST(I_STC);
nkeynes@995:     MOVL_rbpdisp_r32( R_GBR, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: STC VBR, Rn {:  
nkeynes@671:     COUNT_INST(I_STC);
nkeynes@386:     check_priv();
nkeynes@995:     MOVL_rbpdisp_r32( R_VBR, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC SSR, Rn {:  
nkeynes@671:     COUNT_INST(I_STC);
nkeynes@386:     check_priv();
nkeynes@995:     MOVL_rbpdisp_r32( R_SSR, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC SPC, Rn {:  
nkeynes@671:     COUNT_INST(I_STC);
nkeynes@386:     check_priv();
nkeynes@995:     MOVL_rbpdisp_r32( R_SPC, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC SGR, Rn {:  
nkeynes@671:     COUNT_INST(I_STC);
nkeynes@386:     check_priv();
nkeynes@995:     MOVL_rbpdisp_r32( R_SGR, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC DBR, Rn {:  
nkeynes@671:     COUNT_INST(I_STC);
nkeynes@386:     check_priv();
nkeynes@995:     MOVL_rbpdisp_r32( R_DBR, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@374: STC Rm_BANK, Rn {:
nkeynes@671:     COUNT_INST(I_STC);
nkeynes@386:     check_priv();
nkeynes@995:     MOVL_rbpdisp_r32( REG_OFFSET(r_bank[Rm_BANK]), REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@374: STC.L SR, @-Rn {:
nkeynes@671:     COUNT_INST(I_STCSRM);
nkeynes@559:     check_priv();
nkeynes@995:     CALL_ptr( sh4_read_sr );
nkeynes@991:     MOVL_r32_r32( REG_EAX, REG_EDX );
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC.L VBR, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_VBR, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC.L SSR, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_SSR, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@416: STC.L SPC, @-Rn {:
nkeynes@671:     COUNT_INST(I_STCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_SPC, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC.L SGR, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_SGR, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STC.L DBR, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_DBR, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@374: STC.L Rm_BANK, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STCM);
nkeynes@559:     check_priv();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( REG_OFFSET(r_bank[Rm_BANK]), REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@374: :}
nkeynes@359: STC.L GBR, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STCM);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_GBR, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STS FPSCR, Rn {:  
nkeynes@673:     COUNT_INST(I_STSFPSCR);
nkeynes@626:     check_fpuen();
nkeynes@995:     MOVL_rbpdisp_r32( R_FPSCR, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: STS.L FPSCR, @-Rn {:  
nkeynes@673:     COUNT_INST(I_STSFPSCRM);
nkeynes@626:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_FPSCR, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STS FPUL, Rn {:  
nkeynes@671:     COUNT_INST(I_STS);
nkeynes@626:     check_fpuen();
nkeynes@995:     MOVL_rbpdisp_r32( R_FPUL, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: STS.L FPUL, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STSM);
nkeynes@626:     check_fpuen();
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_FPUL, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STS MACH, Rn {:  
nkeynes@671:     COUNT_INST(I_STS);
nkeynes@995:     MOVL_rbpdisp_r32( R_MACH, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: STS.L MACH, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STSM);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_MACH, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STS MACL, Rn {:  
nkeynes@671:     COUNT_INST(I_STS);
nkeynes@995:     MOVL_rbpdisp_r32( R_MACL, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: STS.L MACL, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STSM);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_MACL, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: STS PR, Rn {:  
nkeynes@671:     COUNT_INST(I_STS);
nkeynes@995:     MOVL_rbpdisp_r32( R_PR, REG_EAX );
nkeynes@991:     store_reg( REG_EAX, Rn );
nkeynes@359: :}
nkeynes@359: STS.L PR, @-Rn {:  
nkeynes@671:     COUNT_INST(I_STSM);
nkeynes@991:     load_reg( REG_EAX, Rn );
nkeynes@991:     check_walign32( REG_EAX );
nkeynes@991:     ADDL_imms_r32( -4, REG_EAX );
nkeynes@995:     MOVL_rbpdisp_r32( R_PR, REG_EDX );
nkeynes@991:     MEM_WRITE_LONG( REG_EAX, REG_EDX );
nkeynes@991:     ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
nkeynes@417:     sh4_x86.tstate = TSTATE_NONE;
nkeynes@359: :}
nkeynes@359: 
nkeynes@671: NOP {: 
nkeynes@671:     COUNT_INST(I_NOP);
nkeynes@671:     /* Do nothing. Well, we could emit an 0x90, but what would really be the point? */ 
nkeynes@671: :}
nkeynes@359: %%
nkeynes@590:     sh4_x86.in_delay_slot = DELAY_NONE;
nkeynes@359:     return 0;
nkeynes@359: }
nkeynes@995: 
nkeynes@995: 
nkeynes@995: /**
nkeynes@995:  * The unwind methods only work if we compiled with DWARF2 frame information
nkeynes@995:  * (ie -fexceptions), otherwise we have to use the direct frame scan.
nkeynes@995:  */
nkeynes@995: #ifdef HAVE_EXCEPTIONS
nkeynes@995: #include <unwind.h>
nkeynes@995: 
nkeynes@995: struct UnwindInfo {
nkeynes@995:     uintptr_t block_start;
nkeynes@995:     uintptr_t block_end;
nkeynes@995:     void *pc;
nkeynes@995: };
nkeynes@995: 
nkeynes@995: static _Unwind_Reason_Code xlat_check_frame( struct _Unwind_Context *context, void *arg )
nkeynes@995: {
nkeynes@995:     struct UnwindInfo *info = arg;
nkeynes@995:     void *pc = (void *)_Unwind_GetIP(context);
nkeynes@995:     if( ((uintptr_t)pc) >= info->block_start && ((uintptr_t)pc) < info->block_end ) {
nkeynes@995:         info->pc = pc;
nkeynes@995:         return _URC_NORMAL_STOP;
nkeynes@995:     }
nkeynes@995:     return _URC_NO_REASON;
nkeynes@995: }
nkeynes@995: 
nkeynes@995: void *xlat_get_native_pc( void *code, uint32_t code_size )
nkeynes@995: {
nkeynes@995:     struct _Unwind_Exception exc;
nkeynes@995:     struct UnwindInfo info;
nkeynes@995: 
nkeynes@995:     info.pc = NULL;
nkeynes@995:     info.block_start = (uintptr_t)code;
nkeynes@995:     info.block_end = info.block_start + code_size;
nkeynes@995:     void *result = NULL;
nkeynes@995:     _Unwind_Backtrace( xlat_check_frame, &info );
nkeynes@995:     return info.pc;
nkeynes@995: }
nkeynes@995: #else
nkeynes@995: /* Assume this is an ia32 build - amd64 should always have dwarf information */
nkeynes@995: void *xlat_get_native_pc( void *code, uint32_t code_size )
nkeynes@995: {
nkeynes@995:     void *result = NULL;
nkeynes@995:     asm(
nkeynes@995:         "mov %%ebp, %%eax\n\t"
nkeynes@995:         "mov $0x8, %%ecx\n\t"
nkeynes@995:         "mov %1, %%edx\n"
nkeynes@995:         "frame_loop: test %%eax, %%eax\n\t"
nkeynes@995:         "je frame_not_found\n\t"
nkeynes@995:         "cmp (%%eax), %%edx\n\t"
nkeynes@995:         "je frame_found\n\t"
nkeynes@995:         "sub $0x1, %%ecx\n\t"
nkeynes@995:         "je frame_not_found\n\t"
nkeynes@995:         "movl (%%eax), %%eax\n\t"
nkeynes@995:         "jmp frame_loop\n"
nkeynes@995:         "frame_found: movl 0x4(%%eax), %0\n"
nkeynes@995:         "frame_not_found:"
nkeynes@995:         : "=r" (result)
nkeynes@995:         : "r" (((uint8_t *)&sh4r) + 128 )
nkeynes@995:         : "eax", "ecx", "edx" );
nkeynes@995:     return result;
nkeynes@995: }
nkeynes@995: #endif
nkeynes@995: