nkeynes@555: .section .text nkeynes@555: .include "sh4/inc.s" nkeynes@555: ! nkeynes@555: ! Test for correct UTLB operation. nkeynes@555: ! nkeynes@555: ! Note we don't test triggering a TLB multiple-hit exception - it's a reset nkeynes@555: ! rather than a regular exception. nkeynes@555: nkeynes@555: .global _test_tlb nkeynes@555: _test_tlb: nkeynes@555: start_test nkeynes@555: nkeynes@555: ! Turn on AT, and flush the current TLB (if any) nkeynes@555: ! Initialize to SV=0, SQMD=0, URB=URC=LRUI=0 nkeynes@555: mov.l test_tlb_mmucr, r0 nkeynes@555: mov #5, r1 nkeynes@555: mov.l r1, @r0 nkeynes@555: nkeynes@555: ! Privileged mode tests first (much easier) nkeynes@555: add #1, r12 nkeynes@555: mov.l test_tlb1_pteh, r1 nkeynes@555: mov.l test_tlb_pteh, r2 nkeynes@555: mov.l r1, @r2 nkeynes@555: mov.l test_tlb1_ptel, r1 nkeynes@555: mov.l test_tlb_ptel, r2 nkeynes@555: mov.l r1, @r2 nkeynes@555: ldtlb nkeynes@555: nkeynes@555: ! Simple read nkeynes@555: mov.l test_tlb1_direct, r3 nkeynes@555: mov #42, r2 nkeynes@555: mov.l r2, @r3 nkeynes@555: mov.l test_tlb1_mmu, r0 nkeynes@555: mov.l @r0, r1 nkeynes@555: cmp/eq r1, r2 nkeynes@555: bt test_tlb_2 nkeynes@555: fail test_tlb_str_k nkeynes@555: bra test_tlb_2 nkeynes@555: nop nkeynes@555: test_tlb1_pteh: nkeynes@555: .long 0x12345012 nkeynes@555: test_tlb1_ptel: nkeynes@555: .long 0x005F8120 nkeynes@555: nkeynes@555: test_tlb_2: nkeynes@555: ! Trigger an initial-page-write exception nkeynes@555: add #1, r12 nkeynes@555: expect_exc 0x00000080 nkeynes@555: mov.l test_tlb1_mmu, r0 nkeynes@555: test_tlb2_exc: nkeynes@555: mov.l r0, @r0 nkeynes@555: assert_tlb_exc_caught test_tlb_str_k test_tlb2_exc test_tlb1_mmu nkeynes@555: nkeynes@555: test_tlb_3: nkeynes@555: ! Trigger a missing page read exception by invalidation nkeynes@555: add #1, r12 nkeynes@555: mov.l test_tlb3_addr, r1 nkeynes@555: mov.l test_tlb3_data, r2 nkeynes@555: mov.l r2, @r1 nkeynes@555: nkeynes@555: expect_exc 0x00000040 nkeynes@555: mov.l test_tlb1_mmu, r0 nkeynes@555: test_tlb3_exc: nkeynes@555: mov.l @r0, r2 nkeynes@555: assert_tlb_exc_caught test_tlb_str_k, test_tlb3_exc, test_tlb1_mmu nkeynes@555: bra test_tlb_4 nkeynes@555: nop nkeynes@555: nkeynes@555: test_tlb3_addr: nkeynes@555: .long 0xF6000F80 nkeynes@555: test_tlb3_data: nkeynes@555: .long 0x12345212 nkeynes@555: nkeynes@555: test_tlb_4: nkeynes@555: ! Test missing page write exception on the same page nkeynes@555: add #1, r12 nkeynes@555: expect_exc 0x00000060 nkeynes@555: mov.l test_tlb1_mmu, r0 nkeynes@555: test_tlb4_exc: nkeynes@555: mov.l r2, @r0 nkeynes@555: assert_tlb_exc_caught test_tlb_str_k, test_tlb4_exc, test_tlb1_mmu nkeynes@555: nkeynes@555: test_tlb_5: ! Test initial write exception nkeynes@555: add #1, r12 nkeynes@555: nkeynes@555: mov.l test_tlb5_addr, r1 nkeynes@555: mov.l test_tlb5_data, r2 nkeynes@555: mov.l r2, @r1 nkeynes@555: nkeynes@555: expect_exc 0x00000080 nkeynes@555: mov.l test_tlb1_mmu, r0 nkeynes@555: mov #63, r3 nkeynes@555: test_tlb5_exc: nkeynes@555: mov.l r3, @r0 nkeynes@555: assert_tlb_exc_caught test_tlb_str_k, test_tlb5_exc, test_tlb1_mmu nkeynes@555: mov.l test_tlb1_direct, r3 nkeynes@555: mov.l @r3, r4 nkeynes@555: mov #42, r2 nkeynes@555: cmp/eq r2, r4 nkeynes@555: bf test_tlb5_fail nkeynes@555: mov.l test_tlb1_mmu, r0 nkeynes@555: mov.l @r0, r3 nkeynes@555: cmp/eq r2, r3 nkeynes@555: bt test_tlb_6 nkeynes@555: test_tlb5_fail: nkeynes@555: fail test_tlb_str_k nkeynes@976: bra test_tlb_6 nkeynes@976: nop nkeynes@555: nkeynes@555: test_tlb5_addr: nkeynes@586: .long 0xF6000000 nkeynes@555: test_tlb5_data: nkeynes@555: .long 0x12345112 nkeynes@555: nkeynes@555: test_tlb_6:! Test successful write. nkeynes@555: add #1, r12 nkeynes@555: nkeynes@555: mov.l test_tlb6_addr, r1 nkeynes@555: mov.l test_tlb6_data, r2 nkeynes@555: mov.l r2, @r1 nkeynes@555: nkeynes@555: mov.l test_tlb1_mmu, r0 nkeynes@555: mov #77, r3 nkeynes@555: mov.l r3, @r0 nkeynes@555: mov.l test_tlb1_direct, r1 nkeynes@555: mov.l @r1, r2 nkeynes@555: cmp/eq r2, r3 nkeynes@555: bt test_tlb_7 nkeynes@555: fail test_tlb_str_k nkeynes@555: bra test_tlb_7 nkeynes@555: nop nkeynes@555: nkeynes@555: test_tlb_7: nkeynes@555: bra test_tlb_end nkeynes@555: nop nkeynes@555: nkeynes@555: test_tlb6_addr: nkeynes@555: .long 0xF6000F80 nkeynes@555: test_tlb6_data: nkeynes@555: .long 0x12345312 nkeynes@555: nkeynes@555: nkeynes@555: test_tlb1_mmu: nkeynes@555: .long 0x12345040 nkeynes@555: test_tlb1_direct: nkeynes@555: .long 0xA05F8040 ! Display border colour nkeynes@555: nkeynes@555: test_tlb_end: nkeynes@555: xor r0, r0 nkeynes@555: mov.l test_tlb_mmucr, r1 nkeynes@555: mov.l r0, @r1 nkeynes@555: nkeynes@555: end_test test_tlb_str_k nkeynes@555: nkeynes@555: test_tlb_mmucr: nkeynes@555: .long 0xFF000010 nkeynes@555: test_tlb_pteh: nkeynes@555: .long 0xFF000000 nkeynes@555: test_tlb_ptel: nkeynes@555: .long 0xFF000004 nkeynes@555: test_tlb_tea: nkeynes@555: .long 0xFF00000C nkeynes@555: test_tlb_str: nkeynes@555: .string "TLB" nkeynes@555: .align 4 nkeynes@555: test_tlb_str_k: nkeynes@555: .long test_tlb_str