nkeynes@23: /** nkeynes@32: * $Id: sh4core.c,v 1.12 2005-12-26 03:10:23 nkeynes Exp $ nkeynes@23: * nkeynes@23: * SH4 emulation core, and parent module for all the SH4 peripheral nkeynes@23: * modules. nkeynes@23: * nkeynes@23: * Copyright (c) 2005 Nathan Keynes. nkeynes@23: * nkeynes@23: * This program is free software; you can redistribute it and/or modify nkeynes@23: * it under the terms of the GNU General Public License as published by nkeynes@23: * the Free Software Foundation; either version 2 of the License, or nkeynes@23: * (at your option) any later version. nkeynes@23: * nkeynes@23: * This program is distributed in the hope that it will be useful, nkeynes@23: * but WITHOUT ANY WARRANTY; without even the implied warranty of nkeynes@23: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the nkeynes@23: * GNU General Public License for more details. nkeynes@23: */ nkeynes@23: nkeynes@1: #include nkeynes@1: #include "dream.h" nkeynes@15: #include "modules.h" nkeynes@1: #include "sh4core.h" nkeynes@1: #include "sh4mmio.h" nkeynes@1: #include "mem.h" nkeynes@23: #include "clock.h" nkeynes@1: #include "intc.h" nkeynes@1: nkeynes@27: /* CPU-generated exception code/vector pairs */ nkeynes@27: #define EXC_POWER_RESET 0x000 /* vector special */ nkeynes@27: #define EXC_MANUAL_RESET 0x020 nkeynes@27: #define EXC_SLOT_ILLEGAL 0x1A0 nkeynes@27: #define EXC_ILLEGAL 0x180 nkeynes@27: #define EXV_ILLEGAL 0x100 nkeynes@27: #define EXC_TRAP 0x160 nkeynes@27: #define EXV_TRAP 0x100 nkeynes@27: #define EXC_FPDISABLE 0x800 nkeynes@27: #define EXV_FPDISABLE 0x100 nkeynes@27: nkeynes@23: uint32_t sh4_freq = SH4_BASE_RATE; nkeynes@23: uint32_t sh4_bus_freq = SH4_BASE_RATE; nkeynes@23: uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2; nkeynes@23: nkeynes@30: uint32_t sh4_cpu_period = 1000 / SH4_BASE_RATE; /* in nanoseconds */ nkeynes@30: uint32_t sh4_bus_period = 1000 / SH4_BASE_RATE; nkeynes@30: uint32_t sh4_peripheral_period = 2000 / SH4_BASE_RATE; nkeynes@30: nkeynes@23: /********************** SH4 Module Definition ****************************/ nkeynes@23: nkeynes@23: void sh4_init( void ); nkeynes@23: void sh4_reset( void ); nkeynes@30: uint32_t sh4_run_slice( uint32_t ); nkeynes@23: void sh4_start( void ); nkeynes@23: void sh4_stop( void ); nkeynes@23: void sh4_save_state( FILE *f ); nkeynes@23: int sh4_load_state( FILE *f ); nkeynes@16: nkeynes@15: struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, nkeynes@23: NULL, sh4_run_slice, sh4_stop, nkeynes@23: sh4_save_state, sh4_load_state }; nkeynes@15: nkeynes@1: struct sh4_registers sh4r; nkeynes@1: nkeynes@1: void sh4_init(void) nkeynes@1: { nkeynes@1: register_io_regions( mmio_list_sh4mmio ); nkeynes@10: mmu_init(); nkeynes@27: sh4_reset(); nkeynes@1: } nkeynes@1: nkeynes@1: void sh4_reset(void) nkeynes@1: { nkeynes@19: /* zero everything out, for the sake of having a consistent state. */ nkeynes@19: memset( &sh4r, 0, sizeof(sh4r) ); nkeynes@27: nkeynes@27: /* Resume running if we were halted */ nkeynes@27: sh4r.sh4_state = SH4_STATE_RUNNING; nkeynes@27: nkeynes@1: sh4r.pc = 0xA0000000; nkeynes@1: sh4r.new_pc= 0xA0000002; nkeynes@1: sh4r.vbr = 0x00000000; nkeynes@1: sh4r.fpscr = 0x00040001; nkeynes@1: sh4r.sr = 0x700000F0; nkeynes@27: nkeynes@27: /* Mem reset will do this, but if we want to reset _just_ the SH4... */ nkeynes@27: MMIO_WRITE( MMU, EXPEVT, EXC_POWER_RESET ); nkeynes@27: nkeynes@27: /* Peripheral modules */ nkeynes@1: intc_reset(); nkeynes@32: SCIF_reset(); nkeynes@1: } nkeynes@1: nkeynes@30: uint32_t sh4_run_slice( uint32_t nanosecs ) nkeynes@1: { nkeynes@30: int target = sh4r.icount + nanosecs / sh4_cpu_period; nkeynes@27: int start = sh4r.icount; nkeynes@23: int i; nkeynes@23: nkeynes@27: if( sh4r.sh4_state != SH4_STATE_RUNNING ) { nkeynes@27: if( sh4r.int_pending != 0 ) nkeynes@27: sh4r.sh4_state = SH4_STATE_RUNNING;; nkeynes@23: } nkeynes@27: nkeynes@27: while( sh4r.icount < target && sh4r.sh4_state == SH4_STATE_RUNNING ) { nkeynes@27: sh4r.icount++; nkeynes@27: if( !sh4_execute_instruction() ) nkeynes@27: break; nkeynes@27: } nkeynes@30: nkeynes@30: /* If we aborted early, but the cpu is still technically running, nkeynes@30: * we're doing a hard abort - cut the timeslice back to what we nkeynes@30: * actually executed nkeynes@30: */ nkeynes@30: if( target != sh4r.icount && sh4r.sh4_state == SH4_STATE_RUNNING ) { nkeynes@27: /* Halted - compute time actually executed */ nkeynes@30: nanosecs = (sh4r.icount - start) * sh4_cpu_period; nkeynes@27: } nkeynes@27: if( sh4r.sh4_state != SH4_STATE_STANDBY ) { nkeynes@30: TMU_run_slice( nanosecs ); nkeynes@30: SCIF_run_slice( nanosecs ); nkeynes@27: } nkeynes@30: return nanosecs; nkeynes@1: } nkeynes@1: nkeynes@1: void sh4_stop(void) nkeynes@1: { nkeynes@27: nkeynes@1: } nkeynes@1: nkeynes@23: void sh4_save_state( FILE *f ) nkeynes@16: { nkeynes@16: fwrite( &sh4r, sizeof(sh4r), 1, f ); nkeynes@23: SCIF_save_state( f ); nkeynes@16: } nkeynes@16: nkeynes@23: int sh4_load_state( FILE * f ) nkeynes@16: { nkeynes@18: fread( &sh4r, sizeof(sh4r), 1, f ); nkeynes@23: return SCIF_load_state( f ); nkeynes@16: } nkeynes@16: nkeynes@23: /********************** SH4 emulation core ****************************/ nkeynes@23: nkeynes@23: void sh4_set_pc( int pc ) nkeynes@23: { nkeynes@23: sh4r.pc = pc; nkeynes@23: sh4r.new_pc = pc+2; nkeynes@23: } nkeynes@23: nkeynes@23: void sh4_set_breakpoint( uint32_t pc, int type ) nkeynes@23: { nkeynes@23: nkeynes@23: } nkeynes@23: nkeynes@27: #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", sh4r.pc, ir ); RAISE( EXC_ILLEGAL, EXV_ILLEGAL ); }while(0) nkeynes@27: #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", sh4r.pc, ir ); dreamcast_stop(); return FALSE; }while(0) nkeynes@1: nkeynes@1: #define RAISE( x, v ) do{ \ nkeynes@1: if( sh4r.vbr == 0 ) { \ nkeynes@1: ERROR( "%08X: VBR not initialized while raising exception %03X, halting", sh4r.pc, x ); \ nkeynes@1: sh4_stop(); \ nkeynes@1: } else { \ nkeynes@1: sh4r.spc = sh4r.pc + 2; \ nkeynes@1: sh4r.ssr = sh4_read_sr(); \ nkeynes@1: sh4r.sgr = sh4r.r[15]; \ nkeynes@1: MMIO_WRITE(MMU,EXPEVT,x); \ nkeynes@1: sh4r.pc = sh4r.vbr + v; \ nkeynes@1: sh4r.new_pc = sh4r.pc + 2; \ nkeynes@1: sh4_load_sr( sh4r.ssr |SR_MD|SR_BL|SR_RB ); \ nkeynes@1: } \ nkeynes@27: return TRUE; } while(0) nkeynes@1: nkeynes@10: #define MEM_READ_BYTE( addr ) sh4_read_byte(addr) nkeynes@10: #define MEM_READ_WORD( addr ) sh4_read_word(addr) nkeynes@10: #define MEM_READ_LONG( addr ) sh4_read_long(addr) nkeynes@10: #define MEM_WRITE_BYTE( addr, val ) sh4_write_byte(addr, val) nkeynes@10: #define MEM_WRITE_WORD( addr, val ) sh4_write_word(addr, val) nkeynes@10: #define MEM_WRITE_LONG( addr, val ) sh4_write_long(addr, val) nkeynes@1: nkeynes@1: #define MEM_FP_READ( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \ nkeynes@10: ((uint32_t *)FR)[(reg)&0xE0] = sh4_read_long(addr); \ nkeynes@10: ((uint32_t *)FR)[(reg)|1] = sh4_read_long(addr+4); \ nkeynes@10: } else ((uint32_t *)FR)[reg] = sh4_read_long(addr) nkeynes@1: nkeynes@1: #define MEM_FP_WRITE( addr, reg ) if( IS_FPU_DOUBLESIZE() ) { \ nkeynes@10: sh4_write_long( addr, ((uint32_t *)FR)[(reg)&0xE0] ); \ nkeynes@10: sh4_write_long( addr+4, ((uint32_t *)FR)[(reg)|1] ); \ nkeynes@10: } else sh4_write_long( addr, ((uint32_t *)FR)[reg] ) nkeynes@1: nkeynes@1: #define FP_WIDTH (IS_FPU_DOUBLESIZE() ? 8 : 4) nkeynes@1: nkeynes@1: #define CHECK( x, c, v ) if( !x ) RAISE( c, v ) nkeynes@1: #define CHECKPRIV() CHECK( IS_SH4_PRIVMODE(), EXC_ILLEGAL, EXV_ILLEGAL ) nkeynes@1: #define CHECKFPUEN() CHECK( IS_FPU_ENABLED(), EXC_FPDISABLE, EXV_FPDISABLE ) nkeynes@1: #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); sh4_stop(); return; } nkeynes@2: #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) { RAISE(EXC_SLOT_ILLEGAL,EXV_ILLEGAL); } nkeynes@1: nkeynes@1: static void sh4_switch_banks( ) nkeynes@1: { nkeynes@1: uint32_t tmp[8]; nkeynes@1: nkeynes@1: memcpy( tmp, sh4r.r, sizeof(uint32_t)*8 ); nkeynes@1: memcpy( sh4r.r, sh4r.r_bank, sizeof(uint32_t)*8 ); nkeynes@1: memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 ); nkeynes@1: } nkeynes@1: nkeynes@1: static void sh4_load_sr( uint32_t newval ) nkeynes@1: { nkeynes@1: if( (newval ^ sh4r.sr) & SR_RB ) nkeynes@1: sh4_switch_banks(); nkeynes@1: sh4r.sr = newval; nkeynes@1: sh4r.t = (newval&SR_T) ? 1 : 0; nkeynes@1: sh4r.s = (newval&SR_S) ? 1 : 0; nkeynes@1: sh4r.m = (newval&SR_M) ? 1 : 0; nkeynes@1: sh4r.q = (newval&SR_Q) ? 1 : 0; nkeynes@1: intc_mask_changed(); nkeynes@1: } nkeynes@1: nkeynes@1: static uint32_t sh4_read_sr( void ) nkeynes@1: { nkeynes@1: /* synchronize sh4r.sr with the various bitflags */ nkeynes@1: sh4r.sr &= SR_MQSTMASK; nkeynes@1: if( sh4r.t ) sh4r.sr |= SR_T; nkeynes@1: if( sh4r.s ) sh4r.sr |= SR_S; nkeynes@1: if( sh4r.m ) sh4r.sr |= SR_M; nkeynes@1: if( sh4r.q ) sh4r.sr |= SR_Q; nkeynes@1: return sh4r.sr; nkeynes@1: } nkeynes@1: /* function for external use */ nkeynes@1: void sh4_raise_exception( int code, int vector ) nkeynes@1: { nkeynes@1: RAISE(code, vector); nkeynes@1: } nkeynes@1: nkeynes@1: static void sh4_accept_interrupt( void ) nkeynes@1: { nkeynes@1: uint32_t code = intc_accept_interrupt(); nkeynes@1: sh4r.ssr = sh4_read_sr(); nkeynes@1: sh4r.spc = sh4r.pc; nkeynes@1: sh4r.sgr = sh4r.r[15]; nkeynes@1: sh4_load_sr( sh4r.ssr|SR_BL|SR_MD|SR_RB ); nkeynes@1: MMIO_WRITE( MMU, INTEVT, code ); nkeynes@1: sh4r.pc = sh4r.vbr + 0x600; nkeynes@1: sh4r.new_pc = sh4r.pc + 2; nkeynes@2: WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc ); nkeynes@1: } nkeynes@1: nkeynes@27: gboolean sh4_execute_instruction( void ) nkeynes@1: { nkeynes@2: int pc; nkeynes@2: unsigned short ir; nkeynes@1: uint32_t tmp; nkeynes@1: uint64_t tmpl; nkeynes@1: nkeynes@1: #define R0 sh4r.r[0] nkeynes@1: #define FR0 (FR[0]) nkeynes@1: #define RN(ir) sh4r.r[(ir&0x0F00)>>8] nkeynes@1: #define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4] nkeynes@1: #define RM(ir) sh4r.r[(ir&0x00F0)>>4] nkeynes@1: #define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */ nkeynes@1: #define DISP8(ir) (ir&0x00FF) nkeynes@1: #define PCDISP8(ir) SIGNEXT8(ir&0x00FF) nkeynes@1: #define IMM8(ir) SIGNEXT8(ir&0x00FF) nkeynes@1: #define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */ nkeynes@1: #define DISP12(ir) SIGNEXT12(ir&0x0FFF) nkeynes@2: #define FVN(ir) ((ir&0x0C00)>>8) nkeynes@2: #define FVM(ir) ((ir&0x0300)>>6) nkeynes@1: #define FRN(ir) (FR[(ir&0x0F00)>>8]) nkeynes@1: #define FRM(ir) (FR[(ir&0x00F0)>>4]) nkeynes@1: #define FRNi(ir) (((uint32_t *)FR)[(ir&0x0F00)>>8]) nkeynes@1: #define FRMi(ir) (((uint32_t *)FR)[(ir&0x00F0)>>4]) nkeynes@1: #define DRN(ir) (((double *)FR)[(ir&0x0E00)>>9]) nkeynes@1: #define DRM(ir) (((double *)FR)[(ir&0x00E0)>>5]) nkeynes@1: #define DRNi(ir) (((uint64_t *)FR)[(ir&0x0E00)>>9]) nkeynes@1: #define DRMi(ir) (((uint64_t *)FR)[(ir&0x00E0)>>5]) nkeynes@1: #define FRNn(ir) ((ir&0x0F00)>>8) nkeynes@1: #define FRMn(ir) ((ir&0x00F0)>>4) nkeynes@1: #define FPULf *((float *)&sh4r.fpul) nkeynes@1: #define FPULi (sh4r.fpul) nkeynes@1: nkeynes@2: if( SH4_INT_PENDING() ) nkeynes@2: sh4_accept_interrupt(); nkeynes@1: nkeynes@2: pc = sh4r.pc; nkeynes@2: ir = MEM_READ_WORD(pc); nkeynes@1: sh4r.icount++; nkeynes@1: nkeynes@1: switch( (ir&0xF000)>>12 ) { nkeynes@1: case 0: /* 0000nnnnmmmmxxxx */ nkeynes@1: switch( ir&0x000F ) { nkeynes@1: case 2: nkeynes@1: switch( (ir&0x00F0)>>4 ) { nkeynes@1: case 0: /* STC SR, Rn */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) = sh4_read_sr(); nkeynes@1: break; nkeynes@1: case 1: /* STC GBR, Rn */ nkeynes@1: RN(ir) = sh4r.gbr; nkeynes@1: break; nkeynes@1: case 2: /* STC VBR, Rn */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) = sh4r.vbr; nkeynes@1: break; nkeynes@1: case 3: /* STC SSR, Rn */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) = sh4r.ssr; nkeynes@1: break; nkeynes@1: case 4: /* STC SPC, Rn */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) = sh4r.spc; nkeynes@1: break; nkeynes@1: case 8: case 9: case 10: case 11: case 12: case 13: nkeynes@1: case 14: case 15:/* STC Rm_bank, Rn */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) = RN_BANK(ir); nkeynes@1: break; nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 3: nkeynes@1: switch( (ir&0x00F0)>>4 ) { nkeynes@1: case 0: /* BSRF Rn */ nkeynes@1: CHECKDEST( pc + 4 + RN(ir) ); nkeynes@2: CHECKSLOTILLEGAL(); nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pr = sh4r.pc + 4; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = pc + 4 + RN(ir); nkeynes@27: return TRUE; nkeynes@1: case 2: /* BRAF Rn */ nkeynes@1: CHECKDEST( pc + 4 + RN(ir) ); nkeynes@2: CHECKSLOTILLEGAL(); nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = pc + 4 + RN(ir); nkeynes@27: return TRUE; nkeynes@1: case 8: /* PREF [Rn] */ nkeynes@2: tmp = RN(ir); nkeynes@2: if( (tmp & 0xFC000000) == 0xE0000000 ) { nkeynes@2: /* Store queue operation */ nkeynes@2: int queue = (tmp&0x20)>>2; nkeynes@2: int32_t *src = &sh4r.store_queue[queue]; nkeynes@2: uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24; nkeynes@2: uint32_t target = tmp&0x03FFFFE0 | hi; nkeynes@2: mem_copy_to_sh4( target, src, 32 ); nkeynes@2: WARN( "Executed SQ%c => %08X", nkeynes@2: (queue == 0 ? '0' : '1'), target ); nkeynes@2: } nkeynes@2: break; nkeynes@1: case 9: /* OCBI [Rn] */ nkeynes@1: case 10:/* OCBP [Rn] */ nkeynes@1: case 11:/* OCBWB [Rn] */ nkeynes@1: /* anything? */ nkeynes@1: break; nkeynes@1: case 12:/* MOVCA.L R0, [Rn] */ nkeynes@1: UNIMP(ir); nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 4: /* MOV.B Rm, [R0 + Rn] */ nkeynes@1: MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 5: /* MOV.W Rm, [R0 + Rn] */ nkeynes@1: MEM_WRITE_WORD( R0 + RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 6: /* MOV.L Rm, [R0 + Rn] */ nkeynes@1: MEM_WRITE_LONG( R0 + RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 7: /* MUL.L Rm, Rn */ nkeynes@2: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | nkeynes@1: (RM(ir) * RN(ir)); nkeynes@1: break; nkeynes@1: case 8: nkeynes@1: switch( (ir&0x0FF0)>>4 ) { nkeynes@1: case 0: /* CLRT */ nkeynes@1: sh4r.t = 0; nkeynes@1: break; nkeynes@1: case 1: /* SETT */ nkeynes@1: sh4r.t = 1; nkeynes@1: break; nkeynes@1: case 2: /* CLRMAC */ nkeynes@1: sh4r.mac = 0; nkeynes@1: break; nkeynes@1: case 3: /* LDTLB */ nkeynes@1: break; nkeynes@1: case 4: /* CLRS */ nkeynes@1: sh4r.s = 0; nkeynes@1: break; nkeynes@1: case 5: /* SETS */ nkeynes@1: sh4r.s = 1; nkeynes@1: break; nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 9: nkeynes@1: if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */ nkeynes@1: RN(ir) = sh4r.t; nkeynes@1: else if( ir == 0x0019 ) /* DIV0U */ nkeynes@1: sh4r.m = sh4r.q = sh4r.t = 0; nkeynes@1: else if( ir == 0x0009 ) nkeynes@1: /* NOP */; nkeynes@1: else UNDEF(ir); nkeynes@1: break; nkeynes@1: case 10: nkeynes@1: switch( (ir&0x00F0) >> 4 ) { nkeynes@1: case 0: /* STS MACH, Rn */ nkeynes@1: RN(ir) = sh4r.mac >> 32; nkeynes@1: break; nkeynes@1: case 1: /* STS MACL, Rn */ nkeynes@1: RN(ir) = (uint32_t)sh4r.mac; nkeynes@1: break; nkeynes@1: case 2: /* STS PR, Rn */ nkeynes@1: RN(ir) = sh4r.pr; nkeynes@1: break; nkeynes@1: case 3: /* STC SGR, Rn */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) = sh4r.sgr; nkeynes@1: break; nkeynes@1: case 5:/* STS FPUL, Rn */ nkeynes@1: RN(ir) = sh4r.fpul; nkeynes@1: break; nkeynes@1: case 6: /* STS FPSCR, Rn */ nkeynes@1: RN(ir) = sh4r.fpscr; nkeynes@1: break; nkeynes@1: case 15:/* STC DBR, Rn */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) = sh4r.dbr; nkeynes@1: break; nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 11: nkeynes@1: switch( (ir&0x0FF0)>>4 ) { nkeynes@1: case 0: /* RTS */ nkeynes@1: CHECKDEST( sh4r.pr ); nkeynes@2: CHECKSLOTILLEGAL(); nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = sh4r.pr; nkeynes@27: return TRUE; nkeynes@1: case 1: /* SLEEP */ nkeynes@27: if( MMIO_READ( CPG, STBCR ) & 0x80 ) { nkeynes@27: sh4r.sh4_state = SH4_STATE_STANDBY; nkeynes@27: } else { nkeynes@27: sh4r.sh4_state = SH4_STATE_SLEEP; nkeynes@27: } nkeynes@27: return FALSE; /* Halt CPU */ nkeynes@1: case 2: /* RTE */ nkeynes@1: CHECKPRIV(); nkeynes@1: CHECKDEST( sh4r.spc ); nkeynes@2: CHECKSLOTILLEGAL(); nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = sh4r.spc; nkeynes@1: sh4_load_sr( sh4r.ssr ); nkeynes@2: WARN( "RTE => %08X", sh4r.new_pc ); nkeynes@27: return TRUE; nkeynes@1: default:UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 12:/* MOV.B [R0+R%d], R%d */ nkeynes@1: RN(ir) = MEM_READ_BYTE( R0 + RM(ir) ); nkeynes@1: break; nkeynes@1: case 13:/* MOV.W [R0+R%d], R%d */ nkeynes@1: RN(ir) = MEM_READ_WORD( R0 + RM(ir) ); nkeynes@1: break; nkeynes@1: case 14:/* MOV.L [R0+R%d], R%d */ nkeynes@1: RN(ir) = MEM_READ_LONG( R0 + RM(ir) ); nkeynes@1: break; nkeynes@1: case 15:/* MAC.L [Rm++], [Rn++] */ nkeynes@1: tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) * nkeynes@1: SIGNEXT32(MEM_READ_LONG(RN(ir))) ); nkeynes@1: if( sh4r.s ) { nkeynes@1: /* 48-bit Saturation. Yuch */ nkeynes@1: tmpl += SIGNEXT48(sh4r.mac); nkeynes@2: if( tmpl < 0xFFFF800000000000LL ) nkeynes@2: tmpl = 0xFFFF800000000000LL; nkeynes@2: else if( tmpl > 0x00007FFFFFFFFFFFLL ) nkeynes@2: tmpl = 0x00007FFFFFFFFFFFLL; nkeynes@2: sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) | nkeynes@2: (tmpl&0x0000FFFFFFFFFFFFLL); nkeynes@1: } else sh4r.mac = tmpl; nkeynes@1: nkeynes@1: RM(ir) += 4; nkeynes@1: RN(ir) += 4; nkeynes@1: nkeynes@1: break; nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 1: /* 0001nnnnmmmmdddd */ nkeynes@1: /* MOV.L Rm, [Rn + disp4*4] */ nkeynes@1: MEM_WRITE_LONG( RN(ir) + (DISP4(ir)<<2), RM(ir) ); nkeynes@1: break; nkeynes@1: case 2: /* 0010nnnnmmmmxxxx */ nkeynes@1: switch( ir&0x000F ) { nkeynes@1: case 0: /* MOV.B Rm, [Rn] */ nkeynes@1: MEM_WRITE_BYTE( RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 1: /* MOV.W Rm, [Rn] */ nkeynes@1: MEM_WRITE_WORD( RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 2: /* MOV.L Rm, [Rn] */ nkeynes@1: MEM_WRITE_LONG( RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 3: UNDEF(ir); nkeynes@1: break; nkeynes@1: case 4: /* MOV.B Rm, [--Rn] */ nkeynes@1: RN(ir) --; nkeynes@1: MEM_WRITE_BYTE( RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 5: /* MOV.W Rm, [--Rn] */ nkeynes@1: RN(ir) -= 2; nkeynes@1: MEM_WRITE_WORD( RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 6: /* MOV.L Rm, [--Rn] */ nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), RM(ir) ); nkeynes@1: break; nkeynes@1: case 7: /* DIV0S Rm, Rn */ nkeynes@1: sh4r.q = RN(ir)>>31; nkeynes@1: sh4r.m = RM(ir)>>31; nkeynes@1: sh4r.t = sh4r.q ^ sh4r.m; nkeynes@1: break; nkeynes@1: case 8: /* TST Rm, Rn */ nkeynes@1: sh4r.t = (RN(ir)&RM(ir) ? 0 : 1); nkeynes@1: break; nkeynes@1: case 9: /* AND Rm, Rn */ nkeynes@1: RN(ir) &= RM(ir); nkeynes@1: break; nkeynes@1: case 10:/* XOR Rm, Rn */ nkeynes@1: RN(ir) ^= RM(ir); nkeynes@1: break; nkeynes@1: case 11:/* OR Rm, Rn */ nkeynes@1: RN(ir) |= RM(ir); nkeynes@1: break; nkeynes@1: case 12:/* CMP/STR Rm, Rn */ nkeynes@1: /* set T = 1 if any byte in RM & RN is the same */ nkeynes@1: tmp = RM(ir) ^ RN(ir); nkeynes@1: sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 || nkeynes@1: (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0; nkeynes@1: break; nkeynes@1: case 13:/* XTRCT Rm, Rn */ nkeynes@1: RN(ir) = (RN(ir)>>16) | (RM(ir)<<16); nkeynes@1: break; nkeynes@1: case 14:/* MULU.W Rm, Rn */ nkeynes@2: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | nkeynes@1: (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF)); nkeynes@1: break; nkeynes@1: case 15:/* MULS.W Rm, Rn */ nkeynes@2: sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | nkeynes@1: (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF)); nkeynes@1: break; nkeynes@1: } nkeynes@1: break; nkeynes@1: case 3: /* 0011nnnnmmmmxxxx */ nkeynes@1: switch( ir&0x000F ) { nkeynes@1: case 0: /* CMP/EQ Rm, Rn */ nkeynes@1: sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 2: /* CMP/HS Rm, Rn */ nkeynes@1: sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 3: /* CMP/GE Rm, Rn */ nkeynes@1: sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 4: { /* DIV1 Rm, Rn */ nkeynes@1: /* This is just from the sh4p manual with some nkeynes@1: * simplifications (someone want to check it's correct? :) nkeynes@1: * Why they couldn't just provide a real DIV instruction... nkeynes@1: * Please oh please let the translator batch these things nkeynes@1: * up into a single DIV... */ nkeynes@1: uint32_t tmp0, tmp1, tmp2, dir; nkeynes@1: nkeynes@1: dir = sh4r.q ^ sh4r.m; nkeynes@1: sh4r.q = (RN(ir) >> 31); nkeynes@1: tmp2 = RM(ir); nkeynes@1: RN(ir) = (RN(ir) << 1) | sh4r.t; nkeynes@1: tmp0 = RN(ir); nkeynes@1: if( dir ) { nkeynes@1: RN(ir) += tmp2; nkeynes@1: tmp1 = (RN(ir)tmp0 ? 1 : 0 ); nkeynes@1: } nkeynes@1: sh4r.q ^= sh4r.m ^ tmp1; nkeynes@1: sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 ); nkeynes@1: break; } nkeynes@1: case 5: /* DMULU.L Rm, Rn */ nkeynes@1: sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir)); nkeynes@1: break; nkeynes@1: case 6: /* CMP/HI Rm, Rn */ nkeynes@1: sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 7: /* CMP/GT Rm, Rn */ nkeynes@1: sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 8: /* SUB Rm, Rn */ nkeynes@1: RN(ir) -= RM(ir); nkeynes@1: break; nkeynes@1: case 10:/* SUBC Rm, Rn */ nkeynes@1: tmp = RN(ir); nkeynes@1: RN(ir) = RN(ir) - RM(ir) - sh4r.t; nkeynes@1: sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1)); nkeynes@1: break; nkeynes@1: case 11:/* SUBV Rm, Rn */ nkeynes@1: UNIMP(ir); nkeynes@1: break; nkeynes@1: case 12:/* ADD Rm, Rn */ nkeynes@1: RN(ir) += RM(ir); nkeynes@1: break; nkeynes@1: case 13:/* DMULS.L Rm, Rn */ nkeynes@1: sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir)); nkeynes@1: break; nkeynes@1: case 14:/* ADDC Rm, Rn */ nkeynes@1: tmp = RN(ir); nkeynes@1: RN(ir) += RM(ir) + sh4r.t; nkeynes@1: sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 15:/* ADDV Rm, Rn */ nkeynes@1: UNIMP(ir); nkeynes@1: break; nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 4: /* 0100nnnnxxxxxxxx */ nkeynes@1: switch( ir&0x00FF ) { nkeynes@1: case 0x00: /* SHLL Rn */ nkeynes@1: sh4r.t = RN(ir) >> 31; nkeynes@1: RN(ir) <<= 1; nkeynes@1: break; nkeynes@1: case 0x01: /* SHLR Rn */ nkeynes@1: sh4r.t = RN(ir) & 0x00000001; nkeynes@1: RN(ir) >>= 1; nkeynes@1: break; nkeynes@1: case 0x02: /* STS.L MACH, [--Rn] */ nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) ); nkeynes@1: break; nkeynes@1: case 0x03: /* STC.L SR, [--Rn] */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4_read_sr() ); nkeynes@1: break; nkeynes@1: case 0x04: /* ROTL Rn */ nkeynes@1: sh4r.t = RN(ir) >> 31; nkeynes@1: RN(ir) <<= 1; nkeynes@1: RN(ir) |= sh4r.t; nkeynes@1: break; nkeynes@1: case 0x05: /* ROTR Rn */ nkeynes@1: sh4r.t = RN(ir) & 0x00000001; nkeynes@1: RN(ir) >>= 1; nkeynes@1: RN(ir) |= (sh4r.t << 31); nkeynes@1: break; nkeynes@1: case 0x06: /* LDS.L [Rn++], MACH */ nkeynes@1: sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) | nkeynes@1: (((uint64_t)MEM_READ_LONG(RN(ir)))<<32); nkeynes@1: RN(ir) += 4; nkeynes@1: break; nkeynes@1: case 0x07: /* LDC.L [Rn++], SR */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4_load_sr( MEM_READ_LONG(RN(ir)) ); nkeynes@1: RN(ir) +=4; nkeynes@1: break; nkeynes@1: case 0x08: /* SHLL2 Rn */ nkeynes@1: RN(ir) <<= 2; nkeynes@1: break; nkeynes@1: case 0x09: /* SHLR2 Rn */ nkeynes@1: RN(ir) >>= 2; nkeynes@1: break; nkeynes@1: case 0x0A: /* LDS Rn, MACH */ nkeynes@1: sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) | nkeynes@1: (((uint64_t)RN(ir))<<32); nkeynes@1: break; nkeynes@1: case 0x0B: /* JSR [Rn] */ nkeynes@1: CHECKDEST( RN(ir) ); nkeynes@2: CHECKSLOTILLEGAL(); nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = RN(ir); nkeynes@1: sh4r.pr = pc + 4; nkeynes@27: return TRUE; nkeynes@1: case 0x0E: /* LDC Rn, SR */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4_load_sr( RN(ir) ); nkeynes@1: break; nkeynes@1: case 0x10: /* DT Rn */ nkeynes@1: RN(ir) --; nkeynes@1: sh4r.t = ( RN(ir) == 0 ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 0x11: /* CMP/PZ Rn */ nkeynes@1: sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 0x12: /* STS.L MACL, [--Rn] */ nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac ); nkeynes@1: break; nkeynes@1: case 0x13: /* STC.L GBR, [--Rn] */ nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4r.gbr ); nkeynes@1: break; nkeynes@1: case 0x15: /* CMP/PL Rn */ nkeynes@1: sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 0x16: /* LDS.L [Rn++], MACL */ nkeynes@2: sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | nkeynes@1: (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir))); nkeynes@1: RN(ir) += 4; nkeynes@1: break; nkeynes@1: case 0x17: /* LDC.L [Rn++], GBR */ nkeynes@1: sh4r.gbr = MEM_READ_LONG(RN(ir)); nkeynes@1: RN(ir) +=4; nkeynes@1: break; nkeynes@1: case 0x18: /* SHLL8 Rn */ nkeynes@1: RN(ir) <<= 8; nkeynes@1: break; nkeynes@1: case 0x19: /* SHLR8 Rn */ nkeynes@1: RN(ir) >>= 8; nkeynes@1: break; nkeynes@1: case 0x1A: /* LDS Rn, MACL */ nkeynes@2: sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | nkeynes@1: (uint64_t)((uint32_t)(RN(ir))); nkeynes@1: break; nkeynes@1: case 0x1B: /* TAS.B [Rn] */ nkeynes@1: tmp = MEM_READ_BYTE( RN(ir) ); nkeynes@1: sh4r.t = ( tmp == 0 ? 1 : 0 ); nkeynes@1: MEM_WRITE_BYTE( RN(ir), tmp | 0x80 ); nkeynes@1: break; nkeynes@1: case 0x1E: /* LDC Rn, GBR */ nkeynes@1: sh4r.gbr = RN(ir); nkeynes@1: break; nkeynes@1: case 0x20: /* SHAL Rn */ nkeynes@1: sh4r.t = RN(ir) >> 31; nkeynes@1: RN(ir) <<= 1; nkeynes@1: break; nkeynes@1: case 0x21: /* SHAR Rn */ nkeynes@1: sh4r.t = RN(ir) & 0x00000001; nkeynes@1: RN(ir) = ((int32_t)RN(ir)) >> 1; nkeynes@1: break; nkeynes@1: case 0x22: /* STS.L PR, [--Rn] */ nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4r.pr ); nkeynes@1: break; nkeynes@1: case 0x23: /* STC.L VBR, [--Rn] */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) -= 4; nkeynes@2: MEM_WRITE_LONG( RN(ir), sh4r.vbr ); nkeynes@1: break; nkeynes@1: case 0x24: /* ROTCL Rn */ nkeynes@1: tmp = RN(ir) >> 31; nkeynes@1: RN(ir) <<= 1; nkeynes@1: RN(ir) |= sh4r.t; nkeynes@1: sh4r.t = tmp; nkeynes@1: break; nkeynes@1: case 0x25: /* ROTCR Rn */ nkeynes@1: tmp = RN(ir) & 0x00000001; nkeynes@1: RN(ir) >>= 1; nkeynes@1: RN(ir) |= (sh4r.t << 31 ); nkeynes@1: sh4r.t = tmp; nkeynes@1: break; nkeynes@1: case 0x26: /* LDS.L [Rn++], PR */ nkeynes@1: sh4r.pr = MEM_READ_LONG( RN(ir) ); nkeynes@1: RN(ir) += 4; nkeynes@1: break; nkeynes@1: case 0x27: /* LDC.L [Rn++], VBR */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4r.vbr = MEM_READ_LONG(RN(ir)); nkeynes@1: RN(ir) +=4; nkeynes@1: break; nkeynes@1: case 0x28: /* SHLL16 Rn */ nkeynes@1: RN(ir) <<= 16; nkeynes@1: break; nkeynes@1: case 0x29: /* SHLR16 Rn */ nkeynes@1: RN(ir) >>= 16; nkeynes@1: break; nkeynes@1: case 0x2A: /* LDS Rn, PR */ nkeynes@1: sh4r.pr = RN(ir); nkeynes@1: break; nkeynes@1: case 0x2B: /* JMP [Rn] */ nkeynes@1: CHECKDEST( RN(ir) ); nkeynes@2: CHECKSLOTILLEGAL(); nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = RN(ir); nkeynes@27: return TRUE; nkeynes@1: case 0x2E: /* LDC Rn, VBR */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4r.vbr = RN(ir); nkeynes@1: break; nkeynes@1: case 0x32: /* STC.L SGR, [--Rn] */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4r.sgr ); nkeynes@1: break; nkeynes@1: case 0x33: /* STC.L SSR, [--Rn] */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4r.ssr ); nkeynes@1: break; nkeynes@1: case 0x37: /* LDC.L [Rn++], SSR */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4r.ssr = MEM_READ_LONG(RN(ir)); nkeynes@1: RN(ir) +=4; nkeynes@1: break; nkeynes@1: case 0x3E: /* LDC Rn, SSR */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4r.ssr = RN(ir); nkeynes@1: break; nkeynes@1: case 0x43: /* STC.L SPC, [--Rn] */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4r.spc ); nkeynes@1: break; nkeynes@1: case 0x47: /* LDC.L [Rn++], SPC */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4r.spc = MEM_READ_LONG(RN(ir)); nkeynes@1: RN(ir) +=4; nkeynes@1: break; nkeynes@1: case 0x4E: /* LDC Rn, SPC */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4r.spc = RN(ir); nkeynes@1: break; nkeynes@1: case 0x52: /* STS.L FPUL, [--Rn] */ nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4r.fpul ); nkeynes@1: break; nkeynes@1: case 0x56: /* LDS.L [Rn++], FPUL */ nkeynes@1: sh4r.fpul = MEM_READ_LONG(RN(ir)); nkeynes@1: RN(ir) +=4; nkeynes@1: break; nkeynes@1: case 0x5A: /* LDS Rn, FPUL */ nkeynes@1: sh4r.fpul = RN(ir); nkeynes@1: break; nkeynes@1: case 0x62: /* STS.L FPSCR, [--Rn] */ nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4r.fpscr ); nkeynes@1: break; nkeynes@1: case 0x66: /* LDS.L [Rn++], FPSCR */ nkeynes@1: sh4r.fpscr = MEM_READ_LONG(RN(ir)); nkeynes@1: RN(ir) +=4; nkeynes@1: break; nkeynes@1: case 0x6A: /* LDS Rn, FPSCR */ nkeynes@1: sh4r.fpscr = RN(ir); nkeynes@1: break; nkeynes@1: case 0xF2: /* STC.L DBR, [--Rn] */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), sh4r.dbr ); nkeynes@1: break; nkeynes@1: case 0xF6: /* LDC.L [Rn++], DBR */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4r.dbr = MEM_READ_LONG(RN(ir)); nkeynes@1: RN(ir) +=4; nkeynes@1: break; nkeynes@1: case 0xFA: /* LDC Rn, DBR */ nkeynes@1: CHECKPRIV(); nkeynes@1: sh4r.dbr = RN(ir); nkeynes@1: break; nkeynes@1: case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3: nkeynes@1: case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN(ir) -= 4; nkeynes@1: MEM_WRITE_LONG( RN(ir), RN_BANK(ir) ); nkeynes@1: break; nkeynes@1: case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7: nkeynes@1: case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN_BANK(ir) = MEM_READ_LONG( RN(ir) ); nkeynes@1: RN(ir) += 4; nkeynes@1: break; nkeynes@1: case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE: nkeynes@1: case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */ nkeynes@1: CHECKPRIV(); nkeynes@1: RN_BANK(ir) = RM(ir); nkeynes@1: break; nkeynes@1: default: nkeynes@1: if( (ir&0x000F) == 0x0F ) { nkeynes@1: /* MAC.W [Rm++], [Rn++] */ nkeynes@1: tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) * nkeynes@1: SIGNEXT16(MEM_READ_WORD(RN(ir))); nkeynes@1: if( sh4r.s ) { nkeynes@1: /* FIXME */ nkeynes@1: UNIMP(ir); nkeynes@1: } else sh4r.mac += SIGNEXT32(tmp); nkeynes@1: RM(ir) += 2; nkeynes@1: RN(ir) += 2; nkeynes@1: } else if( (ir&0x000F) == 0x0C ) { nkeynes@1: /* SHAD Rm, Rn */ nkeynes@1: tmp = RM(ir); nkeynes@1: if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f); nkeynes@9: else if( (tmp & 0x1F) == 0 ) nkeynes@9: RN(ir) = ((int32_t)RN(ir)) >> 31; nkeynes@9: else nkeynes@9: RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1); nkeynes@1: } else if( (ir&0x000F) == 0x0D ) { nkeynes@1: /* SHLD Rm, Rn */ nkeynes@1: tmp = RM(ir); nkeynes@1: if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f); nkeynes@1: else if( (tmp & 0x1F) == 0 ) RN(ir) = 0; nkeynes@1: else RN(ir) >>= (((~tmp) & 0x1F)+1); nkeynes@1: } else UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 5: /* 0101nnnnmmmmdddd */ nkeynes@1: /* MOV.L [Rm + disp4*4], Rn */ nkeynes@1: RN(ir) = MEM_READ_LONG( RM(ir) + (DISP4(ir)<<2) ); nkeynes@1: break; nkeynes@1: case 6: /* 0110xxxxxxxxxxxx */ nkeynes@1: switch( ir&0x000f ) { nkeynes@1: case 0: /* MOV.B [Rm], Rn */ nkeynes@1: RN(ir) = MEM_READ_BYTE( RM(ir) ); nkeynes@1: break; nkeynes@1: case 1: /* MOV.W [Rm], Rn */ nkeynes@1: RN(ir) = MEM_READ_WORD( RM(ir) ); nkeynes@1: break; nkeynes@1: case 2: /* MOV.L [Rm], Rn */ nkeynes@1: RN(ir) = MEM_READ_LONG( RM(ir) ); nkeynes@1: break; nkeynes@1: case 3: /* MOV Rm, Rn */ nkeynes@1: RN(ir) = RM(ir); nkeynes@1: break; nkeynes@1: case 4: /* MOV.B [Rm++], Rn */ nkeynes@1: RN(ir) = MEM_READ_BYTE( RM(ir) ); nkeynes@1: RM(ir) ++; nkeynes@1: break; nkeynes@1: case 5: /* MOV.W [Rm++], Rn */ nkeynes@1: RN(ir) = MEM_READ_WORD( RM(ir) ); nkeynes@1: RM(ir) += 2; nkeynes@1: break; nkeynes@1: case 6: /* MOV.L [Rm++], Rn */ nkeynes@1: RN(ir) = MEM_READ_LONG( RM(ir) ); nkeynes@1: RM(ir) += 4; nkeynes@1: break; nkeynes@1: case 7: /* NOT Rm, Rn */ nkeynes@1: RN(ir) = ~RM(ir); nkeynes@1: break; nkeynes@1: case 8: /* SWAP.B Rm, Rn */ nkeynes@1: RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) | nkeynes@1: ((RM(ir)&0x000000FF)<<8); nkeynes@1: break; nkeynes@1: case 9: /* SWAP.W Rm, Rn */ nkeynes@1: RN(ir) = (RM(ir)>>16) | (RM(ir)<<16); nkeynes@1: break; nkeynes@1: case 10:/* NEGC Rm, Rn */ nkeynes@1: tmp = 0 - RM(ir); nkeynes@1: RN(ir) = tmp - sh4r.t; nkeynes@1: sh4r.t = ( 0> 8 ) { nkeynes@1: case 0: /* MOV.B R0, [Rm + disp4] */ nkeynes@1: MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 ); nkeynes@1: break; nkeynes@1: case 1: /* MOV.W R0, [Rm + disp4*2] */ nkeynes@1: MEM_WRITE_WORD( RM(ir) + (DISP4(ir)<<1), R0 ); nkeynes@1: break; nkeynes@1: case 4: /* MOV.B [Rm + disp4], R0 */ nkeynes@1: R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) ); nkeynes@1: break; nkeynes@1: case 5: /* MOV.W [Rm + disp4*2], R0 */ nkeynes@1: R0 = MEM_READ_WORD( RM(ir) + (DISP4(ir)<<1) ); nkeynes@1: break; nkeynes@1: case 8: /* CMP/EQ imm, R0 */ nkeynes@1: sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 9: /* BT disp8 */ nkeynes@2: CHECKSLOTILLEGAL() nkeynes@1: if( sh4r.t ) { nkeynes@1: CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) nkeynes@1: sh4r.pc += (PCDISP8(ir)<<1) + 4; nkeynes@1: sh4r.new_pc = sh4r.pc + 2; nkeynes@27: return TRUE; nkeynes@1: } nkeynes@1: break; nkeynes@1: case 11:/* BF disp8 */ nkeynes@2: CHECKSLOTILLEGAL() nkeynes@1: if( !sh4r.t ) { nkeynes@1: CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) nkeynes@1: sh4r.pc += (PCDISP8(ir)<<1) + 4; nkeynes@1: sh4r.new_pc = sh4r.pc + 2; nkeynes@27: return TRUE; nkeynes@1: } nkeynes@1: break; nkeynes@1: case 13:/* BT/S disp8 */ nkeynes@2: CHECKSLOTILLEGAL() nkeynes@1: if( sh4r.t ) { nkeynes@1: CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4; nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@27: return TRUE; nkeynes@1: } nkeynes@1: break; nkeynes@1: case 15:/* BF/S disp8 */ nkeynes@2: CHECKSLOTILLEGAL() nkeynes@1: if( !sh4r.t ) { nkeynes@1: CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4; nkeynes@27: return TRUE; nkeynes@1: } nkeynes@1: break; nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 9: /* 1001xxxxxxxxxxxx */ nkeynes@1: /* MOV.W [disp8*2 + pc + 4], Rn */ nkeynes@1: RN(ir) = MEM_READ_WORD( pc + 4 + (DISP8(ir)<<1) ); nkeynes@1: break; nkeynes@1: case 10:/* 1010dddddddddddd */ nkeynes@1: /* BRA disp12 */ nkeynes@2: CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 ) nkeynes@2: CHECKSLOTILLEGAL() nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = pc + 4 + (DISP12(ir)<<1); nkeynes@27: return TRUE; nkeynes@1: case 11:/* 1011dddddddddddd */ nkeynes@1: /* BSR disp12 */ nkeynes@1: CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 ) nkeynes@2: CHECKSLOTILLEGAL() nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: sh4r.pr = pc + 4; nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc = pc + 4 + (DISP12(ir)<<1); nkeynes@27: return TRUE; nkeynes@1: case 12:/* 1100xxxxdddddddd */ nkeynes@1: switch( (ir&0x0F00)>>8 ) { nkeynes@1: case 0: /* MOV.B R0, [GBR + disp8] */ nkeynes@1: MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 ); nkeynes@1: break; nkeynes@1: case 1: /* MOV.W R0, [GBR + disp8*2] */ nkeynes@1: MEM_WRITE_WORD( sh4r.gbr + (DISP8(ir)<<1), R0 ); nkeynes@1: break; nkeynes@1: case 2: /*MOV.L R0, [GBR + disp8*4] */ nkeynes@1: MEM_WRITE_LONG( sh4r.gbr + (DISP8(ir)<<2), R0 ); nkeynes@1: break; nkeynes@1: case 3: /* TRAPA imm8 */ nkeynes@2: CHECKSLOTILLEGAL() nkeynes@2: sh4r.in_delay_slot = 1; nkeynes@1: MMIO_WRITE( MMU, TRA, UIMM8(ir) ); nkeynes@1: sh4r.pc = sh4r.new_pc; /* RAISE ends the instruction */ nkeynes@1: sh4r.new_pc += 2; nkeynes@1: RAISE( EXC_TRAP, EXV_TRAP ); nkeynes@1: break; nkeynes@1: case 4: /* MOV.B [GBR + disp8], R0 */ nkeynes@1: R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) ); nkeynes@1: break; nkeynes@1: case 5: /* MOV.W [GBR + disp8*2], R0 */ nkeynes@1: R0 = MEM_READ_WORD( sh4r.gbr + (DISP8(ir)<<1) ); nkeynes@1: break; nkeynes@1: case 6: /* MOV.L [GBR + disp8*4], R0 */ nkeynes@1: R0 = MEM_READ_LONG( sh4r.gbr + (DISP8(ir)<<2) ); nkeynes@1: break; nkeynes@1: case 7: /* MOVA disp8 + pc&~3 + 4, R0 */ nkeynes@1: R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4; nkeynes@1: break; nkeynes@1: case 8: /* TST imm8, R0 */ nkeynes@1: sh4r.t = (R0 & UIMM8(ir) ? 0 : 1); nkeynes@1: break; nkeynes@1: case 9: /* AND imm8, R0 */ nkeynes@1: R0 &= UIMM8(ir); nkeynes@1: break; nkeynes@1: case 10:/* XOR imm8, R0 */ nkeynes@1: R0 ^= UIMM8(ir); nkeynes@1: break; nkeynes@1: case 11:/* OR imm8, R0 */ nkeynes@1: R0 |= UIMM8(ir); nkeynes@1: break; nkeynes@1: case 12:/* TST.B imm8, [R0+GBR] */ nkeynes@1: sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 ); nkeynes@1: break; nkeynes@1: case 13:/* AND.B imm8, [R0+GBR] */ nkeynes@1: MEM_WRITE_BYTE( R0 + sh4r.gbr, nkeynes@1: UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) ); nkeynes@1: break; nkeynes@1: case 14:/* XOR.B imm8, [R0+GBR] */ nkeynes@1: MEM_WRITE_BYTE( R0 + sh4r.gbr, nkeynes@1: UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); nkeynes@1: break; nkeynes@1: case 15:/* OR.B imm8, [R0+GBR] */ nkeynes@1: MEM_WRITE_BYTE( R0 + sh4r.gbr, nkeynes@1: UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) ); nkeynes@1: break; nkeynes@1: } nkeynes@1: break; nkeynes@1: case 13:/* 1101nnnndddddddd */ nkeynes@1: /* MOV.L [disp8*4 + pc&~3 + 4], Rn */ nkeynes@1: RN(ir) = MEM_READ_LONG( (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4 ); nkeynes@1: break; nkeynes@1: case 14:/* 1110nnnniiiiiiii */ nkeynes@1: /* MOV imm8, Rn */ nkeynes@1: RN(ir) = IMM8(ir); nkeynes@1: break; nkeynes@1: case 15:/* 1111xxxxxxxxxxxx */ nkeynes@1: CHECKFPUEN(); nkeynes@1: switch( ir&0x000F ) { nkeynes@1: case 0: /* FADD FRm, FRn */ nkeynes@1: FRN(ir) += FRM(ir); nkeynes@1: break; nkeynes@1: case 1: /* FSUB FRm, FRn */ nkeynes@1: FRN(ir) -= FRM(ir); nkeynes@1: break; nkeynes@1: case 2: /* FMUL FRm, FRn */ nkeynes@1: FRN(ir) = FRN(ir) * FRM(ir); nkeynes@1: break; nkeynes@1: case 3: /* FDIV FRm, FRn */ nkeynes@1: FRN(ir) = FRN(ir) / FRM(ir); nkeynes@1: break; nkeynes@1: case 4: /* FCMP/EQ FRm, FRn */ nkeynes@1: sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 5: /* FCMP/GT FRm, FRn */ nkeynes@1: sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 ); nkeynes@1: break; nkeynes@1: case 6: /* FMOV.S [Rm+R0], FRn */ nkeynes@1: MEM_FP_READ( RM(ir) + R0, FRNn(ir) ); nkeynes@1: break; nkeynes@1: case 7: /* FMOV.S FRm, [Rn+R0] */ nkeynes@1: MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) ); nkeynes@1: break; nkeynes@1: case 8: /* FMOV.S [Rm], FRn */ nkeynes@1: MEM_FP_READ( RM(ir), FRNn(ir) ); nkeynes@1: break; nkeynes@1: case 9: /* FMOV.S [Rm++], FRn */ nkeynes@1: MEM_FP_READ( RM(ir), FRNn(ir) ); nkeynes@1: RM(ir) += FP_WIDTH; nkeynes@1: break; nkeynes@1: case 10:/* FMOV.S FRm, [Rn] */ nkeynes@1: MEM_FP_WRITE( RN(ir), FRMn(ir) ); nkeynes@1: break; nkeynes@1: case 11:/* FMOV.S FRm, [--Rn] */ nkeynes@1: RN(ir) -= FP_WIDTH; nkeynes@1: MEM_FP_WRITE( RN(ir), FRMn(ir) ); nkeynes@1: break; nkeynes@1: case 12:/* FMOV FRm, FRn */ nkeynes@1: if( IS_FPU_DOUBLESIZE() ) { nkeynes@1: DRN(ir) = DRM(ir); nkeynes@1: } else { nkeynes@1: FRN(ir) = FRM(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 13: nkeynes@1: switch( (ir&0x00F0) >> 4 ) { nkeynes@1: case 0: /* FSTS FPUL, FRn */ nkeynes@1: FRN(ir) = FPULf; nkeynes@1: break; nkeynes@1: case 1: /* FLDS FRn, FPUL */ nkeynes@1: FPULf = FRN(ir); nkeynes@1: break; nkeynes@1: case 2: /* FLOAT FPUL, FRn */ nkeynes@1: FRN(ir) = (float)FPULi; nkeynes@1: break; nkeynes@1: case 3: /* FTRC FRn, FPUL */ nkeynes@1: FPULi = (uint32_t)FRN(ir); nkeynes@1: /* FIXME: is this sufficient? */ nkeynes@1: break; nkeynes@1: case 4: /* FNEG FRn */ nkeynes@1: FRN(ir) = -FRN(ir); nkeynes@1: break; nkeynes@1: case 5: /* FABS FRn */ nkeynes@1: FRN(ir) = fabsf(FRN(ir)); nkeynes@1: break; nkeynes@1: case 6: /* FSQRT FRn */ nkeynes@1: FRN(ir) = sqrtf(FRN(ir)); nkeynes@1: break; nkeynes@2: case 7: /* FSRRA FRn */ nkeynes@2: FRN(ir) = 1.0/sqrtf(FRN(ir)); nkeynes@2: break; nkeynes@1: case 8: /* FLDI0 FRn */ nkeynes@1: FRN(ir) = 0.0; nkeynes@1: break; nkeynes@1: case 9: /* FLDI1 FRn */ nkeynes@1: FRN(ir) = 1.0; nkeynes@1: break; nkeynes@1: case 10: /* FCNVSD FPUL, DRn */ nkeynes@1: if( IS_FPU_DOUBLEPREC() ) nkeynes@1: DRN(ir) = (double)FPULf; nkeynes@1: else UNDEF(ir); nkeynes@1: break; nkeynes@1: case 11: /* FCNVDS DRn, FPUL */ nkeynes@1: if( IS_FPU_DOUBLEPREC() ) nkeynes@1: FPULf = (float)DRN(ir); nkeynes@1: else UNDEF(ir); nkeynes@1: break; nkeynes@2: case 14:/* FIPR FVm, FVn */ nkeynes@2: /* FIXME: This is not going to be entirely accurate nkeynes@2: * as the SH4 instruction is less precise. Also nkeynes@2: * need to check for 0s and infinities. nkeynes@2: */ nkeynes@2: { nkeynes@2: float *fr_bank = FR; nkeynes@2: int tmp2 = FVN(ir); nkeynes@2: tmp = FVM(ir); nkeynes@2: fr_bank[tmp2+3] = fr_bank[tmp]*fr_bank[tmp2] + nkeynes@2: fr_bank[tmp+1]*fr_bank[tmp2+1] + nkeynes@2: fr_bank[tmp+2]*fr_bank[tmp2+2] + nkeynes@2: fr_bank[tmp+3]*fr_bank[tmp2+3]; nkeynes@1: break; nkeynes@2: } nkeynes@1: case 15: nkeynes@2: if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */ nkeynes@2: float *fvout = FR+FVN(ir); nkeynes@2: float *xm = XF; nkeynes@2: float fv[4] = { fvout[0], fvout[1], fvout[2], fvout[3] }; nkeynes@2: fvout[0] = xm[0] * fv[0] + xm[4]*fv[1] + nkeynes@2: xm[8]*fv[2] + xm[12]*fv[3]; nkeynes@2: fvout[1] = xm[1] * fv[0] + xm[5]*fv[1] + nkeynes@2: xm[9]*fv[2] + xm[13]*fv[3]; nkeynes@2: fvout[2] = xm[2] * fv[0] + xm[6]*fv[1] + nkeynes@2: xm[10]*fv[2] + xm[14]*fv[3]; nkeynes@2: fvout[3] = xm[3] * fv[0] + xm[7]*fv[1] + nkeynes@2: xm[11]*fv[2] + xm[15]*fv[3]; nkeynes@2: break; nkeynes@2: } nkeynes@2: else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */ nkeynes@2: float angle = (((float)(short)(FPULi>>16)) + nkeynes@2: ((float)(FPULi&16)/65536.0)) * nkeynes@2: 2 * M_PI; nkeynes@2: int reg = FRNn(ir); nkeynes@2: FR[reg] = sinf(angle); nkeynes@2: FR[reg+1] = cosf(angle); nkeynes@2: break; nkeynes@2: } nkeynes@2: else if( ir == 0xFBFD ) { nkeynes@2: /* FRCHG */ nkeynes@1: sh4r.fpscr ^= FPSCR_FR; nkeynes@2: break; nkeynes@2: } nkeynes@2: else if( ir == 0xF3FD ) { nkeynes@2: /* FSCHG */ nkeynes@1: sh4r.fpscr ^= FPSCR_SZ; nkeynes@2: break; nkeynes@2: } nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: case 14:/* FMAC FR0, FRm, FRn */ nkeynes@1: FRN(ir) += FRM(ir)*FR0; nkeynes@1: break; nkeynes@1: default: UNDEF(ir); nkeynes@1: } nkeynes@1: break; nkeynes@1: } nkeynes@1: sh4r.pc = sh4r.new_pc; nkeynes@1: sh4r.new_pc += 2; nkeynes@2: sh4r.in_delay_slot = 0; nkeynes@1: }