nkeynes@31: /**
nkeynes@561:  * $Id$
nkeynes@31:  *
nkeynes@31:  * SH4 onboard interrupt controller (INTC) definitions.
nkeynes@31:  *
nkeynes@31:  * Copyright (c) 2005 Nathan Keynes.
nkeynes@31:  *
nkeynes@31:  * This program is free software; you can redistribute it and/or modify
nkeynes@31:  * it under the terms of the GNU General Public License as published by
nkeynes@31:  * the Free Software Foundation; either version 2 of the License, or
nkeynes@31:  * (at your option) any later version.
nkeynes@31:  *
nkeynes@31:  * This program is distributed in the hope that it will be useful,
nkeynes@31:  * but WITHOUT ANY WARRANTY; without even the implied warranty of
nkeynes@31:  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
nkeynes@31:  * GNU General Public License for more details.
nkeynes@31:  */
nkeynes@31: 
nkeynes@736: #ifndef lxdream_intc_H
nkeynes@736: #define lxdream_intc_H 1
nkeynes@1: 
nkeynes@1: #include "sh4core.h"
nkeynes@1: 
nkeynes@1: #ifdef __cplusplus
nkeynes@1: extern "C" {
nkeynes@1: #endif
nkeynes@1: 
nkeynes@1: #define INT_IRQ0        0     /* External Interrupt request 0 */
nkeynes@1: #define INT_IRQ1        1
nkeynes@1: #define INT_IRQ2        2
nkeynes@1: #define INT_IRQ3        3
nkeynes@1: #define INT_IRQ4        4
nkeynes@1: #define INT_IRQ5        5
nkeynes@1: #define INT_IRQ6        6
nkeynes@1: #define INT_IRQ7        7
nkeynes@1: #define INT_IRQ8        8
nkeynes@1: #define INT_IRQ9        9
nkeynes@1: #define INT_IRQ10      10
nkeynes@1: #define INT_IRQ11      11
nkeynes@1: #define INT_IRQ12      12
nkeynes@1: #define INT_IRQ13      13
nkeynes@1: #define INT_IRQ14      14
nkeynes@1: #define INT_NMI        15     /* Non-Maskable Interrupt */
nkeynes@1: #define INT_HUDI       16     /* Hitachi use debug interface */
nkeynes@1: #define INT_GPIO       17     /* I/O port interrupt */
nkeynes@1: #define INT_DMA_DMTE0  18     /* DMA transfer end 0 */
nkeynes@1: #define INT_DMA_DMTE1  19     /* DMA transfer end 1 */
nkeynes@1: #define INT_DMA_DMTE2  20     /* DMA transfer end 2 */
nkeynes@1: #define INT_DMA_DMTE3  21     /* DMA transfer end 3 */
nkeynes@1: #define INT_DMA_DMAE   22     /* DMA address error */
nkeynes@1: #define INT_TMU_TUNI0  23     /* Timer underflow interrupt 0 */
nkeynes@1: #define INT_TMU_TUNI1  24     /* Timer underflow interrupt 1 */
nkeynes@1: #define INT_TMU_TUNI2  25     /* Timer underflow interrupt 2 */
nkeynes@1: #define INT_TMU_TICPI2 26     /* Timer input capture interrupt */
nkeynes@1: #define INT_RTC_ATI    27     /* RTC Alarm interrupt */
nkeynes@1: #define INT_RTC_PRI    28     /* RTC periodic interrupt */
nkeynes@1: #define INT_RTC_CUI    29     /* RTC Carry-up interrupt */
nkeynes@1: #define INT_SCI_ERI    30     /* SCI receive-error interrupt */
nkeynes@1: #define INT_SCI_RXI    31     /* SCI receive-data-full interrupt */
nkeynes@1: #define INT_SCI_TXI    32     /* SCI transmit-data-empty interrupt */
nkeynes@1: #define INT_SCI_TEI    33     /* SCI transmit-end interrupt */
nkeynes@1: #define INT_SCIF_ERI   34     /* SCIF receive-error interrupt */
nkeynes@1: #define INT_SCIF_RXI   35     /* SCIF receive-data-full interrupt */
nkeynes@1: #define INT_SCIF_BRI   36     /* SCIF break interrupt request */
nkeynes@1: #define INT_SCIF_TXI   37     /* SCIF Transmit-data-empty interrupt */
nkeynes@1: #define INT_WDT_ITI    38     /* WDT Interval timer interval (CPG) */
nkeynes@1: #define INT_REF_RCMI   39     /* Compare-match interrupt */
nkeynes@1: #define INT_REF_ROVI   40     /* Refresh counter overflow interrupt */
nkeynes@1: 
nkeynes@1: #define INT_NUM_SOURCES 41
nkeynes@1: 
nkeynes@1: char *intc_get_interrupt_name( int which );
nkeynes@1: void intc_raise_interrupt( int which );
nkeynes@1: void intc_clear_interrupt( int which );
nkeynes@1: uint32_t intc_accept_interrupt( void );
nkeynes@1: void intc_reset( void );
nkeynes@1: void intc_mask_changed( void );
nkeynes@1: 
nkeynes@1: #ifdef __cplusplus
nkeynes@1: }
nkeynes@1: #endif
nkeynes@1: 
nkeynes@736: #endif /* !lxdream_intc_H */