nkeynes@10: /** nkeynes@561: * $Id$ nkeynes@10: * nkeynes@54: * This file defines the internal functions exported/used by the SH4 core, nkeynes@54: * except for disassembly functions defined in sh4dasm.h nkeynes@10: * nkeynes@10: * Copyright (c) 2005 Nathan Keynes. nkeynes@10: * nkeynes@10: * This program is free software; you can redistribute it and/or modify nkeynes@10: * it under the terms of the GNU General Public License as published by nkeynes@10: * the Free Software Foundation; either version 2 of the License, or nkeynes@10: * (at your option) any later version. nkeynes@10: * nkeynes@10: * This program is distributed in the hope that it will be useful, nkeynes@10: * but WITHOUT ANY WARRANTY; without even the implied warranty of nkeynes@10: * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the nkeynes@10: * GNU General Public License for more details. nkeynes@1: */ nkeynes@30: nkeynes@1: #ifndef sh4core_H nkeynes@1: #define sh4core_H 1 nkeynes@1: nkeynes@27: #include nkeynes@1: #include nkeynes@23: #include nkeynes@378: #include "mem.h" nkeynes@564: #include "sh4/sh4.h" nkeynes@1: nkeynes@1: #ifdef __cplusplus nkeynes@1: extern "C" { nkeynes@1: #endif nkeynes@1: nkeynes@564: /* Breakpoint data structure */ nkeynes@378: extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS]; nkeynes@378: extern int sh4_breakpoint_count; nkeynes@569: extern sh4ptr_t sh4_main_ram; nkeynes@569: nkeynes@569: /** nkeynes@569: * Cached direct pointer to the current instruction page. If AT is on, this nkeynes@569: * is derived from the ITLB, otherwise this will be the entire memory region. nkeynes@569: * This is actually a fairly useful optimization, as we can make a lot of nkeynes@569: * assumptions about the "current page" that we can't make in general for nkeynes@569: * arbitrary virtual addresses. nkeynes@569: */ nkeynes@569: struct sh4_icache_struct { nkeynes@569: sh4ptr_t page; // Page pointer (NULL if no page) nkeynes@569: sh4vma_t page_vma; // virtual address of the page. nkeynes@569: sh4addr_t page_ppa; // physical address of the page nkeynes@569: uint32_t mask; // page mask nkeynes@569: }; nkeynes@569: extern struct sh4_icache_struct sh4_icache; nkeynes@569: nkeynes@569: /** nkeynes@569: * Test if a given address is contained in the current icache entry nkeynes@569: */ nkeynes@569: #define IS_IN_ICACHE(addr) (sh4_icache.page_vma == ((addr) & sh4_icache.mask)) nkeynes@569: /** nkeynes@569: * Return a pointer for the given vma, under the assumption that it is nkeynes@569: * actually contained in the current icache entry. nkeynes@569: */ nkeynes@569: #define GET_ICACHE_PTR(addr) (sh4_icache.page + ((addr)-sh4_icache.page_vma)) nkeynes@569: /** nkeynes@569: * Return the physical (external) address for the given vma, assuming that it is nkeynes@569: * actually contained in the current icache entry. nkeynes@569: */ nkeynes@569: #define GET_ICACHE_PHYS(addr) (sh4_icache.page_ppa + ((addr)-sh4_icache.page_vma)) nkeynes@378: nkeynes@564: /* SH4 module functions */ nkeynes@1: void sh4_init( void ); nkeynes@1: void sh4_reset( void ); nkeynes@1: void sh4_run( void ); nkeynes@1: void sh4_stop( void ); nkeynes@564: nkeynes@564: /* SH4 peripheral module functions */ nkeynes@564: void CPG_reset( void ); nkeynes@564: void DMAC_reset( void ); nkeynes@564: void DMAC_run_slice( uint32_t ); nkeynes@564: void DMAC_save_state( FILE * ); nkeynes@564: int DMAC_load_state( FILE * ); nkeynes@564: void INTC_reset( void ); nkeynes@564: void INTC_save_state( FILE *f ); nkeynes@564: int INTC_load_state( FILE *f ); nkeynes@564: void MMU_init( void ); nkeynes@564: void MMU_reset( void ); nkeynes@564: void MMU_save_state( FILE *f ); nkeynes@564: int MMU_load_state( FILE *f ); nkeynes@564: void MMU_ldtlb(); nkeynes@564: void SCIF_reset( void ); nkeynes@564: void SCIF_run_slice( uint32_t ); nkeynes@564: void SCIF_save_state( FILE *f ); nkeynes@564: int SCIF_load_state( FILE *f ); nkeynes@564: void SCIF_update_line_speed(void); nkeynes@564: void TMU_reset( void ); nkeynes@564: void TMU_run_slice( uint32_t ); nkeynes@564: void TMU_save_state( FILE * ); nkeynes@564: int TMU_load_state( FILE * ); nkeynes@564: void TMU_update_clocks( void ); nkeynes@564: nkeynes@564: /* SH4 instruction support methods */ nkeynes@401: void sh4_sleep( void ); nkeynes@401: void sh4_fsca( uint32_t angle, float *fr ); nkeynes@401: void sh4_ftrv( float *fv, float *xmtrx ); nkeynes@564: uint32_t sh4_read_sr(void); nkeynes@564: void sh4_write_sr(uint32_t val); nkeynes@401: void signsat48(void); nkeynes@378: nkeynes@10: /* SH4 Memory */ nkeynes@570: #define MMU_VMA_ERROR 0x8000000 nkeynes@570: /** nkeynes@570: * Update the sh4_icache structure to contain the specified vma. If the vma nkeynes@570: * cannot be resolved, an MMU exception is raised and the function returns nkeynes@570: * FALSE. Otherwise, returns TRUE and updates sh4_icache accordingly. nkeynes@570: * Note: If the vma resolves to a non-memory area, sh4_icache will be nkeynes@570: * invalidated, but the function will still return TRUE. nkeynes@570: * @return FALSE if an MMU exception was raised, otherwise TRUE. nkeynes@570: */ nkeynes@569: gboolean mmu_update_icache( sh4vma_t addr ); nkeynes@570: nkeynes@570: /** nkeynes@570: * Resolve a virtual address through the TLB for a read operation, returning nkeynes@570: * the resultant P4 or external address. If the resolution fails, the nkeynes@570: * appropriate MMU exception is raised and the value MMU_VMA_ERROR is returned. nkeynes@570: * @return An external address (0x00000000-0x1FFFFFFF), a P4 address nkeynes@570: * (0xE0000000 - 0xFFFFFFFF), or MMU_VMA_ERROR. nkeynes@570: */ nkeynes@570: sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr ); nkeynes@570: sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr ); nkeynes@559: nkeynes@527: int64_t sh4_read_quad( sh4addr_t addr ); nkeynes@570: int32_t sh4_read_long( sh4addr_t addr ); nkeynes@570: int32_t sh4_read_word( sh4addr_t addr ); nkeynes@570: int32_t sh4_read_byte( sh4addr_t addr ); nkeynes@527: void sh4_write_quad( sh4addr_t addr, uint64_t val ); nkeynes@570: void sh4_write_long( sh4addr_t addr, uint32_t val ); nkeynes@570: void sh4_write_word( sh4addr_t addr, uint32_t val ); nkeynes@570: void sh4_write_byte( sh4addr_t addr, uint32_t val ); nkeynes@527: int32_t sh4_read_phys_word( sh4addr_t addr ); nkeynes@527: void sh4_flush_store_queue( sh4addr_t addr ); nkeynes@10: nkeynes@564: /* SH4 Exceptions */ nkeynes@564: #define EXC_POWER_RESET 0x000 /* reset vector */ nkeynes@564: #define EXC_MANUAL_RESET 0x020 /* reset vector */ nkeynes@564: #define EXC_TLB_MISS_READ 0x040 /* TLB vector */ nkeynes@564: #define EXC_TLB_MISS_WRITE 0x060 /* TLB vector */ nkeynes@564: #define EXC_INIT_PAGE_WRITE 0x080 nkeynes@564: #define EXC_TLB_PROT_READ 0x0A0 nkeynes@564: #define EXC_TLB_PROT_WRITE 0x0C0 nkeynes@564: #define EXC_DATA_ADDR_READ 0x0E0 nkeynes@564: #define EXC_DATA_ADDR_WRITE 0x100 nkeynes@564: #define EXC_TLB_MULTI_HIT 0x140 nkeynes@564: #define EXC_SLOT_ILLEGAL 0x1A0 nkeynes@564: #define EXC_ILLEGAL 0x180 nkeynes@564: #define EXC_TRAP 0x160 nkeynes@564: #define EXC_FPU_DISABLED 0x800 nkeynes@564: #define EXC_SLOT_FPU_DISABLED 0x820 nkeynes@374: nkeynes@564: #define EXV_EXCEPTION 0x100 /* General exception vector */ nkeynes@564: #define EXV_TLBMISS 0x400 /* TLB-miss exception vector */ nkeynes@564: #define EXV_INTERRUPT 0x600 /* External interrupt vector */ nkeynes@564: nkeynes@564: gboolean sh4_raise_exception( int ); nkeynes@564: gboolean sh4_raise_reset( int ); nkeynes@564: gboolean sh4_raise_trap( int ); nkeynes@564: gboolean sh4_raise_slot_exception( int, int ); nkeynes@564: gboolean sh4_raise_tlb_exception( int ); nkeynes@564: void sh4_accept_interrupt( void ); nkeynes@1: nkeynes@1: #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28) nkeynes@1: #define SIGNEXT8(n) ((int32_t)((int8_t)(n))) nkeynes@1: #define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20) nkeynes@1: #define SIGNEXT16(n) ((int32_t)((int16_t)(n))) nkeynes@1: #define SIGNEXT32(n) ((int64_t)((int32_t)(n))) nkeynes@1: #define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16) nkeynes@559: #define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n)))) nkeynes@1: nkeynes@1: /* Status Register (SR) bits */ nkeynes@1: #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */ nkeynes@1: #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */ nkeynes@1: #define SR_BL 0x10000000 /* Exception/interupt block (1 = masked) */ nkeynes@1: #define SR_FD 0x00008000 /* FPU disable */ nkeynes@1: #define SR_M 0x00000200 nkeynes@1: #define SR_Q 0x00000100 nkeynes@1: #define SR_IMASK 0x000000F0 /* Interrupt mask level */ nkeynes@1: #define SR_S 0x00000002 /* Saturation operation for MAC instructions */ nkeynes@1: #define SR_T 0x00000001 /* True/false or carry/borrow */ nkeynes@1: #define SR_MASK 0x700083F3 nkeynes@1: #define SR_MQSTMASK 0xFFFFFCFC /* Mask to clear the flags we're keeping separately */ nkeynes@1: nkeynes@1: #define IS_SH4_PRIVMODE() (sh4r.sr&SR_MD) nkeynes@1: #define SH4_INTMASK() ((sh4r.sr&SR_IMASK)>>4) nkeynes@265: #define SH4_EVENT_PENDING() (sh4r.event_pending <= sh4r.slice_cycle && !sh4r.in_delay_slot) nkeynes@1: nkeynes@1: #define FPSCR_FR 0x00200000 /* FPU register bank */ nkeynes@1: #define FPSCR_SZ 0x00100000 /* FPU transfer size (0=32 bits, 1=64 bits) */ nkeynes@1: #define FPSCR_PR 0x00080000 /* Precision (0=32 bites, 1=64 bits) */ nkeynes@1: #define FPSCR_DN 0x00040000 /* Denormalization mode (1 = treat as 0) */ nkeynes@1: #define FPSCR_CAUSE 0x0003F000 nkeynes@1: #define FPSCR_ENABLE 0x00000F80 nkeynes@1: #define FPSCR_FLAG 0x0000007C nkeynes@1: #define FPSCR_RM 0x00000003 /* Rounding mode (0=nearest, 1=to zero) */ nkeynes@1: nkeynes@1: #define IS_FPU_DOUBLEPREC() (sh4r.fpscr&FPSCR_PR) nkeynes@1: #define IS_FPU_DOUBLESIZE() (sh4r.fpscr&FPSCR_SZ) nkeynes@1: #define IS_FPU_ENABLED() ((sh4r.sr&SR_FD)==0) nkeynes@1: nkeynes@374: #define FR(x) sh4r.fr_bank[(x)^1] nkeynes@374: #define DRF(x) ((double *)sh4r.fr_bank)[x] nkeynes@84: #define XF(x) sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][(x)^1] nkeynes@95: #define XDR(x) ((double *)(sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21]))[x] nkeynes@95: #define DRb(x,b) ((double *)(sh4r.fr[((b ? (~sh4r.fpscr) : sh4r.fpscr)&FPSCR_FR)>>21]))[x] nkeynes@359: #define DR(x) DRb((x>>1), (x&1)) nkeynes@359: #define FPULf *((float *)&sh4r.fpul) nkeynes@359: #define FPULi (sh4r.fpul) nkeynes@359: nkeynes@2: #define SH4_WRITE_STORE_QUEUE(addr,val) sh4r.store_queue[(addr>>2)&0xF] = val; nkeynes@1: nkeynes@1: #ifdef __cplusplus nkeynes@1: } nkeynes@1: #endif nkeynes@1: #endif nkeynes@359: