--- a/src/sh4/sh4x86.in	Thu Oct 30 05:50:21 2008 +0000
+++ b/src/sh4/sh4x86.in	Fri Oct 31 02:57:59 2008 +0000
@@ -411,16 +411,6 @@
     assert( IS_IN_ICACHE(pc) );
     ir = *(uint16_t *)GET_ICACHE_PTR(pc);
     
-	/* PC is not in the current icache - this usually means we're running
-	 * with MMU on, and we've gone past the end of the page. And since 
-	 * sh4_translate_block is pretty careful about this, it means we're
-	 * almost certainly in a delay slot.
-	 *
-	 * Since we can't assume the page is present (and we can't fault it in
-	 * at this point, inline a call to sh4_execute_instruction (with a few
-	 * small repairs to cope with the different environment).
-	 */
-
     if( !sh4_x86.in_delay_slot ) {
 	sh4_translate_add_recovery( (pc - sh4_x86.block_start_pc)>>1 );
     }
@@ -444,7 +434,7 @@
 ADDC Rm, Rn {:
     COUNT_INST(I_ADDC);
     if( sh4_x86.tstate != TSTATE_C ) {
-	LDC_t();
+        LDC_t();
     }
     load_reg( R_EAX, Rm );
     load_reg( R_ECX, Rn );
@@ -2567,9 +2557,13 @@
     AND_imm32_r32( 0xFC000000, R_ECX );
     CMP_imm32_r32( 0xE0000000, R_ECX );
     JNE_rel8(end);
-    call_func1( sh4_flush_store_queue, R_EAX );
-    TEST_r32_r32( R_EAX, R_EAX );
-    JE_exc(-1);
+    if( sh4_x86.tlb_on ) {
+    	call_func1( sh4_flush_store_queue_mmu, R_EAX );
+        TEST_r32_r32( R_EAX, R_EAX );
+        JE_exc(-1);
+    } else {
+    	call_func1( sh4_flush_store_queue, R_EAX );
+   	}
     JMP_TARGET(end);
     sh4_x86.tstate = TSTATE_NONE;
 :}