--- a/src/sh4/sh4x86.in Mon Jan 26 07:26:24 2009 +0000 +++ b/src/sh4/sh4x86.in Wed Mar 04 23:12:21 2009 +0000 @@ -26,17 +26,39 @@ #endif #include "lxdream.h" -#include "sh4/xltcache.h" #include "sh4/sh4core.h" #include "sh4/sh4trans.h" #include "sh4/sh4stat.h" #include "sh4/sh4mmio.h" -#include "sh4/x86op.h" #include "sh4/mmu.h" +#include "xlat/xltcache.h" +#include "xlat/x86/x86op.h" #include "clock.h" #define DEFAULT_BACKPATCH_SIZE 4096 +/* Offset of a reg relative to the sh4r structure */ +#define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r) - 128) + +#define R_T REG_OFFSET(t) +#define R_Q REG_OFFSET(q) +#define R_S REG_OFFSET(s) +#define R_M REG_OFFSET(m) +#define R_SR REG_OFFSET(sr) +#define R_GBR REG_OFFSET(gbr) +#define R_SSR REG_OFFSET(ssr) +#define R_SPC REG_OFFSET(spc) +#define R_VBR REG_OFFSET(vbr) +#define R_MACH REG_OFFSET(mac)+4 +#define R_MACL REG_OFFSET(mac) +#define R_PC REG_OFFSET(pc) +#define R_NEW_PC REG_OFFSET(new_pc) +#define R_PR REG_OFFSET(pr) +#define R_SGR REG_OFFSET(sgr) +#define R_FPUL REG_OFFSET(fpul) +#define R_FPSCR REG_OFFSET(fpscr) +#define R_DBR REG_OFFSET(dbr) + struct backpatch_record { uint32_t fixup_offset; uint32_t fixup_icount; @@ -72,32 +94,6 @@ uint32_t backpatch_size; }; -#define TSTATE_NONE -1 -#define TSTATE_O 0 -#define TSTATE_C 2 -#define TSTATE_E 4 -#define TSTATE_NE 5 -#define TSTATE_G 0xF -#define TSTATE_GE 0xD -#define TSTATE_A 7 -#define TSTATE_AE 3 - -#ifdef ENABLE_SH4STATS -#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE -#else -#define COUNT_INST(id) -#endif - -/** Branch if T is set (either in the current cflags, or in sh4r.t) */ -#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \ - CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ - OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1) - -/** Branch if T is clear (either in the current cflags or in sh4r.t) */ -#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \ - CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ - OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1) - static struct sh4_x86_state sh4_x86; static uint32_t max_int = 0x7FFFFFFF; @@ -125,6 +121,12 @@ static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code ) { + int reloc_size = 4; + + if( exc_code == -2 ) { + reloc_size = sizeof(void *); + } + if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) { sh4_x86.backpatch_size <<= 1; sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, @@ -134,106 +136,107 @@ if( sh4_x86.in_delay_slot ) { fixup_pc -= 2; } + sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = - ((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code); + (((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size; sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1; sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code; sh4_x86.backpatch_posn++; } -/** - * Emit an instruction to load an SH4 reg into a real register - */ -static inline void load_reg( int x86reg, int sh4reg ) -{ - /* mov [bp+n], reg */ - OP(0x8B); - OP(0x45 + (x86reg<<3)); - OP(REG_OFFSET(r[sh4reg])); -} +#define TSTATE_NONE -1 +#define TSTATE_O 0 +#define TSTATE_C 2 +#define TSTATE_E 4 +#define TSTATE_NE 5 +#define TSTATE_G 0xF +#define TSTATE_GE 0xD +#define TSTATE_A 7 +#define TSTATE_AE 3 -static inline void load_reg16s( int x86reg, int sh4reg ) -{ - OP(0x0F); - OP(0xBF); - MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg])); -} +#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1) +#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x) -static inline void load_reg16u( int x86reg, int sh4reg ) -{ - OP(0x0F); - OP(0xB7); - MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg])); +/* Convenience instructions */ +#define LDC_t() CMPB_imms_rbpdisp(1,R_T); CMC() +#define SETE_t() SETCCB_cc_rbpdisp(X86_COND_E,R_T) +#define SETA_t() SETCCB_cc_rbpdisp(X86_COND_A,R_T) +#define SETAE_t() SETCCB_cc_rbpdisp(X86_COND_AE,R_T) +#define SETG_t() SETCCB_cc_rbpdisp(X86_COND_G,R_T) +#define SETGE_t() SETCCB_cc_rbpdisp(X86_COND_GE,R_T) +#define SETC_t() SETCCB_cc_rbpdisp(X86_COND_C,R_T) +#define SETO_t() SETCCB_cc_rbpdisp(X86_COND_O,R_T) +#define SETNE_t() SETCCB_cc_rbpdisp(X86_COND_NE,R_T) +#define SETC_r8(r1) SETCCB_cc_r8(X86_COND_C, r1) +#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label) +#define JE_label(label) JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label) +#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label) +#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label) +#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label) +#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label) +#define JS_label(label) JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label) +#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label) +#define JNE_exc(exc) JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc) -} +/** Branch if T is set (either in the current cflags, or in sh4r.t) */ +#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \ + CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ + JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label) -#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg ) -#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff ) -/** - * Emit an instruction to load an immediate value into a register - */ -static inline void load_imm32( int x86reg, uint32_t value ) { - /* mov #value, reg */ - OP(0xB8 + x86reg); - OP32(value); -} +/** Branch if T is clear (either in the current cflags or in sh4r.t) */ +#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \ + CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \ + JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label) - -/** - * Load an immediate 64-bit quantity (note: x86-64 only) - */ -static inline void load_imm64( int x86reg, uint64_t value ) { - /* mov #value, reg */ - REXW(); - OP(0xB8 + x86reg); - OP64(value); -} - -/** - * Emit an instruction to store an SH4 reg (RN) - */ -void static inline store_reg( int x86reg, int sh4reg ) { - /* mov reg, [bp+n] */ - OP(0x89); - OP(0x45 + (x86reg<<3)); - OP(REG_OFFSET(r[sh4reg])); -} +#define load_reg16s(x86reg,sh4reg) MOVSXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg ) +#define load_reg16u(x86reg,sh4reg) MOVZXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg ) +#define load_imm32(x86reg,value) MOVL_imm32_r32(value,x86reg) +#define load_imm64(x86reg,value) MOVQ_imm64_r64(value,x86reg) +#define load_reg(x86reg,sh4reg) MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg ) +#define store_reg(x86reg,sh4reg) MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) ) +#define load_spreg(x86reg, regoff) MOVL_rbpdisp_r32( regoff, x86reg ) +#define store_spreg(x86reg, regoff) MOVL_r32_rbpdisp( x86reg, regoff ) /** * Load an FR register (single-precision floating point) into an integer x86 * register (eg for register-to-register moves) */ -#define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) ) -#define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) ) +#define load_fr(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg ) +#define load_xf(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg ) /** * Load the low half of a DR register (DR or XD) into an integer x86 register */ -#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) ) -#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) ) +#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg ) +#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg ) /** * Store an FR register (single-precision floating point) from an integer x86+ * register (eg for register-to-register moves) */ -#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) ) -#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) ) +#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) ) +#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) ) -#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) ) -#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) ) +#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) ) +#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) ) -#define push_fpul() FLDF_sh4r(R_FPUL) -#define pop_fpul() FSTPF_sh4r(R_FPUL) -#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) ) -#define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) ) -#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) ) -#define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) ) -#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) ) -#define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) ) -#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) ) -#define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) ) +#define push_fpul() FLDF_rbpdisp(R_FPUL) +#define pop_fpul() FSTPF_rbpdisp(R_FPUL) +#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) ) +#define pop_fr(frm) FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) ) +#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) ) +#define pop_xf(frm) FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) ) +#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) ) +#define pop_dr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) ) +#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) ) +#define pop_xdr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) ) +#ifdef ENABLE_SH4STATS +#define COUNT_INST(id) load_imm32(REG_EAX,id); call_func1(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE +#else +#define COUNT_INST(id) +#endif /* Exception checks - Note that all exception checks will clobber EAX */ @@ -253,8 +256,8 @@ #define check_fpuen( ) \ if( !sh4_x86.fpuen_checked ) {\ sh4_x86.fpuen_checked = TRUE;\ - load_spreg( R_EAX, R_SR );\ - AND_imm32_r32( SR_FD, R_EAX );\ + load_spreg( REG_EAX, R_SR );\ + ANDL_imms_r32( SR_FD, REG_EAX );\ if( sh4_x86.in_delay_slot ) {\ JNE_exc(EXC_SLOT_FPU_DISABLED);\ } else {\ @@ -264,46 +267,46 @@ } #define check_ralign16( x86reg ) \ - TEST_imm32_r32( 0x00000001, x86reg ); \ + TESTL_imms_r32( 0x00000001, x86reg ); \ JNE_exc(EXC_DATA_ADDR_READ) #define check_walign16( x86reg ) \ - TEST_imm32_r32( 0x00000001, x86reg ); \ + TESTL_imms_r32( 0x00000001, x86reg ); \ JNE_exc(EXC_DATA_ADDR_WRITE); #define check_ralign32( x86reg ) \ - TEST_imm32_r32( 0x00000003, x86reg ); \ + TESTL_imms_r32( 0x00000003, x86reg ); \ JNE_exc(EXC_DATA_ADDR_READ) #define check_walign32( x86reg ) \ - TEST_imm32_r32( 0x00000003, x86reg ); \ + TESTL_imms_r32( 0x00000003, x86reg ); \ JNE_exc(EXC_DATA_ADDR_WRITE); #define check_ralign64( x86reg ) \ - TEST_imm32_r32( 0x00000007, x86reg ); \ + TESTL_imms_r32( 0x00000007, x86reg ); \ JNE_exc(EXC_DATA_ADDR_READ) #define check_walign64( x86reg ) \ - TEST_imm32_r32( 0x00000007, x86reg ); \ + TESTL_imms_r32( 0x00000007, x86reg ); \ JNE_exc(EXC_DATA_ADDR_WRITE); #define UNDEF(ir) #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name ) -#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); } +#define MEM_RESULT(value_reg) if(value_reg != REG_EAX) { MOVL_r32_r32(REG_EAX,value_reg); } /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so * don't waste the cycles expecting them. Otherwise we need to save the exception pointer. */ #ifdef HAVE_FRAME_ADDRESS #define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \ - call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \ - call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } + call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \ + call_func1_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } #define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \ - call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \ - call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); } + call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \ + call_func2_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); } #else -#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg) -#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg) +#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg) +#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg) #endif #define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg) @@ -354,8 +357,8 @@ */ void sh4_translate_emit_breakpoint( sh4vma_t pc ) { - load_imm32( R_EAX, pc ); - call_func1( sh4_translate_breakpoint_hit, R_EAX ); + load_imm32( REG_EAX, pc ); + call_func1( sh4_translate_breakpoint_hit, REG_EAX ); sh4_x86.tstate = TSTATE_NONE; } @@ -376,20 +379,20 @@ */ void exit_block_emu( sh4vma_t endpc ) { - load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 5 - ADD_r32_sh4r( R_ECX, R_PC ); + load_imm32( REG_ECX, endpc - sh4_x86.block_start_pc ); // 5 + ADDL_r32_rbpdisp( REG_ECX, R_PC ); - load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 6 - load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 ); - store_spreg( R_ECX, REG_OFFSET(in_delay_slot) ); + load_imm32( REG_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 6 + load_imm32( REG_ECX, sh4_x86.in_delay_slot ? 1 : 0 ); + store_spreg( REG_ECX, REG_OFFSET(in_delay_slot) ); call_func0( sh4_execute_instruction ); - load_spreg( R_EAX, R_PC ); + load_spreg( REG_EAX, R_PC ); if( sh4_x86.tlb_on ) { - call_func1(xlat_get_code_by_vma,R_EAX); + call_func1(xlat_get_code_by_vma,REG_EAX); } else { - call_func1(xlat_get_code,R_EAX); + call_func1(xlat_get_code,REG_EAX); } exit_block(); } @@ -417,15 +420,15 @@ /* ALU operations */ ADD Rm, Rn {: COUNT_INST(I_ADD); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - ADD_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + ADDL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} ADD #imm, Rn {: COUNT_INST(I_ADDI); - ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) ); + ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} ADDC Rm, Rn {: @@ -433,122 +436,122 @@ if( sh4_x86.tstate != TSTATE_C ) { LDC_t(); } - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - ADC_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + ADCL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); SETC_t(); sh4_x86.tstate = TSTATE_C; :} ADDV Rm, Rn {: COUNT_INST(I_ADDV); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - ADD_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + ADDL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); SETO_t(); sh4_x86.tstate = TSTATE_O; :} AND Rm, Rn {: COUNT_INST(I_AND); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - AND_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + ANDL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} AND #imm, R0 {: COUNT_INST(I_ANDI); - load_reg( R_EAX, 0 ); - AND_imm32_r32(imm, R_EAX); - store_reg( R_EAX, 0 ); + load_reg( REG_EAX, 0 ); + ANDL_imms_r32(imm, REG_EAX); + store_reg( REG_EAX, 0 ); sh4_x86.tstate = TSTATE_NONE; :} AND.B #imm, @(R0, GBR) {: COUNT_INST(I_ANDB); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( R_GBR, R_EAX ); - MOV_r32_esp8(R_EAX, 0); - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX ); - MOV_esp8_r32(0, R_EAX); - AND_imm32_r32(imm, R_EDX ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( R_GBR, REG_EAX ); + MOVL_r32_rspdisp(REG_EAX, 0); + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); + MOVL_rspdisp_r32(0, REG_EAX); + ANDL_imms_r32(imm, REG_EDX ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} CMP/EQ Rm, Rn {: COUNT_INST(I_CMPEQ); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - CMP_r32_r32( R_EAX, R_ECX ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + CMPL_r32_r32( REG_EAX, REG_ECX ); SETE_t(); sh4_x86.tstate = TSTATE_E; :} CMP/EQ #imm, R0 {: COUNT_INST(I_CMPEQI); - load_reg( R_EAX, 0 ); - CMP_imm8s_r32(imm, R_EAX); + load_reg( REG_EAX, 0 ); + CMPL_imms_r32(imm, REG_EAX); SETE_t(); sh4_x86.tstate = TSTATE_E; :} CMP/GE Rm, Rn {: COUNT_INST(I_CMPGE); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - CMP_r32_r32( R_EAX, R_ECX ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + CMPL_r32_r32( REG_EAX, REG_ECX ); SETGE_t(); sh4_x86.tstate = TSTATE_GE; :} CMP/GT Rm, Rn {: COUNT_INST(I_CMPGT); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - CMP_r32_r32( R_EAX, R_ECX ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + CMPL_r32_r32( REG_EAX, REG_ECX ); SETG_t(); sh4_x86.tstate = TSTATE_G; :} CMP/HI Rm, Rn {: COUNT_INST(I_CMPHI); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - CMP_r32_r32( R_EAX, R_ECX ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + CMPL_r32_r32( REG_EAX, REG_ECX ); SETA_t(); sh4_x86.tstate = TSTATE_A; :} CMP/HS Rm, Rn {: COUNT_INST(I_CMPHS); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - CMP_r32_r32( R_EAX, R_ECX ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + CMPL_r32_r32( REG_EAX, REG_ECX ); SETAE_t(); sh4_x86.tstate = TSTATE_AE; :} CMP/PL Rn {: COUNT_INST(I_CMPPL); - load_reg( R_EAX, Rn ); - CMP_imm8s_r32( 0, R_EAX ); + load_reg( REG_EAX, Rn ); + CMPL_imms_r32( 0, REG_EAX ); SETG_t(); sh4_x86.tstate = TSTATE_G; :} CMP/PZ Rn {: COUNT_INST(I_CMPPZ); - load_reg( R_EAX, Rn ); - CMP_imm8s_r32( 0, R_EAX ); + load_reg( REG_EAX, Rn ); + CMPL_imms_r32( 0, REG_EAX ); SETGE_t(); sh4_x86.tstate = TSTATE_GE; :} CMP/STR Rm, Rn {: COUNT_INST(I_CMPSTR); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - XOR_r32_r32( R_ECX, R_EAX ); - TEST_r8_r8( R_AL, R_AL ); - JE_rel8(target1); - TEST_r8_r8( R_AH, R_AH ); - JE_rel8(target2); - SHR_imm8_r32( 16, R_EAX ); - TEST_r8_r8( R_AL, R_AL ); - JE_rel8(target3); - TEST_r8_r8( R_AH, R_AH ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + XORL_r32_r32( REG_ECX, REG_EAX ); + TESTB_r8_r8( REG_AL, REG_AL ); + JE_label(target1); + TESTB_r8_r8( REG_AH, REG_AH ); + JE_label(target2); + SHRL_imm_r32( 16, REG_EAX ); + TESTB_r8_r8( REG_AL, REG_AL ); + JE_label(target3); + TESTB_r8_r8( REG_AH, REG_AH ); JMP_TARGET(target1); JMP_TARGET(target2); JMP_TARGET(target3); @@ -557,130 +560,130 @@ :} DIV0S Rm, Rn {: COUNT_INST(I_DIV0S); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - SHR_imm8_r32( 31, R_EAX ); - SHR_imm8_r32( 31, R_ECX ); - store_spreg( R_EAX, R_M ); - store_spreg( R_ECX, R_Q ); - CMP_r32_r32( R_EAX, R_ECX ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + SHRL_imm_r32( 31, REG_EAX ); + SHRL_imm_r32( 31, REG_ECX ); + store_spreg( REG_EAX, R_M ); + store_spreg( REG_ECX, R_Q ); + CMPL_r32_r32( REG_EAX, REG_ECX ); SETNE_t(); sh4_x86.tstate = TSTATE_NE; :} DIV0U {: COUNT_INST(I_DIV0U); - XOR_r32_r32( R_EAX, R_EAX ); - store_spreg( R_EAX, R_Q ); - store_spreg( R_EAX, R_M ); - store_spreg( R_EAX, R_T ); + XORL_r32_r32( REG_EAX, REG_EAX ); + store_spreg( REG_EAX, R_Q ); + store_spreg( REG_EAX, R_M ); + store_spreg( REG_EAX, R_T ); sh4_x86.tstate = TSTATE_C; // works for DIV1 :} DIV1 Rm, Rn {: COUNT_INST(I_DIV1); - load_spreg( R_ECX, R_M ); - load_reg( R_EAX, Rn ); + load_spreg( REG_ECX, R_M ); + load_reg( REG_EAX, Rn ); if( sh4_x86.tstate != TSTATE_C ) { LDC_t(); } - RCL1_r32( R_EAX ); - SETC_r8( R_DL ); // Q' - CMP_sh4r_r32( R_Q, R_ECX ); - JE_rel8(mqequal); - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX ); - JMP_rel8(end); + RCLL_imm_r32( 1, REG_EAX ); + SETC_r8( REG_DL ); // Q' + CMPL_rbpdisp_r32( R_Q, REG_ECX ); + JE_label(mqequal); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); + JMP_label(end); JMP_TARGET(mqequal); - SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX ); + SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); JMP_TARGET(end); - store_reg( R_EAX, Rn ); // Done with Rn now - SETC_r8(R_AL); // tmp1 - XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1 - XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M - store_spreg( R_ECX, R_Q ); - XOR_imm8s_r32( 1, R_AL ); // T = !Q' - MOVZX_r8_r32( R_AL, R_EAX ); - store_spreg( R_EAX, R_T ); + store_reg( REG_EAX, Rn ); // Done with Rn now + SETC_r8(REG_AL); // tmp1 + XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1 + XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M + store_spreg( REG_ECX, R_Q ); + XORL_imms_r32( 1, REG_AL ); // T = !Q' + MOVZXL_r8_r32( REG_AL, REG_EAX ); + store_spreg( REG_EAX, R_T ); sh4_x86.tstate = TSTATE_NONE; :} DMULS.L Rm, Rn {: COUNT_INST(I_DMULS); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - IMUL_r32(R_ECX); - store_spreg( R_EDX, R_MACH ); - store_spreg( R_EAX, R_MACL ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + IMULL_r32(REG_ECX); + store_spreg( REG_EDX, R_MACH ); + store_spreg( REG_EAX, R_MACL ); sh4_x86.tstate = TSTATE_NONE; :} DMULU.L Rm, Rn {: COUNT_INST(I_DMULU); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - MUL_r32(R_ECX); - store_spreg( R_EDX, R_MACH ); - store_spreg( R_EAX, R_MACL ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + MULL_r32(REG_ECX); + store_spreg( REG_EDX, R_MACH ); + store_spreg( REG_EAX, R_MACL ); sh4_x86.tstate = TSTATE_NONE; :} DT Rn {: COUNT_INST(I_DT); - load_reg( R_EAX, Rn ); - ADD_imm8s_r32( -1, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + ADDL_imms_r32( -1, REG_EAX ); + store_reg( REG_EAX, Rn ); SETE_t(); sh4_x86.tstate = TSTATE_E; :} EXTS.B Rm, Rn {: COUNT_INST(I_EXTSB); - load_reg( R_EAX, Rm ); - MOVSX_r8_r32( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + MOVSXL_r8_r32( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); :} EXTS.W Rm, Rn {: COUNT_INST(I_EXTSW); - load_reg( R_EAX, Rm ); - MOVSX_r16_r32( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + MOVSXL_r16_r32( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); :} EXTU.B Rm, Rn {: COUNT_INST(I_EXTUB); - load_reg( R_EAX, Rm ); - MOVZX_r8_r32( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + MOVZXL_r8_r32( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); :} EXTU.W Rm, Rn {: COUNT_INST(I_EXTUW); - load_reg( R_EAX, Rm ); - MOVZX_r16_r32( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + MOVZXL_r16_r32( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); :} MAC.L @Rm+, @Rn+ {: COUNT_INST(I_MACL); if( Rm == Rn ) { - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - MOV_r32_esp8(R_EAX, 0); - load_reg( R_EAX, Rm ); - LEA_r32disp8_r32( R_EAX, 4, R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + MOVL_r32_rspdisp(REG_EAX, 0); + load_reg( REG_EAX, Rm ); + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) ); } else { - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - MOV_r32_esp8( R_EAX, 0 ); - load_reg( R_EAX, Rn ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + MOVL_r32_rspdisp( REG_EAX, 0 ); + load_reg( REG_EAX, Rn ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); } - IMUL_esp8( 0 ); - ADD_r32_sh4r( R_EAX, R_MACL ); - ADC_r32_sh4r( R_EDX, R_MACH ); + IMULL_rspdisp( 0 ); + ADDL_r32_rbpdisp( REG_EAX, R_MACL ); + ADCL_r32_rbpdisp( REG_EDX, R_MACH ); - load_spreg( R_ECX, R_S ); - TEST_r32_r32(R_ECX, R_ECX); - JE_rel8( nosat ); + load_spreg( REG_ECX, R_S ); + TESTL_r32_r32(REG_ECX, REG_ECX); + JE_label( nosat ); call_func0( signsat48 ); JMP_TARGET( nosat ); sh4_x86.tstate = TSTATE_NONE; @@ -688,49 +691,49 @@ MAC.W @Rm+, @Rn+ {: COUNT_INST(I_MACW); if( Rm == Rn ) { - load_reg( R_EAX, Rm ); - check_ralign16( R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); - MOV_r32_esp8( R_EAX, 0 ); - load_reg( R_EAX, Rm ); - LEA_r32disp8_r32( R_EAX, 2, R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rm ); + check_ralign16( REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); + MOVL_r32_rspdisp( REG_EAX, 0 ); + load_reg( REG_EAX, Rm ); + LEAL_r32disp_r32( REG_EAX, 2, REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) ); // Note translate twice in case of page boundaries. Maybe worth // adding a page-boundary check to skip the second translation } else { - load_reg( R_EAX, Rm ); - check_ralign16( R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); - MOV_r32_esp8( R_EAX, 0 ); - load_reg( R_EAX, Rn ); - check_ralign16( R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) ); - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) ); + load_reg( REG_EAX, Rm ); + check_ralign16( REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); + MOVL_r32_rspdisp( REG_EAX, 0 ); + load_reg( REG_EAX, Rn ); + check_ralign16( REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) ); + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) ); } - IMUL_esp8( 0 ); - load_spreg( R_ECX, R_S ); - TEST_r32_r32( R_ECX, R_ECX ); - JE_rel8( nosat ); + IMULL_rspdisp( 0 ); + load_spreg( REG_ECX, R_S ); + TESTL_r32_r32( REG_ECX, REG_ECX ); + JE_label( nosat ); - ADD_r32_sh4r( R_EAX, R_MACL ); // 6 - JNO_rel8( end ); // 2 - load_imm32( R_EDX, 1 ); // 5 - store_spreg( R_EDX, R_MACH ); // 6 - JS_rel8( positive ); // 2 - load_imm32( R_EAX, 0x80000000 );// 5 - store_spreg( R_EAX, R_MACL ); // 6 - JMP_rel8(end2); // 2 + ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 + JNO_label( end ); // 2 + load_imm32( REG_EDX, 1 ); // 5 + store_spreg( REG_EDX, R_MACH ); // 6 + JS_label( positive ); // 2 + load_imm32( REG_EAX, 0x80000000 );// 5 + store_spreg( REG_EAX, R_MACL ); // 6 + JMP_label(end2); // 2 JMP_TARGET(positive); - load_imm32( R_EAX, 0x7FFFFFFF );// 5 - store_spreg( R_EAX, R_MACL ); // 6 - JMP_rel8(end3); // 2 + load_imm32( REG_EAX, 0x7FFFFFFF );// 5 + store_spreg( REG_EAX, R_MACL ); // 6 + JMP_label(end3); // 2 JMP_TARGET(nosat); - ADD_r32_sh4r( R_EAX, R_MACL ); // 6 - ADC_r32_sh4r( R_EDX, R_MACH ); // 6 + ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 6 + ADCL_r32_rbpdisp( REG_EDX, R_MACH ); // 6 JMP_TARGET(end); JMP_TARGET(end2); JMP_TARGET(end3); @@ -738,556 +741,556 @@ :} MOVT Rn {: COUNT_INST(I_MOVT); - load_spreg( R_EAX, R_T ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_T ); + store_reg( REG_EAX, Rn ); :} MUL.L Rm, Rn {: COUNT_INST(I_MULL); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - MUL_r32( R_ECX ); - store_spreg( R_EAX, R_MACL ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + MULL_r32( REG_ECX ); + store_spreg( REG_EAX, R_MACL ); sh4_x86.tstate = TSTATE_NONE; :} MULS.W Rm, Rn {: COUNT_INST(I_MULSW); - load_reg16s( R_EAX, Rm ); - load_reg16s( R_ECX, Rn ); - MUL_r32( R_ECX ); - store_spreg( R_EAX, R_MACL ); + load_reg16s( REG_EAX, Rm ); + load_reg16s( REG_ECX, Rn ); + MULL_r32( REG_ECX ); + store_spreg( REG_EAX, R_MACL ); sh4_x86.tstate = TSTATE_NONE; :} MULU.W Rm, Rn {: COUNT_INST(I_MULUW); - load_reg16u( R_EAX, Rm ); - load_reg16u( R_ECX, Rn ); - MUL_r32( R_ECX ); - store_spreg( R_EAX, R_MACL ); + load_reg16u( REG_EAX, Rm ); + load_reg16u( REG_ECX, Rn ); + MULL_r32( REG_ECX ); + store_spreg( REG_EAX, R_MACL ); sh4_x86.tstate = TSTATE_NONE; :} NEG Rm, Rn {: COUNT_INST(I_NEG); - load_reg( R_EAX, Rm ); - NEG_r32( R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + NEGL_r32( REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} NEGC Rm, Rn {: COUNT_INST(I_NEGC); - load_reg( R_EAX, Rm ); - XOR_r32_r32( R_ECX, R_ECX ); + load_reg( REG_EAX, Rm ); + XORL_r32_r32( REG_ECX, REG_ECX ); LDC_t(); - SBB_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + SBBL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); SETC_t(); sh4_x86.tstate = TSTATE_C; :} NOT Rm, Rn {: COUNT_INST(I_NOT); - load_reg( R_EAX, Rm ); - NOT_r32( R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + NOTL_r32( REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} OR Rm, Rn {: COUNT_INST(I_OR); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - OR_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + ORL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} OR #imm, R0 {: COUNT_INST(I_ORI); - load_reg( R_EAX, 0 ); - OR_imm32_r32(imm, R_EAX); - store_reg( R_EAX, 0 ); + load_reg( REG_EAX, 0 ); + ORL_imms_r32(imm, REG_EAX); + store_reg( REG_EAX, 0 ); sh4_x86.tstate = TSTATE_NONE; :} OR.B #imm, @(R0, GBR) {: COUNT_INST(I_ORB); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( R_GBR, R_EAX ); - MOV_r32_esp8( R_EAX, 0 ); - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX ); - MOV_esp8_r32( 0, R_EAX ); - OR_imm32_r32(imm, R_EDX ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( R_GBR, REG_EAX ); + MOVL_r32_rspdisp( REG_EAX, 0 ); + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); + MOVL_rspdisp_r32( 0, REG_EAX ); + ORL_imms_r32(imm, REG_EDX ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} ROTCL Rn {: COUNT_INST(I_ROTCL); - load_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); if( sh4_x86.tstate != TSTATE_C ) { LDC_t(); } - RCL1_r32( R_EAX ); - store_reg( R_EAX, Rn ); + RCLL_imm_r32( 1, REG_EAX ); + store_reg( REG_EAX, Rn ); SETC_t(); sh4_x86.tstate = TSTATE_C; :} ROTCR Rn {: COUNT_INST(I_ROTCR); - load_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); if( sh4_x86.tstate != TSTATE_C ) { LDC_t(); } - RCR1_r32( R_EAX ); - store_reg( R_EAX, Rn ); + RCRL_imm_r32( 1, REG_EAX ); + store_reg( REG_EAX, Rn ); SETC_t(); sh4_x86.tstate = TSTATE_C; :} ROTL Rn {: COUNT_INST(I_ROTL); - load_reg( R_EAX, Rn ); - ROL1_r32( R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + ROLL_imm_r32( 1, REG_EAX ); + store_reg( REG_EAX, Rn ); SETC_t(); sh4_x86.tstate = TSTATE_C; :} ROTR Rn {: COUNT_INST(I_ROTR); - load_reg( R_EAX, Rn ); - ROR1_r32( R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + RORL_imm_r32( 1, REG_EAX ); + store_reg( REG_EAX, Rn ); SETC_t(); sh4_x86.tstate = TSTATE_C; :} SHAD Rm, Rn {: COUNT_INST(I_SHAD); /* Annoyingly enough, not directly convertible */ - load_reg( R_EAX, Rn ); - load_reg( R_ECX, Rm ); - CMP_imm32_r32( 0, R_ECX ); - JGE_rel8(doshl); + load_reg( REG_EAX, Rn ); + load_reg( REG_ECX, Rm ); + CMPL_imms_r32( 0, REG_ECX ); + JGE_label(doshl); - NEG_r32( R_ECX ); // 2 - AND_imm8_r8( 0x1F, R_CL ); // 3 - JE_rel8(emptysar); // 2 - SAR_r32_CL( R_EAX ); // 2 - JMP_rel8(end); // 2 + NEGL_r32( REG_ECX ); // 2 + ANDB_imms_r8( 0x1F, REG_CL ); // 3 + JE_label(emptysar); // 2 + SARL_cl_r32( REG_EAX ); // 2 + JMP_label(end); // 2 JMP_TARGET(emptysar); - SAR_imm8_r32(31, R_EAX ); // 3 - JMP_rel8(end2); + SARL_imm_r32(31, REG_EAX ); // 3 + JMP_label(end2); JMP_TARGET(doshl); - AND_imm8_r8( 0x1F, R_CL ); // 3 - SHL_r32_CL( R_EAX ); // 2 + ANDB_imms_r8( 0x1F, REG_CL ); // 3 + SHLL_cl_r32( REG_EAX ); // 2 JMP_TARGET(end); JMP_TARGET(end2); - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SHLD Rm, Rn {: COUNT_INST(I_SHLD); - load_reg( R_EAX, Rn ); - load_reg( R_ECX, Rm ); - CMP_imm32_r32( 0, R_ECX ); - JGE_rel8(doshl); + load_reg( REG_EAX, Rn ); + load_reg( REG_ECX, Rm ); + CMPL_imms_r32( 0, REG_ECX ); + JGE_label(doshl); - NEG_r32( R_ECX ); // 2 - AND_imm8_r8( 0x1F, R_CL ); // 3 - JE_rel8(emptyshr ); - SHR_r32_CL( R_EAX ); // 2 - JMP_rel8(end); // 2 + NEGL_r32( REG_ECX ); // 2 + ANDB_imms_r8( 0x1F, REG_CL ); // 3 + JE_label(emptyshr ); + SHRL_cl_r32( REG_EAX ); // 2 + JMP_label(end); // 2 JMP_TARGET(emptyshr); - XOR_r32_r32( R_EAX, R_EAX ); - JMP_rel8(end2); + XORL_r32_r32( REG_EAX, REG_EAX ); + JMP_label(end2); JMP_TARGET(doshl); - AND_imm8_r8( 0x1F, R_CL ); // 3 - SHL_r32_CL( R_EAX ); // 2 + ANDB_imms_r8( 0x1F, REG_CL ); // 3 + SHLL_cl_r32( REG_EAX ); // 2 JMP_TARGET(end); JMP_TARGET(end2); - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SHAL Rn {: COUNT_INST(I_SHAL); - load_reg( R_EAX, Rn ); - SHL1_r32( R_EAX ); + load_reg( REG_EAX, Rn ); + SHLL_imm_r32( 1, REG_EAX ); SETC_t(); - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_C; :} SHAR Rn {: COUNT_INST(I_SHAR); - load_reg( R_EAX, Rn ); - SAR1_r32( R_EAX ); + load_reg( REG_EAX, Rn ); + SARL_imm_r32( 1, REG_EAX ); SETC_t(); - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_C; :} SHLL Rn {: COUNT_INST(I_SHLL); - load_reg( R_EAX, Rn ); - SHL1_r32( R_EAX ); + load_reg( REG_EAX, Rn ); + SHLL_imm_r32( 1, REG_EAX ); SETC_t(); - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_C; :} SHLL2 Rn {: COUNT_INST(I_SHLL); - load_reg( R_EAX, Rn ); - SHL_imm8_r32( 2, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + SHLL_imm_r32( 2, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SHLL8 Rn {: COUNT_INST(I_SHLL); - load_reg( R_EAX, Rn ); - SHL_imm8_r32( 8, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + SHLL_imm_r32( 8, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SHLL16 Rn {: COUNT_INST(I_SHLL); - load_reg( R_EAX, Rn ); - SHL_imm8_r32( 16, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + SHLL_imm_r32( 16, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SHLR Rn {: COUNT_INST(I_SHLR); - load_reg( R_EAX, Rn ); - SHR1_r32( R_EAX ); + load_reg( REG_EAX, Rn ); + SHRL_imm_r32( 1, REG_EAX ); SETC_t(); - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_C; :} SHLR2 Rn {: COUNT_INST(I_SHLR); - load_reg( R_EAX, Rn ); - SHR_imm8_r32( 2, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + SHRL_imm_r32( 2, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SHLR8 Rn {: COUNT_INST(I_SHLR); - load_reg( R_EAX, Rn ); - SHR_imm8_r32( 8, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + SHRL_imm_r32( 8, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SHLR16 Rn {: COUNT_INST(I_SHLR); - load_reg( R_EAX, Rn ); - SHR_imm8_r32( 16, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); + SHRL_imm_r32( 16, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SUB Rm, Rn {: COUNT_INST(I_SUB); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - SUB_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + SUBL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} SUBC Rm, Rn {: COUNT_INST(I_SUBC); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); if( sh4_x86.tstate != TSTATE_C ) { LDC_t(); } - SBB_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + SBBL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); SETC_t(); sh4_x86.tstate = TSTATE_C; :} SUBV Rm, Rn {: COUNT_INST(I_SUBV); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - SUB_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + SUBL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); SETO_t(); sh4_x86.tstate = TSTATE_O; :} SWAP.B Rm, Rn {: COUNT_INST(I_SWAPB); - load_reg( R_EAX, Rm ); - XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS + store_reg( REG_EAX, Rn ); :} SWAP.W Rm, Rn {: COUNT_INST(I_SWAPB); - load_reg( R_EAX, Rm ); - MOV_r32_r32( R_EAX, R_ECX ); - SHL_imm8_r32( 16, R_ECX ); - SHR_imm8_r32( 16, R_EAX ); - OR_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + MOVL_r32_r32( REG_EAX, REG_ECX ); + SHLL_imm_r32( 16, REG_ECX ); + SHRL_imm_r32( 16, REG_EAX ); + ORL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} TAS.B @Rn {: COUNT_INST(I_TASB); - load_reg( R_EAX, Rn ); - MOV_r32_esp8( R_EAX, 0 ); - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX ); - TEST_r8_r8( R_DL, R_DL ); + load_reg( REG_EAX, Rn ); + MOVL_r32_rspdisp( REG_EAX, 0 ); + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX ); + TESTB_r8_r8( REG_DL, REG_DL ); SETE_t(); - OR_imm8_r8( 0x80, R_DL ); - MOV_esp8_r32( 0, R_EAX ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); + ORB_imms_r8( 0x80, REG_DL ); + MOVL_rspdisp_r32( 0, REG_EAX ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} TST Rm, Rn {: COUNT_INST(I_TST); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - TEST_r32_r32( R_EAX, R_ECX ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + TESTL_r32_r32( REG_EAX, REG_ECX ); SETE_t(); sh4_x86.tstate = TSTATE_E; :} TST #imm, R0 {: COUNT_INST(I_TSTI); - load_reg( R_EAX, 0 ); - TEST_imm32_r32( imm, R_EAX ); + load_reg( REG_EAX, 0 ); + TESTL_imms_r32( imm, REG_EAX ); SETE_t(); sh4_x86.tstate = TSTATE_E; :} TST.B #imm, @(R0, GBR) {: COUNT_INST(I_TSTB); - load_reg( R_EAX, 0); - ADD_sh4r_r32( R_GBR, R_EAX ); - MEM_READ_BYTE( R_EAX, R_EAX ); - TEST_imm8_r8( imm, R_AL ); + load_reg( REG_EAX, 0); + ADDL_rbpdisp_r32( R_GBR, REG_EAX ); + MEM_READ_BYTE( REG_EAX, REG_EAX ); + TESTB_imms_r8( imm, REG_AL ); SETE_t(); sh4_x86.tstate = TSTATE_E; :} XOR Rm, Rn {: COUNT_INST(I_XOR); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - XOR_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + XORL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} XOR #imm, R0 {: COUNT_INST(I_XORI); - load_reg( R_EAX, 0 ); - XOR_imm32_r32( imm, R_EAX ); - store_reg( R_EAX, 0 ); + load_reg( REG_EAX, 0 ); + XORL_imms_r32( imm, REG_EAX ); + store_reg( REG_EAX, 0 ); sh4_x86.tstate = TSTATE_NONE; :} XOR.B #imm, @(R0, GBR) {: COUNT_INST(I_XORB); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( R_GBR, R_EAX ); - MOV_r32_esp8( R_EAX, 0 ); - MEM_READ_BYTE_FOR_WRITE(R_EAX, R_EDX); - MOV_esp8_r32( 0, R_EAX ); - XOR_imm32_r32( imm, R_EDX ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( R_GBR, REG_EAX ); + MOVL_r32_rspdisp( REG_EAX, 0 ); + MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX); + MOVL_rspdisp_r32( 0, REG_EAX ); + XORL_imms_r32( imm, REG_EDX ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} XTRCT Rm, Rn {: COUNT_INST(I_XTRCT); - load_reg( R_EAX, Rm ); - load_reg( R_ECX, Rn ); - SHL_imm8_r32( 16, R_EAX ); - SHR_imm8_r32( 16, R_ECX ); - OR_r32_r32( R_EAX, R_ECX ); - store_reg( R_ECX, Rn ); + load_reg( REG_EAX, Rm ); + load_reg( REG_ECX, Rn ); + SHLL_imm_r32( 16, REG_EAX ); + SHRL_imm_r32( 16, REG_ECX ); + ORL_r32_r32( REG_EAX, REG_ECX ); + store_reg( REG_ECX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} /* Data move instructions */ MOV Rm, Rn {: COUNT_INST(I_MOV); - load_reg( R_EAX, Rm ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + store_reg( REG_EAX, Rn ); :} MOV #imm, Rn {: COUNT_INST(I_MOVI); - load_imm32( R_EAX, imm ); - store_reg( R_EAX, Rn ); + load_imm32( REG_EAX, imm ); + store_reg( REG_EAX, Rn ); :} MOV.B Rm, @Rn {: COUNT_INST(I_MOVB); - load_reg( R_EAX, Rn ); - load_reg( R_EDX, Rm ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); + load_reg( REG_EAX, Rn ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B Rm, @-Rn {: COUNT_INST(I_MOVB); - load_reg( R_EAX, Rn ); - LEA_r32disp8_r32( R_EAX, -1, R_EAX ); - load_reg( R_EDX, Rm ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + LEAL_r32disp_r32( REG_EAX, -1, REG_EAX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B Rm, @(R0, Rn) {: COUNT_INST(I_MOVB); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX ); - load_reg( R_EDX, Rm ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B R0, @(disp, GBR) {: COUNT_INST(I_MOVB); - load_spreg( R_EAX, R_GBR ); - ADD_imm32_r32( disp, R_EAX ); - load_reg( R_EDX, 0 ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); + load_spreg( REG_EAX, R_GBR ); + ADDL_imms_r32( disp, REG_EAX ); + load_reg( REG_EDX, 0 ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B R0, @(disp, Rn) {: COUNT_INST(I_MOVB); - load_reg( R_EAX, Rn ); - ADD_imm32_r32( disp, R_EAX ); - load_reg( R_EDX, 0 ); - MEM_WRITE_BYTE( R_EAX, R_EDX ); + load_reg( REG_EAX, Rn ); + ADDL_imms_r32( disp, REG_EAX ); + load_reg( REG_EDX, 0 ); + MEM_WRITE_BYTE( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B @Rm, Rn {: COUNT_INST(I_MOVB); - load_reg( R_EAX, Rm ); - MEM_READ_BYTE( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + MEM_READ_BYTE( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B @Rm+, Rn {: COUNT_INST(I_MOVB); - load_reg( R_EAX, Rm ); - MEM_READ_BYTE( R_EAX, R_EAX ); + load_reg( REG_EAX, Rm ); + MEM_READ_BYTE( REG_EAX, REG_EAX ); if( Rm != Rn ) { - ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) ); + ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) ); } - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B @(R0, Rm), Rn {: COUNT_INST(I_MOVB); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX ); - MEM_READ_BYTE( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); + MEM_READ_BYTE( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B @(disp, GBR), R0 {: COUNT_INST(I_MOVB); - load_spreg( R_EAX, R_GBR ); - ADD_imm32_r32( disp, R_EAX ); - MEM_READ_BYTE( R_EAX, R_EAX ); - store_reg( R_EAX, 0 ); + load_spreg( REG_EAX, R_GBR ); + ADDL_imms_r32( disp, REG_EAX ); + MEM_READ_BYTE( REG_EAX, REG_EAX ); + store_reg( REG_EAX, 0 ); sh4_x86.tstate = TSTATE_NONE; :} MOV.B @(disp, Rm), R0 {: COUNT_INST(I_MOVB); - load_reg( R_EAX, Rm ); - ADD_imm32_r32( disp, R_EAX ); - MEM_READ_BYTE( R_EAX, R_EAX ); - store_reg( R_EAX, 0 ); + load_reg( REG_EAX, Rm ); + ADDL_imms_r32( disp, REG_EAX ); + MEM_READ_BYTE( REG_EAX, REG_EAX ); + store_reg( REG_EAX, 0 ); sh4_x86.tstate = TSTATE_NONE; :} MOV.L Rm, @Rn {: COUNT_INST(I_MOVL); - load_reg( R_EAX, Rn ); - check_walign32(R_EAX); - MOV_r32_r32( R_EAX, R_ECX ); - AND_imm32_r32( 0xFC000000, R_ECX ); - CMP_imm32_r32( 0xE0000000, R_ECX ); - JNE_rel8( notsq ); - AND_imm8s_r32( 0x3C, R_EAX ); - load_reg( R_EDX, Rm ); - MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) ); - JMP_rel8(end); + load_reg( REG_EAX, Rn ); + check_walign32(REG_EAX); + MOVL_r32_r32( REG_EAX, REG_ECX ); + ANDL_imms_r32( 0xFC000000, REG_ECX ); + CMPL_imms_r32( 0xE0000000, REG_ECX ); + JNE_label( notsq ); + ANDL_imms_r32( 0x3C, REG_EAX ); + load_reg( REG_EDX, Rm ); + MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) ); + JMP_label(end); JMP_TARGET(notsq); - load_reg( R_EDX, Rm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); JMP_TARGET(end); sh4_x86.tstate = TSTATE_NONE; :} MOV.L Rm, @-Rn {: COUNT_INST(I_MOVL); - load_reg( R_EAX, Rn ); - ADD_imm8s_r32( -4, R_EAX ); - check_walign32( R_EAX ); - load_reg( R_EDX, Rm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + ADDL_imms_r32( -4, REG_EAX ); + check_walign32( REG_EAX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} MOV.L Rm, @(R0, Rn) {: COUNT_INST(I_MOVL); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX ); - check_walign32( R_EAX ); - load_reg( R_EDX, Rm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); + check_walign32( REG_EAX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.L R0, @(disp, GBR) {: COUNT_INST(I_MOVL); - load_spreg( R_EAX, R_GBR ); - ADD_imm32_r32( disp, R_EAX ); - check_walign32( R_EAX ); - load_reg( R_EDX, 0 ); - MEM_WRITE_LONG( R_EAX, R_EDX ); + load_spreg( REG_EAX, R_GBR ); + ADDL_imms_r32( disp, REG_EAX ); + check_walign32( REG_EAX ); + load_reg( REG_EDX, 0 ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.L Rm, @(disp, Rn) {: COUNT_INST(I_MOVL); - load_reg( R_EAX, Rn ); - ADD_imm32_r32( disp, R_EAX ); - check_walign32( R_EAX ); - MOV_r32_r32( R_EAX, R_ECX ); - AND_imm32_r32( 0xFC000000, R_ECX ); - CMP_imm32_r32( 0xE0000000, R_ECX ); - JNE_rel8( notsq ); - AND_imm8s_r32( 0x3C, R_EAX ); - load_reg( R_EDX, Rm ); - MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) ); - JMP_rel8(end); + load_reg( REG_EAX, Rn ); + ADDL_imms_r32( disp, REG_EAX ); + check_walign32( REG_EAX ); + MOVL_r32_r32( REG_EAX, REG_ECX ); + ANDL_imms_r32( 0xFC000000, REG_ECX ); + CMPL_imms_r32( 0xE0000000, REG_ECX ); + JNE_label( notsq ); + ANDL_imms_r32( 0x3C, REG_EAX ); + load_reg( REG_EDX, Rm ); + MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) ); + JMP_label(end); JMP_TARGET(notsq); - load_reg( R_EDX, Rm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); JMP_TARGET(end); sh4_x86.tstate = TSTATE_NONE; :} MOV.L @Rm, Rn {: COUNT_INST(I_MOVL); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.L @Rm+, Rn {: COUNT_INST(I_MOVL); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); if( Rm != Rn ) { - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); } - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.L @(R0, Rm), Rn {: COUNT_INST(I_MOVL); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.L @(disp, GBR), R0 {: COUNT_INST(I_MOVL); - load_spreg( R_EAX, R_GBR ); - ADD_imm32_r32( disp, R_EAX ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_reg( R_EAX, 0 ); + load_spreg( REG_EAX, R_GBR ); + ADDL_imms_r32( disp, REG_EAX ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_reg( REG_EAX, 0 ); sh4_x86.tstate = TSTATE_NONE; :} MOV.L @(disp, PC), Rn {: @@ -1307,108 +1310,108 @@ // behaviour to confirm) Unlikely to be anyone depending on this // behaviour though. sh4ptr_t ptr = GET_ICACHE_PTR(target); - MOV_moff32_EAX( ptr ); + MOVL_moffptr_eax( ptr ); } else { // Note: we use sh4r.pc for the calc as we could be running at a // different virtual address than the translation was done with, // but we can safely assume that the low bits are the same. - load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) ); - ADD_sh4r_r32( R_PC, R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); + load_imm32( REG_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) ); + ADDL_rbpdisp_r32( R_PC, REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); sh4_x86.tstate = TSTATE_NONE; } - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); } :} MOV.L @(disp, Rm), Rn {: COUNT_INST(I_MOVL); - load_reg( R_EAX, Rm ); - ADD_imm8s_r32( disp, R_EAX ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + ADDL_imms_r32( disp, REG_EAX ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W Rm, @Rn {: COUNT_INST(I_MOVW); - load_reg( R_EAX, Rn ); - check_walign16( R_EAX ); - load_reg( R_EDX, Rm ); - MEM_WRITE_WORD( R_EAX, R_EDX ); + load_reg( REG_EAX, Rn ); + check_walign16( REG_EAX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_WORD( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W Rm, @-Rn {: COUNT_INST(I_MOVW); - load_reg( R_EAX, Rn ); - check_walign16( R_EAX ); - LEA_r32disp8_r32( R_EAX, -2, R_EAX ); - load_reg( R_EDX, Rm ); - MEM_WRITE_WORD( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign16( REG_EAX ); + LEAL_r32disp_r32( REG_EAX, -2, REG_EAX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_WORD( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W Rm, @(R0, Rn) {: COUNT_INST(I_MOVW); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX ); - check_walign16( R_EAX ); - load_reg( R_EDX, Rm ); - MEM_WRITE_WORD( R_EAX, R_EDX ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); + check_walign16( REG_EAX ); + load_reg( REG_EDX, Rm ); + MEM_WRITE_WORD( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W R0, @(disp, GBR) {: COUNT_INST(I_MOVW); - load_spreg( R_EAX, R_GBR ); - ADD_imm32_r32( disp, R_EAX ); - check_walign16( R_EAX ); - load_reg( R_EDX, 0 ); - MEM_WRITE_WORD( R_EAX, R_EDX ); + load_spreg( REG_EAX, R_GBR ); + ADDL_imms_r32( disp, REG_EAX ); + check_walign16( REG_EAX ); + load_reg( REG_EDX, 0 ); + MEM_WRITE_WORD( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W R0, @(disp, Rn) {: COUNT_INST(I_MOVW); - load_reg( R_EAX, Rn ); - ADD_imm32_r32( disp, R_EAX ); - check_walign16( R_EAX ); - load_reg( R_EDX, 0 ); - MEM_WRITE_WORD( R_EAX, R_EDX ); + load_reg( REG_EAX, Rn ); + ADDL_imms_r32( disp, REG_EAX ); + check_walign16( REG_EAX ); + load_reg( REG_EDX, 0 ); + MEM_WRITE_WORD( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W @Rm, Rn {: COUNT_INST(I_MOVW); - load_reg( R_EAX, Rm ); - check_ralign16( R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rm ); + check_ralign16( REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W @Rm+, Rn {: COUNT_INST(I_MOVW); - load_reg( R_EAX, Rm ); - check_ralign16( R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); + load_reg( REG_EAX, Rm ); + check_ralign16( REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); if( Rm != Rn ) { - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) ); + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) ); } - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W @(R0, Rm), Rn {: COUNT_INST(I_MOVW); - load_reg( R_EAX, 0 ); - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX ); - check_ralign16( R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); - store_reg( R_EAX, Rn ); + load_reg( REG_EAX, 0 ); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX ); + check_ralign16( REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W @(disp, GBR), R0 {: COUNT_INST(I_MOVW); - load_spreg( R_EAX, R_GBR ); - ADD_imm32_r32( disp, R_EAX ); - check_ralign16( R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); - store_reg( R_EAX, 0 ); + load_spreg( REG_EAX, R_GBR ); + ADDL_imms_r32( disp, REG_EAX ); + check_ralign16( REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); + store_reg( REG_EAX, 0 ); sh4_x86.tstate = TSTATE_NONE; :} MOV.W @(disp, PC), Rn {: @@ -1420,24 +1423,24 @@ uint32_t target = pc + disp + 4; if( IS_IN_ICACHE(target) ) { sh4ptr_t ptr = GET_ICACHE_PTR(target); - MOV_moff32_EAX( ptr ); - MOVSX_r16_r32( R_EAX, R_EAX ); + MOVL_moffptr_eax( ptr ); + MOVSXL_r16_r32( REG_EAX, REG_EAX ); } else { - load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 ); - ADD_sh4r_r32( R_PC, R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); + load_imm32( REG_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 ); + ADDL_rbpdisp_r32( R_PC, REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); sh4_x86.tstate = TSTATE_NONE; } - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); } :} MOV.W @(disp, Rm), R0 {: COUNT_INST(I_MOVW); - load_reg( R_EAX, Rm ); - ADD_imm32_r32( disp, R_EAX ); - check_ralign16( R_EAX ); - MEM_READ_WORD( R_EAX, R_EAX ); - store_reg( R_EAX, 0 ); + load_reg( REG_EAX, Rm ); + ADDL_imms_r32( disp, REG_EAX ); + check_ralign16( REG_EAX ); + MEM_READ_WORD( REG_EAX, REG_EAX ); + store_reg( REG_EAX, 0 ); sh4_x86.tstate = TSTATE_NONE; :} MOVA @(disp, PC), R0 {: @@ -1445,18 +1448,18 @@ if( sh4_x86.in_delay_slot ) { SLOTILLEGAL(); } else { - load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) ); - ADD_sh4r_r32( R_PC, R_ECX ); - store_reg( R_ECX, 0 ); + load_imm32( REG_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) ); + ADDL_rbpdisp_r32( R_PC, REG_ECX ); + store_reg( REG_ECX, 0 ); sh4_x86.tstate = TSTATE_NONE; } :} MOVCA.L R0, @Rn {: COUNT_INST(I_MOVCA); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - load_reg( R_EDX, 0 ); - MEM_WRITE_LONG( R_EAX, R_EDX ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + load_reg( REG_EDX, 0 ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); sh4_x86.tstate = TSTATE_NONE; :} @@ -1467,7 +1470,7 @@ SLOTILLEGAL(); } else { sh4vma_t target = disp + pc + 4; - JT_rel8( nottaken ); + JT_label( nottaken ); exit_block_rel(target, pc+2 ); JMP_TARGET(nottaken); return 2; @@ -1480,22 +1483,23 @@ } else { sh4_x86.in_delay_slot = DELAY_PC; if( UNTRANSLATABLE(pc+2) ) { - load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc ); - JT_rel8(nottaken); - ADD_imm32_r32( disp, R_EAX ); + load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc ); + JT_label(nottaken); + ADDL_imms_r32( disp, REG_EAX ); JMP_TARGET(nottaken); - ADD_sh4r_r32( R_PC, R_EAX ); - store_spreg( R_EAX, R_NEW_PC ); + ADDL_rbpdisp_r32( R_PC, REG_EAX ); + store_spreg( REG_EAX, R_NEW_PC ); exit_block_emu(pc+2); sh4_x86.branch_taken = TRUE; return 2; } else { if( sh4_x86.tstate == TSTATE_NONE ) { - CMP_imm8s_sh4r( 1, R_T ); + CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } sh4vma_t target = disp + pc + 4; - OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32 + JCC_cc_rel32(sh4_x86.tstate,0); + uint32_t *patch = ((uint32_t *)xlat_output)-1; int save_tstate = sh4_x86.tstate; sh4_translate_instruction(pc+2); exit_block_rel( target, pc+4 ); @@ -1516,9 +1520,9 @@ sh4_x86.in_delay_slot = DELAY_PC; sh4_x86.branch_taken = TRUE; if( UNTRANSLATABLE(pc+2) ) { - load_spreg( R_EAX, R_PC ); - ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX ); - store_spreg( R_EAX, R_NEW_PC ); + load_spreg( REG_EAX, R_PC ); + ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX ); + store_spreg( REG_EAX, R_NEW_PC ); exit_block_emu(pc+2); return 2; } else { @@ -1533,10 +1537,10 @@ if( sh4_x86.in_delay_slot ) { SLOTILLEGAL(); } else { - load_spreg( R_EAX, R_PC ); - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX ); - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX ); - store_spreg( R_EAX, R_NEW_PC ); + load_spreg( REG_EAX, R_PC ); + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); + store_spreg( REG_EAX, R_NEW_PC ); sh4_x86.in_delay_slot = DELAY_PC; sh4_x86.tstate = TSTATE_NONE; sh4_x86.branch_taken = TRUE; @@ -1555,15 +1559,15 @@ if( sh4_x86.in_delay_slot ) { SLOTILLEGAL(); } else { - load_spreg( R_EAX, R_PC ); - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX ); - store_spreg( R_EAX, R_PR ); + load_spreg( REG_EAX, R_PC ); + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); + store_spreg( REG_EAX, R_PR ); sh4_x86.in_delay_slot = DELAY_PC; sh4_x86.branch_taken = TRUE; sh4_x86.tstate = TSTATE_NONE; if( UNTRANSLATABLE(pc+2) ) { - ADD_imm32_r32( disp, R_EAX ); - store_spreg( R_EAX, R_NEW_PC ); + ADDL_imms_r32( disp, REG_EAX ); + store_spreg( REG_EAX, R_NEW_PC ); exit_block_emu(pc+2); return 2; } else { @@ -1578,11 +1582,11 @@ if( sh4_x86.in_delay_slot ) { SLOTILLEGAL(); } else { - load_spreg( R_EAX, R_PC ); - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX ); - store_spreg( R_EAX, R_PR ); - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX ); - store_spreg( R_EAX, R_NEW_PC ); + load_spreg( REG_EAX, R_PC ); + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); + store_spreg( REG_EAX, R_PR ); + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX ); + store_spreg( REG_EAX, R_NEW_PC ); sh4_x86.in_delay_slot = DELAY_PC; sh4_x86.tstate = TSTATE_NONE; @@ -1603,7 +1607,7 @@ SLOTILLEGAL(); } else { sh4vma_t target = disp + pc + 4; - JF_rel8( nottaken ); + JF_label( nottaken ); exit_block_rel(target, pc+2 ); JMP_TARGET(nottaken); return 2; @@ -1616,21 +1620,23 @@ } else { sh4_x86.in_delay_slot = DELAY_PC; if( UNTRANSLATABLE(pc+2) ) { - load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc ); - JF_rel8(nottaken); - ADD_imm32_r32( disp, R_EAX ); + load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc ); + JF_label(nottaken); + ADDL_imms_r32( disp, REG_EAX ); JMP_TARGET(nottaken); - ADD_sh4r_r32( R_PC, R_EAX ); - store_spreg( R_EAX, R_NEW_PC ); + ADDL_rbpdisp_r32( R_PC, REG_EAX ); + store_spreg( REG_EAX, R_NEW_PC ); exit_block_emu(pc+2); sh4_x86.branch_taken = TRUE; return 2; } else { if( sh4_x86.tstate == TSTATE_NONE ) { - CMP_imm8s_sh4r( 1, R_T ); + CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } - OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32 + JCC_cc_rel32(sh4_x86.tstate^1,0); + uint32_t *patch = ((uint32_t *)xlat_output)-1; + int save_tstate = sh4_x86.tstate; sh4_translate_instruction(pc+2); exit_block_rel( disp + pc + 4, pc+4 ); @@ -1647,8 +1653,8 @@ if( sh4_x86.in_delay_slot ) { SLOTILLEGAL(); } else { - load_reg( R_ECX, Rn ); - store_spreg( R_ECX, R_NEW_PC ); + load_reg( REG_ECX, Rn ); + store_spreg( REG_ECX, R_NEW_PC ); sh4_x86.in_delay_slot = DELAY_PC; sh4_x86.branch_taken = TRUE; if( UNTRANSLATABLE(pc+2) ) { @@ -1666,11 +1672,11 @@ if( sh4_x86.in_delay_slot ) { SLOTILLEGAL(); } else { - load_spreg( R_EAX, R_PC ); - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX ); - store_spreg( R_EAX, R_PR ); - load_reg( R_ECX, Rn ); - store_spreg( R_ECX, R_NEW_PC ); + load_spreg( REG_EAX, R_PC ); + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX ); + store_spreg( REG_EAX, R_PR ); + load_reg( REG_ECX, Rn ); + store_spreg( REG_ECX, R_NEW_PC ); sh4_x86.in_delay_slot = DELAY_PC; sh4_x86.branch_taken = TRUE; sh4_x86.tstate = TSTATE_NONE; @@ -1690,10 +1696,10 @@ SLOTILLEGAL(); } else { check_priv(); - load_spreg( R_ECX, R_SPC ); - store_spreg( R_ECX, R_NEW_PC ); - load_spreg( R_EAX, R_SSR ); - call_func1( sh4_write_sr, R_EAX ); + load_spreg( REG_ECX, R_SPC ); + store_spreg( REG_ECX, R_NEW_PC ); + load_spreg( REG_EAX, R_SSR ); + call_func1( sh4_write_sr, REG_EAX ); sh4_x86.in_delay_slot = DELAY_PC; sh4_x86.fpuen_checked = FALSE; sh4_x86.tstate = TSTATE_NONE; @@ -1713,8 +1719,8 @@ if( sh4_x86.in_delay_slot ) { SLOTILLEGAL(); } else { - load_spreg( R_ECX, R_PR ); - store_spreg( R_ECX, R_NEW_PC ); + load_spreg( REG_ECX, R_PR ); + store_spreg( REG_ECX, R_NEW_PC ); sh4_x86.in_delay_slot = DELAY_PC; sh4_x86.branch_taken = TRUE; if( UNTRANSLATABLE(pc+2) ) { @@ -1732,10 +1738,10 @@ if( sh4_x86.in_delay_slot ) { SLOTILLEGAL(); } else { - load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc ); // 5 - ADD_r32_sh4r( R_ECX, R_PC ); - load_imm32( R_EAX, imm ); - call_func1( sh4_raise_trap, R_EAX ); + load_imm32( REG_ECX, pc+2 - sh4_x86.block_start_pc ); // 5 + ADDL_r32_rbpdisp( REG_ECX, R_PC ); + load_imm32( REG_EAX, imm ); + call_func1( sh4_raise_trap, REG_EAX ); sh4_x86.tstate = TSTATE_NONE; exit_block_pcset(pc+2); sh4_x86.branch_taken = TRUE; @@ -1754,15 +1760,15 @@ CLRMAC {: COUNT_INST(I_CLRMAC); - XOR_r32_r32(R_EAX, R_EAX); - store_spreg( R_EAX, R_MACL ); - store_spreg( R_EAX, R_MACH ); + XORL_r32_r32(REG_EAX, REG_EAX); + store_spreg( REG_EAX, R_MACL ); + store_spreg( REG_EAX, R_MACH ); sh4_x86.tstate = TSTATE_NONE; :} CLRS {: COUNT_INST(I_CLRS); CLC(); - SETC_sh4r(R_S); + SETCCB_cc_rbpdisp(X86_COND_C, R_S); sh4_x86.tstate = TSTATE_NONE; :} CLRT {: @@ -1774,7 +1780,7 @@ SETS {: COUNT_INST(I_SETS); STC(); - SETC_sh4r(R_S); + SETCCB_cc_rbpdisp(X86_COND_C, R_S); sh4_x86.tstate = TSTATE_NONE; :} SETT {: @@ -1789,136 +1795,136 @@ COUNT_INST(I_FMOV1); check_fpuen(); if( sh4_x86.double_size ) { - load_dr0( R_EAX, FRm ); - load_dr1( R_ECX, FRm ); - store_dr0( R_EAX, FRn ); - store_dr1( R_ECX, FRn ); + load_dr0( REG_EAX, FRm ); + load_dr1( REG_ECX, FRm ); + store_dr0( REG_EAX, FRn ); + store_dr1( REG_ECX, FRn ); } else { - load_fr( R_EAX, FRm ); // SZ=0 branch - store_fr( R_EAX, FRn ); + load_fr( REG_EAX, FRm ); // SZ=0 branch + store_fr( REG_EAX, FRn ); } :} FMOV FRm, @Rn {: COUNT_INST(I_FMOV2); check_fpuen(); - load_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); if( sh4_x86.double_size ) { - check_walign64( R_EAX ); - load_dr0( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - load_reg( R_EAX, Rn ); - LEA_r32disp8_r32( R_EAX, 4, R_EAX ); - load_dr1( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); + check_walign64( REG_EAX ); + load_dr0( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + load_reg( REG_EAX, Rn ); + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); + load_dr1( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); } else { - check_walign32( R_EAX ); - load_fr( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); + check_walign32( REG_EAX ); + load_fr( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); } sh4_x86.tstate = TSTATE_NONE; :} FMOV @Rm, FRn {: COUNT_INST(I_FMOV5); check_fpuen(); - load_reg( R_EAX, Rm ); + load_reg( REG_EAX, Rm ); if( sh4_x86.double_size ) { - check_ralign64( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_dr0( R_EAX, FRn ); - load_reg( R_EAX, Rm ); - LEA_r32disp8_r32( R_EAX, 4, R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_dr1( R_EAX, FRn ); + check_ralign64( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_dr0( REG_EAX, FRn ); + load_reg( REG_EAX, Rm ); + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_dr1( REG_EAX, FRn ); } else { - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_fr( R_EAX, FRn ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_fr( REG_EAX, FRn ); } sh4_x86.tstate = TSTATE_NONE; :} FMOV FRm, @-Rn {: COUNT_INST(I_FMOV3); check_fpuen(); - load_reg( R_EAX, Rn ); + load_reg( REG_EAX, Rn ); if( sh4_x86.double_size ) { - check_walign64( R_EAX ); - LEA_r32disp8_r32( R_EAX, -8, R_EAX ); - load_dr0( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - load_reg( R_EAX, Rn ); - LEA_r32disp8_r32( R_EAX, -4, R_EAX ); - load_dr1( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn])); + check_walign64( REG_EAX ); + LEAL_r32disp_r32( REG_EAX, -8, REG_EAX ); + load_dr0( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + load_reg( REG_EAX, Rn ); + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); + load_dr1( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn])); } else { - check_walign32( R_EAX ); - LEA_r32disp8_r32( R_EAX, -4, R_EAX ); - load_fr( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn])); + check_walign32( REG_EAX ); + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); + load_fr( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn])); } sh4_x86.tstate = TSTATE_NONE; :} FMOV @Rm+, FRn {: COUNT_INST(I_FMOV6); check_fpuen(); - load_reg( R_EAX, Rm ); + load_reg( REG_EAX, Rm ); if( sh4_x86.double_size ) { - check_ralign64( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_dr0( R_EAX, FRn ); - load_reg( R_EAX, Rm ); - LEA_r32disp8_r32( R_EAX, 4, R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_dr1( R_EAX, FRn ); - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) ); + check_ralign64( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_dr0( REG_EAX, FRn ); + load_reg( REG_EAX, Rm ); + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_dr1( REG_EAX, FRn ); + ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) ); } else { - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_fr( R_EAX, FRn ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_fr( REG_EAX, FRn ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); } sh4_x86.tstate = TSTATE_NONE; :} FMOV FRm, @(R0, Rn) {: COUNT_INST(I_FMOV4); check_fpuen(); - load_reg( R_EAX, Rn ); - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX ); + load_reg( REG_EAX, Rn ); + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); if( sh4_x86.double_size ) { - check_walign64( R_EAX ); - load_dr0( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - load_reg( R_EAX, Rn ); - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX ); - LEA_r32disp8_r32( R_EAX, 4, R_EAX ); - load_dr1( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); + check_walign64( REG_EAX ); + load_dr0( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + load_reg( REG_EAX, Rn ); + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); + load_dr1( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); } else { - check_walign32( R_EAX ); - load_fr( R_EDX, FRm ); - MEM_WRITE_LONG( R_EAX, R_EDX ); // 12 + check_walign32( REG_EAX ); + load_fr( REG_EDX, FRm ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12 } sh4_x86.tstate = TSTATE_NONE; :} FMOV @(R0, Rm), FRn {: COUNT_INST(I_FMOV7); check_fpuen(); - load_reg( R_EAX, Rm ); - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX ); + load_reg( REG_EAX, Rm ); + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); if( sh4_x86.double_size ) { - check_ralign64( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_dr0( R_EAX, FRn ); - load_reg( R_EAX, Rm ); - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX ); - LEA_r32disp8_r32( R_EAX, 4, R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_dr1( R_EAX, FRn ); + check_ralign64( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_dr0( REG_EAX, FRn ); + load_reg( REG_EAX, Rm ); + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX ); + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_dr1( REG_EAX, FRn ); } else { - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - store_fr( R_EAX, FRn ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + store_fr( REG_EAX, FRn ); } sh4_x86.tstate = TSTATE_NONE; :} @@ -1926,8 +1932,8 @@ COUNT_INST(I_FLDI0); check_fpuen(); if( sh4_x86.double_prec == 0 ) { - XOR_r32_r32( R_EAX, R_EAX ); - store_fr( R_EAX, FRn ); + XORL_r32_r32( REG_EAX, REG_EAX ); + store_fr( REG_EAX, FRn ); } sh4_x86.tstate = TSTATE_NONE; :} @@ -1935,15 +1941,15 @@ COUNT_INST(I_FLDI1); check_fpuen(); if( sh4_x86.double_prec == 0 ) { - load_imm32(R_EAX, 0x3F800000); - store_fr( R_EAX, FRn ); + load_imm32(REG_EAX, 0x3F800000); + store_fr( REG_EAX, FRn ); } :} FLOAT FPUL, FRn {: COUNT_INST(I_FLOAT); check_fpuen(); - FILD_sh4r(R_FPUL); + FILD_rbpdisp(R_FPUL); if( sh4_x86.double_prec ) { pop_dr( FRn ); } else { @@ -1958,26 +1964,26 @@ } else { push_fr( FRm ); } - load_ptr( R_ECX, &max_int ); - FILD_r32ind( R_ECX ); + load_ptr( REG_ECX, &max_int ); + FILD_r32disp( REG_ECX, 0 ); FCOMIP_st(1); - JNA_rel8( sat ); - load_ptr( R_ECX, &min_int ); // 5 - FILD_r32ind( R_ECX ); // 2 + JNA_label( sat ); + load_ptr( REG_ECX, &min_int ); // 5 + FILD_r32disp( REG_ECX, 0 ); // 2 FCOMIP_st(1); // 2 - JAE_rel8( sat2 ); // 2 - load_ptr( R_EAX, &save_fcw ); - FNSTCW_r32ind( R_EAX ); - load_ptr( R_EDX, &trunc_fcw ); - FLDCW_r32ind( R_EDX ); - FISTP_sh4r(R_FPUL); // 3 - FLDCW_r32ind( R_EAX ); - JMP_rel8(end); // 2 + JAE_label( sat2 ); // 2 + load_ptr( REG_EAX, &save_fcw ); + FNSTCW_r32disp( REG_EAX, 0 ); + load_ptr( REG_EDX, &trunc_fcw ); + FLDCW_r32disp( REG_EDX, 0 ); + FISTP_rbpdisp(R_FPUL); // 3 + FLDCW_r32disp( REG_EAX, 0 ); + JMP_label(end); // 2 JMP_TARGET(sat); JMP_TARGET(sat2); - MOV_r32ind_r32( R_ECX, R_ECX ); // 2 - store_spreg( R_ECX, R_FPUL ); + MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2 + store_spreg( REG_ECX, R_FPUL ); FPOP_st(); JMP_TARGET(end); sh4_x86.tstate = TSTATE_NONE; @@ -1985,14 +1991,14 @@ FLDS FRm, FPUL {: COUNT_INST(I_FLDS); check_fpuen(); - load_fr( R_EAX, FRm ); - store_spreg( R_EAX, R_FPUL ); + load_fr( REG_EAX, FRm ); + store_spreg( REG_EAX, R_FPUL ); :} FSTS FPUL, FRn {: COUNT_INST(I_FSTS); check_fpuen(); - load_spreg( R_EAX, R_FPUL ); - store_fr( R_EAX, FRn ); + load_spreg( REG_EAX, R_FPUL ); + store_fr( REG_EAX, FRn ); :} FCNVDS FRm, FPUL {: COUNT_INST(I_FCNVDS); @@ -2178,9 +2184,9 @@ COUNT_INST(I_FSCA); check_fpuen(); if( sh4_x86.double_prec == 0 ) { - LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX ); - load_spreg( R_EAX, R_FPUL ); - call_func2( sh4_fsca, R_EAX, R_EDX ); + LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX ); + load_spreg( REG_EAX, R_FPUL ); + call_func2( sh4_fsca, REG_EAX, REG_EDX ); } sh4_x86.tstate = TSTATE_NONE; :} @@ -2189,11 +2195,11 @@ check_fpuen(); if( sh4_x86.double_prec == 0 ) { if( sh4_x86.sse3_enabled ) { - MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 ); - MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 ); + MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); HADDPS_xmm_xmm( 4, 4 ); HADDPS_xmm_xmm( 4, 4 ); - MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) ); + MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) ); } else { push_fr( FVm<<2 ); push_fr( FVn<<2 ); @@ -2219,15 +2225,15 @@ check_fpuen(); if( sh4_x86.double_prec == 0 ) { if( sh4_x86.sse3_enabled ) { - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M2 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M6 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M10 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M2 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M6 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M10 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14 - MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3 - MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2 - MOVAPS_xmm_xmm( 4, 6 ); - MOVAPS_xmm_xmm( 5, 7 ); + MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3 + MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2 + MOV_xmm_xmm( 4, 6 ); + MOV_xmm_xmm( 5, 7 ); MOVLHPS_xmm_xmm( 4, 4 ); // V1 V1 V1 V1 MOVHLPS_xmm_xmm( 6, 6 ); // V3 V3 V3 V3 MOVLHPS_xmm_xmm( 5, 5 ); // V0 V0 V0 V0 @@ -2239,10 +2245,10 @@ ADDPS_xmm_xmm( 5, 4 ); ADDPS_xmm_xmm( 7, 6 ); ADDPS_xmm_xmm( 6, 4 ); - MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) ); + MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) ); } else { - LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX ); - call_func1( sh4_ftrv, R_EAX ); + LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX ); + call_func1( sh4_ftrv, REG_EAX ); } } sh4_x86.tstate = TSTATE_NONE; @@ -2251,15 +2257,15 @@ FRCHG {: COUNT_INST(I_FRCHG); check_fpuen(); - XOR_imm32_sh4r( FPSCR_FR, R_FPSCR ); + XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR ); call_func0( sh4_switch_fr_banks ); sh4_x86.tstate = TSTATE_NONE; :} FSCHG {: COUNT_INST(I_FSCHG); check_fpuen(); - XOR_imm32_sh4r( FPSCR_SZ, R_FPSCR); - XOR_imm32_sh4r( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) ); + XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR); + XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) ); sh4_x86.tstate = TSTATE_NONE; sh4_x86.double_size = !sh4_x86.double_size; :} @@ -2271,8 +2277,8 @@ SLOTILLEGAL(); } else { check_priv(); - load_reg( R_EAX, Rm ); - call_func1( sh4_write_sr, R_EAX ); + load_reg( REG_EAX, Rm ); + call_func1( sh4_write_sr, REG_EAX ); sh4_x86.fpuen_checked = FALSE; sh4_x86.tstate = TSTATE_NONE; return 2; @@ -2280,58 +2286,58 @@ :} LDC Rm, GBR {: COUNT_INST(I_LDC); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_GBR ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_GBR ); :} LDC Rm, VBR {: COUNT_INST(I_LDC); check_priv(); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_VBR ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_VBR ); sh4_x86.tstate = TSTATE_NONE; :} LDC Rm, SSR {: COUNT_INST(I_LDC); check_priv(); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_SSR ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_SSR ); sh4_x86.tstate = TSTATE_NONE; :} LDC Rm, SGR {: COUNT_INST(I_LDC); check_priv(); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_SGR ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_SGR ); sh4_x86.tstate = TSTATE_NONE; :} LDC Rm, SPC {: COUNT_INST(I_LDC); check_priv(); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_SPC ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_SPC ); sh4_x86.tstate = TSTATE_NONE; :} LDC Rm, DBR {: COUNT_INST(I_LDC); check_priv(); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_DBR ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_DBR ); sh4_x86.tstate = TSTATE_NONE; :} LDC Rm, Rn_BANK {: COUNT_INST(I_LDC); check_priv(); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); sh4_x86.tstate = TSTATE_NONE; :} LDC.L @Rm+, GBR {: COUNT_INST(I_LDCM); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_GBR ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_GBR ); sh4_x86.tstate = TSTATE_NONE; :} LDC.L @Rm+, SR {: @@ -2340,11 +2346,11 @@ SLOTILLEGAL(); } else { check_priv(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - call_func1( sh4_write_sr, R_EAX ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + call_func1( sh4_write_sr, REG_EAX ); sh4_x86.fpuen_checked = FALSE; sh4_x86.tstate = TSTATE_NONE; return 2; @@ -2353,138 +2359,138 @@ LDC.L @Rm+, VBR {: COUNT_INST(I_LDCM); check_priv(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_VBR ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_VBR ); sh4_x86.tstate = TSTATE_NONE; :} LDC.L @Rm+, SSR {: COUNT_INST(I_LDCM); check_priv(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_SSR ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_SSR ); sh4_x86.tstate = TSTATE_NONE; :} LDC.L @Rm+, SGR {: COUNT_INST(I_LDCM); check_priv(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_SGR ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_SGR ); sh4_x86.tstate = TSTATE_NONE; :} LDC.L @Rm+, SPC {: COUNT_INST(I_LDCM); check_priv(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_SPC ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_SPC ); sh4_x86.tstate = TSTATE_NONE; :} LDC.L @Rm+, DBR {: COUNT_INST(I_LDCM); check_priv(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_DBR ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_DBR ); sh4_x86.tstate = TSTATE_NONE; :} LDC.L @Rm+, Rn_BANK {: COUNT_INST(I_LDCM); check_priv(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) ); sh4_x86.tstate = TSTATE_NONE; :} LDS Rm, FPSCR {: COUNT_INST(I_LDSFPSCR); check_fpuen(); - load_reg( R_EAX, Rm ); - call_func1( sh4_write_fpscr, R_EAX ); + load_reg( REG_EAX, Rm ); + call_func1( sh4_write_fpscr, REG_EAX ); sh4_x86.tstate = TSTATE_NONE; return 2; :} LDS.L @Rm+, FPSCR {: COUNT_INST(I_LDSFPSCRM); check_fpuen(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - call_func1( sh4_write_fpscr, R_EAX ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + call_func1( sh4_write_fpscr, REG_EAX ); sh4_x86.tstate = TSTATE_NONE; return 2; :} LDS Rm, FPUL {: COUNT_INST(I_LDS); check_fpuen(); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_FPUL ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_FPUL ); :} LDS.L @Rm+, FPUL {: COUNT_INST(I_LDSM); check_fpuen(); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_FPUL ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_FPUL ); sh4_x86.tstate = TSTATE_NONE; :} LDS Rm, MACH {: COUNT_INST(I_LDS); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_MACH ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_MACH ); :} LDS.L @Rm+, MACH {: COUNT_INST(I_LDSM); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_MACH ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_MACH ); sh4_x86.tstate = TSTATE_NONE; :} LDS Rm, MACL {: COUNT_INST(I_LDS); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_MACL ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_MACL ); :} LDS.L @Rm+, MACL {: COUNT_INST(I_LDSM); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_MACL ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_MACL ); sh4_x86.tstate = TSTATE_NONE; :} LDS Rm, PR {: COUNT_INST(I_LDS); - load_reg( R_EAX, Rm ); - store_spreg( R_EAX, R_PR ); + load_reg( REG_EAX, Rm ); + store_spreg( REG_EAX, R_PR ); :} LDS.L @Rm+, PR {: COUNT_INST(I_LDSM); - load_reg( R_EAX, Rm ); - check_ralign32( R_EAX ); - MEM_READ_LONG( R_EAX, R_EAX ); - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) ); - store_spreg( R_EAX, R_PR ); + load_reg( REG_EAX, Rm ); + check_ralign32( REG_EAX ); + MEM_READ_LONG( REG_EAX, REG_EAX ); + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) ); + store_spreg( REG_EAX, R_PR ); sh4_x86.tstate = TSTATE_NONE; :} LDTLB {: @@ -2503,8 +2509,8 @@ :} PREF @Rn {: COUNT_INST(I_PREF); - load_reg( R_EAX, Rn ); - MEM_PREFETCH( R_EAX ); + load_reg( REG_EAX, Rn ); + MEM_PREFETCH( REG_EAX ); sh4_x86.tstate = TSTATE_NONE; :} SLEEP {: @@ -2519,221 +2525,221 @@ COUNT_INST(I_STCSR); check_priv(); call_func0(sh4_read_sr); - store_reg( R_EAX, Rn ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} STC GBR, Rn {: COUNT_INST(I_STC); - load_spreg( R_EAX, R_GBR ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_GBR ); + store_reg( REG_EAX, Rn ); :} STC VBR, Rn {: COUNT_INST(I_STC); check_priv(); - load_spreg( R_EAX, R_VBR ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_VBR ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} STC SSR, Rn {: COUNT_INST(I_STC); check_priv(); - load_spreg( R_EAX, R_SSR ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_SSR ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} STC SPC, Rn {: COUNT_INST(I_STC); check_priv(); - load_spreg( R_EAX, R_SPC ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_SPC ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} STC SGR, Rn {: COUNT_INST(I_STC); check_priv(); - load_spreg( R_EAX, R_SGR ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_SGR ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} STC DBR, Rn {: COUNT_INST(I_STC); check_priv(); - load_spreg( R_EAX, R_DBR ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_DBR ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} STC Rm_BANK, Rn {: COUNT_INST(I_STC); check_priv(); - load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, REG_OFFSET(r_bank[Rm_BANK]) ); + store_reg( REG_EAX, Rn ); sh4_x86.tstate = TSTATE_NONE; :} STC.L SR, @-Rn {: COUNT_INST(I_STCSRM); check_priv(); call_func0( sh4_read_sr ); - MOV_r32_r32( R_EAX, R_EDX ); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - LEA_r32disp8_r32( R_EAX, -4, R_EAX ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + MOVL_r32_r32( REG_EAX, REG_EDX ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STC.L VBR, @-Rn {: COUNT_INST(I_STCM); check_priv(); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_VBR ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_VBR ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STC.L SSR, @-Rn {: COUNT_INST(I_STCM); check_priv(); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_SSR ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_SSR ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STC.L SPC, @-Rn {: COUNT_INST(I_STCM); check_priv(); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_SPC ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_SPC ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STC.L SGR, @-Rn {: COUNT_INST(I_STCM); check_priv(); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_SGR ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_SGR ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STC.L DBR, @-Rn {: COUNT_INST(I_STCM); check_priv(); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_DBR ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_DBR ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STC.L Rm_BANK, @-Rn {: COUNT_INST(I_STCM); check_priv(); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, REG_OFFSET(r_bank[Rm_BANK]) ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STC.L GBR, @-Rn {: COUNT_INST(I_STCM); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_GBR ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_GBR ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STS FPSCR, Rn {: COUNT_INST(I_STSFPSCR); check_fpuen(); - load_spreg( R_EAX, R_FPSCR ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_FPSCR ); + store_reg( REG_EAX, Rn ); :} STS.L FPSCR, @-Rn {: COUNT_INST(I_STSFPSCRM); check_fpuen(); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_FPSCR ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_FPSCR ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STS FPUL, Rn {: COUNT_INST(I_STS); check_fpuen(); - load_spreg( R_EAX, R_FPUL ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_FPUL ); + store_reg( REG_EAX, Rn ); :} STS.L FPUL, @-Rn {: COUNT_INST(I_STSM); check_fpuen(); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_FPUL ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_FPUL ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STS MACH, Rn {: COUNT_INST(I_STS); - load_spreg( R_EAX, R_MACH ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_MACH ); + store_reg( REG_EAX, Rn ); :} STS.L MACH, @-Rn {: COUNT_INST(I_STSM); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_MACH ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_MACH ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STS MACL, Rn {: COUNT_INST(I_STS); - load_spreg( R_EAX, R_MACL ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_MACL ); + store_reg( REG_EAX, Rn ); :} STS.L MACL, @-Rn {: COUNT_INST(I_STSM); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_MACL ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_MACL ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :} STS PR, Rn {: COUNT_INST(I_STS); - load_spreg( R_EAX, R_PR ); - store_reg( R_EAX, Rn ); + load_spreg( REG_EAX, R_PR ); + store_reg( REG_EAX, Rn ); :} STS.L PR, @-Rn {: COUNT_INST(I_STSM); - load_reg( R_EAX, Rn ); - check_walign32( R_EAX ); - ADD_imm8s_r32( -4, R_EAX ); - load_spreg( R_EDX, R_PR ); - MEM_WRITE_LONG( R_EAX, R_EDX ); - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) ); + load_reg( REG_EAX, Rn ); + check_walign32( REG_EAX ); + ADDL_imms_r32( -4, REG_EAX ); + load_spreg( REG_EDX, R_PR ); + MEM_WRITE_LONG( REG_EAX, REG_EDX ); + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) ); sh4_x86.tstate = TSTATE_NONE; :}