--- a/src/sh4/dmac.c	Tue Jan 01 05:08:38 2008 +0000
+++ b/src/sh4/dmac.c	Sun Dec 14 07:50:48 2008 +0000
@@ -63,18 +63,18 @@
     uint32_t oldval = DMA_CONTROL(channel);
     int resource;
     MMIO_WRITE( DMAC, CHCR0 + (channel<<4), val );
-    
+
     /* If TE or IE are cleared, clear the interrupt request */
     if( IS_CHANNEL_IRQ_ACTIVE(oldval) &&
-	!IS_CHANNEL_IRQ_ACTIVE(val) )
-	intc_clear_interrupt( INT_DMA_DMTE0+channel );
-    
+            !IS_CHANNEL_IRQ_ACTIVE(val) )
+        intc_clear_interrupt( INT_DMA_DMTE0+channel );
+
     resource = CHANNEL_RESOURCE(val);
     if( IS_CHANNEL_ENABLED(val) ) {
-	if( resource >= DMARES_MEMORY_TO_MEMORY_AUTO && 
-	    resource < DMARES_SCI_TRANSMIT_EMPTY ) {
-	    /* Autorun */
-	}
+        if( resource >= DMARES_MEMORY_TO_MEMORY_AUTO && 
+                resource < DMARES_SCI_TRANSMIT_EMPTY ) {
+            /* Autorun */
+        }
     }
 
     /* Everything else we don't need to care about until we actually try to
@@ -91,14 +91,14 @@
 {
     switch( reg ) {
     case DMAOR:
-	MMIO_WRITE( DMAC, reg, val );
-	break;
+        MMIO_WRITE( DMAC, reg, val );
+        break;
     case CHCR0: DMAC_set_control( 0, val ); break;
     case CHCR1: DMAC_set_control( 1, val ); break;
     case CHCR2: DMAC_set_control( 2, val ); break;
     case CHCR3: DMAC_set_control( 3, val ); break;
     default:
-	MMIO_WRITE( DMAC, reg, val );
+        MMIO_WRITE( DMAC, reg, val );
     }
 }
 
@@ -118,46 +118,46 @@
     uint32_t control = DMA_CONTROL(channel);
 
     if( IS_CHANNEL_ENABLED(control) ) {
-	uint32_t source = DMA_SOURCE(channel);
-	uint32_t dest = DMA_DEST(channel);
-	uint32_t count = DMA_COUNT( channel );
-	if( count == 0 )
-	    count = 0x01000000;
-	if( run_count == 0 || run_count > count )
-	    run_count = count;
-	uint32_t xfersize = DMAC_xfer_size[ (control >> 4)&0x07 ];
-	int source_step, dest_step;
-	int resource = (control >> 8) & 0x0F;
-	switch( (control >> 14) & 0x03 ) {
-	case 0: dest_step = 0; break;
-	case 1: dest_step = xfersize; break;
-	case 2: dest_step = -xfersize; break;
-	case 3: dest_step = 0; break; /* Illegal */
-	}
-	switch( (control >> 12) & 0x03 ) {
-	case 0: source_step = 0; break;
-	case 1: source_step = xfersize; break;
-	case 2: source_step = -xfersize; break;
-	case 3: source_step = 0; break; /* Illegal */
-	}
-	
-	while( run_count > 0 ) {
-	    /* Origin */
-	    if( (resource & 0x02) == 0 ) {
-		/* Source is a normal memory address */
-		
-	    } else {
-		/* Device */
-	    }
-	    
-	    /* Destination */
-	    if( (resource & 0x01) == 0 ) {
-		/* Destination is a normal memory address */
-	    } else {
-	    }
-	    run_count--; 
-	    count--;
-	}
+        uint32_t source = DMA_SOURCE(channel);
+        uint32_t dest = DMA_DEST(channel);
+        uint32_t count = DMA_COUNT( channel );
+        if( count == 0 )
+            count = 0x01000000;
+        if( run_count == 0 || run_count > count )
+            run_count = count;
+        uint32_t xfersize = DMAC_xfer_size[ (control >> 4)&0x07 ];
+        int source_step, dest_step;
+        int resource = (control >> 8) & 0x0F;
+        switch( (control >> 14) & 0x03 ) {
+        case 0: dest_step = 0; break;
+        case 1: dest_step = xfersize; break;
+        case 2: dest_step = -xfersize; break;
+        case 3: dest_step = 0; break; /* Illegal */
+        }
+        switch( (control >> 12) & 0x03 ) {
+        case 0: source_step = 0; break;
+        case 1: source_step = xfersize; break;
+        case 2: source_step = -xfersize; break;
+        case 3: source_step = 0; break; /* Illegal */
+        }
+
+        while( run_count > 0 ) {
+            /* Origin */
+            if( (resource & 0x02) == 0 ) {
+                /* Source is a normal memory address */
+
+            } else {
+                /* Device */
+            }
+
+            /* Destination */
+            if( (resource & 0x01) == 0 ) {
+                /* Destination is a normal memory address */
+            } else {
+            }
+            run_count--; 
+            count--;
+        }
     }
 #endif
 }
@@ -177,14 +177,14 @@
     char tmp[32];
 
     if( !IS_CHANNEL_ENABLED(control) || !IS_DMAC_ENABLED() )
-	return 0;
-    
+        return 0;
+
     if( ((control >> 8) & 0x0F) !=  DMARES_MEMORY_TO_DEVICE ) {
-	/* Error? */
-	
-	return 0;
+        /* Error? */
+
+        return 0;
     } 
-    
+
     source = DMA_SOURCE(channel);
     count = DMA_COUNT(channel);
     if( count == 0 ) count = 0x01000000;
@@ -192,33 +192,33 @@
     size = DMAC_xfer_size[ (control >> 4)&0x07 ];
     run_count = numBytes / size;
     if( run_count > count || run_count == 0 )
-	run_count = count;
+        run_count = count;
 
     /* Do copy - FIXME: doesn't work when crossing regions */
     sh4ptr_t region = mem_get_region( source );
     switch( (control >> 12) & 0x03 ) {
     case 0: 
-	memcpy( tmp, region, size );
-	for( i=0; i<run_count; i++ ) {
-	    memcpy( buf, tmp, size );
-	    buf += size;
-	}
-	break;
+        memcpy( tmp, region, size );
+        for( i=0; i<run_count; i++ ) {
+            memcpy( buf, tmp, size );
+            buf += size;
+        }
+        break;
     case 1: 
-	i = run_count * size;
-	memcpy( buf, region, i );
-	source += i;
-	break;
+        i = run_count * size;
+        memcpy( buf, region, i );
+        source += i;
+        break;
     case 2: 
-	for( i=0; i<run_count; i++ ) {
-	    memcpy( buf, region, size );
-	    buf += size;
-	    region -= size;
-	}
-	source -= (run_count * size);
-	break;
+        for( i=0; i<run_count; i++ ) {
+            memcpy( buf, region, size );
+            buf += size;
+            region -= size;
+        }
+        source -= (run_count * size);
+        break;
     default:
-	return 0; /* Illegal */
+        return 0; /* Illegal */
     }
 
     /* Update the channel registers */
@@ -226,10 +226,10 @@
     MMIO_WRITE( DMAC, SAR0 + (channel<<4), source );
     MMIO_WRITE( DMAC, DMATCR0 + (channel<<4), count );
     if( count == 0 ) {
-	control |= CHCR_TE; 
-	if( IS_CHANNEL_IRQ_ENABLED(control) )
-	    intc_raise_interrupt( INT_DMA_DMTE0 + channel );
-	MMIO_WRITE( DMAC, CHCR0 + (channel<<4), control );
+        control |= CHCR_TE; 
+        if( IS_CHANNEL_IRQ_ENABLED(control) )
+            intc_raise_interrupt( INT_DMA_DMTE0 + channel );
+        MMIO_WRITE( DMAC, CHCR0 + (channel<<4), control );
     }
 
     return run_count * size;
@@ -241,13 +241,13 @@
     uint32_t dest, count, run_count, size, i;
 
     if( !IS_CHANNEL_ENABLED(control) || !IS_DMAC_ENABLED() )
-	return 0;
-    
+        return 0;
+
     if( ((control >> 8) & 0x0F) !=  DMARES_DEVICE_TO_MEMORY ) {
-	/* Error? */
-	return 0;
+        /* Error? */
+        return 0;
     } 
-    
+
     dest = DMA_DEST(channel);
     count = DMA_COUNT(channel);
     if( count == 0 ) count = 0x01000000;
@@ -255,33 +255,33 @@
     size = DMAC_xfer_size[ (control >> 4)&0x07 ];
     run_count = numBytes / size;
     if( run_count > count || run_count == 0 )
-	run_count = count;
+        run_count = count;
 
     /* Do copy - FIXME: doesn't work when crossing regions */
     sh4ptr_t region = mem_get_region( dest );
     switch( (control >> 12) & 0x03 ) {
     case 0: 
-	for( i=0; i<run_count; i++ ) { 
-	    /* Doesn't make a whole lot of sense, but hey... */
-	    memcpy( region, buf, size );
-	    buf += size;
-	}
-	break;
+        for( i=0; i<run_count; i++ ) { 
+            /* Doesn't make a whole lot of sense, but hey... */
+            memcpy( region, buf, size );
+            buf += size;
+        }
+        break;
     case 1: 
-	i = run_count * size;
-	memcpy( region, buf, i );
-	dest += i;
-	break;
+        i = run_count * size;
+        memcpy( region, buf, i );
+        dest += i;
+        break;
     case 2: 
-	for( i=0; i<run_count; i++ ) {
-	    memcpy( region, buf, size );
-	    buf += size;
-	    region -= size;
-	}
-	dest -= (run_count * size);
-	break;
+        for( i=0; i<run_count; i++ ) {
+            memcpy( region, buf, size );
+            buf += size;
+            region -= size;
+        }
+        dest -= (run_count * size);
+        break;
     default:
-	return 0; /* Illegal */
+        return 0; /* Illegal */
     }
 
     /* Update the channel registers */
@@ -289,10 +289,10 @@
     MMIO_WRITE( DMAC, DAR0 + (channel<<4), dest );
     MMIO_WRITE( DMAC, DMATCR0 + (channel<<4), count );
     if( count == 0 ) {
-	control |= CHCR_TE; 
-	if( IS_CHANNEL_IRQ_ENABLED(control) )
-	    intc_raise_interrupt( INT_DMA_DMTE0 + channel );
-	MMIO_WRITE( DMAC, CHCR0 + (channel<<4), control );
+        control |= CHCR_TE; 
+        if( IS_CHANNEL_IRQ_ENABLED(control) )
+            intc_raise_interrupt( INT_DMA_DMTE0 + channel );
+        MMIO_WRITE( DMAC, CHCR0 + (channel<<4), control );
     }
     return run_count * size;
 }
@@ -316,37 +316,37 @@
 {
     int i;
     if( !IS_DMAC_ENABLED() )
-	return;
+        return;
     for( i=0; i<4; i++ ) {
-	uint32_t control = DMA_CONTROL(i);
-	if( IS_CHANNEL_ENABLED(control) ) {
-	    uint32_t channel_res = CHANNEL_RESOURCE(control);
-	    switch( resource ) {
-	    case DMAC_EXTERNAL:
-		if( channel_res == DMARES_MEMORY_TO_MEMORY )
-		    DMAC_run_channel(i,1);
-		break;
-	    case DMAC_SCI_TDE:
-		if( channel_res == DMARES_SCI_TRANSMIT_EMPTY )
-		    DMAC_run_channel(i,1);
-		break;
-	    case DMAC_SCI_RDF:
-		if( channel_res == DMARES_SCI_RECEIVE_FULL )
-		    DMAC_run_channel(i,1);
-		break;
-	    case DMAC_SCIF_TDE:
-		if( channel_res == DMARES_SCIF_TRANSMIT_EMPTY )
-		    DMAC_run_channel(i,1);
-		break;
-	    case DMAC_SCIF_RDF:
-		if( channel_res == DMARES_SCIF_RECEIVE_FULL )
-		    DMAC_run_channel(i,1);
-		break;
-	    case DMAC_TMU_ICI:
-		if( channel_res >= DMARES_MEMORY_TO_MEMORY_TMU ) 
-		    DMAC_run_channel(i,1);
-		break;
-	    }
-	}
+        uint32_t control = DMA_CONTROL(i);
+        if( IS_CHANNEL_ENABLED(control) ) {
+            uint32_t channel_res = CHANNEL_RESOURCE(control);
+            switch( resource ) {
+            case DMAC_EXTERNAL:
+                if( channel_res == DMARES_MEMORY_TO_MEMORY )
+                    DMAC_run_channel(i,1);
+                break;
+            case DMAC_SCI_TDE:
+                if( channel_res == DMARES_SCI_TRANSMIT_EMPTY )
+                    DMAC_run_channel(i,1);
+                break;
+            case DMAC_SCI_RDF:
+                if( channel_res == DMARES_SCI_RECEIVE_FULL )
+                    DMAC_run_channel(i,1);
+                break;
+            case DMAC_SCIF_TDE:
+                if( channel_res == DMARES_SCIF_TRANSMIT_EMPTY )
+                    DMAC_run_channel(i,1);
+                break;
+            case DMAC_SCIF_RDF:
+                if( channel_res == DMARES_SCIF_RECEIVE_FULL )
+                    DMAC_run_channel(i,1);
+                break;
+            case DMAC_TMU_ICI:
+                if( channel_res >= DMARES_MEMORY_TO_MEMORY_TMU ) 
+                    DMAC_run_channel(i,1);
+                break;
+            }
+        }
     }
 }