--- a/src/sh4/cache.c	Wed Dec 24 06:06:23 2008 +0000
+++ b/src/sh4/cache.c	Sat Jan 03 03:30:26 2009 +0000
@@ -1,6 +1,6 @@
 /**
  * $Id$
- * Implements the on-chip operand cache and instruction caches
+ * Implements the on-chip operand cache, instruction cache, and store queue.
  *
  * Copyright (c) 2008 Nathan Keynes.
  *
@@ -295,4 +295,21 @@
             sh4_address_space[i] = &mem_region_unmapped;
         break;
     }
-}
\ No newline at end of file
+}
+
+
+/***** Store-queue (considered part of the cache by the SH7750 manual) ******/
+static void FASTCALL p4_storequeue_write_long( sh4addr_t addr, uint32_t val )
+{
+    sh4r.store_queue[(addr>>2)&0xF] = val;
+}
+static int32_t FASTCALL p4_storequeue_read_long( sh4addr_t addr )
+{
+    return sh4r.store_queue[(addr>>2)&0xF];
+}
+
+struct mem_region_fn p4_region_storequeue = { 
+        p4_storequeue_read_long, p4_storequeue_write_long,
+        p4_storequeue_read_long, p4_storequeue_write_long,
+        p4_storequeue_read_long, p4_storequeue_write_long,
+        unmapped_read_burst, unmapped_write_burst }; // No burst access.