--- a/src/sh4/sh4x86.in	Thu Nov 08 11:54:16 2007 +0000
+++ b/src/sh4/sh4x86.in	Sat Nov 17 06:04:19 2007 +0000
@@ -522,7 +522,7 @@
  * @return true if the instruction marks the end of a basic block
  * (eg a branch or 
  */
-uint32_t sh4_x86_translate_instruction( sh4addr_t pc )
+uint32_t sh4_translate_instruction( sh4addr_t pc )
 {
     uint32_t ir;
     /* Read instruction */
@@ -1478,11 +1478,11 @@
 	    sh4_x86.tstate = TSTATE_E;
 	}
 	OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JNE rel32
-	sh4_x86_translate_instruction(pc+2);
+	sh4_translate_instruction(pc+2);
 	exit_block( disp + pc + 4, pc+4 );
 	// not taken
 	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
-	sh4_x86_translate_instruction(pc+2);
+	sh4_translate_instruction(pc+2);
 	return 4;
     }
 :}
@@ -1491,7 +1491,7 @@
 	SLOTILLEGAL();
     } else {
 	sh4_x86.in_delay_slot = TRUE;
-	sh4_x86_translate_instruction( pc + 2 );
+	sh4_translate_instruction( pc + 2 );
 	exit_block( disp + pc + 4, pc+4 );
 	sh4_x86.branch_taken = TRUE;
 	return 4;
@@ -1506,7 +1506,7 @@
 	store_spreg( R_EAX, REG_OFFSET(pc) );
 	sh4_x86.in_delay_slot = TRUE;
 	sh4_x86.tstate = TSTATE_NONE;
-	sh4_x86_translate_instruction( pc + 2 );
+	sh4_translate_instruction( pc + 2 );
 	exit_block_pcset(pc+2);
 	sh4_x86.branch_taken = TRUE;
 	return 4;
@@ -1519,7 +1519,7 @@
 	load_imm32( R_EAX, pc + 4 );
 	store_spreg( R_EAX, R_PR );
 	sh4_x86.in_delay_slot = TRUE;
-	sh4_x86_translate_instruction( pc + 2 );
+	sh4_translate_instruction( pc + 2 );
 	exit_block( disp + pc + 4, pc+4 );
 	sh4_x86.branch_taken = TRUE;
 	return 4;
@@ -1535,7 +1535,7 @@
 	store_spreg( R_ECX, REG_OFFSET(pc) );
 	sh4_x86.in_delay_slot = TRUE;
 	sh4_x86.tstate = TSTATE_NONE;
-	sh4_x86_translate_instruction( pc + 2 );
+	sh4_translate_instruction( pc + 2 );
 	exit_block_pcset(pc+2);
 	sh4_x86.branch_taken = TRUE;
 	return 4;
@@ -1561,11 +1561,11 @@
 	    sh4_x86.tstate = TSTATE_E;
 	}
 	OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JE rel32
-	sh4_x86_translate_instruction(pc+2);
+	sh4_translate_instruction(pc+2);
 	exit_block( disp + pc + 4, pc+4 );
 	// not taken
 	*patch = (xlat_output - ((uint8_t *)patch)) - 4;
-	sh4_x86_translate_instruction(pc+2);
+	sh4_translate_instruction(pc+2);
 	return 4;
     }
 :}
@@ -1576,7 +1576,7 @@
 	load_reg( R_ECX, Rn );
 	store_spreg( R_ECX, REG_OFFSET(pc) );
 	sh4_x86.in_delay_slot = TRUE;
-	sh4_x86_translate_instruction(pc+2);
+	sh4_translate_instruction(pc+2);
 	exit_block_pcset(pc+2);
 	sh4_x86.branch_taken = TRUE;
 	return 4;
@@ -1591,7 +1591,7 @@
 	load_reg( R_ECX, Rn );
 	store_spreg( R_ECX, REG_OFFSET(pc) );
 	sh4_x86.in_delay_slot = TRUE;
-	sh4_x86_translate_instruction(pc+2);
+	sh4_translate_instruction(pc+2);
 	exit_block_pcset(pc+2);
 	sh4_x86.branch_taken = TRUE;
 	return 4;
@@ -1610,7 +1610,7 @@
 	sh4_x86.priv_checked = FALSE;
 	sh4_x86.fpuen_checked = FALSE;
 	sh4_x86.tstate = TSTATE_NONE;
-	sh4_x86_translate_instruction(pc+2);
+	sh4_translate_instruction(pc+2);
 	exit_block_pcset(pc+2);
 	sh4_x86.branch_taken = TRUE;
 	return 4;
@@ -1623,7 +1623,7 @@
 	load_spreg( R_ECX, R_PR );
 	store_spreg( R_ECX, REG_OFFSET(pc) );
 	sh4_x86.in_delay_slot = TRUE;
-	sh4_x86_translate_instruction(pc+2);
+	sh4_translate_instruction(pc+2);
 	exit_block_pcset(pc+2);
 	sh4_x86.branch_taken = TRUE;
 	return 4;