--- a/src/sh4/sh4core.c Tue Jan 23 08:17:06 2007 +0000 +++ b/src/sh4/sh4core.c Tue Aug 28 08:46:14 2007 +0000 @@ -1,5 +1,5 @@ /** - * $Id: sh4core.c,v 1.40 2007-01-23 08:17:06 nkeynes Exp $ + * $Id: sh4core.c,v 1.41 2007-08-23 12:33:27 nkeynes Exp $ * * SH4 emulation core, and parent module for all the SH4 peripheral * modules. @@ -58,7 +58,7 @@ void sh4_stop( void ); void sh4_save_state( FILE *f ); int sh4_load_state( FILE *f ); -static void sh4_accept_interrupt( void ); +void sh4_accept_interrupt( void ); struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, NULL, sh4_run_slice, sh4_stop, @@ -327,7 +327,7 @@ #define CHECKWALIGN16(addr) if( (addr)&0x01 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR ) #define CHECKWALIGN32(addr) if( (addr)&0x03 ) return sh4_raise_exception( EXC_WRITE_ADDR_ERR ) -#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE ) +#define CHECKFPUEN() if( !IS_FPU_ENABLED() ) { if( ir == 0xFFFD ) { UNDEF(ir); } else { return sh4_raise_slot_exception( EXC_FPDISABLE, EXC_SLOT_FPDISABLE ); } } #define CHECKDEST(p) if( (p) == 0 ) { ERROR( "%08X: Branch/jump to NULL, CPU halted", sh4r.pc ); dreamcast_stop(); return FALSE; } #define CHECKSLOTILLEGAL() if(sh4r.in_delay_slot) return sh4_raise_exception(EXC_SLOT_ILLEGAL) @@ -415,7 +415,7 @@ RAISE( code, EXV_TLBMISS ); } -static void sh4_accept_interrupt( void ) +void sh4_accept_interrupt( void ) { uint32_t code = intc_accept_interrupt(); sh4r.ssr = sh4_read_sr(); @@ -433,39 +433,10 @@ uint32_t pc; unsigned short ir; uint32_t tmp; - uint64_t tmpl; float ftmp; double dtmp; #define R0 sh4r.r[0] -#define FR0 FR(0) -#define DR0 DR(0) -#define RN(ir) sh4r.r[(ir&0x0F00)>>8] -#define RN_BANK(ir) sh4r.r_bank[(ir&0x0070)>>4] -#define RM(ir) sh4r.r[(ir&0x00F0)>>4] -#define DISP4(ir) (ir&0x000F) /* 4-bit displacements are *NOT* sign-extended */ -#define DISP8(ir) (ir&0x00FF) -#define PCDISP8(ir) SIGNEXT8(ir&0x00FF) -#define IMM8(ir) SIGNEXT8(ir&0x00FF) -#define UIMM8(ir) (ir&0x00FF) /* Unsigned immmediate */ -#define DISP12(ir) SIGNEXT12(ir&0x0FFF) -#define FRNn(ir) ((ir&0x0F00)>>8) -#define FRMn(ir) ((ir&0x00F0)>>4) -#define DRNn(ir) ((ir&0x0E00)>>9) -#define DRMn(ir) ((ir&0x00E0)>>5) -#define FVN(ir) ((ir&0x0C00)>>8) -#define FVM(ir) ((ir&0x0300)>>6) -#define FRN(ir) FR(FRNn(ir)) -#define FRM(ir) FR(FRMn(ir)) -#define FRNi(ir) (*((uint32_t *)&FR(FRNn(ir)))) -#define FRMi(ir) (*((uint32_t *)&FR(FRMn(ir)))) -#define DRN(ir) DRb(DRNn(ir), ir&0x0100) -#define DRM(ir) DRb(DRMn(ir),ir&0x0010) -#define DRNi(ir) (*((uint64_t *)&DR(FRNn(ir)))) -#define DRMi(ir) (*((uint64_t *)&DR(FRMn(ir)))) -#define FPULf *((float *)&sh4r.fpul) -#define FPULi (sh4r.fpul) - pc = sh4r.pc; if( pc > 0xFFFFFF00 ) { /* SYSCALL Magic */ @@ -493,1176 +464,1891 @@ ir = sh4_icache[(pc&0xFFF)>>1]; } } - - switch( (ir&0xF000)>>12 ) { - case 0: /* 0000nnnnmmmmxxxx */ - switch( ir&0x000F ) { - case 2: - switch( (ir&0x00F0)>>4 ) { - case 0: /* STC SR, Rn */ - CHECKPRIV(); - RN(ir) = sh4_read_sr(); - break; - case 1: /* STC GBR, Rn */ - RN(ir) = sh4r.gbr; - break; - case 2: /* STC VBR, Rn */ - CHECKPRIV(); - RN(ir) = sh4r.vbr; - break; - case 3: /* STC SSR, Rn */ - CHECKPRIV(); - RN(ir) = sh4r.ssr; - break; - case 4: /* STC SPC, Rn */ - CHECKPRIV(); - RN(ir) = sh4r.spc; - break; - case 8: case 9: case 10: case 11: case 12: case 13: - case 14: case 15:/* STC Rm_bank, Rn */ - CHECKPRIV(); - RN(ir) = RN_BANK(ir); - break; - default: UNDEF(ir); - } - break; - case 3: - switch( (ir&0x00F0)>>4 ) { - case 0: /* BSRF Rn */ - CHECKSLOTILLEGAL(); - CHECKDEST( pc + 4 + RN(ir) ); - sh4r.in_delay_slot = 1; - sh4r.pr = sh4r.pc + 4; - sh4r.pc = sh4r.new_pc; - sh4r.new_pc = pc + 4 + RN(ir); - TRACE_CALL( pc, sh4r.new_pc ); + switch( (ir&0xF000) >> 12 ) { + case 0x0: + switch( ir&0xF ) { + case 0x2: + switch( (ir&0x80) >> 7 ) { + case 0x0: + switch( (ir&0x70) >> 4 ) { + case 0x0: + { /* STC SR, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] = sh4_read_sr(); + } + break; + case 0x1: + { /* STC GBR, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] = sh4r.gbr; + } + break; + case 0x2: + { /* STC VBR, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] = sh4r.vbr; + } + break; + case 0x3: + { /* STC SSR, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] = sh4r.ssr; + } + break; + case 0x4: + { /* STC SPC, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] = sh4r.spc; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x1: + { /* STC Rm_BANK, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); + CHECKPRIV(); + sh4r.r[Rn] = sh4r.r_bank[Rm_BANK]; + } + break; + } + break; + case 0x3: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* BSRF Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKSLOTILLEGAL(); + CHECKDEST( pc + 4 + sh4r.r[Rn] ); + sh4r.in_delay_slot = 1; + sh4r.pr = sh4r.pc + 4; + sh4r.pc = sh4r.new_pc; + sh4r.new_pc = pc + 4 + sh4r.r[Rn]; + TRACE_CALL( pc, sh4r.new_pc ); + return TRUE; + } + break; + case 0x2: + { /* BRAF Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKSLOTILLEGAL(); + CHECKDEST( pc + 4 + sh4r.r[Rn] ); + sh4r.in_delay_slot = 1; + sh4r.pc = sh4r.new_pc; + sh4r.new_pc = pc + 4 + sh4r.r[Rn]; + return TRUE; + } + break; + case 0x8: + { /* PREF @Rn */ + uint32_t Rn = ((ir>>8)&0xF); + tmp = sh4r.r[Rn]; + if( (tmp & 0xFC000000) == 0xE0000000 ) { + /* Store queue operation */ + int queue = (tmp&0x20)>>2; + int32_t *src = &sh4r.store_queue[queue]; + uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24; + uint32_t target = tmp&0x03FFFFE0 | hi; + mem_copy_to_sh4( target, src, 32 ); + } + } + break; + case 0x9: + { /* OCBI @Rn */ + uint32_t Rn = ((ir>>8)&0xF); + } + break; + case 0xA: + { /* OCBP @Rn */ + uint32_t Rn = ((ir>>8)&0xF); + } + break; + case 0xB: + { /* OCBWB @Rn */ + uint32_t Rn = ((ir>>8)&0xF); + } + break; + case 0xC: + { /* MOVCA.L R0, @Rn */ + uint32_t Rn = ((ir>>8)&0xF); + tmp = sh4r.r[Rn]; + CHECKWALIGN32(tmp); + MEM_WRITE_LONG( tmp, R0 ); + } + break; + default: + UNDEF(); + break; + } + break; + case 0x4: + { /* MOV.B Rm, @(R0, Rn) */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + MEM_WRITE_BYTE( R0 + sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x5: + { /* MOV.W Rm, @(R0, Rn) */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKWALIGN16( R0 + sh4r.r[Rn] ); + MEM_WRITE_WORD( R0 + sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x6: + { /* MOV.L Rm, @(R0, Rn) */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKWALIGN32( R0 + sh4r.r[Rn] ); + MEM_WRITE_LONG( R0 + sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x7: + { /* MUL.L Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | + (sh4r.r[Rm] * sh4r.r[Rn]); + } + break; + case 0x8: + switch( (ir&0xFF0) >> 4 ) { + case 0x0: + { /* CLRT */ + sh4r.t = 0; + } + break; + case 0x1: + { /* SETT */ + sh4r.t = 1; + } + break; + case 0x2: + { /* CLRMAC */ + sh4r.mac = 0; + } + break; + case 0x3: + { /* LDTLB */ + /* TODO */ + } + break; + case 0x4: + { /* CLRS */ + sh4r.s = 0; + } + break; + case 0x5: + { /* SETS */ + sh4r.s = 1; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x9: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* NOP */ + /* NOP */ + } + break; + case 0x1: + { /* DIV0U */ + sh4r.m = sh4r.q = sh4r.t = 0; + } + break; + case 0x2: + { /* MOVT Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] = sh4r.t; + } + break; + default: + UNDEF(); + break; + } + break; + case 0xA: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* STS MACH, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] = (sh4r.mac>>32); + } + break; + case 0x1: + { /* STS MACL, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] = (uint32_t)sh4r.mac; + } + break; + case 0x2: + { /* STS PR, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] = sh4r.pr; + } + break; + case 0x3: + { /* STC SGR, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] = sh4r.sgr; + } + break; + case 0x5: + { /* STS FPUL, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] = sh4r.fpul; + } + break; + case 0x6: + { /* STS FPSCR, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] = sh4r.fpscr; + } + break; + case 0xF: + { /* STC DBR, Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); sh4r.r[Rn] = sh4r.dbr; + } + break; + default: + UNDEF(); + break; + } + break; + case 0xB: + switch( (ir&0xFF0) >> 4 ) { + case 0x0: + { /* RTS */ + CHECKSLOTILLEGAL(); + CHECKDEST( sh4r.pr ); + sh4r.in_delay_slot = 1; + sh4r.pc = sh4r.new_pc; + sh4r.new_pc = sh4r.pr; + TRACE_RETURN( pc, sh4r.new_pc ); + return TRUE; + } + break; + case 0x1: + { /* SLEEP */ + if( MMIO_READ( CPG, STBCR ) & 0x80 ) { + sh4r.sh4_state = SH4_STATE_STANDBY; + } else { + sh4r.sh4_state = SH4_STATE_SLEEP; + } + return FALSE; /* Halt CPU */ + } + break; + case 0x2: + { /* RTE */ + CHECKPRIV(); + CHECKDEST( sh4r.spc ); + CHECKSLOTILLEGAL(); + sh4r.in_delay_slot = 1; + sh4r.pc = sh4r.new_pc; + sh4r.new_pc = sh4r.spc; + sh4_load_sr( sh4r.ssr ); + return TRUE; + } + break; + default: + UNDEF(); + break; + } + break; + case 0xC: + { /* MOV.B @(R0, Rm), Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = MEM_READ_BYTE( R0 + sh4r.r[Rm] ); + } + break; + case 0xD: + { /* MOV.W @(R0, Rm), Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKRALIGN16( R0 + sh4r.r[Rm] ); + sh4r.r[Rn] = MEM_READ_WORD( R0 + sh4r.r[Rm] ); + } + break; + case 0xE: + { /* MOV.L @(R0, Rm), Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKRALIGN32( R0 + sh4r.r[Rm] ); + sh4r.r[Rn] = MEM_READ_LONG( R0 + sh4r.r[Rm] ); + } + break; + case 0xF: + { /* MAC.L @Rm+, @Rn+ */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); + CHECKRALIGN32( sh4r.r[Rn] ); + int64_t tmpl = SIGNEXT32(MEM_READ_LONG(sh4r.r[Rn])); + sh4r.r[Rn] += 4; + tmpl = tmpl * SIGNEXT32(MEM_READ_LONG(sh4r.r[Rm])) + sh4r.mac; + sh4r.r[Rm] += 4; + if( sh4r.s ) { + /* 48-bit Saturation. Yuch */ + if( tmpl < (int64_t)0xFFFF800000000000LL ) + tmpl = 0xFFFF800000000000LL; + else if( tmpl > (int64_t)0x00007FFFFFFFFFFFLL ) + tmpl = 0x00007FFFFFFFFFFFLL; + } + sh4r.mac = tmpl; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x1: + { /* MOV.L Rm, @(disp, Rn) */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; + tmp = sh4r.r[Rn] + disp; + CHECKWALIGN32( tmp ); + MEM_WRITE_LONG( tmp, sh4r.r[Rm] ); + } + break; + case 0x2: + switch( ir&0xF ) { + case 0x0: + { /* MOV.B Rm, @Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x1: + { /* MOV.W Rm, @Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x2: + { /* MOV.L Rm, @Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x4: + { /* MOV.B Rm, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] --; MEM_WRITE_BYTE( sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x5: + { /* MOV.W Rm, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] -= 2; CHECKWALIGN16( sh4r.r[Rn] ); MEM_WRITE_WORD( sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x6: + { /* MOV.L Rm, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] -= 4; CHECKWALIGN32( sh4r.r[Rn] ); MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r[Rm] ); + } + break; + case 0x7: + { /* DIV0S Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.q = sh4r.r[Rn]>>31; + sh4r.m = sh4r.r[Rm]>>31; + sh4r.t = sh4r.q ^ sh4r.m; + } + break; + case 0x8: + { /* TST Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.t = (sh4r.r[Rn]&sh4r.r[Rm] ? 0 : 1); + } + break; + case 0x9: + { /* AND Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] &= sh4r.r[Rm]; + } + break; + case 0xA: + { /* XOR Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] ^= sh4r.r[Rm]; + } + break; + case 0xB: + { /* OR Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] |= sh4r.r[Rm]; + } + break; + case 0xC: + { /* CMP/STR Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + /* set T = 1 if any byte in RM & RN is the same */ + tmp = sh4r.r[Rm] ^ sh4r.r[Rn]; + sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 || + (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0; + } + break; + case 0xD: + { /* XTRCT Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = (sh4r.r[Rn]>>16) | (sh4r.r[Rm]<<16); + } + break; + case 0xE: + { /* MULU.W Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | + (uint32_t)((sh4r.r[Rm]&0xFFFF) * (sh4r.r[Rn]&0xFFFF)); + } + break; + case 0xF: + { /* MULS.W Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | + (uint32_t)(SIGNEXT32(sh4r.r[Rm]&0xFFFF) * SIGNEXT32(sh4r.r[Rn]&0xFFFF)); + } + break; + default: + UNDEF(); + break; + } + break; + case 0x3: + switch( ir&0xF ) { + case 0x0: + { /* CMP/EQ Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.t = ( sh4r.r[Rm] == sh4r.r[Rn] ? 1 : 0 ); + } + break; + case 0x2: + { /* CMP/HS Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.t = ( sh4r.r[Rn] >= sh4r.r[Rm] ? 1 : 0 ); + } + break; + case 0x3: + { /* CMP/GE Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); + } + break; + case 0x4: + { /* DIV1 Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + /* This is just from the sh4p manual with some + * simplifications (someone want to check it's correct? :) + * Why they couldn't just provide a real DIV instruction... + */ + uint32_t tmp0, tmp1, tmp2, dir; + + dir = sh4r.q ^ sh4r.m; + sh4r.q = (sh4r.r[Rn] >> 31); + tmp2 = sh4r.r[Rm]; + sh4r.r[Rn] = (sh4r.r[Rn] << 1) | sh4r.t; + tmp0 = sh4r.r[Rn]; + if( dir ) { + sh4r.r[Rn] += tmp2; + tmp1 = (sh4r.r[Rn]tmp0 ? 1 : 0 ); + } + sh4r.q ^= sh4r.m ^ tmp1; + sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 ); + } + break; + case 0x5: + { /* DMULU.L Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.mac = ((uint64_t)sh4r.r[Rm]) * ((uint64_t)sh4r.r[Rn]); + } + break; + case 0x6: + { /* CMP/HI Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.t = ( sh4r.r[Rn] > sh4r.r[Rm] ? 1 : 0 ); + } + break; + case 0x7: + { /* CMP/GT Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.t = ( ((int32_t)sh4r.r[Rn]) > ((int32_t)sh4r.r[Rm]) ? 1 : 0 ); + } + break; + case 0x8: + { /* SUB Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] -= sh4r.r[Rm]; + } + break; + case 0xA: + { /* SUBC Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + tmp = sh4r.r[Rn]; + sh4r.r[Rn] = sh4r.r[Rn] - sh4r.r[Rm] - sh4r.t; + sh4r.t = (sh4r.r[Rn] > tmp || (sh4r.r[Rn] == tmp && sh4r.t == 1)); + } + break; + case 0xB: + UNIMP(ir); /* SUBV Rm, Rn */ + break; + case 0xC: + { /* ADD Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] += sh4r.r[Rm]; + } + break; + case 0xD: + { /* DMULS.L Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.mac = SIGNEXT32(sh4r.r[Rm]) * SIGNEXT32(sh4r.r[Rn]); + } + break; + case 0xE: + { /* ADDC Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + tmp = sh4r.r[Rn]; + sh4r.r[Rn] += sh4r.r[Rm] + sh4r.t; + sh4r.t = ( sh4r.r[Rn] < tmp || (sh4r.r[Rn] == tmp && sh4r.t != 0) ? 1 : 0 ); + } + break; + case 0xF: + { /* ADDV Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + tmp = sh4r.r[Rn] + sh4r.r[Rm]; + sh4r.t = ( (sh4r.r[Rn]>>31) == (sh4r.r[Rm]>>31) && ((sh4r.r[Rn]>>31) != (tmp>>31)) ); + sh4r.r[Rn] = tmp; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x4: + switch( ir&0xF ) { + case 0x0: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* SHLL Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.t = sh4r.r[Rn] >> 31; sh4r.r[Rn] <<= 1; + } + break; + case 0x1: + { /* DT Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] --; + sh4r.t = ( sh4r.r[Rn] == 0 ? 1 : 0 ); + } + break; + case 0x2: + { /* SHAL Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.t = sh4r.r[Rn] >> 31; + sh4r.r[Rn] <<= 1; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x1: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* SHLR Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.t = sh4r.r[Rn] & 0x00000001; sh4r.r[Rn] >>= 1; + } + break; + case 0x1: + { /* CMP/PZ Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.t = ( ((int32_t)sh4r.r[Rn]) >= 0 ? 1 : 0 ); + } + break; + case 0x2: + { /* SHAR Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.t = sh4r.r[Rn] & 0x00000001; + sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 1; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x2: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* STS.L MACH, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], (sh4r.mac>>32) ); + } + break; + case 0x1: + { /* STS.L MACL, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], (uint32_t)sh4r.mac ); + } + break; + case 0x2: + { /* STS.L PR, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.pr ); + } + break; + case 0x3: + { /* STC.L SGR, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.sgr ); + } + break; + case 0x5: + { /* STS.L FPUL, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpul ); + } + break; + case 0x6: + { /* STS.L FPSCR, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.fpscr ); + } + break; + case 0xF: + { /* STC.L DBR, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.dbr ); + } + break; + default: + UNDEF(); + break; + } + break; + case 0x3: + switch( (ir&0x80) >> 7 ) { + case 0x0: + switch( (ir&0x70) >> 4 ) { + case 0x0: + { /* STC.L SR, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4_read_sr() ); + } + break; + case 0x1: + { /* STC.L GBR, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.gbr ); + } + break; + case 0x2: + { /* STC.L VBR, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.vbr ); + } + break; + case 0x3: + { /* STC.L SSR, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.ssr ); + } + break; + case 0x4: + { /* STC.L SPC, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.spc ); + } + break; + default: + UNDEF(); + break; + } + break; + case 0x1: + { /* STC.L Rm_BANK, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7); + CHECKPRIV(); + sh4r.r[Rn] -= 4; + CHECKWALIGN32( sh4r.r[Rn] ); + MEM_WRITE_LONG( sh4r.r[Rn], sh4r.r_bank[Rm_BANK] ); + } + break; + } + break; + case 0x4: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* ROTL Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.t = sh4r.r[Rn] >> 31; + sh4r.r[Rn] <<= 1; + sh4r.r[Rn] |= sh4r.t; + } + break; + case 0x2: + { /* ROTCL Rn */ + uint32_t Rn = ((ir>>8)&0xF); + tmp = sh4r.r[Rn] >> 31; + sh4r.r[Rn] <<= 1; + sh4r.r[Rn] |= sh4r.t; + sh4r.t = tmp; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x5: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* ROTR Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.t = sh4r.r[Rn] & 0x00000001; + sh4r.r[Rn] >>= 1; + sh4r.r[Rn] |= (sh4r.t << 31); + } + break; + case 0x1: + { /* CMP/PL Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.t = ( ((int32_t)sh4r.r[Rn]) > 0 ? 1 : 0 ); + } + break; + case 0x2: + { /* ROTCR Rn */ + uint32_t Rn = ((ir>>8)&0xF); + tmp = sh4r.r[Rn] & 0x00000001; + sh4r.r[Rn] >>= 1; + sh4r.r[Rn] |= (sh4r.t << 31 ); + sh4r.t = tmp; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x6: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* LDS.L @Rm+, MACH */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) | + (((uint64_t)MEM_READ_LONG(sh4r.r[Rm]))<<32); + sh4r.r[Rm] += 4; + } + break; + case 0x1: + { /* LDS.L @Rm+, MACL */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | + (uint64_t)((uint32_t)MEM_READ_LONG(sh4r.r[Rm])); + sh4r.r[Rm] += 4; + } + break; + case 0x2: + { /* LDS.L @Rm+, PR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.pr = MEM_READ_LONG( sh4r.r[Rm] ); + sh4r.r[Rm] += 4; + } + break; + case 0x3: + { /* LDC.L @Rm+, SGR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.sgr = MEM_READ_LONG(sh4r.r[Rm]); + sh4r.r[Rm] +=4; + } + break; + case 0x5: + { /* LDS.L @Rm+, FPUL */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.fpul = MEM_READ_LONG(sh4r.r[Rm]); + sh4r.r[Rm] +=4; + } + break; + case 0x6: + { /* LDS.L @Rm+, FPSCR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.fpscr = MEM_READ_LONG(sh4r.r[Rm]); + sh4r.r[Rm] +=4; + } + break; + case 0xF: + { /* LDC.L @Rm+, DBR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.dbr = MEM_READ_LONG(sh4r.r[Rm]); + sh4r.r[Rm] +=4; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x7: + switch( (ir&0x80) >> 7 ) { + case 0x0: + switch( (ir&0x70) >> 4 ) { + case 0x0: + { /* LDC.L @Rm+, SR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKSLOTILLEGAL(); + CHECKPRIV(); + CHECKWALIGN32( sh4r.r[Rm] ); + sh4_load_sr( MEM_READ_LONG(sh4r.r[Rm]) ); + sh4r.r[Rm] +=4; + } + break; + case 0x1: + { /* LDC.L @Rm+, GBR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.gbr = MEM_READ_LONG(sh4r.r[Rm]); + sh4r.r[Rm] +=4; + } + break; + case 0x2: + { /* LDC.L @Rm+, VBR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.vbr = MEM_READ_LONG(sh4r.r[Rm]); + sh4r.r[Rm] +=4; + } + break; + case 0x3: + { /* LDC.L @Rm+, SSR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.ssr = MEM_READ_LONG(sh4r.r[Rm]); + sh4r.r[Rm] +=4; + } + break; + case 0x4: + { /* LDC.L @Rm+, SPC */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.spc = MEM_READ_LONG(sh4r.r[Rm]); + sh4r.r[Rm] +=4; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x1: + { /* LDC.L @Rm+, Rn_BANK */ + uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); + CHECKPRIV(); + CHECKRALIGN32( sh4r.r[Rm] ); + sh4r.r_bank[Rn_BANK] = MEM_READ_LONG( sh4r.r[Rm] ); + sh4r.r[Rm] += 4; + } + break; + } + break; + case 0x8: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* SHLL2 Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] <<= 2; + } + break; + case 0x1: + { /* SHLL8 Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] <<= 8; + } + break; + case 0x2: + { /* SHLL16 Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] <<= 16; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x9: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* SHLR2 Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] >>= 2; + } + break; + case 0x1: + { /* SHLR8 Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] >>= 8; + } + break; + case 0x2: + { /* SHLR16 Rn */ + uint32_t Rn = ((ir>>8)&0xF); + sh4r.r[Rn] >>= 16; + } + break; + default: + UNDEF(); + break; + } + break; + case 0xA: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* LDS Rm, MACH */ + uint32_t Rm = ((ir>>8)&0xF); + sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) | + (((uint64_t)sh4r.r[Rm])<<32); + } + break; + case 0x1: + { /* LDS Rm, MACL */ + uint32_t Rm = ((ir>>8)&0xF); + sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | + (uint64_t)((uint32_t)(sh4r.r[Rm])); + } + break; + case 0x2: + { /* LDS Rm, PR */ + uint32_t Rm = ((ir>>8)&0xF); + sh4r.pr = sh4r.r[Rm]; + } + break; + case 0x3: + { /* LDC Rm, SGR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.sgr = sh4r.r[Rm]; + } + break; + case 0x5: + { /* LDS Rm, FPUL */ + uint32_t Rm = ((ir>>8)&0xF); + sh4r.fpul = sh4r.r[Rm]; + } + break; + case 0x6: + { /* LDS Rm, FPSCR */ + uint32_t Rm = ((ir>>8)&0xF); + sh4r.fpscr = sh4r.r[Rm]; + } + break; + case 0xF: + { /* LDC Rm, DBR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.dbr = sh4r.r[Rm]; + } + break; + default: + UNDEF(); + break; + } + break; + case 0xB: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* JSR @Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKDEST( sh4r.r[Rn] ); + CHECKSLOTILLEGAL(); + sh4r.in_delay_slot = 1; + sh4r.pc = sh4r.new_pc; + sh4r.new_pc = sh4r.r[Rn]; + sh4r.pr = pc + 4; + TRACE_CALL( pc, sh4r.new_pc ); + return TRUE; + } + break; + case 0x1: + { /* TAS.B @Rn */ + uint32_t Rn = ((ir>>8)&0xF); + tmp = MEM_READ_BYTE( sh4r.r[Rn] ); + sh4r.t = ( tmp == 0 ? 1 : 0 ); + MEM_WRITE_BYTE( sh4r.r[Rn], tmp | 0x80 ); + } + break; + case 0x2: + { /* JMP @Rn */ + uint32_t Rn = ((ir>>8)&0xF); + CHECKDEST( sh4r.r[Rn] ); + CHECKSLOTILLEGAL(); + sh4r.in_delay_slot = 1; + sh4r.pc = sh4r.new_pc; + sh4r.new_pc = sh4r.r[Rn]; + return TRUE; + } + break; + default: + UNDEF(); + break; + } + break; + case 0xC: + { /* SHAD Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + tmp = sh4r.r[Rm]; + if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f); + else if( (tmp & 0x1F) == 0 ) + sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> 31; + else + sh4r.r[Rn] = ((int32_t)sh4r.r[Rn]) >> (((~sh4r.r[Rm]) & 0x1F)+1); + } + break; + case 0xD: + { /* SHLD Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + tmp = sh4r.r[Rm]; + if( (tmp & 0x80000000) == 0 ) sh4r.r[Rn] <<= (tmp&0x1f); + else if( (tmp & 0x1F) == 0 ) sh4r.r[Rn] = 0; + else sh4r.r[Rn] >>= (((~tmp) & 0x1F)+1); + } + break; + case 0xE: + switch( (ir&0x80) >> 7 ) { + case 0x0: + switch( (ir&0x70) >> 4 ) { + case 0x0: + { /* LDC Rm, SR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKSLOTILLEGAL(); + CHECKPRIV(); + sh4_load_sr( sh4r.r[Rm] ); + } + break; + case 0x1: + { /* LDC Rm, GBR */ + uint32_t Rm = ((ir>>8)&0xF); + sh4r.gbr = sh4r.r[Rm]; + } + break; + case 0x2: + { /* LDC Rm, VBR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.vbr = sh4r.r[Rm]; + } + break; + case 0x3: + { /* LDC Rm, SSR */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.ssr = sh4r.r[Rm]; + } + break; + case 0x4: + { /* LDC Rm, SPC */ + uint32_t Rm = ((ir>>8)&0xF); + CHECKPRIV(); + sh4r.spc = sh4r.r[Rm]; + } + break; + default: + UNDEF(); + break; + } + break; + case 0x1: + { /* LDC Rm, Rn_BANK */ + uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7); + CHECKPRIV(); + sh4r.r_bank[Rn_BANK] = sh4r.r[Rm]; + } + break; + } + break; + case 0xF: + { /* MAC.W @Rm+, @Rn+ */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKRALIGN16( sh4r.r[Rn] ); + CHECKRALIGN16( sh4r.r[Rm] ); + int32_t stmp = SIGNEXT16(MEM_READ_WORD(sh4r.r[Rn])); + sh4r.r[Rn] += 2; + stmp = stmp * SIGNEXT16(MEM_READ_WORD(sh4r.r[Rm])); + sh4r.r[Rm] += 2; + if( sh4r.s ) { + int64_t tmpl = (int64_t)((int32_t)sh4r.mac) + (int64_t)stmp; + if( tmpl > (int64_t)0x000000007FFFFFFFLL ) { + sh4r.mac = 0x000000017FFFFFFFLL; + } else if( tmpl < (int64_t)0xFFFFFFFF80000000LL ) { + sh4r.mac = 0x0000000180000000LL; + } else { + sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | + ((uint32_t)(sh4r.mac + stmp)); + } + } else { + sh4r.mac += SIGNEXT32(stmp); + } + } + break; + } + break; + case 0x5: + { /* MOV.L @(disp, Rm), Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2; + tmp = sh4r.r[Rm] + disp; + CHECKRALIGN32( tmp ); + sh4r.r[Rn] = MEM_READ_LONG( tmp ); + } + break; + case 0x6: + switch( ir&0xF ) { + case 0x0: + { /* MOV.B @Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); + } + break; + case 0x1: + { /* MOV.W @Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); + } + break; + case 0x2: + { /* MOV.L @Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); + } + break; + case 0x3: + { /* MOV Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = sh4r.r[Rm]; + } + break; + case 0x4: + { /* MOV.B @Rm+, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = MEM_READ_BYTE( sh4r.r[Rm] ); sh4r.r[Rm] ++; + } + break; + case 0x5: + { /* MOV.W @Rm+, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKRALIGN16( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_WORD( sh4r.r[Rm] ); sh4r.r[Rm] += 2; + } + break; + case 0x6: + { /* MOV.L @Rm+, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + CHECKRALIGN32( sh4r.r[Rm] ); sh4r.r[Rn] = MEM_READ_LONG( sh4r.r[Rm] ); sh4r.r[Rm] += 4; + } + break; + case 0x7: + { /* NOT Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = ~sh4r.r[Rm]; + } + break; + case 0x8: + { /* SWAP.B Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = (sh4r.r[Rm]&0xFFFF0000) | ((sh4r.r[Rm]&0x0000FF00)>>8) | ((sh4r.r[Rm]&0x000000FF)<<8); + } + break; + case 0x9: + { /* SWAP.W Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = (sh4r.r[Rm]>>16) | (sh4r.r[Rm]<<16); + } + break; + case 0xA: + { /* NEGC Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + tmp = 0 - sh4r.r[Rm]; + sh4r.r[Rn] = tmp - sh4r.t; + sh4r.t = ( 0>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = 0 - sh4r.r[Rm]; + } + break; + case 0xC: + { /* EXTU.B Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = sh4r.r[Rm]&0x000000FF; + } + break; + case 0xD: + { /* EXTU.W Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = sh4r.r[Rm]&0x0000FFFF; + } + break; + case 0xE: + { /* EXTS.B Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = SIGNEXT8( sh4r.r[Rm]&0x000000FF ); + } + break; + case 0xF: + { /* EXTS.W Rm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + sh4r.r[Rn] = SIGNEXT16( sh4r.r[Rm]&0x0000FFFF ); + } + break; + } + break; + case 0x7: + { /* ADD #imm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); + sh4r.r[Rn] += imm; + } + break; + case 0x8: + switch( (ir&0xF00) >> 8 ) { + case 0x0: + { /* MOV.B R0, @(disp, Rn) */ + uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); + MEM_WRITE_BYTE( sh4r.r[Rn] + disp, R0 ); + } + break; + case 0x1: + { /* MOV.W R0, @(disp, Rn) */ + uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; + tmp = sh4r.r[Rn] + disp; + CHECKWALIGN16( tmp ); + MEM_WRITE_WORD( tmp, R0 ); + } + break; + case 0x4: + { /* MOV.B @(disp, Rm), R0 */ + uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF); + R0 = MEM_READ_BYTE( sh4r.r[Rm] + disp ); + } + break; + case 0x5: + { /* MOV.W @(disp, Rm), R0 */ + uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1; + tmp = sh4r.r[Rm] + disp; + CHECKRALIGN16( tmp ); + R0 = MEM_READ_WORD( tmp ); + } + break; + case 0x8: + { /* CMP/EQ #imm, R0 */ + int32_t imm = SIGNEXT8(ir&0xFF); + sh4r.t = ( R0 == imm ? 1 : 0 ); + } + break; + case 0x9: + { /* BT disp */ + int32_t disp = SIGNEXT8(ir&0xFF)<<1; + CHECKSLOTILLEGAL(); + if( sh4r.t ) { + CHECKDEST( sh4r.pc + disp + 4 ) + sh4r.pc += disp + 4; + sh4r.new_pc = sh4r.pc + 2; return TRUE; - case 2: /* BRAF Rn */ - CHECKSLOTILLEGAL(); - CHECKDEST( pc + 4 + RN(ir) ); + } + } + break; + case 0xB: + { /* BF disp */ + int32_t disp = SIGNEXT8(ir&0xFF)<<1; + CHECKSLOTILLEGAL(); + if( !sh4r.t ) { + CHECKDEST( sh4r.pc + disp + 4 ) + sh4r.pc += disp + 4; + sh4r.new_pc = sh4r.pc + 2; + return TRUE; + } + } + break; + case 0xD: + { /* BT/S disp */ + int32_t disp = SIGNEXT8(ir&0xFF)<<1; + CHECKSLOTILLEGAL(); + if( sh4r.t ) { + CHECKDEST( sh4r.pc + disp + 4 ) sh4r.in_delay_slot = 1; sh4r.pc = sh4r.new_pc; - sh4r.new_pc = pc + 4 + RN(ir); + sh4r.new_pc = pc + disp + 4; + sh4r.in_delay_slot = 1; return TRUE; - case 8: /* PREF [Rn] */ - tmp = RN(ir); - if( (tmp & 0xFC000000) == 0xE0000000 ) { - /* Store queue operation */ - int queue = (tmp&0x20)>>2; - int32_t *src = &sh4r.store_queue[queue]; - uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24; - uint32_t target = tmp&0x03FFFFE0 | hi; - mem_copy_to_sh4( target, src, 32 ); - } - break; - case 9: /* OCBI [Rn] */ - case 10:/* OCBP [Rn] */ - case 11:/* OCBWB [Rn] */ - /* anything? */ - break; - case 12:/* MOVCA.L R0, [Rn] */ - tmp = RN(ir); - CHECKWALIGN32(tmp); - MEM_WRITE_LONG( tmp, R0 ); - break; - default: UNDEF(ir); - } - break; - case 4: /* MOV.B Rm, [R0 + Rn] */ - MEM_WRITE_BYTE( R0 + RN(ir), RM(ir) ); - break; - case 5: /* MOV.W Rm, [R0 + Rn] */ - CHECKWALIGN16( R0 + RN(ir) ); - MEM_WRITE_WORD( R0 + RN(ir), RM(ir) ); - break; - case 6: /* MOV.L Rm, [R0 + Rn] */ - CHECKWALIGN32( R0 + RN(ir) ); - MEM_WRITE_LONG( R0 + RN(ir), RM(ir) ); - break; - case 7: /* MUL.L Rm, Rn */ - sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | - (RM(ir) * RN(ir)); - break; - case 8: - switch( (ir&0x0FF0)>>4 ) { - case 0: /* CLRT */ - sh4r.t = 0; - break; - case 1: /* SETT */ - sh4r.t = 1; - break; - case 2: /* CLRMAC */ - sh4r.mac = 0; - break; - case 3: /* LDTLB */ - break; - case 4: /* CLRS */ - sh4r.s = 0; - break; - case 5: /* SETS */ - sh4r.s = 1; - break; - default: UNDEF(ir); - } - break; - case 9: - if( (ir&0x00F0) == 0x20 ) /* MOVT Rn */ - RN(ir) = sh4r.t; - else if( ir == 0x0019 ) /* DIV0U */ - sh4r.m = sh4r.q = sh4r.t = 0; - else if( ir == 0x0009 ) - /* NOP */; - else UNDEF(ir); - break; - case 10: - switch( (ir&0x00F0) >> 4 ) { - case 0: /* STS MACH, Rn */ - RN(ir) = sh4r.mac >> 32; - break; - case 1: /* STS MACL, Rn */ - RN(ir) = (uint32_t)sh4r.mac; - break; - case 2: /* STS PR, Rn */ - RN(ir) = sh4r.pr; - break; - case 3: /* STC SGR, Rn */ - CHECKPRIV(); - RN(ir) = sh4r.sgr; - break; - case 5:/* STS FPUL, Rn */ - RN(ir) = sh4r.fpul; - break; - case 6: /* STS FPSCR, Rn */ - RN(ir) = sh4r.fpscr; - break; - case 15:/* STC DBR, Rn */ - CHECKPRIV(); - RN(ir) = sh4r.dbr; - break; - default: UNDEF(ir); - } - break; - case 11: - switch( (ir&0x0FF0)>>4 ) { - case 0: /* RTS */ - CHECKSLOTILLEGAL(); - CHECKDEST( sh4r.pr ); + } + } + break; + case 0xF: + { /* BF/S disp */ + int32_t disp = SIGNEXT8(ir&0xFF)<<1; + CHECKSLOTILLEGAL(); + if( !sh4r.t ) { + CHECKDEST( sh4r.pc + disp + 4 ) sh4r.in_delay_slot = 1; sh4r.pc = sh4r.new_pc; - sh4r.new_pc = sh4r.pr; - TRACE_RETURN( pc, sh4r.new_pc ); + sh4r.new_pc = pc + disp + 4; return TRUE; - case 1: /* SLEEP */ - if( MMIO_READ( CPG, STBCR ) & 0x80 ) { - sh4r.sh4_state = SH4_STATE_STANDBY; - } else { - sh4r.sh4_state = SH4_STATE_SLEEP; - } - return FALSE; /* Halt CPU */ - case 2: /* RTE */ - CHECKPRIV(); - CHECKDEST( sh4r.spc ); - CHECKSLOTILLEGAL(); - sh4r.in_delay_slot = 1; - sh4r.pc = sh4r.new_pc; - sh4r.new_pc = sh4r.spc; - sh4_load_sr( sh4r.ssr ); - return TRUE; - default:UNDEF(ir); - } - break; - case 12:/* MOV.B [R0+R%d], R%d */ - RN(ir) = MEM_READ_BYTE( R0 + RM(ir) ); - break; - case 13:/* MOV.W [R0+R%d], R%d */ - CHECKRALIGN16( R0 + RM(ir) ); - RN(ir) = MEM_READ_WORD( R0 + RM(ir) ); - break; - case 14:/* MOV.L [R0+R%d], R%d */ - CHECKRALIGN32( R0 + RM(ir) ); - RN(ir) = MEM_READ_LONG( R0 + RM(ir) ); - break; - case 15:/* MAC.L [Rm++], [Rn++] */ - CHECKRALIGN32( RM(ir) ); - CHECKRALIGN32( RN(ir) ); - tmpl = ( SIGNEXT32(MEM_READ_LONG(RM(ir))) * - SIGNEXT32(MEM_READ_LONG(RN(ir))) ); - if( sh4r.s ) { - /* 48-bit Saturation. Yuch */ - tmpl += SIGNEXT48(sh4r.mac); - if( tmpl < 0xFFFF800000000000LL ) - tmpl = 0xFFFF800000000000LL; - else if( tmpl > 0x00007FFFFFFFFFFFLL ) - tmpl = 0x00007FFFFFFFFFFFLL; - sh4r.mac = (sh4r.mac&0xFFFF000000000000LL) | - (tmpl&0x0000FFFFFFFFFFFFLL); - } else sh4r.mac = tmpl; - - RM(ir) += 4; - RN(ir) += 4; - - break; - default: UNDEF(ir); - } - break; - case 1: /* 0001nnnnmmmmdddd */ - /* MOV.L Rm, [Rn + disp4*4] */ - tmp = RN(ir) + (DISP4(ir)<<2); - CHECKWALIGN32( tmp ); - MEM_WRITE_LONG( tmp, RM(ir) ); - break; - case 2: /* 0010nnnnmmmmxxxx */ - switch( ir&0x000F ) { - case 0: /* MOV.B Rm, [Rn] */ - MEM_WRITE_BYTE( RN(ir), RM(ir) ); - break; - case 1: /* MOV.W Rm, [Rn] */ - CHECKWALIGN16( RN(ir) ); - MEM_WRITE_WORD( RN(ir), RM(ir) ); - break; - case 2: /* MOV.L Rm, [Rn] */ - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), RM(ir) ); - break; - case 3: UNDEF(ir); - break; - case 4: /* MOV.B Rm, [--Rn] */ - RN(ir) --; - MEM_WRITE_BYTE( RN(ir), RM(ir) ); - break; - case 5: /* MOV.W Rm, [--Rn] */ - RN(ir) -= 2; - CHECKWALIGN16( RN(ir) ); - MEM_WRITE_WORD( RN(ir), RM(ir) ); - break; - case 6: /* MOV.L Rm, [--Rn] */ - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), RM(ir) ); - break; - case 7: /* DIV0S Rm, Rn */ - sh4r.q = RN(ir)>>31; - sh4r.m = RM(ir)>>31; - sh4r.t = sh4r.q ^ sh4r.m; - break; - case 8: /* TST Rm, Rn */ - sh4r.t = (RN(ir)&RM(ir) ? 0 : 1); - break; - case 9: /* AND Rm, Rn */ - RN(ir) &= RM(ir); - break; - case 10:/* XOR Rm, Rn */ - RN(ir) ^= RM(ir); - break; - case 11:/* OR Rm, Rn */ - RN(ir) |= RM(ir); - break; - case 12:/* CMP/STR Rm, Rn */ - /* set T = 1 if any byte in RM & RN is the same */ - tmp = RM(ir) ^ RN(ir); - sh4r.t = ((tmp&0x000000FF)==0 || (tmp&0x0000FF00)==0 || - (tmp&0x00FF0000)==0 || (tmp&0xFF000000)==0)?1:0; - break; - case 13:/* XTRCT Rm, Rn */ - RN(ir) = (RN(ir)>>16) | (RM(ir)<<16); - break; - case 14:/* MULU.W Rm, Rn */ - sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | - (uint32_t)((RM(ir)&0xFFFF) * (RN(ir)&0xFFFF)); - break; - case 15:/* MULS.W Rm, Rn */ - sh4r.mac = (sh4r.mac&0xFFFFFFFF00000000LL) | - (uint32_t)(SIGNEXT32(RM(ir)&0xFFFF) * SIGNEXT32(RN(ir)&0xFFFF)); - break; - } - break; - case 3: /* 0011nnnnmmmmxxxx */ - switch( ir&0x000F ) { - case 0: /* CMP/EQ Rm, Rn */ - sh4r.t = ( RM(ir) == RN(ir) ? 1 : 0 ); - break; - case 2: /* CMP/HS Rm, Rn */ - sh4r.t = ( RN(ir) >= RM(ir) ? 1 : 0 ); - break; - case 3: /* CMP/GE Rm, Rn */ - sh4r.t = ( ((int32_t)RN(ir)) >= ((int32_t)RM(ir)) ? 1 : 0 ); - break; - case 4: { /* DIV1 Rm, Rn */ - /* This is just from the sh4p manual with some - * simplifications (someone want to check it's correct? :) - * Why they couldn't just provide a real DIV instruction... - * Please oh please let the translator batch these things - * up into a single DIV... */ - uint32_t tmp0, tmp1, tmp2, dir; + } + } + break; + default: + UNDEF(); + break; + } + break; + case 0x9: + { /* MOV.W @(disp, PC), Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1; + CHECKSLOTILLEGAL(); + tmp = pc + 4 + disp; + sh4r.r[Rn] = MEM_READ_WORD( tmp ); + } + break; + case 0xA: + { /* BRA disp */ + int32_t disp = SIGNEXT12(ir&0xFFF)<<1; + CHECKSLOTILLEGAL(); + CHECKDEST( sh4r.pc + disp + 4 ); + sh4r.in_delay_slot = 1; + sh4r.pc = sh4r.new_pc; + sh4r.new_pc = pc + 4 + disp; + return TRUE; + } + break; + case 0xB: + { /* BSR disp */ + int32_t disp = SIGNEXT12(ir&0xFFF)<<1; + CHECKDEST( sh4r.pc + disp + 4 ); + CHECKSLOTILLEGAL(); + sh4r.in_delay_slot = 1; + sh4r.pr = pc + 4; + sh4r.pc = sh4r.new_pc; + sh4r.new_pc = pc + 4 + disp; + TRACE_CALL( pc, sh4r.new_pc ); + return TRUE; + } + break; + case 0xC: + switch( (ir&0xF00) >> 8 ) { + case 0x0: + { /* MOV.B R0, @(disp, GBR) */ + uint32_t disp = (ir&0xFF); + MEM_WRITE_BYTE( sh4r.gbr + disp, R0 ); + } + break; + case 0x1: + { /* MOV.W R0, @(disp, GBR) */ + uint32_t disp = (ir&0xFF)<<1; + tmp = sh4r.gbr + disp; + CHECKWALIGN16( tmp ); + MEM_WRITE_WORD( tmp, R0 ); + } + break; + case 0x2: + { /* MOV.L R0, @(disp, GBR) */ + uint32_t disp = (ir&0xFF)<<2; + tmp = sh4r.gbr + disp; + CHECKWALIGN32( tmp ); + MEM_WRITE_LONG( tmp, R0 ); + } + break; + case 0x3: + { /* TRAPA #imm */ + uint32_t imm = (ir&0xFF); + CHECKSLOTILLEGAL(); + MMIO_WRITE( MMU, TRA, imm<<2 ); + sh4r.pc += 2; + sh4_raise_exception( EXC_TRAP ); + } + break; + case 0x4: + { /* MOV.B @(disp, GBR), R0 */ + uint32_t disp = (ir&0xFF); + R0 = MEM_READ_BYTE( sh4r.gbr + disp ); + } + break; + case 0x5: + { /* MOV.W @(disp, GBR), R0 */ + uint32_t disp = (ir&0xFF)<<1; + tmp = sh4r.gbr + disp; + CHECKRALIGN16( tmp ); + R0 = MEM_READ_WORD( tmp ); + } + break; + case 0x6: + { /* MOV.L @(disp, GBR), R0 */ + uint32_t disp = (ir&0xFF)<<2; + tmp = sh4r.gbr + disp; + CHECKRALIGN32( tmp ); + R0 = MEM_READ_LONG( tmp ); + } + break; + case 0x7: + { /* MOVA @(disp, PC), R0 */ + uint32_t disp = (ir&0xFF)<<2; + CHECKSLOTILLEGAL(); + R0 = (pc&0xFFFFFFFC) + disp + 4; + } + break; + case 0x8: + { /* TST #imm, R0 */ + uint32_t imm = (ir&0xFF); + sh4r.t = (R0 & imm ? 0 : 1); + } + break; + case 0x9: + { /* AND #imm, R0 */ + uint32_t imm = (ir&0xFF); + R0 &= imm; + } + break; + case 0xA: + { /* XOR #imm, R0 */ + uint32_t imm = (ir&0xFF); + R0 ^= imm; + } + break; + case 0xB: + { /* OR #imm, R0 */ + uint32_t imm = (ir&0xFF); + R0 |= imm; + } + break; + case 0xC: + { /* TST.B #imm, @(R0, GBR) */ + uint32_t imm = (ir&0xFF); + sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & imm ? 0 : 1 ); + } + break; + case 0xD: + { /* AND.B #imm, @(R0, GBR) */ + uint32_t imm = (ir&0xFF); + MEM_WRITE_BYTE( R0 + sh4r.gbr, imm & MEM_READ_BYTE(R0 + sh4r.gbr) ); + } + break; + case 0xE: + { /* XOR.B #imm, @(R0, GBR) */ + uint32_t imm = (ir&0xFF); + MEM_WRITE_BYTE( R0 + sh4r.gbr, imm ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); + } + break; + case 0xF: + { /* OR.B #imm, @(R0, GBR) */ + uint32_t imm = (ir&0xFF); + MEM_WRITE_BYTE( R0 + sh4r.gbr, imm | MEM_READ_BYTE(R0 + sh4r.gbr) ); + } + break; + } + break; + case 0xD: + { /* MOV.L @(disp, PC), Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2; + CHECKSLOTILLEGAL(); + tmp = (pc&0xFFFFFFFC) + disp + 4; + sh4r.r[Rn] = MEM_READ_LONG( tmp ); + } + break; + case 0xE: + { /* MOV #imm, Rn */ + uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF); + sh4r.r[Rn] = imm; + } + break; + case 0xF: + switch( ir&0xF ) { + case 0x0: + { /* FADD FRm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) += DR(FRm); + } else { + FR(FRn) += FR(FRm); + } + } + break; + case 0x1: + { /* FSUB FRm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) -= DR(FRm); + } else { + FR(FRn) -= FR(FRm); + } + } + break; + case 0x2: + { /* FMUL FRm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) *= DR(FRm); + } else { + FR(FRn) *= FR(FRm); + } + } + break; + case 0x3: + { /* FDIV FRm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) /= DR(FRm); + } else { + FR(FRn) /= FR(FRm); + } + } + break; + case 0x4: + { /* FCMP/EQ FRm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + sh4r.t = ( DR(FRn) == DR(FRm) ? 1 : 0 ); + } else { + sh4r.t = ( FR(FRn) == FR(FRm) ? 1 : 0 ); + } + } + break; + case 0x5: + { /* FCMP/GT FRm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + sh4r.t = ( DR(FRn) > DR(FRm) ? 1 : 0 ); + } else { + sh4r.t = ( FR(FRn) > FR(FRm) ? 1 : 0 ); + } + } + break; + case 0x6: + { /* FMOV @(R0, Rm), FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + MEM_FP_READ( sh4r.r[Rm] + R0, FRn ); + } + break; + case 0x7: + { /* FMOV FRm, @(R0, Rn) */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + MEM_FP_WRITE( sh4r.r[Rn] + R0, FRm ); + } + break; + case 0x8: + { /* FMOV @Rm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + MEM_FP_READ( sh4r.r[Rm], FRn ); + } + break; + case 0x9: + { /* FMOV @Rm+, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); + MEM_FP_READ( sh4r.r[Rm], FRn ); sh4r.r[Rm] += FP_WIDTH; + } + break; + case 0xA: + { /* FMOV FRm, @Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + MEM_FP_WRITE( sh4r.r[Rn], FRm ); + } + break; + case 0xB: + { /* FMOV FRm, @-Rn */ + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + sh4r.r[Rn] -= FP_WIDTH; MEM_FP_WRITE( sh4r.r[Rn], FRm ); + } + break; + case 0xC: + { /* FMOV FRm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + if( IS_FPU_DOUBLESIZE() ) + DR(FRn) = DR(FRm); + else + FR(FRn) = FR(FRm); + } + break; + case 0xD: + switch( (ir&0xF0) >> 4 ) { + case 0x0: + { /* FSTS FPUL, FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); FR(FRn) = FPULf; + } + break; + case 0x1: + { /* FLDS FRm, FPUL */ + uint32_t FRm = ((ir>>8)&0xF); + CHECKFPUEN(); FPULf = FR(FRm); + } + break; + case 0x2: + { /* FLOAT FPUL, FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) + DR(FRn) = (float)FPULi; + else + FR(FRn) = (float)FPULi; + } + break; + case 0x3: + { /* FTRC FRm, FPUL */ + uint32_t FRm = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + dtmp = DR(FRm); + if( dtmp >= MAX_INTF ) + FPULi = MAX_INT; + else if( dtmp <= MIN_INTF ) + FPULi = MIN_INT; + else + FPULi = (int32_t)dtmp; + } else { + ftmp = FR(FRm); + if( ftmp >= MAX_INTF ) + FPULi = MAX_INT; + else if( ftmp <= MIN_INTF ) + FPULi = MIN_INT; + else + FPULi = (int32_t)ftmp; + } + } + break; + case 0x4: + { /* FNEG FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) = -DR(FRn); + } else { + FR(FRn) = -FR(FRn); + } + } + break; + case 0x5: + { /* FABS FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) = fabs(DR(FRn)); + } else { + FR(FRn) = fabsf(FR(FRn)); + } + } + break; + case 0x6: + { /* FSQRT FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) = sqrt(DR(FRn)); + } else { + FR(FRn) = sqrtf(FR(FRn)); + } + } + break; + case 0x7: + { /* FSRRA FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); + if( !IS_FPU_DOUBLEPREC() ) { + FR(FRn) = 1.0/sqrtf(FR(FRn)); + } + } + break; + case 0x8: + { /* FLDI0 FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) = 0.0; + } else { + FR(FRn) = 0.0; + } + } + break; + case 0x9: + { /* FLDI1 FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) = 1.0; + } else { + FR(FRn) = 1.0; + } + } + break; + case 0xA: + { /* FCNVSD FPUL, FRn */ + uint32_t FRn = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) { + DR(FRn) = (double)FPULf; + } + } + break; + case 0xB: + { /* FCNVDS FRm, FPUL */ + uint32_t FRm = ((ir>>8)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() && !IS_FPU_DOUBLESIZE() ) { + FPULf = (float)DR(FRm); + } + } + break; + case 0xE: + { /* FIPR FVm, FVn */ + uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3); + CHECKFPUEN(); + if( !IS_FPU_DOUBLEPREC() ) { + int tmp2 = FVn<<2; + tmp = FVm<<2; + FR(tmp2+3) = FR(tmp)*FR(tmp2) + + FR(tmp+1)*FR(tmp2+1) + + FR(tmp+2)*FR(tmp2+2) + + FR(tmp+3)*FR(tmp2+3); + } + } + break; + case 0xF: + switch( (ir&0x100) >> 8 ) { + case 0x0: + { /* FSCA FPUL, FRn */ + uint32_t FRn = ((ir>>9)&0x7)<<1; + CHECKFPUEN(); + if( !IS_FPU_DOUBLEPREC() ) { + float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI; + FR(FRn) = sinf(angle); + FR((FRn)+1) = cosf(angle); + } + } + break; + case 0x1: + switch( (ir&0x200) >> 9 ) { + case 0x0: + { /* FTRV XMTRX, FVn */ + uint32_t FVn = ((ir>>10)&0x3); + CHECKFPUEN(); + if( !IS_FPU_DOUBLEPREC() ) { + tmp = FVn<<2; + float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) }; + FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] + + XF(8)*fv[2] + XF(12)*fv[3]; + FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] + + XF(9)*fv[2] + XF(13)*fv[3]; + FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] + + XF(10)*fv[2] + XF(14)*fv[3]; + FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] + + XF(11)*fv[2] + XF(15)*fv[3]; + } + } + break; + case 0x1: + switch( (ir&0xC00) >> 10 ) { + case 0x0: + { /* FSCHG */ + CHECKFPUEN(); sh4r.fpscr ^= FPSCR_SZ; + } + break; + case 0x2: + { /* FRCHG */ + CHECKFPUEN(); sh4r.fpscr ^= FPSCR_FR; + } + break; + case 0x3: + { /* UNDEF */ + UNDEF(ir); + } + break; + default: + UNDEF(); + break; + } + break; + } + break; + } + break; + default: + UNDEF(); + break; + } + break; + case 0xE: + { /* FMAC FR0, FRm, FRn */ + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); + CHECKFPUEN(); + if( IS_FPU_DOUBLEPREC() ) { + DR(FRn) += DR(FRm)*DR(0); + } else { + FR(FRn) += FR(FRm)*FR(0); + } + } + break; + default: + UNDEF(); + break; + } + break; + } - dir = sh4r.q ^ sh4r.m; - sh4r.q = (RN(ir) >> 31); - tmp2 = RM(ir); - RN(ir) = (RN(ir) << 1) | sh4r.t; - tmp0 = RN(ir); - if( dir ) { - RN(ir) += tmp2; - tmp1 = (RN(ir)tmp0 ? 1 : 0 ); - } - sh4r.q ^= sh4r.m ^ tmp1; - sh4r.t = ( sh4r.q == sh4r.m ? 1 : 0 ); - break; } - case 5: /* DMULU.L Rm, Rn */ - sh4r.mac = ((uint64_t)RM(ir)) * ((uint64_t)RN(ir)); - break; - case 6: /* CMP/HI Rm, Rn */ - sh4r.t = ( RN(ir) > RM(ir) ? 1 : 0 ); - break; - case 7: /* CMP/GT Rm, Rn */ - sh4r.t = ( ((int32_t)RN(ir)) > ((int32_t)RM(ir)) ? 1 : 0 ); - break; - case 8: /* SUB Rm, Rn */ - RN(ir) -= RM(ir); - break; - case 10:/* SUBC Rm, Rn */ - tmp = RN(ir); - RN(ir) = RN(ir) - RM(ir) - sh4r.t; - sh4r.t = (RN(ir) > tmp || (RN(ir) == tmp && sh4r.t == 1)); - break; - case 11:/* SUBV Rm, Rn */ - UNIMP(ir); - break; - case 12:/* ADD Rm, Rn */ - RN(ir) += RM(ir); - break; - case 13:/* DMULS.L Rm, Rn */ - sh4r.mac = SIGNEXT32(RM(ir)) * SIGNEXT32(RN(ir)); - break; - case 14:/* ADDC Rm, Rn */ - tmp = RN(ir); - RN(ir) += RM(ir) + sh4r.t; - sh4r.t = ( RN(ir) < tmp || (RN(ir) == tmp && sh4r.t != 0) ? 1 : 0 ); - break; - case 15:/* ADDV Rm, Rn */ - tmp = RN(ir) + RM(ir); - sh4r.t = ( (RN(ir)>>31) == (RM(ir)>>31) && ((RN(ir)>>31) != (tmp>>31)) ); - RN(ir) = tmp; - break; - default: UNDEF(ir); - } - break; - case 4: /* 0100nnnnxxxxxxxx */ - switch( ir&0x00FF ) { - case 0x00: /* SHLL Rn */ - sh4r.t = RN(ir) >> 31; - RN(ir) <<= 1; - break; - case 0x01: /* SHLR Rn */ - sh4r.t = RN(ir) & 0x00000001; - RN(ir) >>= 1; - break; - case 0x02: /* STS.L MACH, [--Rn] */ - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), (sh4r.mac>>32) ); - break; - case 0x03: /* STC.L SR, [--Rn] */ - CHECKPRIV(); - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4_read_sr() ); - break; - case 0x04: /* ROTL Rn */ - sh4r.t = RN(ir) >> 31; - RN(ir) <<= 1; - RN(ir) |= sh4r.t; - break; - case 0x05: /* ROTR Rn */ - sh4r.t = RN(ir) & 0x00000001; - RN(ir) >>= 1; - RN(ir) |= (sh4r.t << 31); - break; - case 0x06: /* LDS.L [Rn++], MACH */ - CHECKRALIGN32( RN(ir) ); - sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) | - (((uint64_t)MEM_READ_LONG(RN(ir)))<<32); - RN(ir) += 4; - break; - case 0x07: /* LDC.L [Rn++], SR */ - CHECKSLOTILLEGAL(); - CHECKPRIV(); - CHECKWALIGN32( RN(ir) ); - sh4_load_sr( MEM_READ_LONG(RN(ir)) ); - RN(ir) +=4; - break; - case 0x08: /* SHLL2 Rn */ - RN(ir) <<= 2; - break; - case 0x09: /* SHLR2 Rn */ - RN(ir) >>= 2; - break; - case 0x0A: /* LDS Rn, MACH */ - sh4r.mac = (sh4r.mac & 0x00000000FFFFFFFF) | - (((uint64_t)RN(ir))<<32); - break; - case 0x0B: /* JSR [Rn] */ - CHECKDEST( RN(ir) ); - CHECKSLOTILLEGAL(); - sh4r.in_delay_slot = 1; - sh4r.pc = sh4r.new_pc; - sh4r.new_pc = RN(ir); - sh4r.pr = pc + 4; - TRACE_CALL( pc, sh4r.new_pc ); - return TRUE; - case 0x0E: /* LDC Rn, SR */ - CHECKSLOTILLEGAL(); - CHECKPRIV(); - sh4_load_sr( RN(ir) ); - break; - case 0x10: /* DT Rn */ - RN(ir) --; - sh4r.t = ( RN(ir) == 0 ? 1 : 0 ); - break; - case 0x11: /* CMP/PZ Rn */ - sh4r.t = ( ((int32_t)RN(ir)) >= 0 ? 1 : 0 ); - break; - case 0x12: /* STS.L MACL, [--Rn] */ - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), (uint32_t)sh4r.mac ); - break; - case 0x13: /* STC.L GBR, [--Rn] */ - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.gbr ); - break; - case 0x15: /* CMP/PL Rn */ - sh4r.t = ( ((int32_t)RN(ir)) > 0 ? 1 : 0 ); - break; - case 0x16: /* LDS.L [Rn++], MACL */ - CHECKRALIGN32( RN(ir) ); - sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | - (uint64_t)((uint32_t)MEM_READ_LONG(RN(ir))); - RN(ir) += 4; - break; - case 0x17: /* LDC.L [Rn++], GBR */ - CHECKRALIGN32( RN(ir) ); - sh4r.gbr = MEM_READ_LONG(RN(ir)); - RN(ir) +=4; - break; - case 0x18: /* SHLL8 Rn */ - RN(ir) <<= 8; - break; - case 0x19: /* SHLR8 Rn */ - RN(ir) >>= 8; - break; - case 0x1A: /* LDS Rn, MACL */ - sh4r.mac = (sh4r.mac & 0xFFFFFFFF00000000LL) | - (uint64_t)((uint32_t)(RN(ir))); - break; - case 0x1B: /* TAS.B [Rn] */ - tmp = MEM_READ_BYTE( RN(ir) ); - sh4r.t = ( tmp == 0 ? 1 : 0 ); - MEM_WRITE_BYTE( RN(ir), tmp | 0x80 ); - break; - case 0x1E: /* LDC Rn, GBR */ - sh4r.gbr = RN(ir); - break; - case 0x20: /* SHAL Rn */ - sh4r.t = RN(ir) >> 31; - RN(ir) <<= 1; - break; - case 0x21: /* SHAR Rn */ - sh4r.t = RN(ir) & 0x00000001; - RN(ir) = ((int32_t)RN(ir)) >> 1; - break; - case 0x22: /* STS.L PR, [--Rn] */ - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.pr ); - break; - case 0x23: /* STC.L VBR, [--Rn] */ - CHECKPRIV(); - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.vbr ); - break; - case 0x24: /* ROTCL Rn */ - tmp = RN(ir) >> 31; - RN(ir) <<= 1; - RN(ir) |= sh4r.t; - sh4r.t = tmp; - break; - case 0x25: /* ROTCR Rn */ - tmp = RN(ir) & 0x00000001; - RN(ir) >>= 1; - RN(ir) |= (sh4r.t << 31 ); - sh4r.t = tmp; - break; - case 0x26: /* LDS.L [Rn++], PR */ - CHECKRALIGN32( RN(ir) ); - sh4r.pr = MEM_READ_LONG( RN(ir) ); - RN(ir) += 4; - break; - case 0x27: /* LDC.L [Rn++], VBR */ - CHECKPRIV(); - CHECKRALIGN32( RN(ir) ); - sh4r.vbr = MEM_READ_LONG(RN(ir)); - RN(ir) +=4; - break; - case 0x28: /* SHLL16 Rn */ - RN(ir) <<= 16; - break; - case 0x29: /* SHLR16 Rn */ - RN(ir) >>= 16; - break; - case 0x2A: /* LDS Rn, PR */ - sh4r.pr = RN(ir); - break; - case 0x2B: /* JMP [Rn] */ - CHECKDEST( RN(ir) ); - CHECKSLOTILLEGAL(); - sh4r.in_delay_slot = 1; - sh4r.pc = sh4r.new_pc; - sh4r.new_pc = RN(ir); - return TRUE; - case 0x2E: /* LDC Rn, VBR */ - CHECKPRIV(); - sh4r.vbr = RN(ir); - break; - case 0x32: /* STC.L SGR, [--Rn] */ - CHECKPRIV(); - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.sgr ); - break; - case 0x33: /* STC.L SSR, [--Rn] */ - CHECKPRIV(); - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.ssr ); - break; - case 0x37: /* LDC.L [Rn++], SSR */ - CHECKPRIV(); - CHECKRALIGN32( RN(ir) ); - sh4r.ssr = MEM_READ_LONG(RN(ir)); - RN(ir) +=4; - break; - case 0x3E: /* LDC Rn, SSR */ - CHECKPRIV(); - sh4r.ssr = RN(ir); - break; - case 0x43: /* STC.L SPC, [--Rn] */ - CHECKPRIV(); - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.spc ); - break; - case 0x47: /* LDC.L [Rn++], SPC */ - CHECKPRIV(); - CHECKRALIGN32( RN(ir) ); - sh4r.spc = MEM_READ_LONG(RN(ir)); - RN(ir) +=4; - break; - case 0x4E: /* LDC Rn, SPC */ - CHECKPRIV(); - sh4r.spc = RN(ir); - break; - case 0x52: /* STS.L FPUL, [--Rn] */ - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.fpul ); - break; - case 0x56: /* LDS.L [Rn++], FPUL */ - CHECKRALIGN32( RN(ir) ); - sh4r.fpul = MEM_READ_LONG(RN(ir)); - RN(ir) +=4; - break; - case 0x5A: /* LDS Rn, FPUL */ - sh4r.fpul = RN(ir); - break; - case 0x62: /* STS.L FPSCR, [--Rn] */ - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.fpscr ); - break; - case 0x66: /* LDS.L [Rn++], FPSCR */ - CHECKRALIGN32( RN(ir) ); - sh4r.fpscr = MEM_READ_LONG(RN(ir)); - RN(ir) +=4; - break; - case 0x6A: /* LDS Rn, FPSCR */ - sh4r.fpscr = RN(ir); - break; - case 0xF2: /* STC.L DBR, [--Rn] */ - CHECKPRIV(); - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), sh4r.dbr ); - break; - case 0xF6: /* LDC.L [Rn++], DBR */ - CHECKPRIV(); - CHECKRALIGN32( RN(ir) ); - sh4r.dbr = MEM_READ_LONG(RN(ir)); - RN(ir) +=4; - break; - case 0xFA: /* LDC Rn, DBR */ - CHECKPRIV(); - sh4r.dbr = RN(ir); - break; - case 0x83: case 0x93: case 0xA3: case 0xB3: case 0xC3: - case 0xD3: case 0xE3: case 0xF3: /* STC.L Rn_BANK, [--Rn] */ - CHECKPRIV(); - RN(ir) -= 4; - CHECKWALIGN32( RN(ir) ); - MEM_WRITE_LONG( RN(ir), RN_BANK(ir) ); - break; - case 0x87: case 0x97: case 0xA7: case 0xB7: case 0xC7: - case 0xD7: case 0xE7: case 0xF7: /* LDC.L [Rn++], Rn_BANK */ - CHECKPRIV(); - CHECKRALIGN32( RN(ir) ); - RN_BANK(ir) = MEM_READ_LONG( RN(ir) ); - RN(ir) += 4; - break; - case 0x8E: case 0x9E: case 0xAE: case 0xBE: case 0xCE: - case 0xDE: case 0xEE: case 0xFE: /* LDC Rm, Rn_BANK */ - CHECKPRIV(); - RN_BANK(ir) = RM(ir); - break; - default: - if( (ir&0x000F) == 0x0F ) { - /* MAC.W [Rm++], [Rn++] */ - CHECKRALIGN16( RN(ir) ); - CHECKRALIGN16( RM(ir) ); - tmp = SIGNEXT16(MEM_READ_WORD(RM(ir))) * - SIGNEXT16(MEM_READ_WORD(RN(ir))); - if( sh4r.s ) { - /* FIXME */ - UNIMP(ir); - } else sh4r.mac += SIGNEXT32(tmp); - RM(ir) += 2; - RN(ir) += 2; - } else if( (ir&0x000F) == 0x0C ) { - /* SHAD Rm, Rn */ - tmp = RM(ir); - if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f); - else if( (tmp & 0x1F) == 0 ) - RN(ir) = ((int32_t)RN(ir)) >> 31; - else - RN(ir) = ((int32_t)RN(ir)) >> (((~RM(ir)) & 0x1F)+1); - } else if( (ir&0x000F) == 0x0D ) { - /* SHLD Rm, Rn */ - tmp = RM(ir); - if( (tmp & 0x80000000) == 0 ) RN(ir) <<= (tmp&0x1f); - else if( (tmp & 0x1F) == 0 ) RN(ir) = 0; - else RN(ir) >>= (((~tmp) & 0x1F)+1); - } else UNDEF(ir); - } - break; - case 5: /* 0101nnnnmmmmdddd */ - /* MOV.L [Rm + disp4*4], Rn */ - tmp = RM(ir) + (DISP4(ir)<<2); - CHECKRALIGN32( tmp ); - RN(ir) = MEM_READ_LONG( tmp ); - break; - case 6: /* 0110xxxxxxxxxxxx */ - switch( ir&0x000f ) { - case 0: /* MOV.B [Rm], Rn */ - RN(ir) = MEM_READ_BYTE( RM(ir) ); - break; - case 1: /* MOV.W [Rm], Rn */ - CHECKRALIGN16( RM(ir) ); - RN(ir) = MEM_READ_WORD( RM(ir) ); - break; - case 2: /* MOV.L [Rm], Rn */ - CHECKRALIGN32( RM(ir) ); - RN(ir) = MEM_READ_LONG( RM(ir) ); - break; - case 3: /* MOV Rm, Rn */ - RN(ir) = RM(ir); - break; - case 4: /* MOV.B [Rm++], Rn */ - RN(ir) = MEM_READ_BYTE( RM(ir) ); - RM(ir) ++; - break; - case 5: /* MOV.W [Rm++], Rn */ - CHECKRALIGN16( RM(ir) ); - RN(ir) = MEM_READ_WORD( RM(ir) ); - RM(ir) += 2; - break; - case 6: /* MOV.L [Rm++], Rn */ - CHECKRALIGN32( RM(ir) ); - RN(ir) = MEM_READ_LONG( RM(ir) ); - RM(ir) += 4; - break; - case 7: /* NOT Rm, Rn */ - RN(ir) = ~RM(ir); - break; - case 8: /* SWAP.B Rm, Rn */ - RN(ir) = (RM(ir)&0xFFFF0000) | ((RM(ir)&0x0000FF00)>>8) | - ((RM(ir)&0x000000FF)<<8); - break; - case 9: /* SWAP.W Rm, Rn */ - RN(ir) = (RM(ir)>>16) | (RM(ir)<<16); - break; - case 10:/* NEGC Rm, Rn */ - tmp = 0 - RM(ir); - RN(ir) = tmp - sh4r.t; - sh4r.t = ( 0> 8 ) { - case 0: /* MOV.B R0, [Rm + disp4] */ - MEM_WRITE_BYTE( RM(ir) + DISP4(ir), R0 ); - break; - case 1: /* MOV.W R0, [Rm + disp4*2] */ - tmp = RM(ir) + (DISP4(ir)<<1); - CHECKWALIGN16( tmp ); - MEM_WRITE_WORD( tmp, R0 ); - break; - case 4: /* MOV.B [Rm + disp4], R0 */ - R0 = MEM_READ_BYTE( RM(ir) + DISP4(ir) ); - break; - case 5: /* MOV.W [Rm + disp4*2], R0 */ - tmp = RM(ir) + (DISP4(ir)<<1); - CHECKRALIGN16( tmp ); - R0 = MEM_READ_WORD( tmp ); - break; - case 8: /* CMP/EQ imm, R0 */ - sh4r.t = ( R0 == IMM8(ir) ? 1 : 0 ); - break; - case 9: /* BT disp8 */ - CHECKSLOTILLEGAL(); - if( sh4r.t ) { - CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) - sh4r.pc += (PCDISP8(ir)<<1) + 4; - sh4r.new_pc = sh4r.pc + 2; - return TRUE; - } - break; - case 11:/* BF disp8 */ - CHECKSLOTILLEGAL(); - if( !sh4r.t ) { - CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) - sh4r.pc += (PCDISP8(ir)<<1) + 4; - sh4r.new_pc = sh4r.pc + 2; - return TRUE; - } - break; - case 13:/* BT/S disp8 */ - CHECKSLOTILLEGAL(); - if( sh4r.t ) { - CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) - sh4r.in_delay_slot = 1; - sh4r.pc = sh4r.new_pc; - sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4; - sh4r.in_delay_slot = 1; - return TRUE; - } - break; - case 15:/* BF/S disp8 */ - CHECKSLOTILLEGAL(); - if( !sh4r.t ) { - CHECKDEST( sh4r.pc + (PCDISP8(ir)<<1) + 4 ) - sh4r.in_delay_slot = 1; - sh4r.pc = sh4r.new_pc; - sh4r.new_pc = pc + (PCDISP8(ir)<<1) + 4; - return TRUE; - } - break; - default: UNDEF(ir); - } - break; - case 9: /* 1001xxxxxxxxxxxx */ - /* MOV.W [disp8*2 + pc + 4], Rn */ - CHECKSLOTILLEGAL(); - tmp = pc + 4 + (DISP8(ir)<<1); - RN(ir) = MEM_READ_WORD( tmp ); - break; - case 10:/* 1010dddddddddddd */ - /* BRA disp12 */ - CHECKSLOTILLEGAL(); - CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 ); - sh4r.in_delay_slot = 1; - sh4r.pc = sh4r.new_pc; - sh4r.new_pc = pc + 4 + (DISP12(ir)<<1); - return TRUE; - case 11:/* 1011dddddddddddd */ - /* BSR disp12 */ - CHECKDEST( sh4r.pc + (DISP12(ir)<<1) + 4 ); - CHECKSLOTILLEGAL(); - sh4r.in_delay_slot = 1; - sh4r.pr = pc + 4; - sh4r.pc = sh4r.new_pc; - sh4r.new_pc = pc + 4 + (DISP12(ir)<<1); - TRACE_CALL( pc, sh4r.new_pc ); - return TRUE; - case 12:/* 1100xxxxdddddddd */ - switch( (ir&0x0F00)>>8 ) { - case 0: /* MOV.B R0, [GBR + disp8] */ - MEM_WRITE_BYTE( sh4r.gbr + DISP8(ir), R0 ); - break; - case 1: /* MOV.W R0, [GBR + disp8*2] */ - tmp = sh4r.gbr + (DISP8(ir)<<1); - CHECKWALIGN16( tmp ); - MEM_WRITE_WORD( tmp, R0 ); - break; - case 2: /*MOV.L R0, [GBR + disp8*4] */ - tmp = sh4r.gbr + (DISP8(ir)<<2); - CHECKWALIGN32( tmp ); - MEM_WRITE_LONG( tmp, R0 ); - break; - case 3: /* TRAPA imm8 */ - CHECKSLOTILLEGAL(); - MMIO_WRITE( MMU, TRA, UIMM8(ir)<<2 ); - sh4r.pc += 2; - sh4_raise_exception( EXC_TRAP ); - break; - case 4: /* MOV.B [GBR + disp8], R0 */ - R0 = MEM_READ_BYTE( sh4r.gbr + DISP8(ir) ); - break; - case 5: /* MOV.W [GBR + disp8*2], R0 */ - tmp = sh4r.gbr + (DISP8(ir)<<1); - CHECKRALIGN16( tmp ); - R0 = MEM_READ_WORD( tmp ); - break; - case 6: /* MOV.L [GBR + disp8*4], R0 */ - tmp = sh4r.gbr + (DISP8(ir)<<2); - CHECKRALIGN32( tmp ); - R0 = MEM_READ_LONG( tmp ); - break; - case 7: /* MOVA disp8 + pc&~3 + 4, R0 */ - CHECKSLOTILLEGAL(); - R0 = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4; - break; - case 8: /* TST imm8, R0 */ - sh4r.t = (R0 & UIMM8(ir) ? 0 : 1); - break; - case 9: /* AND imm8, R0 */ - R0 &= UIMM8(ir); - break; - case 10:/* XOR imm8, R0 */ - R0 ^= UIMM8(ir); - break; - case 11:/* OR imm8, R0 */ - R0 |= UIMM8(ir); - break; - case 12:/* TST.B imm8, [R0+GBR] */ - sh4r.t = ( MEM_READ_BYTE(R0 + sh4r.gbr) & UIMM8(ir) ? 0 : 1 ); - break; - case 13:/* AND.B imm8, [R0+GBR] */ - MEM_WRITE_BYTE( R0 + sh4r.gbr, - UIMM8(ir) & MEM_READ_BYTE(R0 + sh4r.gbr) ); - break; - case 14:/* XOR.B imm8, [R0+GBR] */ - MEM_WRITE_BYTE( R0 + sh4r.gbr, - UIMM8(ir) ^ MEM_READ_BYTE(R0 + sh4r.gbr) ); - break; - case 15:/* OR.B imm8, [R0+GBR] */ - MEM_WRITE_BYTE( R0 + sh4r.gbr, - UIMM8(ir) | MEM_READ_BYTE(R0 + sh4r.gbr) ); - break; - } - break; - case 13:/* 1101nnnndddddddd */ - /* MOV.L [disp8*4 + pc&~3 + 4], Rn */ - CHECKSLOTILLEGAL(); - tmp = (pc&0xFFFFFFFC) + (DISP8(ir)<<2) + 4; - RN(ir) = MEM_READ_LONG( tmp ); - break; - case 14:/* 1110nnnniiiiiiii */ - /* MOV imm8, Rn */ - RN(ir) = IMM8(ir); - break; - case 15:/* 1111xxxxxxxxxxxx */ - CHECKFPUEN(); - if( IS_FPU_DOUBLEPREC() ) { - switch( ir&0x000F ) { - case 0: /* FADD FRm, FRn */ - DRN(ir) += DRM(ir); - break; - case 1: /* FSUB FRm, FRn */ - DRN(ir) -= DRM(ir); - break; - case 2: /* FMUL FRm, FRn */ - DRN(ir) = DRN(ir) * DRM(ir); - break; - case 3: /* FDIV FRm, FRn */ - DRN(ir) = DRN(ir) / DRM(ir); - break; - case 4: /* FCMP/EQ FRm, FRn */ - sh4r.t = ( DRN(ir) == DRM(ir) ? 1 : 0 ); - break; - case 5: /* FCMP/GT FRm, FRn */ - sh4r.t = ( DRN(ir) > DRM(ir) ? 1 : 0 ); - break; - case 6: /* FMOV.S [Rm+R0], FRn */ - MEM_FP_READ( RM(ir) + R0, FRNn(ir) ); - break; - case 7: /* FMOV.S FRm, [Rn+R0] */ - MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) ); - break; - case 8: /* FMOV.S [Rm], FRn */ - MEM_FP_READ( RM(ir), FRNn(ir) ); - break; - case 9: /* FMOV.S [Rm++], FRn */ - MEM_FP_READ( RM(ir), FRNn(ir) ); - RM(ir) += FP_WIDTH; - break; - case 10:/* FMOV.S FRm, [Rn] */ - MEM_FP_WRITE( RN(ir), FRMn(ir) ); - break; - case 11:/* FMOV.S FRm, [--Rn] */ - RN(ir) -= FP_WIDTH; - MEM_FP_WRITE( RN(ir), FRMn(ir) ); - break; - case 12:/* FMOV FRm, FRn */ - if( IS_FPU_DOUBLESIZE() ) - DRN(ir) = DRM(ir); - else - FRN(ir) = FRM(ir); - break; - case 13: - switch( (ir&0x00F0) >> 4 ) { - case 0: /* FSTS FPUL, FRn */ - FRN(ir) = FPULf; - break; - case 1: /* FLDS FRn,FPUL */ - FPULf = FRN(ir); - break; - case 2: /* FLOAT FPUL, FRn */ - DRN(ir) = (float)FPULi; - break; - case 3: /* FTRC FRn, FPUL */ - dtmp = DRN(ir); - if( dtmp >= MAX_INTF ) - FPULi = MAX_INT; - else if( dtmp <= MIN_INTF ) - FPULi = MIN_INT; - else - FPULi = (int32_t)dtmp; - break; - case 4: /* FNEG FRn */ - DRN(ir) = -DRN(ir); - break; - case 5: /* FABS FRn */ - DRN(ir) = fabs(DRN(ir)); - break; - case 6: /* FSQRT FRn */ - DRN(ir) = sqrt(DRN(ir)); - break; - case 7: /* FSRRA FRn */ - /* NO-OP when PR=1 */ - break; - case 8: /* FLDI0 FRn */ - DRN(ir) = 0.0; - break; - case 9: /* FLDI1 FRn */ - DRN(ir) = 1.0; - break; - case 10: /* FCNVSD FPUL, DRn */ - if( ! IS_FPU_DOUBLESIZE() ) - DRN(ir) = (double)FPULf; - break; - case 11: /* FCNVDS DRn, FPUL */ - if( ! IS_FPU_DOUBLESIZE() ) - FPULf = (float)DRN(ir); - break; - case 14:/* FIPR FVm, FVn */ - /* NO-OP when PR=1 */ - break; - case 15: - if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */ - /* NO-OP when PR=1 */ - break; - } - else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */ - /* NO-OP when PR=1 */ - break; - } - else if( ir == 0xFBFD ) { - /* FRCHG */ - sh4r.fpscr ^= FPSCR_FR; - break; - } - else if( ir == 0xF3FD ) { - /* FSCHG */ - sh4r.fpscr ^= FPSCR_SZ; - break; - } - default: UNDEF(ir); - } - break; - case 14:/* FMAC FR0, FRm, FRn */ - DRN(ir) += DRM(ir)*DR0; - break; - default: UNDEF(ir); - } - } else { /* Single precision */ - switch( ir&0x000F ) { - case 0: /* FADD FRm, FRn */ - FRN(ir) += FRM(ir); - break; - case 1: /* FSUB FRm, FRn */ - FRN(ir) -= FRM(ir); - break; - case 2: /* FMUL FRm, FRn */ - FRN(ir) = FRN(ir) * FRM(ir); - break; - case 3: /* FDIV FRm, FRn */ - FRN(ir) = FRN(ir) / FRM(ir); - break; - case 4: /* FCMP/EQ FRm, FRn */ - sh4r.t = ( FRN(ir) == FRM(ir) ? 1 : 0 ); - break; - case 5: /* FCMP/GT FRm, FRn */ - sh4r.t = ( FRN(ir) > FRM(ir) ? 1 : 0 ); - break; - case 6: /* FMOV.S [Rm+R0], FRn */ - MEM_FP_READ( RM(ir) + R0, FRNn(ir) ); - break; - case 7: /* FMOV.S FRm, [Rn+R0] */ - MEM_FP_WRITE( RN(ir) + R0, FRMn(ir) ); - break; - case 8: /* FMOV.S [Rm], FRn */ - MEM_FP_READ( RM(ir), FRNn(ir) ); - break; - case 9: /* FMOV.S [Rm++], FRn */ - MEM_FP_READ( RM(ir), FRNn(ir) ); - RM(ir) += FP_WIDTH; - break; - case 10:/* FMOV.S FRm, [Rn] */ - MEM_FP_WRITE( RN(ir), FRMn(ir) ); - break; - case 11:/* FMOV.S FRm, [--Rn] */ - RN(ir) -= FP_WIDTH; - MEM_FP_WRITE( RN(ir), FRMn(ir) ); - break; - case 12:/* FMOV FRm, FRn */ - if( IS_FPU_DOUBLESIZE() ) - DRN(ir) = DRM(ir); - else - FRN(ir) = FRM(ir); - break; - case 13: - switch( (ir&0x00F0) >> 4 ) { - case 0: /* FSTS FPUL, FRn */ - FRN(ir) = FPULf; - break; - case 1: /* FLDS FRn,FPUL */ - FPULf = FRN(ir); - break; - case 2: /* FLOAT FPUL, FRn */ - FRN(ir) = (float)FPULi; - break; - case 3: /* FTRC FRn, FPUL */ - ftmp = FRN(ir); - if( ftmp >= MAX_INTF ) - FPULi = MAX_INT; - else if( ftmp <= MIN_INTF ) - FPULi = MIN_INT; - else - FPULi = (int32_t)ftmp; - break; - case 4: /* FNEG FRn */ - FRN(ir) = -FRN(ir); - break; - case 5: /* FABS FRn */ - FRN(ir) = fabsf(FRN(ir)); - break; - case 6: /* FSQRT FRn */ - FRN(ir) = sqrtf(FRN(ir)); - break; - case 7: /* FSRRA FRn */ - FRN(ir) = 1.0/sqrtf(FRN(ir)); - break; - case 8: /* FLDI0 FRn */ - FRN(ir) = 0.0; - break; - case 9: /* FLDI1 FRn */ - FRN(ir) = 1.0; - break; - case 10: /* FCNVSD FPUL, DRn */ - break; - case 11: /* FCNVDS DRn, FPUL */ - break; - case 14:/* FIPR FVm, FVn */ - /* FIXME: This is not going to be entirely accurate - * as the SH4 instruction is less precise. Also - * need to check for 0s and infinities. - */ - { - int tmp2 = FVN(ir); - tmp = FVM(ir); - FR(tmp2+3) = FR(tmp)*FR(tmp2) + - FR(tmp+1)*FR(tmp2+1) + - FR(tmp+2)*FR(tmp2+2) + - FR(tmp+3)*FR(tmp2+3); - break; - } - case 15: - if( (ir&0x0300) == 0x0100 ) { /* FTRV XMTRX,FVn */ - tmp = FVN(ir); - float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) }; - FR(tmp) = XF(0) * fv[0] + XF(4)*fv[1] + - XF(8)*fv[2] + XF(12)*fv[3]; - FR(tmp+1) = XF(1) * fv[0] + XF(5)*fv[1] + - XF(9)*fv[2] + XF(13)*fv[3]; - FR(tmp+2) = XF(2) * fv[0] + XF(6)*fv[1] + - XF(10)*fv[2] + XF(14)*fv[3]; - FR(tmp+3) = XF(3) * fv[0] + XF(7)*fv[1] + - XF(11)*fv[2] + XF(15)*fv[3]; - break; - } - else if( (ir&0x0100) == 0 ) { /* FSCA FPUL, DRn */ - float angle = (((float)(short)(FPULi>>16)) + - (((float)(FPULi&0xFFFF))/65536.0)) * - 2 * M_PI; - int reg = FRNn(ir); - FR(reg) = sinf(angle); - FR(reg+1) = cosf(angle); - break; - } - else if( ir == 0xFBFD ) { - /* FRCHG */ - sh4r.fpscr ^= FPSCR_FR; - break; - } - else if( ir == 0xF3FD ) { - /* FSCHG */ - sh4r.fpscr ^= FPSCR_SZ; - break; - } - default: UNDEF(ir); - } - break; - case 14:/* FMAC FR0, FRm, FRn */ - FRN(ir) += FRM(ir)*FR0; - break; - default: UNDEF(ir); - } - } - break; - } sh4r.pc = sh4r.new_pc; sh4r.new_pc += 2; sh4r.in_delay_slot = 0;