# HG changeset patch # User nkeynes # Date 1134302409 0 # Node ID 0a82ef380c45484ff79a36b7b533492a0ea1a20a # Parent c898b37506e0a44739f92b6809435b6e95d0c179 Moved arm material under aica/ Hooked arm disasm up --- a/src/Makefile.am Sun Dec 11 05:15:36 2005 +0000 +++ b/src/Makefile.am Sun Dec 11 12:00:09 2005 +0000 @@ -16,13 +16,14 @@ gui.c gui.h mmr_win.c debug_win.c dump_win.c \ mem.c mem.h mmio.h \ asic.c asic.h pvr2.c pvr2.h ide.c ide.h \ - video.c dreamcast.c dreamcast.h aica.c aica.h\ + video.c dreamcast.c dreamcast.h \ maple.c maple.h maple/controller.c maple/controller.h \ sh4/intc.c sh4/intc.h sh4/sh4mem.c \ sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \ sh4/sh4mmio.c sh4/sh4mmio.h sh4/watch.c \ + aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \ + aica/aica.c aica/aica.h \ fileio.c ipbin.c -## aica/armcore.c aica/armcore.h aica/armdasm.c \ dream_LDADD = @PACKAGE_LIBS@ $(INTLLIBS) --- a/src/Makefile.in Sun Dec 11 05:15:36 2005 +0000 +++ b/src/Makefile.in Sun Dec 11 12:00:09 2005 +0000 @@ -143,11 +143,13 @@ gui.c gui.h mmr_win.c debug_win.c dump_win.c \ mem.c mem.h mmio.h \ asic.c asic.h pvr2.c pvr2.h ide.c ide.h \ - video.c dreamcast.c dreamcast.h aica.c aica.h\ + video.c dreamcast.c dreamcast.h \ maple.c maple.h maple/controller.c maple/controller.h \ sh4/intc.c sh4/intc.h sh4/sh4mem.c \ sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \ sh4/sh4mmio.c sh4/sh4mmio.h sh4/watch.c \ + aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \ + aica/aica.c aica/aica.h \ fileio.c ipbin.c @@ -166,10 +168,11 @@ callbacks.$(OBJEXT) gui.$(OBJEXT) mmr_win.$(OBJEXT) \ debug_win.$(OBJEXT) dump_win.$(OBJEXT) mem.$(OBJEXT) \ asic.$(OBJEXT) pvr2.$(OBJEXT) ide.$(OBJEXT) video.$(OBJEXT) \ - dreamcast.$(OBJEXT) aica.$(OBJEXT) maple.$(OBJEXT) \ - controller.$(OBJEXT) intc.$(OBJEXT) sh4mem.$(OBJEXT) \ - sh4core.$(OBJEXT) sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) \ - watch.$(OBJEXT) fileio.$(OBJEXT) ipbin.$(OBJEXT) + dreamcast.$(OBJEXT) maple.$(OBJEXT) controller.$(OBJEXT) \ + intc.$(OBJEXT) sh4mem.$(OBJEXT) sh4core.$(OBJEXT) \ + sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) watch.$(OBJEXT) \ + armcore.$(OBJEXT) armdasm.$(OBJEXT) armmem.$(OBJEXT) \ + aica.$(OBJEXT) fileio.$(OBJEXT) ipbin.$(OBJEXT) dream_OBJECTS = $(am_dream_OBJECTS) dream_DEPENDENCIES = dream_LDFLAGS = @@ -177,19 +180,20 @@ DEFAULT_INCLUDES = -I. -I$(srcdir) -I$(top_builddir) depcomp = $(SHELL) $(top_srcdir)/depcomp am__depfiles_maybe = depfiles -@AMDEP_TRUE@DEP_FILES = ./$(DEPDIR)/aica.Po ./$(DEPDIR)/asic.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/callbacks.Po ./$(DEPDIR)/controller.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/debug_win.Po ./$(DEPDIR)/dreamcast.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/dump_win.Po ./$(DEPDIR)/fileio.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/gui.Po ./$(DEPDIR)/ide.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/intc.Po ./$(DEPDIR)/interface.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/ipbin.Po ./$(DEPDIR)/main.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/maple.Po ./$(DEPDIR)/mem.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/mmr_win.Po ./$(DEPDIR)/pvr2.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/sh4core.Po ./$(DEPDIR)/sh4dasm.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/sh4mem.Po ./$(DEPDIR)/sh4mmio.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/support.Po ./$(DEPDIR)/video.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/watch.Po +@AMDEP_TRUE@DEP_FILES = ./$(DEPDIR)/aica.Po ./$(DEPDIR)/armcore.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/armdasm.Po ./$(DEPDIR)/armmem.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/asic.Po ./$(DEPDIR)/callbacks.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/controller.Po ./$(DEPDIR)/debug_win.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/dreamcast.Po ./$(DEPDIR)/dump_win.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/fileio.Po ./$(DEPDIR)/gui.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/ide.Po ./$(DEPDIR)/intc.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/interface.Po ./$(DEPDIR)/ipbin.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/main.Po ./$(DEPDIR)/maple.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/mem.Po ./$(DEPDIR)/mmr_win.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/pvr2.Po ./$(DEPDIR)/sh4core.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/sh4dasm.Po ./$(DEPDIR)/sh4mem.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/sh4mmio.Po ./$(DEPDIR)/support.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/video.Po ./$(DEPDIR)/watch.Po COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) CCLD = $(CC) @@ -242,6 +246,9 @@ -rm -f *.tab.c @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/aica.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/armcore.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/armdasm.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/armmem.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/asic.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/callbacks.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/controller.Po@am__quote@ @@ -442,6 +449,94 @@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/watch.Po' tmpdepfile='$(DEPDIR)/watch.TPo' @AMDEPBACKSLASH@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(CC) 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+@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/aica.Po' tmpdepfile='$(DEPDIR)/aica.TPo' @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o aica.o `test -f 'aica/aica.c' || echo '$(srcdir)/'`aica/aica.c + +aica.obj: aica/aica.c +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT aica.obj -MD -MP -MF "$(DEPDIR)/aica.Tpo" \ +@am__fastdepCC_TRUE@ -c -o aica.obj `if test -f 'aica/aica.c'; then $(CYGPATH_W) 'aica/aica.c'; else $(CYGPATH_W) '$(srcdir)/aica/aica.c'; fi`; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/aica.Tpo" "$(DEPDIR)/aica.Po"; \ +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/aica.Tpo"; exit 1; \ +@am__fastdepCC_TRUE@ fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='aica/aica.c' object='aica.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/aica.Po' tmpdepfile='$(DEPDIR)/aica.TPo' @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o aica.obj `if test -f 'aica/aica.c'; then $(CYGPATH_W) 'aica/aica.c'; else $(CYGPATH_W) '$(srcdir)/aica/aica.c'; fi` uninstall-info-am: ETAGS = etags --- a/src/aica.c Sun Dec 11 05:15:36 2005 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,21 +0,0 @@ -#include "dream.h" -#include "aica.h" -#define MMIO_IMPL -#include "aica.h" - -MMIO_REGION_DEFFNS( AICA0 ) -MMIO_REGION_DEFFNS( AICA1 ) -MMIO_REGION_DEFFNS( AICA2 ) - -void aica_init( void ) -{ - register_io_regions( mmio_list_spu ); - MMIO_NOTRACE(AICA0); - MMIO_NOTRACE(AICA1); -} - -void aica_reset( void ) -{ - -} - --- a/src/aica.h Sun Dec 11 05:15:36 2005 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,25 +0,0 @@ -#include "mmio.h" - -MMIO_REGION_BEGIN( 0x00700000, AICA0, "AICA Sound System 0-31" ) -LONG_PORT( 0x000, AICACH0, PORT_MRW, UNDEFINED, "Channel 0" ) -MMIO_REGION_END - -MMIO_REGION_BEGIN( 0x00701000, AICA1, "AICA Sound System 32-63" ) -LONG_PORT( 0x000, AICACH32, PORT_MRW, UNDEFINED, "Channel 32" ) -MMIO_REGION_END - -MMIO_REGION_BEGIN( 0x00702000, AICA2, "AICA Sound System Control" ) -LONG_PORT( 0x040, VOLLEFT, PORT_MRW, 0, "Volume left" ) -LONG_PORT( 0x044, VOLRIGHT, PORT_MRW, 0, "Volume right" ) -LONG_PORT( 0x800, AICA_CTRL, PORT_MRW, UNDEFINED, "AICA control" ) -LONG_PORT( 0xC00, AICA_RESET,PORT_MRW, 0, "AICA reset" ) -MMIO_REGION_END - -MMIO_REGION_LIST_BEGIN( spu ) - MMIO_REGION( AICA0 ) - MMIO_REGION( AICA1 ) - MMIO_REGION( AICA2 ) -MMIO_REGION_LIST_END - -void aica_init( void ); -void aica_reset( void ); --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/aica/aica.c Sun Dec 11 12:00:09 2005 +0000 @@ -0,0 +1,82 @@ +/** + * $Id: aica.c,v 1.1 2005-12-11 12:00:09 nkeynes Exp $ + * + * This is the core sound system (ie the bit which does the actual work) + * + * Copyright (c) 2005 Nathan Keynes. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "dream.h" +#include "aica.h" +#define MMIO_IMPL +#include "aica.h" + +MMIO_REGION_READ_DEFFN( AICA0 ) +MMIO_REGION_READ_DEFFN( AICA1 ) +MMIO_REGION_READ_DEFFN( AICA2 ) + +/** + * Initialize the AICA subsystem. Note requires that + */ +void aica_init( void ) +{ + register_io_regions( mmio_list_spu ); + MMIO_NOTRACE(AICA0); + MMIO_NOTRACE(AICA1); + arm_mem_init(); +} + +void aica_reset( void ) +{ + +} + +/** Channel register structure: + * 00 + * 04 + * 08 4 Loop start address + * 0C 4 Loop end address + * 10 4 Volume envelope + * 14 + * 18 4 Frequency (floating point + * 1C + * 20 + * 24 1 Pan + * 25 1 ?? + * 26 + * 27 + * 28 1 ?? + * 29 1 Volume + * 2C + * 30 + * + +/* Write to channels 0-31 */ +void mmio_region_AICA0_write( uint32_t reg, uint32_t val ) +{ + // aica_write_channel( reg >> 7, reg % 128, val ); + +} + +/* Write to channels 32-64 */ +void mmio_region_AICA1_write( uint32_t reg, uint32_t val ) +{ + // aica_write_channel( (reg >> 7) + 32, reg % 128, val ); + +} + +/* General registers */ +void mmio_region_AICA2_write( uint32_t reg, uint32_t val ) +{ + +} --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/aica/aica.h Sun Dec 11 12:00:09 2005 +0000 @@ -0,0 +1,45 @@ +/** + * $Id: aica.h,v 1.1 2005-12-11 12:00:09 nkeynes Exp $ + * + * MMIO definitions for the AICA sound chip. Note that the regions defined + * here are relative to the SH4 memory map (0x00700000 based), rather than + * the ARM addresses (0x00800000 based). + * + * Copyright (c) 2005 Nathan Keynes. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "mmio.h" + +MMIO_REGION_BEGIN( 0x00700000, AICA0, "AICA Sound System 0-31" ) +LONG_PORT( 0x000, AICACH0, PORT_MRW, UNDEFINED, "Channel 0" ) +MMIO_REGION_END + +MMIO_REGION_BEGIN( 0x00701000, AICA1, "AICA Sound System 32-63" ) +LONG_PORT( 0x000, AICACH32, PORT_MRW, UNDEFINED, "Channel 32" ) +MMIO_REGION_END + +MMIO_REGION_BEGIN( 0x00702000, AICA2, "AICA Sound System Control" ) +LONG_PORT( 0x040, VOLLEFT, PORT_MRW, 0, "Volume left" ) +LONG_PORT( 0x044, VOLRIGHT, PORT_MRW, 0, "Volume right" ) +LONG_PORT( 0x800, AICA_CTRL, PORT_MRW, UNDEFINED, "AICA control" ) +LONG_PORT( 0xC00, AICA_RESET,PORT_MRW, 0, "AICA reset" ) +MMIO_REGION_END + +MMIO_REGION_LIST_BEGIN( spu ) + MMIO_REGION( AICA0 ) + MMIO_REGION( AICA1 ) + MMIO_REGION( AICA2 ) +MMIO_REGION_LIST_END + +void aica_init( void ); +void aica_reset( void ); --- a/src/aica/armcore.c Sun Dec 11 05:15:36 2005 +0000 +++ b/src/aica/armcore.c Sun Dec 11 12:00:09 2005 +0000 @@ -6,12 +6,12 @@ /* NB: The arm has a different memory map, but for the meantime... */ /* Page references are as per ARM DDI 0100E (June 2000) */ -#define MEM_READ_BYTE( addr ) mem_read_byte(addr) -#define MEM_READ_WORD( addr ) mem_read_word(addr) -#define MEM_READ_LONG( addr ) mem_read_long(addr) -#define MEM_WRITE_BYTE( addr, val ) mem_write_byte(addr, val) -#define MEM_WRITE_WORD( addr, val ) mem_write_word(addr, val) -#define MEM_WRITE_LONG( addr, val ) mem_write_long(addr, val) +#define MEM_READ_BYTE( addr ) arm_read_byte(addr) +#define MEM_READ_WORD( addr ) arm_read_word(addr) +#define MEM_READ_LONG( addr ) arm_read_long(addr) +#define MEM_WRITE_BYTE( addr, val ) arm_write_byte(addr, val) +#define MEM_WRITE_WORD( addr, val ) arm_write_word(addr, val) +#define MEM_WRITE_LONG( addr, val ) arm_write_long(addr, val) #define IS_NOTBORROW( result, op1, op2 ) (op2 > op1 ? 0 : 1) @@ -51,6 +51,10 @@ #define UNDEF(ir) do{ ERROR( "Raising exception on undefined instruction at %08x, opcode = %04x", PC, ir ); return; } while(0) #define UNIMP(ir) do{ ERROR( "Halted on unimplemented instruction at %08x, opcode = %04x", PC, ir ); return; }while(0) +void arm_restore_cpsr() +{ + +} static uint32_t arm_get_shift_operand( uint32_t ir ) { --- a/src/aica/armcore.h Sun Dec 11 05:15:36 2005 +0000 +++ b/src/aica/armcore.h Sun Dec 11 12:00:09 2005 +0000 @@ -8,23 +8,24 @@ #define ROTATE_RIGHT_LONG(operand,shift) ((((uint32_t)operand) >> shift) | ((operand<<(32-shift))) ) struct arm_registers { - uint32_t r[16]; /* Current register bank */ - - uint32_t cpsr; - uint32_t spsr; - - /* Various banked versions of the registers. */ - uint32_t fiq_r[7]; /* FIQ bank 8..14 */ - uint32_t irq_r[2]; /* IRQ bank 13..14 */ - uint32_t und_r[2]; /* UND bank 13..14 */ - uint32_t abt_r[2]; /* ABT bank 13..14 */ - uint32_t svc_r[2]; /* SVC bank 13..14 */ - uint32_t user_r[7]; /* User/System bank 8..14 */ - - uint32_t c,n,z,v,t; - - /* "fake" registers */ - uint32_t shift_c; /* used for temporary storage of shifter results */ + uint32_t r[16]; /* Current register bank */ + + uint32_t cpsr; + uint32_t spsr; + + /* Various banked versions of the registers. */ + uint32_t fiq_r[7]; /* FIQ bank 8..14 */ + uint32_t irq_r[2]; /* IRQ bank 13..14 */ + uint32_t und_r[2]; /* UND bank 13..14 */ + uint32_t abt_r[2]; /* ABT bank 13..14 */ + uint32_t svc_r[2]; /* SVC bank 13..14 */ + uint32_t user_r[7]; /* User/System bank 8..14 */ + + uint32_t c,n,z,v,t; + + /* "fake" registers */ + uint32_t shift_c; /* used for temporary storage of shifter results */ + uint32_t icount; /* Instruction counter */ }; #define CPSR_N 0x80000000 /* Negative flag */ @@ -48,4 +49,13 @@ #define CARRY_FLAG (armr.cpsr&CPSR_C) +/* ARM Memory */ +int32_t arm_read_long( uint32_t addr ); +int32_t arm_read_word( uint32_t addr ); +int32_t arm_read_byte( uint32_t addr ); +void arm_write_long( uint32_t addr, uint32_t val ); +void arm_write_word( uint32_t addr, uint32_t val ); +void arm_write_byte( uint32_t addr, uint32_t val ); +int32_t arm_read_phys_word( uint32_t addr ); + #endif /* !dream_armcore_H */ --- a/src/aica/armdasm.c Sun Dec 11 05:15:36 2005 +0000 +++ b/src/aica/armdasm.c Sun Dec 11 12:00:09 2005 +0000 @@ -6,6 +6,7 @@ */ #include "aica/armcore.h" +#include "aica/armdasm.h" #include #define COND(ir) (ir>>28) @@ -32,6 +33,30 @@ #define FSXC(ir) msrFieldMask[RN(ir)] #define ROTIMM12(ir) ROTATE_RIGHT_LONG(IMM8(ir),IMMROT(ir)) + +const struct reg_desc_struct arm_reg_map[] = + { {"R0", REG_INT, &armr.r[0]}, {"R1", REG_INT, &armr.r[1]}, + {"R2", REG_INT, &armr.r[2]}, {"R3", REG_INT, &armr.r[3]}, + {"R4", REG_INT, &armr.r[4]}, {"R5", REG_INT, &armr.r[5]}, + {"R6", REG_INT, &armr.r[6]}, {"R7", REG_INT, &armr.r[7]}, + {"R8", REG_INT, &armr.r[8]}, {"R9", REG_INT, &armr.r[9]}, + {"R10",REG_INT, &armr.r[10]}, {"R11",REG_INT, &armr.r[11]}, + {"R12",REG_INT, &armr.r[12]}, {"R13",REG_INT, &armr.r[13]}, + {"R14",REG_INT, &armr.r[14]}, {"R15",REG_INT, &armr.r[15]}, + {"CPSR", REG_INT, &armr.cpsr}, {"SPSR", REG_INT, &armr.spsr}, + {NULL, 0, NULL} }; + + +const struct cpu_desc_struct arm_cpu_desc = { "ARM7", arm_disasm_instruction, 4, + (char *)&armr, sizeof(armr), arm_reg_map, + &armr.r[15], &armr.icount }; +const struct cpu_desc_struct armt_cpu_desc = { "ARM7T", armt_disasm_instruction, 2, + (char*)&armr, sizeof(armr), arm_reg_map, + &armr.r[15], &armr.icount }; + + + + char *conditionNames[] = { "EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", " " /*AL*/, "NV" }; @@ -127,12 +152,15 @@ } } -int arm_disasm_instruction( uint32_t pc, char *buf, int len ) +uint32_t arm_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode ) { - char operand[32]; - uint32_t ir = arm_mem_read_long(pc); - int i,j; + char operand[32]; + uint32_t ir = arm_read_long(pc); + int i,j; + sprintf( opcode, "%02X %02X %02X %02X", ir&0xFF, (ir>>8) & 0xFF, + (ir>>16)&0xFF, (ir>>24) ); + if( COND(ir) == 0x0F ) { UNIMP(ir); return pc+4; @@ -421,3 +449,12 @@ return pc+4; } + + +uint32_t armt_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode ) +{ + uint32_t ir = arm_read_word(pc); + sprintf( opcode, "%02X %02X", ir&0xFF, (ir>>8) ); + UNIMP(ir); + return pc+2; +} --- a/src/aica/armmem.c Sun Dec 11 05:15:36 2005 +0000 +++ b/src/aica/armmem.c Sun Dec 11 12:00:09 2005 +0000 @@ -1,16 +1,57 @@ +#include +#include "dream.h" #include "mem.h" +char *arm_mem = NULL; + void arm_mem_init() { - + arm_mem = mem_get_region_by_name( MEM_REGION_AUDIO ); + } -uint32_t arm_mem_read_long( uint32_t addr ) { +int32_t arm_read_long( uint32_t addr ) { + if( addr < 0x00200000 ) { + return *(int32_t *)(arm_mem + addr); + /* Main sound ram */ + } else if( addr >= 0x00800000 && addr <= 0x00803000 ) { + /* Sound registers / scratch ram */ + } else { + /* Undefined memory */ + ERROR( "Attempted long read to undefined page: %08X", + addr ); + return 0; + } } -uint32_t arm_mem_read_byte( uint32_t addr ) { +int16_t arm_read_word( uint32_t addr ) { + if( addr < 0x00200000 ) { + return *(int16_t *)(arm_mem + addr); + /* Main sound ram */ + } else { + /* Undefined memory */ + ERROR( "Attempted word read to undefined page: %08X", + addr ); + return 0; + } + } -uint32_t arm_mem_read_long_user( uint32_t addr ) { +int8_t arm_read_byte( uint32_t addr ) { + if( addr < 0x00200000 ) { + return *(int8_t *)(arm_mem + addr); + /* Main sound ram */ + } else { + /* Undefined memory */ + ERROR( "Attempted byte read to undefined page: %08X", + addr ); + return 0; + } } -uint32_t arm_mem_read_byte_user( uint32_t addr ) { +uint32_t arm_read_long_user( uint32_t addr ) { + +} + +uint32_t arm_read_byte_user( uint32_t addr ) { + +} --- a/src/cpu.h Sun Dec 11 05:15:36 2005 +0000 +++ b/src/cpu.h Sun Dec 11 12:00:09 2005 +0000 @@ -16,7 +16,9 @@ * @param buflen Maximum length of buffer * @return next address to disassemble */ -typedef uint32_t (*disasm_func_t)(uint32_t pc, char *buffer, int buflen ); +typedef uint32_t (*disasm_func_t)(uint32_t pc, char *buffer, int buflen, char *opcode ); + +typedef int (*is_valid_page_t)(uint32_t pc); #define REG_INT 0 #define REG_FLT 1 @@ -41,6 +43,7 @@ uint32_t *pc; /* Pointer to PC register */ uint32_t *icount; /* Pointer to instruction counter */ /* Memory map? */ + is_valid_page_t valid_page_func; /* Test for valid memory page */ } *cpu_desc_t; #ifdef __cplusplus --- a/src/dreamcast.c Sun Dec 11 05:15:36 2005 +0000 +++ b/src/dreamcast.c Sun Dec 11 12:00:09 2005 +0000 @@ -1,6 +1,6 @@ #include "dream.h" #include "mem.h" -#include "aica.h" +#include "aica/aica.h" #include "asic.h" #include "ide.h" #include "dreamcast.h" @@ -9,18 +9,19 @@ void dreamcast_init( void ) { mem_init(); + mem_create_ram_region( 0x0C000000, 16 MB, MEM_REGION_MAIN ); + mem_create_ram_region( 0x05000000, 8 MB, MEM_REGION_VIDEO ); + mem_create_ram_region( 0x00800000, 2 MB, MEM_REGION_AUDIO ); + mem_create_ram_region( 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH ); /*???*/ + mem_load_rom( "dcboot.rom", 0x00000000, 0x00200000, 0x89f2b1a1 ); + mem_load_rom( "dcflash.rom",0x00200000, 0x00020000, 0x357c3568 ); + sh4_init(); asic_init(); pvr2_init(); aica_init(); ide_reset(); - mem_create_ram_region( 0x0C000000, 16 MB, MEM_REGION_MAIN ); - mem_create_ram_region( 0x05000000, 8 MB, MEM_REGION_VIDEO ); - mem_create_ram_region( 0x00800000, 2 MB, MEM_REGION_AUDIO ); - mem_create_ram_region( 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH ); /*???*/ - mem_load_rom( "dcboot.rom", 0x00000000, 0x00200000, 0x89f2b1a1 ); - mem_load_rom( "dcflash.rom",0x00200000, 0x00020000, 0x357c3568 ); } void dreamcast_reset( void ) --- a/src/gui/debug_win.c Sun Dec 11 05:15:36 2005 +0000 +++ b/src/gui/debug_win.c Sun Dec 11 12:00:09 2005 +0000 @@ -1,5 +1,5 @@ /** - * $Id: debug_win.c,v 1.4 2005-12-11 05:15:36 nkeynes Exp $ + * $Id: debug_win.c,v 1.5 2005-12-11 12:00:03 nkeynes Exp $ * This file is responsible for the main debugger gui frame. * * Copyright (c) 2005 Nathan Keynes. @@ -30,6 +30,7 @@ int disasm_to; int disasm_pc; struct cpu_desc_struct *cpu; + struct cpu_desc_struct **cpu_list; GtkCList *msgs_list; GtkCList *regs_list; GtkCList *disasm_list; @@ -39,31 +40,20 @@ char saved_regs[0]; }; -debug_info_t init_debug_win(GtkWidget *win, struct cpu_desc_struct *cpu ) +debug_info_t init_debug_win(GtkWidget *win, struct cpu_desc_struct **cpu_list ) { - int i; - char buf[20]; - char *arr[2]; GnomeAppBar *appbar; - debug_info_t data = g_malloc0( sizeof(struct debug_info_struct) + cpu->regs_size ); + debug_info_t data = g_malloc0( sizeof(struct debug_info_struct) + cpu_list[0]->regs_size ); data->disasm_from = -1; data->disasm_to = -1; data->disasm_pc = -1; - data->cpu = cpu; + data->cpu = cpu_list[0]; + data->cpu_list = cpu_list; data->regs_list= gtk_object_get_data(GTK_OBJECT(win), "reg_list"); - arr[1] = buf; - for( i=0; data->cpu->regs_info[i].name != NULL; i++ ) { - arr[0] = data->cpu->regs_info[i].name; - if( data->cpu->regs_info->type == REG_INT ) - sprintf( buf, "%08X", *((uint32_t *)data->cpu->regs_info->value) ); - else - sprintf( buf, "%f", *((float *)data->cpu->regs_info->value) ); - gtk_clist_append( data->regs_list, arr ); - } gtk_widget_modify_font( GTK_WIDGET(data->regs_list), fixed_list_font ); - + init_register_list( data ); data->msgs_list = gtk_object_get_data(GTK_OBJECT(win), "output_list"); data->disasm_list = gtk_object_get_data(GTK_OBJECT(win), "disasm_list"); gtk_clist_set_column_width( data->disasm_list, 1, 16 ); @@ -77,6 +67,24 @@ return data; } +void init_register_list( debug_info_t data ) +{ + int i; + char buf[20]; + char *arr[2]; + + gtk_clist_clear( data->regs_list ); + arr[1] = buf; + for( i=0; data->cpu->regs_info[i].name != NULL; i++ ) { + arr[0] = data->cpu->regs_info[i].name; + if( data->cpu->regs_info->type == REG_INT ) + sprintf( buf, "%08X", *((uint32_t *)data->cpu->regs_info[i].value) ); + else + sprintf( buf, "%f", *((float *)data->cpu->regs_info[i].value) ); + gtk_clist_append( data->regs_list, arr ); + } +} + /* * Check for changed registers and update the display */ @@ -120,11 +128,11 @@ void set_disassembly_region( debug_info_t data, unsigned int page ) { - uint32_t i, posn; + uint32_t i, posn, next; uint16_t op; char buf[80]; char addr[10]; - char opcode[6] = ""; + char opcode[16] = ""; char *arr[4] = { addr, " ", opcode, buf }; unsigned int from = page & 0xFFFFF000; unsigned int to = from + 4096; @@ -139,11 +147,10 @@ gtk_clist_append( data->disasm_list, arr ); gtk_clist_set_foreground( data->disasm_list, 0, &clrError ); } else { - for( i=from; icpu->disasm_func( i, buf, sizeof(buf) ); + for( i=from; icpu->disasm_func( i, buf, sizeof(buf), opcode ); sprintf( addr, "%08X", i ); op = sh4_read_phys_word(i); - sprintf( opcode, "%02X %02X", op&0xFF, op>>8 ); posn = gtk_clist_append( data->disasm_list, arr ); if( buf[0] == '?' ) gtk_clist_set_foreground( data->disasm_list, posn, &clrWarn ); @@ -198,8 +205,17 @@ void set_disassembly_cpu( debug_info_t data, char *cpu ) { - - + int i; + for( i=0; data->cpu_list[i] != NULL; i++ ) { + if( strcmp( data->cpu_list[i]->name, cpu ) == 0 ) { + if( data->cpu != data->cpu_list[i] ) { + data->cpu = data->cpu_list[i]; + set_disassembly_region( data, data->disasm_from ); + init_register_list( data ); + } + return; + } + } } uint32_t row_to_address( debug_info_t data, int row ) { --- a/src/gui/gui.h Sun Dec 11 05:15:36 2005 +0000 +++ b/src/gui/gui.h Sun Dec 11 12:00:09 2005 +0000 @@ -21,7 +21,7 @@ typedef struct debug_info_struct *debug_info_t; extern debug_info_t main_debug; -debug_info_t init_debug_win(GtkWidget *, cpu_desc_t cpu ); +debug_info_t init_debug_win(GtkWidget *, cpu_desc_t *cpu ); debug_info_t get_debug_info(GtkWidget *widget); void open_file_dialog( void ); void update_mmr_win( void ); --- a/src/main.c Sun Dec 11 05:15:36 2005 +0000 +++ b/src/main.c Sun Dec 11 12:00:09 2005 +0000 @@ -13,10 +13,13 @@ #include "gui.h" #include "sh4core.h" #include "sh4dasm.h" +#include "aica/armdasm.h" #include "mem.h" debug_info_t main_debug; +const cpu_desc_t cpu_descs[4] = { &sh4_cpu_desc, &arm_cpu_desc, &armt_cpu_desc, NULL }; + int main (int argc, char *argv[]) { @@ -29,7 +32,7 @@ gnome_init ("dreamon", VERSION, argc, argv); init_gui(); debug_win = create_debug_win (); - main_debug = init_debug_win(debug_win, &sh4_cpu_desc); + main_debug = init_debug_win(debug_win, cpu_descs); video_open(); dreamcast_init(); init_mmr_win(); /* Note: must be done after sh4_init */ --- a/src/mem.c Sun Dec 11 05:15:36 2005 +0000 +++ b/src/mem.c Sun Dec 11 12:00:09 2005 +0000 @@ -1,5 +1,5 @@ /** - * $Id: mem.c,v 1.1 2005-12-11 05:15:36 nkeynes Exp $ + * $Id: mem.c,v 1.2 2005-12-11 12:00:03 nkeynes Exp $ * mem.c is responsible for creating and maintaining the overall system memory * map, as visible from the SH4 processor. * @@ -201,3 +201,4 @@ return page+(addr&0xFFF); } } + --- a/src/mem.h Sun Dec 11 05:15:36 2005 +0000 +++ b/src/mem.h Sun Dec 11 12:00:09 2005 +0000 @@ -26,14 +26,6 @@ #define MB * (1024 * 1024) #define KB * 1024 -int32_t sh4_read_long( uint32_t addr ); -int32_t sh4_read_word( uint32_t addr ); -int32_t sh4_read_byte( uint32_t addr ); -void sh4_write_long( uint32_t addr, uint32_t val ); -void sh4_write_word( uint32_t addr, uint32_t val ); -void sh4_write_byte( uint32_t addr, uint32_t val ); -int32_t sh4_read_phys_word( uint32_t addr ); - void *mem_create_ram_region( uint32_t base, uint32_t size, char *name ); void *mem_load_rom( char *name, uint32_t base, uint32_t size, uint32_t crc ); char *mem_get_region( uint32_t addr ); --- a/src/sh4/sh4dasm.c Sun Dec 11 05:15:36 2005 +0000 +++ b/src/sh4/sh4dasm.c Sun Dec 11 12:00:09 2005 +0000 @@ -5,7 +5,7 @@ #define UNIMP(ir) snprintf( buf, len, "??? " ) -struct reg_desc_struct sh4_reg_map[] = +const struct reg_desc_struct sh4_reg_map[] = { {"R0", REG_INT, &sh4r.r[0]}, {"R1", REG_INT, &sh4r.r[1]}, {"R2", REG_INT, &sh4r.r[2]}, {"R3", REG_INT, &sh4r.r[3]}, {"R4", REG_INT, &sh4r.r[4]}, {"R5", REG_INT, &sh4r.r[5]}, @@ -24,11 +24,11 @@ {NULL, 0, NULL} }; -struct cpu_desc_struct sh4_cpu_desc = { "SH4", sh4_disasm_instruction, 2, +const struct cpu_desc_struct sh4_cpu_desc = { "SH4", sh4_disasm_instruction, 2, (char *)&sh4r, sizeof(sh4r), sh4_reg_map, &sh4r.pc, &sh4r.icount }; -uint32_t sh4_disasm_instruction( uint32_t pc, char *buf, int len ) +uint32_t sh4_disasm_instruction( uint32_t pc, char *buf, int len, char *opcode ) { uint16_t ir = sh4_read_word(pc); @@ -44,6 +44,8 @@ #define FVN(ir) ((ir&0x0C00)>>10) #define FVM(ir) ((ir&0x0300)>>8) + sprintf( opcode, "%02X %02X", ir&0xFF, ir>>8 ); + switch( (ir&0xF000)>>12 ) { case 0: /* 0000nnnnmmmmxxxx */ switch( ir&0x000F ) { @@ -362,12 +364,12 @@ { int pc; char buf[80]; + char opcode[16]; for( pc = from; pc < to; pc+=2 ) { - uint16_t op = sh4_read_word( pc ); buf[0] = '\0'; sh4_disasm_instruction( pc, - buf, sizeof(buf) ); - fprintf( f, " %08x: %04x %s\n", pc + load_addr, op, buf ); + buf, sizeof(buf), opcode ); + fprintf( f, " %08x: %s %s\n", pc + load_addr, opcode, buf ); } } --- a/src/sh4/sh4dasm.h Sun Dec 11 05:15:36 2005 +0000 +++ b/src/sh4/sh4dasm.h Sun Dec 11 12:00:09 2005 +0000 @@ -9,10 +9,10 @@ #include -uint32_t sh4_disasm_instruction( uint32_t pc, char *buf, int len ); +uint32_t sh4_disasm_instruction( uint32_t pc, char *buf, int len, char * ); void sh4_disasm_region( FILE *f, int from, int to, int load_addr ); -extern struct cpu_desc_struct sh4_cpu_desc; +extern const struct cpu_desc_struct sh4_cpu_desc; #ifdef __cplusplus }