# HG changeset patch
# User nkeynes
# Date 1139112177 0
# Node ID 108450d84ce8823416673a8c66f7b08b3a8b6108
# Parent  61bb3ee00cf855d5adb21273e46c58ec8d401b50
Comment out some more info lines

--- a/src/sh4/sh4core.c	Sun Feb 05 04:01:55 2006 +0000
+++ b/src/sh4/sh4core.c	Sun Feb 05 04:02:57 2006 +0000
@@ -1,5 +1,5 @@
 /**
- * $Id: sh4core.c,v 1.18 2006-01-21 11:38:36 nkeynes Exp $
+ * $Id: sh4core.c,v 1.19 2006-02-05 04:02:57 nkeynes Exp $
  * 
  * SH4 emulation core, and parent module for all the SH4 peripheral
  * modules.
@@ -288,7 +288,7 @@
     MMIO_WRITE( MMU, INTEVT, code );
     sh4r.pc = sh4r.vbr + 0x600;
     sh4r.new_pc = sh4r.pc + 2;
-    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
+    //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
 }
 
 gboolean sh4_execute_instruction( void )
@@ -399,8 +399,9 @@
                                 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
                                 uint32_t target = tmp&0x03FFFFE0 | hi;
                                 mem_copy_to_sh4( target, src, 32 );
-				//				WARN( "Executed SQ%c => %08X",
-				//				      (queue == 0 ? '0' : '1'), target );
+				//if( (target &0xFF000000) != 0x04000000 ) 
+				//    WARN( "Executed SQ%c => %08X",
+				//	  (queue == 0 ? '0' : '1'), target );
                             }
                             break;
                         case 9: /* OCBI    [Rn] */
--- a/src/sh4/sh4mmio.c	Sun Feb 05 04:01:55 2006 +0000
+++ b/src/sh4/sh4mmio.c	Sun Feb 05 04:02:57 2006 +0000
@@ -1,5 +1,5 @@
 /**
- * $Id: sh4mmio.c,v 1.7 2006-01-01 08:08:40 nkeynes Exp $
+ * $Id: sh4mmio.c,v 1.8 2006-02-05 04:02:57 nkeynes Exp $
  * 
  * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
  * responsible for including the IMPL side of the SH4 MMIO pages.
@@ -29,7 +29,7 @@
 
 /********************************* MMU *************************************/
 
-MMIO_REGION_READ_STUBFN( MMU )
+MMIO_REGION_READ_DEFFN( MMU )
 
 #define OCRAM_START (0x1C000000>>PAGE_BITS)
 #define OCRAM_END   (0x20000000>>PAGE_BITS)