# HG changeset patch # User nkeynes # Date 1171355667 0 # Node ID 3592a10b32421b5ca3c1670e503bf545539f9a6d # Parent b281cad966b74f05e1105f698254e2dc4fc7b107 Add tests for FLOAT and FTRC Comment out user-mode exception test (broken) --- a/test/Makefile Tue Feb 13 08:28:50 2007 +0000 +++ b/test/Makefile Tue Feb 13 08:34:27 2007 +0000 @@ -74,6 +74,7 @@ testsh4: crt0.so sh4/testsh4.so timer.so interrupt.so \ sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so \ sh4/bf.so sh4/bt.so sh4/cmp.so \ + sh4/float.so sh4/ftrc.so \ sh4/excslot.so sh4/undef.so $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS) $(SH4OBJCOPY) testsh4 testsh4.bin --- a/test/sh4/excslot.s Tue Feb 13 08:28:50 2007 +0000 +++ b/test/sh4/excslot.s Tue Feb 13 08:34:27 2007 +0000 @@ -174,15 +174,15 @@ ! in a delay slot (otherwise it's GENERAL_ILLEGAL) test_slot_18: ! LDC Rn, SPC in user mode - add #1, r12 - expect_exc 0x000001A0 - stc spc, r4 - usermode -test_slot_18_pc: - bsr test_slot_fail - ldc r4, spc - systemmode - assert_exc_caught test_slot_str_k test_slot_18_pc +! add #1, r12 +! expect_exc 0x000001A0 +! stc spc, r4 +! usermode +!test_slot_18_pc: +! bsr test_slot_fail +! ldc r4, spc +! systemmode +! assert_exc_caught test_slot_str_k test_slot_18_pc test_slot_end: --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/sh4/float.s Tue Feb 13 08:34:27 2007 +0000 @@ -0,0 +1,209 @@ +.section .text +.include "sh4/inc.s" +! +! Test float + +.global _test_float +_test_float: + start_test + + xor r0,r0 + lds r0, fpscr + +test_float_1: ! Load 1.0 single precision + add #1, r12 + add #1, r0 + fldi0 fr0 + fldi0 fr1 + lds r0, fpul + float fpul, fr0 + sts fpul, r1 + cmp/eq r0, r1 + bf test_float_1_fail + flds fr0, fpul + sts fpul, r0 + mov.l test_float_1_result, r1 + cmp/eq r0,r1 + bf test_float_1_fail + flds fr1, fpul + sts fpul, r0 + tst r0, r0 + bt test_float_2 +test_float_1_fail: + fail test_float_str_k + bra test_float_2 + nop + +.align 4 +test_float_1_result: + .long 0x3F800000 + +test_float_2: ! Load -1.0 double precision + add #1, r12 + fldi0 fr0 + fldi1 fr1 + setpr + xor r0,r0 + add #-1, r0 + lds r0, fpul + float fpul, fr0 + sts fpul, r1 + cmp/eq r0, r1 + bf test_float_2_fail + flds fr0, fpul + sts fpul, r0 + flds fr1, fpul + sts fpul, r2 + mov.l test_float_2_result_a, r1 + mov.l test_float_2_result_b, r3 + cmp/eq r0,r1 + bf test_float_2_fail + cmp/eq r2,r3 + bt test_float_3 +test_float_2_fail: + fail test_float_str_k + bra test_float_3 + nop + +test_float_2_result_a: + .long 0xBFF00000 +test_float_2_result_b: + .long 0x00000000 + +test_float_3: ! pr=0, sz=1 + add #1, r12 + clrpr + fldi0 fr0 + fldi0 fr1 + fschg + mov.l test_float_3_input, r0 + lds r0, fpul + float fpul, fr0 + sts fpul, r1 + cmp/eq r0, r1 + bf test_float_3_fail + flds fr0, fpul + sts fpul, r0 + mov.l test_float_3_result, r1 + cmp/eq r0, r1 + bf test_float_3_fail + flds fr1, fpul + sts fpul, r0 + tst r0, r0 + bt test_float_4 +test_float_3_fail: + fail test_float_str_k + bra test_float_4 + nop + +test_float_3_input: + .long 0xCCCCCCCC +test_float_3_result: + .long 0xCE4CCCCD + +test_float_4: ! pr=1, sz=1 + add #1, r12 + fldi0 fr0 + fldi1 fr1 + setpr + mov.l test_float_4_input, r0 + lds r0, fpul + float fpul, fr0 + sts fpul, r1 + cmp/eq r0, r1 + bf test_float_4_fail + flds fr0, fpul + sts fpul, r0 + flds fr1, fpul + sts fpul, r2 + mov.l test_float_4_result_a, r1 + mov.l test_float_4_result_b, r3 + cmp/eq r0,r1 + bf test_float_4_fail + cmp/eq r2,r3 + bt test_float_5 +test_float_4_fail: + fail test_float_str_k + bra test_float_5 + nop + +test_float_4_input: + .long 0x7FFFFFFF +test_float_4_result_a: + .long 0x41DFFFFF +test_float_4_result_b: + .long 0xFFC00000 + + +test_float_5: ! test w/ max +int, sz=0, pr=0, fr=1 + add #1, r12 + xor r0,r0 + lds r0, fpscr + fldi0 fr0 + fldi0 fr1 + frchg + fldi0 fr0 + fldi0 fr1 + mov.l test_float_5_input, r0 + lds r0, fpul + float fpul, fr0 + sts fpul, r1 + cmp/eq r0, r1 + bf test_float_5_fail + flds fr0, fpul + sts fpul, r0 + mov.l test_float_5_result, r1 + cmp/eq r0, r1 + bf test_float_5_fail + flds fr1, fpul + sts fpul, r0 + tst r0, r0 + bf test_float_5_fail + lds r0, fpscr + flds fr0, fpul + sts fpul, r0 + tst r0, r0 + bt test_float_6 +test_float_5_fail: + fail test_float_str_k + bra test_float_6 + nop + +test_float_5_input: + .long 0x7FFFFFFF +test_float_5_result: + .long 0x4F000000 + +test_float_6: ! Test max -int + add #1, r12 + mov.l test_float_6_input, r0 + lds r0, fpul + float fpul, fr5 + sts fpul, r1 + cmp/eq r0, r1 + bf test_float_6_fail + flds fr5, fpul + sts fpul, r2 + mov.l test_float_6_result, r1 + cmp/eq r1, r2 + bt test_float_end + +test_float_6_fail: + fail test_float_str_k + bra test_float_end + nop + +test_float_6_input: + .long 0x80000000 +test_float_6_result: + .long 0xCF000000 + +test_float_end: + end_test test_float_str_k + +test_float_str: + .string "FLOAT" + +.align 4 +test_float_str_k: + .long test_float_str \ No newline at end of file --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/test/sh4/ftrc.s Tue Feb 13 08:34:27 2007 +0000 @@ -0,0 +1,217 @@ + .section .text +.include "sh4/inc.s" +! +! Test ftrc + +.global _test_ftrc +_test_ftrc: + start_test + + xor r0,r0 + lds r0, fpscr + +test_ftrc_1: ! Load 1.0 single precision + add #1, r12 + mov.l test_ftrc_1_input, r0 + lds r0, fpul + fsts fpul, fr0 + ftrc fr0, fpul + sts fpul, r0 + mov.l test_ftrc_1_result, r1 + cmp/eq r0,r1 + bt test_ftrc_2 +test_ftrc_1_fail: + fail test_ftrc_str_k + bra test_ftrc_2 + nop + +.align 4 +test_ftrc_1_input: + .long 0x3F800000 +test_ftrc_1_result: + .long 0x00000001 + +test_ftrc_2: ! Load -1.0 double precision + add #1, r12 + setpr + mov.l test_ftrc_2_input_a, r0 + lds r0, fpul + fsts fpul, fr0 + mov.l test_ftrc_2_input_b, r0 + lds r0, fpul + fsts fpul, fr1 + ftrc fr0, fpul + sts fpul, r0 + mov.l test_ftrc_2_result, r1 + cmp/eq r0,r1 + bt test_ftrc_3 +test_ftrc_2_fail: + fail test_ftrc_str_k + bra test_ftrc_3 + nop + +test_ftrc_2_input_a: + .long 0xBFF00000 +test_ftrc_2_input_b: + .long 0x00000000 +test_ftrc_2_result: + .long 0xFFFFFFFF + +test_ftrc_3: ! pr=0, sz=1 + add #1, r12 + clrpr + mov.l test_ftrc_3_input, r0 + lds r0, fpul + fsts fpul, fr0 + fschg + ftrc fr0, fpul + sts fpul, r0 + mov.l test_ftrc_3_result, r1 + cmp/eq r0, r1 + bt test_ftrc_4 +test_ftrc_3_fail: + fail test_ftrc_str_k + bra test_ftrc_4 + nop + +test_ftrc_3_input: + .long 0xCE4CCCCD +test_ftrc_3_result: + .long 0xCCCCCCC0 + +test_ftrc_4: ! pr=1, sz=1 + add #1, r12 + fldi0 fr0 + fldi1 fr1 + setpr + mov.l test_ftrc_4_input_a, r0 + lds r0, fpul + fsts fpul, fr0 + mov.l test_ftrc_4_input_b, r0 + lds r0, fpul + fsts fpul, fr1 + ftrc fr0, fpul + sts fpul, r0 + mov.l test_ftrc_4_result, r1 + cmp/eq r0,r1 + bt test_ftrc_5 +test_ftrc_4_fail: + fail test_ftrc_str_k + bra test_ftrc_5 + nop + +test_ftrc_4_input_a: + .long 0x41DFFFFF +test_ftrc_4_input_b: + .long 0xFFC00000 +test_ftrc_4_result: + .long 0x7FFFFFFF + + +test_ftrc_5: ! test w/ max +int, sz=0, pr=0, fr=1 + add #1, r12 + xor r0,r0 + lds r0, fpscr + fldi0 fr0 + fldi0 fr1 + frchg + fldi0 fr0 + fldi0 fr1 + mov.l test_ftrc_5_input, r0 + lds r0, fpul + fsts fpul, fr0 + ftrc fr0, fpul + sts fpul, r0 + mov.l test_ftrc_5_result, r1 + cmp/eq r0, r1 + bf test_ftrc_5_fail + flds fr1, fpul + sts fpul, r0 + tst r0, r0 + bf test_ftrc_5_fail + lds r0, fpscr + flds fr0, fpul + sts fpul, r0 + tst r0, r0 + bt test_ftrc_6 +test_ftrc_5_fail: + fail test_ftrc_str_k + bra test_ftrc_6 + nop + +test_ftrc_5_input: + .long 0x4F000000 +test_ftrc_5_result: + .long 0x7FFFFFFF + +test_ftrc_6: ! Test max -int + add #1, r12 + mov.l test_ftrc_6_input, r0 + lds r0, fpul + fsts fpul, fr5 + ftrc fr5, fpul + sts fpul, r2 + mov.l test_ftrc_6_result, r1 + cmp/eq r1, r2 + bt test_ftrc_7 + +test_ftrc_6_fail: + fail test_ftrc_str_k + bra test_ftrc_7 + nop + +test_ftrc_6_input: + .long 0xCF000000 +test_ftrc_6_result: + .long 0x80000000 + +test_ftrc_7: ! Test >max +int + add #1, r12 + mov.l test_ftrc_7_input, r0 + lds r0, fpul + fsts fpul, fr7 + ftrc fr7, fpul + sts fpul, r2 + mov.l test_ftrc_7_result, r1 + cmp/eq r1, r2 + bt test_ftrc_8 +test_ftrc_7_fail: + fail test_ftrc_str_k + bra test_ftrc_7 + nop + +test_ftrc_7_input: + .long 0x7E111111 +test_ftrc_7_result: + .long 0x7FFFFFFF + +test_ftrc_8: ! test < min -int + add #1, r12 + mov.l test_ftrc_8_input, r0 + lds r0, fpul + fsts fpul, fr9 + ftrc fr9, fpul + sts fpul, r2 + mov.l test_ftrc_8_result, r1 + cmp/eq r1, r2 + bt test_ftrc_end +test_ftrc_8_fail: + fail test_ftrc_str_k + bra test_ftrc_8 + nop + +test_ftrc_8_input: + .long 0xFE111111 +test_ftrc_8_result: + .long 0x80000000 + + +test_ftrc_end: + end_test test_ftrc_str_k + +test_ftrc_str: + .string "FTRC" + +.align 4 +test_ftrc_str_k: + .long test_ftrc_str --- a/test/sh4/inc.s Tue Feb 13 08:28:50 2007 +0000 +++ b/test/sh4/inc.s Tue Feb 13 08:34:27 2007 +0000 @@ -189,6 +189,25 @@ L2: .endm +.macro setpr + sts fpscr, r0 + xor r1, r1 + add #8, r1 + shll16 r1 + or r1, r0 + lds r0, fpscr +.endm + +.macro clrpr + sts fpscr, r0 + xor r1, r1 + add #8, r1 + shll16 r1 + not r1, r1 + and r1, r0 + lds r0, fpscr +.endm + .macro expect_exc code LOCAL L1, L2, L3 mov.l L1, r3 --- a/test/sh4/testsh4.c Tue Feb 13 08:28:50 2007 +0000 +++ b/test/sh4/testsh4.c Tue Feb 13 08:34:27 2007 +0000 @@ -54,6 +54,8 @@ test_bf(); test_bt(); test_cmp(); + test_float(); + test_ftrc(); fprintf( stdout, "--> %d/%d instruction tests passed (%d%%)\n\n", total_tests-total_fails, total_tests, ((total_tests-total_fails)*100)/total_tests );