# HG changeset patch
# User nkeynes
# Date 1211749315 0
# Node ID 44c579439d733ba098f7a11baccf0481a7405ca0
# Parent  cc2c2b0ab2724d0a2f7b8325770264471fd43b4e
Count fpscr ops separately from other LDS/STS instructions

--- a/src/sh4/sh4stat.c	Sun May 25 20:59:29 2008 +0000
+++ b/src/sh4/sh4stat.c	Sun May 25 21:01:55 2008 +0000
@@ -98,7 +98,9 @@
 "LDC Rm, *",
 "LDC.L @Rm+, SR",
 "LDC.L @Rm+, *",
+"LDS Rm, FPSCR",
 "LDS Rm, *",
+"LDS.L @Rm+, FPSCR",
 "LDS.L @Rm+, *",
 "LDTLB",
 "MAC.L @Rm+, @Rn+",
@@ -145,7 +147,9 @@
 "STC *, Rn",
 "STC.L SR, @-Rn",
 "STC.L *, @-Rn",
+"STS FPSCR, Rn",
 "STS *, Rn",
+"STS.L FPSCR, @-Rn",
 "STS.L *, @-Rn",
 "SUB Rm, Rn",
 "SUBC Rm, Rn",
@@ -410,7 +414,7 @@
                             case 0x6:
                                 { /* STS FPSCR, Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
-                                sh4_stats[I_STS]++;
+                                sh4_stats[I_STSFPSCR]++;
                                 }
                                 break;
                             case 0xF:
@@ -756,7 +760,7 @@
                             case 0x6:
                                 { /* STS.L FPSCR, @-Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
-                                sh4_stats[I_STSM]++;
+                                sh4_stats[I_STSFPSCRM]++;
                                 }
                                 break;
                             case 0xF:
@@ -896,7 +900,7 @@
                             case 0x6:
                                 { /* LDS.L @Rm+, FPSCR */
                                 uint32_t Rm = ((ir>>8)&0xF); 
-                                sh4_stats[I_LDSM]++;
+                                sh4_stats[I_LDSFPSCRM]++;
                                 }
                                 break;
                             case 0xF:
@@ -1042,7 +1046,7 @@
                             case 0x6:
                                 { /* LDS Rm, FPSCR */
                                 uint32_t Rm = ((ir>>8)&0xF); 
-                                sh4_stats[I_LDS]++;
+                                sh4_stats[I_LDSFPSCR]++;
                                 }
                                 break;
                             case 0xF:
--- a/src/sh4/sh4stat.h	Sun May 25 20:59:29 2008 +0000
+++ b/src/sh4/sh4stat.h	Sun May 25 21:01:55 2008 +0000
@@ -37,7 +37,7 @@
     I_FMOV5, I_FMOV6, I_FMOV7, I_FMUL, I_FNEG, I_FRCHG, I_FSCA, I_FSCHG, 
     I_FSQRT, I_FSRRA, I_FSTS, I_FSUB, I_FTRC, I_FTRV,  
     I_JMP, I_JSR,   
-    I_LDCSR, I_LDC, I_LDCSRM, I_LDCM, I_LDS, I_LDSM, I_LDTLB, 
+    I_LDCSR, I_LDC, I_LDCSRM, I_LDCM, I_LDSFPSCR, I_LDS, I_LDSFPSCRM, I_LDSM, I_LDTLB, 
     I_MACL, I_MACW,  
     I_MOV, I_MOVI, I_MOVB, I_MOVL, I_MOVLPC, I_MOVW, I_MOVA, I_MOVCA, I_MOVT,  
     I_MULL, I_MULSW, I_MULUW, 
@@ -50,7 +50,7 @@
     I_SETS, I_SETT,  
     I_SHAD, I_SHAL, I_SHAR, I_SHLD, I_SHLL, I_SHLR,  
     I_SLEEP, 
-    I_STCSR, I_STC, I_STCSRM, I_STCM, I_STS, I_STSM,  
+    I_STCSR, I_STC, I_STCSRM, I_STCM, I_STSFPSCR, I_STS, I_STSFPSCRM, I_STSM,  
     I_SUB, I_SUBC, I_SUBV,  
     I_SWAPB, I_SWAPW, I_TASB,  
     I_TRAPA,
--- a/src/sh4/sh4stat.in	Sun May 25 20:59:29 2008 +0000
+++ b/src/sh4/sh4stat.in	Sun May 25 21:01:55 2008 +0000
@@ -98,7 +98,9 @@
 "LDC Rm, *",
 "LDC.L @Rm+, SR",
 "LDC.L @Rm+, *",
+"LDS Rm, FPSCR",
 "LDS Rm, *",
+"LDS.L @Rm+, FPSCR",
 "LDS.L @Rm+, *",
 "LDTLB",
 "MAC.L @Rm+, @Rn+",
@@ -145,7 +147,9 @@
 "STC *, Rn",
 "STC.L SR, @-Rn",
 "STC.L *, @-Rn",
+"STS FPSCR, Rn",
 "STS *, Rn",
+"STS.L FPSCR, @-Rn",
 "STS.L *, @-Rn",
 "SUB Rm, Rn",
 "SUBC Rm, Rn",
@@ -279,8 +283,8 @@
 LDC.L @Rm+, SPC {: sh4_stats[I_LDCM]++; :}
 LDC.L @Rm+, DBR {: sh4_stats[I_LDCM]++; :}
 LDC.L @Rm+, Rn_BANK {: sh4_stats[I_LDCM]++; :}
-LDS Rm, FPSCR {: sh4_stats[I_LDS]++; :}
-LDS.L @Rm+, FPSCR {: sh4_stats[I_LDSM]++; :}
+LDS Rm, FPSCR {: sh4_stats[I_LDSFPSCR]++; :}
+LDS.L @Rm+, FPSCR {: sh4_stats[I_LDSFPSCRM]++; :}
 LDS Rm, FPUL {: sh4_stats[I_LDS]++; :}
 LDS.L @Rm+, FPUL {: sh4_stats[I_LDSM]++; :}
 LDS Rm, MACH {: sh4_stats[I_LDS]++; :}
@@ -380,8 +384,8 @@
 STC.L DBR, @-Rn {: sh4_stats[I_STCM]++; :}
 STC.L Rm_BANK, @-Rn {: sh4_stats[I_STCM]++; :}
 STC.L GBR, @-Rn {: sh4_stats[I_STCM]++; :}
-STS FPSCR, Rn {: sh4_stats[I_STS]++; :}
-STS.L FPSCR, @-Rn {: sh4_stats[I_STSM]++; :}
+STS FPSCR, Rn {: sh4_stats[I_STSFPSCR]++; :}
+STS.L FPSCR, @-Rn {: sh4_stats[I_STSFPSCRM]++; :}
 STS FPUL, Rn {: sh4_stats[I_STS]++; :}
 STS.L FPUL, @-Rn {: sh4_stats[I_STSM]++; :}
 STS MACH, Rn {: sh4_stats[I_STS]++; :}
--- a/src/sh4/sh4x86.c	Sun May 25 20:59:29 2008 +0000
+++ b/src/sh4/sh4x86.c	Sun May 25 21:01:55 2008 +0000
@@ -750,7 +750,7 @@
                             case 0x6:
                                 { /* STS FPSCR, Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
-                                COUNT_INST(I_STS);
+                                COUNT_INST(I_STSFPSCR);
                                 check_fpuen();
                                 load_spreg( R_EAX, R_FPSCR );
                                 store_reg( R_EAX, Rn );
@@ -1488,7 +1488,7 @@
                             case 0x6:
                                 { /* STS.L FPSCR, @-Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
-                                COUNT_INST(I_STSM);
+                                COUNT_INST(I_STSFPSCRM);
                                 check_fpuen();
                                 load_reg( R_EAX, Rn );
                                 check_walign32( R_EAX );
@@ -1768,7 +1768,7 @@
                             case 0x6:
                                 { /* LDS.L @Rm+, FPSCR */
                                 uint32_t Rm = ((ir>>8)&0xF); 
-                                COUNT_INST(I_LDS);
+                                COUNT_INST(I_LDSFPSCRM);
                                 check_fpuen();
                                 load_reg( R_EAX, Rm );
                                 check_ralign32( R_EAX );
@@ -2020,7 +2020,7 @@
                             case 0x6:
                                 { /* LDS Rm, FPSCR */
                                 uint32_t Rm = ((ir>>8)&0xF); 
-                                COUNT_INST(I_LDS);
+                                COUNT_INST(I_LDSFPSCR);
                                 check_fpuen();
                                 load_reg( R_EAX, Rm );
                                 call_func1( sh4_write_fpscr, R_EAX );
@@ -3296,18 +3296,11 @@
                         { /* FMOV FRm, FRn */
                         uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF); 
                         COUNT_INST(I_FMOV1);
-                        /* As horrible as this looks, it's actually covering 5 separate cases:
-                         * 1. 32-bit fr-to-fr (PR=0)
-                         * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
-                         * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
-                         * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
-                         * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
-                         */
                         check_fpuen();
                         load_spreg( R_ECX, R_FPSCR );
                         TEST_imm32_r32( FPSCR_SZ, R_ECX );
                         JNE_rel8(doublesize);
-                        load_fr( R_EAX, FRm ); // PR=0 branch
+                        load_fr( R_EAX, FRm ); // SZ=0 branch
                         store_fr( R_EAX, FRn );
                         JMP_rel8(end);
                         JMP_TARGET(doublesize);
--- a/src/sh4/sh4x86.in	Sun May 25 20:59:29 2008 +0000
+++ b/src/sh4/sh4x86.in	Sun May 25 21:01:55 2008 +0000
@@ -1798,18 +1798,11 @@
 /* Floating point moves */
 FMOV FRm, FRn {:  
     COUNT_INST(I_FMOV1);
-    /* As horrible as this looks, it's actually covering 5 separate cases:
-     * 1. 32-bit fr-to-fr (PR=0)
-     * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )
-     * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )
-     * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )
-     * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )
-     */
     check_fpuen();
     load_spreg( R_ECX, R_FPSCR );
     TEST_imm32_r32( FPSCR_SZ, R_ECX );
     JNE_rel8(doublesize);
-    load_fr( R_EAX, FRm ); // PR=0 branch
+    load_fr( R_EAX, FRm ); // SZ=0 branch
     store_fr( R_EAX, FRn );
     JMP_rel8(end);
     JMP_TARGET(doublesize);
@@ -2495,14 +2488,14 @@
     sh4_x86.tstate = TSTATE_NONE;
 :}
 LDS Rm, FPSCR {:
-    COUNT_INST(I_LDS);
+    COUNT_INST(I_LDSFPSCR);
     check_fpuen();
     load_reg( R_EAX, Rm );
     call_func1( sh4_write_fpscr, R_EAX );
     sh4_x86.tstate = TSTATE_NONE;
 :}
 LDS.L @Rm+, FPSCR {:  
-    COUNT_INST(I_LDS);
+    COUNT_INST(I_LDSFPSCRM);
     check_fpuen();
     load_reg( R_EAX, Rm );
     check_ralign32( R_EAX );
@@ -2760,13 +2753,13 @@
     sh4_x86.tstate = TSTATE_NONE;
 :}
 STS FPSCR, Rn {:  
-    COUNT_INST(I_STS);
+    COUNT_INST(I_STSFPSCR);
     check_fpuen();
     load_spreg( R_EAX, R_FPSCR );
     store_reg( R_EAX, Rn );
 :}
 STS.L FPSCR, @-Rn {:  
-    COUNT_INST(I_STSM);
+    COUNT_INST(I_STSFPSCRM);
     check_fpuen();
     load_reg( R_EAX, Rn );
     check_walign32( R_EAX );