# HG changeset patch
# User nkeynes
# Date 1200813878 0
# Node ID 6118deafd70561dc115692492606914a9fd20ef2
# Parent  6c710c7c6835f4460aa810759e65cac8528d1c24
Fix broken asic_check_cleared_events()
Handle changes to the event mask which may raise/clear an IRQ

--- a/src/asic.c	Thu Jan 17 21:26:58 2008 +0000
+++ b/src/asic.c	Sun Jan 20 07:24:38 2008 +0000
@@ -247,7 +247,7 @@
 {
     int i, setA = 0, setB = 0, setC = 0;
     uint32_t bits;
-    for( i=0; i<3; i++ ) {
+    for( i=0; i<12; i+=4 ) {
 	bits = MMIO_READ( ASIC, PIRQ0 + i );
 	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
 	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
@@ -261,6 +261,30 @@
 	intc_clear_interrupt( INT_IRQ9 );
 }
 
+void asic_event_mask_changed( )
+{
+    int i, setA = 0, setB = 0, setC = 0;
+    uint32_t bits;
+    for( i=0; i<12; i+=4 ) {
+	bits = MMIO_READ( ASIC, PIRQ0 + i );
+	setA |= (bits & MMIO_READ(ASIC, IRQA0 + i ));
+	setB |= (bits & MMIO_READ(ASIC, IRQB0 + i ));
+	setC |= (bits & MMIO_READ(ASIC, IRQC0 + i ));
+    }
+    if( setA == 0 ) 
+	intc_clear_interrupt( INT_IRQ13 );
+    else
+	intc_raise_interrupt( INT_IRQ13 );
+    if( setB == 0 )
+	intc_clear_interrupt( INT_IRQ11 );
+    else
+	intc_raise_interrupt( INT_IRQ11 );
+    if( setC == 0 )
+	intc_clear_interrupt( INT_IRQ9 );
+    else
+	intc_raise_interrupt( INT_IRQ9 );
+}
+
 void g2_dma_transfer( int channel )
 {
     uint32_t offset = channel << 5;
@@ -345,6 +369,18 @@
 	}
 	asic_check_cleared_events();
 	break;
+    case IRQA0:
+    case IRQA1:
+    case IRQA2:
+    case IRQB0:
+    case IRQB1:
+    case IRQB2:
+    case IRQC0:
+    case IRQC1:
+    case IRQC2:
+	MMIO_WRITE( ASIC, reg, val );
+	asic_event_mask_changed();
+	break;
     case SYSRESET:
 	if( val == 0x7611 ) {
 	    dreamcast_reset();