# HG changeset patch
# User nkeynes
# Date 1219062028 0
# Node ID 866c103d72cda8d5c680672bd3231871aec7335f
# Parent  f1a21df54e19a07d77ce0084b7be8c4b7b753e7b
Implement memcpy_to_aica, still a work in progress though

--- a/test/Makefile.in	Mon Aug 18 12:18:10 2008 +0000
+++ b/test/Makefile.in	Mon Aug 18 12:20:28 2008 +0000
@@ -105,7 +105,7 @@
 	$(SH4CC) $(SH4LDFLAGS) $^  -o $@ $(SH4LIBS)
 	$(SH4OBJCOPY) testta testta.bin
 
-testaica: lib/crt0.so $(SHARED_OBJECTS) testaica.so dmac.so asic.so lib.so
+testaica: lib/crt0.so $(SHARED_OBJECTS) testaica.so dmac.so asic.so lib.so interrupt.so
 	$(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
 	$(SH4OBJCOPY) testaica testaica.bin
 
--- a/test/asic.c	Mon Aug 18 12:18:10 2008 +0000
+++ b/test/asic.c	Mon Aug 18 12:20:28 2008 +0000
@@ -23,6 +23,7 @@
 #define ASIC_IRQA(n) (ASIC_BASE + 0x910 + (n<<2))
 #define ASIC_IRQB(n) (ASIC_BASE + 0x920 + (n<<2))
 #define ASIC_IRQC(n) (ASIC_BASE + 0x930 + (n<<2))
+#define G2_FIFO  (ASIC_BASE + 0x88C)
 #define TIMEOUT 10000000
 
 /**
@@ -111,3 +112,18 @@
     }
     fprintf( f, "\n" );
 }
+
+/**
+ * Wait until the g2 fifo is clear to write more data.
+ */
+int g2_fifo_wait()
+{
+    int i;
+    for (i=0; i<0x1800; i++) {
+        if (!(long_read(G2_FIFO) & 0x11)) {
+            return 0;
+        }
+
+    }
+    return -1;
+}
\ No newline at end of file
--- a/test/asic.h	Mon Aug 18 12:18:10 2008 +0000
+++ b/test/asic.h	Mon Aug 18 12:20:28 2008 +0000
@@ -60,3 +60,8 @@
 void asic_dump( FILE *f );
 
 void asic_mask_all();
+
+/**
+ * Wait until the G2 FIFO buffer is clear to write
+ */
+int g2_fifo_wait();
--- a/test/dmac.c	Mon Aug 18 12:18:10 2008 +0000
+++ b/test/dmac.c	Mon Aug 18 12:20:28 2008 +0000
@@ -16,6 +16,7 @@
  * GNU General Public License for more details.
  */
 
+#include <assert.h>
 #include "dma.h"
 #include "asic.h"
 
@@ -40,7 +41,8 @@
 #define SORT_DMA_CTL   (ASIC_BASE+0x820)
 #define SORT_DMA_COUNT (ASIC_BASE+0x860)
 
-#define G2BASERAM 0x00800000
+#define AICA_RAM_BASE 0xA0800000
+#define AICA_RAM_SIZE 0x00200000
 
 #define G2DMABASE 0xA05F7800
 #define G2DMATIMEOUT (G2DMABASE+0x90)
@@ -203,3 +205,23 @@
 {
     return aica_dma_transfer( aica_addr, data, size, 0 );
 }
+
+int memcpy_to_aica( uint32_t aica_addr, void *data, size_t size )
+{
+    assert( (aica_addr & 0x03) == 0 );
+    uint32_t *src = (uint32_t *)data;
+    uint32_t *dest = (uint32_t *)aica_addr;
+    while( size > 0 ) {
+        int i;
+        if( g2_fifo_wait() != 0 ) {
+            return -1;
+        }
+        irq_disable();
+        for( i=0; i<8 && size > 0; i++ ) {
+            *dest++ = *src++;
+            size -= 4;
+        }
+        irq_enable();
+    }
+    return 0;
+}
--- a/test/interrupt.s	Mon Aug 18 12:18:10 2008 +0000
+++ b/test/interrupt.s	Mon Aug 18 12:20:28 2008 +0000
@@ -265,3 +265,35 @@
 handler_stack:
 	.skip 0x200
 handler_stack_end:	
+
+
+.globl  _irq_disable
+_irq_disable:
+        mov.l   _irqd_and,r1
+        mov.l   _irqd_or,r2
+        stc     sr,r0
+        and     r0,r1
+        or      r2,r1
+        ldc     r1,sr
+        rts
+        nop
+        
+        .align 2
+_irqd_and:
+        .long   0xefffff0f
+_irqd_or:
+        .long   0x000000f0
+
+
+.globl  _irq_enable
+_irq_enable:
+        mov.l   _irqe_and,r1
+        stc     sr,r0
+        and     r0,r1
+        ldc     r1,sr
+        rts
+        nop
+        
+        .align 2
+_irqe_and:
+        .long   0xefffff0f
--- a/test/lib.h	Mon Aug 18 12:18:10 2008 +0000
+++ b/test/lib.h	Mon Aug 18 12:20:28 2008 +0000
@@ -38,7 +38,6 @@
 void *align32(char *buf );
 void write_asic_status(void);
 void reset_asic_status(void);
-void g2_fifo_wait( void );
 
 #define aica_enable() long_write( AICA_RESET, (long_read(AICA_RESET) & 0xFFFFFFFE) )
 #define aica_disable()  long_write( AICA_RESET, (long_read(AICA_RESET) | 1) )