# HG changeset patch
# User nkeynes
# Date 1202429216 0
# Node ID a010e30a30e902a44d5bef7b2aa53bb87d589d59
# Parent  b13c97bf4071da80a66154b96f8325ea7e5b66db
Fix LDS/STS to FPUL/FPSCR to check the FPU disabled bit. Fixes
the linux 2.4.0-test8 kernel boot
(this wasn't exactly very well documented in the original manual)

--- a/src/sh4/sh4core.c	Thu Jan 31 09:50:41 2008 +0000
+++ b/src/sh4/sh4core.c	Fri Feb 08 00:06:56 2008 +0000
@@ -482,12 +482,14 @@
                             case 0x5:
                                 { /* STS FPUL, Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
+                                CHECKFPUEN();
                                 sh4r.r[Rn] = sh4r.fpul;
                                 }
                                 break;
                             case 0x6:
                                 { /* STS FPSCR, Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
+                                CHECKFPUEN();
                                 sh4r.r[Rn] = sh4r.fpscr;
                                 }
                                 break;
@@ -913,6 +915,7 @@
                             case 0x5:
                                 { /* STS.L FPUL, @-Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
+                                CHECKFPUEN();
                                 CHECKWALIGN32( sh4r.r[Rn] );
                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
                                 sh4r.r[Rn] -= 4;
@@ -921,6 +924,7 @@
                             case 0x6:
                                 { /* STS.L FPSCR, @-Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
+                                CHECKFPUEN();
                                 CHECKWALIGN32( sh4r.r[Rn] );
                                 MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
                                 sh4r.r[Rn] -= 4;
@@ -1100,6 +1104,7 @@
                             case 0x5:
                                 { /* LDS.L @Rm+, FPUL */
                                 uint32_t Rm = ((ir>>8)&0xF); 
+                                CHECKFPUEN();
                                 CHECKRALIGN32( sh4r.r[Rm] );
                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
                                 sh4r.r[Rm] +=4;
@@ -1108,6 +1113,7 @@
                             case 0x6:
                                 { /* LDS.L @Rm+, FPSCR */
                                 uint32_t Rm = ((ir>>8)&0xF); 
+                                CHECKFPUEN();
                                 CHECKRALIGN32( sh4r.r[Rm] );
                                 MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
                                 sh4r.r[Rm] +=4;
@@ -1276,12 +1282,14 @@
                             case 0x5:
                                 { /* LDS Rm, FPUL */
                                 uint32_t Rm = ((ir>>8)&0xF); 
+                                CHECKFPUEN();
                                 sh4r.fpul = sh4r.r[Rm];
                                 }
                                 break;
                             case 0x6:
                                 { /* LDS Rm, FPSCR */
                                 uint32_t Rm = ((ir>>8)&0xF); 
+                                CHECKFPUEN();
                                 sh4r.fpscr = sh4r.r[Rm]; 
                                 sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
                                 }
--- a/src/sh4/sh4core.in	Thu Jan 31 09:50:41 2008 +0000
+++ b/src/sh4/sh4core.in	Fri Feb 08 00:06:56 2008 +0000
@@ -851,31 +851,45 @@
     CHECKPRIV();
     sh4r.spc = sh4r.r[Rm];
 :}
-STS FPUL, Rn {: sh4r.r[Rn] = sh4r.fpul; :}
+STS FPUL, Rn {: 
+    CHECKFPUEN();
+    sh4r.r[Rn] = sh4r.fpul; 
+:}
 STS.L FPUL, @-Rn {:
+    CHECKFPUEN();
     CHECKWALIGN32( sh4r.r[Rn] );
     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpul );
     sh4r.r[Rn] -= 4;
 :}
 LDS.L @Rm+, FPUL {:
+    CHECKFPUEN();
     CHECKRALIGN32( sh4r.r[Rm] );
     MEM_READ_LONG(sh4r.r[Rm], sh4r.fpul);
     sh4r.r[Rm] +=4;
 :}
-LDS Rm, FPUL {: sh4r.fpul = sh4r.r[Rm]; :}
-STS FPSCR, Rn {: sh4r.r[Rn] = sh4r.fpscr; :}
+LDS Rm, FPUL {:
+    CHECKFPUEN();
+    sh4r.fpul = sh4r.r[Rm]; 
+:}
+STS FPSCR, Rn {: 
+    CHECKFPUEN();
+    sh4r.r[Rn] = sh4r.fpscr; 
+:}
 STS.L FPSCR, @-Rn {:
+    CHECKFPUEN();
     CHECKWALIGN32( sh4r.r[Rn] );
     MEM_WRITE_LONG( sh4r.r[Rn]-4, sh4r.fpscr );
     sh4r.r[Rn] -= 4;
 :}
 LDS.L @Rm+, FPSCR {:
+    CHECKFPUEN();
     CHECKRALIGN32( sh4r.r[Rm] );
     MEM_READ_LONG(sh4r.r[Rm], sh4r.fpscr);
     sh4r.r[Rm] +=4;
     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
 :}
 LDS Rm, FPSCR {: 
+    CHECKFPUEN();
     sh4r.fpscr = sh4r.r[Rm]; 
     sh4r.fr_bank = &sh4r.fr[(sh4r.fpscr&FPSCR_FR)>>21][0];
 :}
--- a/src/sh4/sh4x86.c	Thu Jan 31 09:50:41 2008 +0000
+++ b/src/sh4/sh4x86.c	Fri Feb 08 00:06:56 2008 +0000
@@ -761,6 +761,7 @@
                             case 0x5:
                                 { /* STS FPUL, Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
+                                check_fpuen();
                                 load_spreg( R_EAX, R_FPUL );
                                 store_reg( R_EAX, Rn );
                                 }
@@ -768,6 +769,7 @@
                             case 0x6:
                                 { /* STS FPSCR, Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
+                                check_fpuen();
                                 load_spreg( R_EAX, R_FPSCR );
                                 store_reg( R_EAX, Rn );
                                 }
@@ -1441,6 +1443,7 @@
                             case 0x5:
                                 { /* STS.L FPUL, @-Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
+                                check_fpuen();
                                 load_reg( R_EAX, Rn );
                                 check_walign32( R_EAX );
                                 ADD_imm8s_r32( -4, R_EAX );
@@ -1454,6 +1457,7 @@
                             case 0x6:
                                 { /* STS.L FPSCR, @-Rn */
                                 uint32_t Rn = ((ir>>8)&0xF); 
+                                check_fpuen();
                                 load_reg( R_EAX, Rn );
                                 check_walign32( R_EAX );
                                 ADD_imm8s_r32( -4, R_EAX );
@@ -1702,6 +1706,7 @@
                             case 0x5:
                                 { /* LDS.L @Rm+, FPUL */
                                 uint32_t Rm = ((ir>>8)&0xF); 
+                                check_fpuen();
                                 load_reg( R_EAX, Rm );
                                 check_ralign32( R_EAX );
                                 MMU_TRANSLATE_READ( R_EAX );
@@ -1714,6 +1719,7 @@
                             case 0x6:
                                 { /* LDS.L @Rm+, FPSCR */
                                 uint32_t Rm = ((ir>>8)&0xF); 
+                                check_fpuen();
                                 load_reg( R_EAX, Rm );
                                 check_ralign32( R_EAX );
                                 MMU_TRANSLATE_READ( R_EAX );
@@ -1939,6 +1945,7 @@
                             case 0x5:
                                 { /* LDS Rm, FPUL */
                                 uint32_t Rm = ((ir>>8)&0xF); 
+                                check_fpuen();
                                 load_reg( R_EAX, Rm );
                                 store_spreg( R_EAX, R_FPUL );
                                 }
@@ -1946,6 +1953,7 @@
                             case 0x6:
                                 { /* LDS Rm, FPSCR */
                                 uint32_t Rm = ((ir>>8)&0xF); 
+                                check_fpuen();
                                 load_reg( R_EAX, Rm );
                                 store_spreg( R_EAX, R_FPSCR );
                                 update_fr_bank( R_EAX );
--- a/src/sh4/sh4x86.in	Thu Jan 31 09:50:41 2008 +0000
+++ b/src/sh4/sh4x86.in	Fri Feb 08 00:06:56 2008 +0000
@@ -2487,13 +2487,15 @@
     store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
     sh4_x86.tstate = TSTATE_NONE;
 :}
-LDS Rm, FPSCR {:  
+LDS Rm, FPSCR {:
+    check_fpuen();
     load_reg( R_EAX, Rm );
     store_spreg( R_EAX, R_FPSCR );
     update_fr_bank( R_EAX );
     sh4_x86.tstate = TSTATE_NONE;
 :}
 LDS.L @Rm+, FPSCR {:  
+    check_fpuen();
     load_reg( R_EAX, Rm );
     check_ralign32( R_EAX );
     MMU_TRANSLATE_READ( R_EAX );
@@ -2504,10 +2506,12 @@
     sh4_x86.tstate = TSTATE_NONE;
 :}
 LDS Rm, FPUL {:  
+    check_fpuen();
     load_reg( R_EAX, Rm );
     store_spreg( R_EAX, R_FPUL );
 :}
 LDS.L @Rm+, FPUL {:  
+    check_fpuen();
     load_reg( R_EAX, Rm );
     check_ralign32( R_EAX );
     MMU_TRANSLATE_READ( R_EAX );
@@ -2716,10 +2720,12 @@
     sh4_x86.tstate = TSTATE_NONE;
 :}
 STS FPSCR, Rn {:  
+    check_fpuen();
     load_spreg( R_EAX, R_FPSCR );
     store_reg( R_EAX, Rn );
 :}
 STS.L FPSCR, @-Rn {:  
+    check_fpuen();
     load_reg( R_EAX, Rn );
     check_walign32( R_EAX );
     ADD_imm8s_r32( -4, R_EAX );
@@ -2730,10 +2736,12 @@
     sh4_x86.tstate = TSTATE_NONE;
 :}
 STS FPUL, Rn {:  
+    check_fpuen();
     load_spreg( R_EAX, R_FPUL );
     store_reg( R_EAX, Rn );
 :}
 STS.L FPUL, @-Rn {:  
+    check_fpuen();
     load_reg( R_EAX, Rn );
     check_walign32( R_EAX );
     ADD_imm8s_r32( -4, R_EAX );