# HG changeset patch # User nkeynes # Date 1196937810 0 # Node ID a27e31340147ad241f21c02ee1ff6c89e1833eff # Parent 828d103ad1158e20c55687ecd52338a338697a58 Add support for the MMIO side of the TLB (and LDTLB) --- a/src/Makefile.am Thu Dec 06 10:40:27 2007 +0000 +++ b/src/Makefile.am Thu Dec 06 10:43:30 2007 +0000 @@ -9,7 +9,10 @@ bin_PROGRAMS = lxdream noinst_PROGRAMS = gendec genglsl +check_PROGRAMS = test/testxlt +AM_CFLAGS = -D_ISOC99_SOURCE -D_BSD_SOURCE +TESTS = test/testxlt BUILT_SOURCES = sh4/sh4core.c sh4/sh4dasm.c sh4/sh4x86.c drivers/gl_slsrc.c gendec_SOURCES = tools/gendec.c tools/gendec.h tools/insparse.c tools/actparse.c @@ -24,7 +27,7 @@ gdrom/gdrom.c gdrom/gdrom.h gdrom/nrg.c gdrom/cdi.c gdrom/gdi.c \ dreamcast.c dreamcast.h eventq.c eventq.h \ sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \ - sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \ + sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \ sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \ sh4/xltcache.c sh4/xltcache.h \ aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \ @@ -46,6 +49,16 @@ sh4/sh4trans.c sh4/sh4trans.h \ x86dasm/x86dasm.c x86dasm/x86dasm.h \ x86dasm/i386-dis.c x86dasm/dis-init.c x86dasm/dis-buf.c + +test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \ + x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \ + x86dasm/dis-buf.c \ + sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \ + sh4/xltcache.h mem.c util.c +test_testsh4x86_LDADD = @GTK_LIBS@ + +check_PROGRAMS += test/testsh4x86 + endif if GUI_GTK @@ -72,21 +85,9 @@ gendec_LDADD = @GTK_LIBS@ $(INTLLIBS) genglsl_LDADD = @GTK_LIBS@ $(INTLLIBS) -TESTS = test/testxlt - -check_PROGRAMS = test/testxlt test/testsh4x86 test_testxlt_SOURCES = test/testxlt.c sh4/xltcache.c sh4/xltcache.h -test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \ - x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \ - x86dasm/dis-buf.c \ - sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \ - sh4/xltcache.h mem.c util.c -test_testsh4x86_LDADD = @PACKAGE_LIBS@ - -AM_CFLAGS = -D_ISOC99_SOURCE -D_BSD_SOURCE - sh4/sh4core.c: gendec sh4/sh4.def sh4/sh4core.in ./gendec sh4/sh4.def sh4/sh4core.in -o sh4/sh4core.c sh4/sh4dasm.c: gendec sh4/sh4.def sh4/sh4dasm.in --- a/src/Makefile.in Thu Dec 06 10:40:27 2007 +0000 +++ b/src/Makefile.in Thu Dec 06 10:43:30 2007 +0000 @@ -42,16 +42,17 @@ @BUILD_SH4X86_TRUE@ x86dasm/x86dasm.c x86dasm/x86dasm.h \ @BUILD_SH4X86_TRUE@ x86dasm/i386-dis.c x86dasm/dis-init.c x86dasm/dis-buf.c -@GUI_GTK_TRUE@am__append_2 = gtkui/gtkui.c gtkui/gtkui.h \ +@BUILD_SH4X86_TRUE@am__append_2 = test/testsh4x86 +@GUI_GTK_TRUE@am__append_3 = gtkui/gtkui.c gtkui/gtkui.h \ @GUI_GTK_TRUE@ gtkui/main_win.c gtkui/gtkcb.c \ @GUI_GTK_TRUE@ gtkui/mmio_win.c gtkui/debug_win.c gtkui/dump_win.c \ @GUI_GTK_TRUE@ gtkui/ctrl_dlg.c gtkui/path_dlg.c gtkui/gdrom_menu.c \ @GUI_GTK_TRUE@ drivers/video_gtk.c drivers/video_gtk.h \ @GUI_GTK_TRUE@ drivers/video_glx.c drivers/video_glx.h -@CDROM_LINUX_TRUE@am__append_3 = drivers/cd_linux.c -@CDROM_LINUX_FALSE@am__append_4 = drivers/cd_none.c -@AUDIO_ESOUND_TRUE@am__append_5 = drivers/audio_esd.c +@CDROM_LINUX_TRUE@am__append_4 = drivers/cd_linux.c +@CDROM_LINUX_FALSE@am__append_5 = drivers/cd_none.c +@AUDIO_ESOUND_TRUE@am__append_6 = drivers/audio_esd.c ACLOCAL = @ACLOCAL@ AMDEP_FALSE = @AMDEP_FALSE@ AMDEP_TRUE = @AMDEP_TRUE@ @@ -192,7 +193,10 @@ bin_PROGRAMS = lxdream noinst_PROGRAMS = gendec genglsl +check_PROGRAMS = test/testxlt $(am__append_2) +AM_CFLAGS = -D_ISOC99_SOURCE -D_BSD_SOURCE +TESTS = test/testxlt BUILT_SOURCES = sh4/sh4core.c sh4/sh4dasm.c sh4/sh4x86.c drivers/gl_slsrc.c gendec_SOURCES = tools/gendec.c tools/gendec.h tools/insparse.c tools/actparse.c @@ -207,7 +211,7 @@ gdrom/gdrom.c gdrom/gdrom.h gdrom/nrg.c gdrom/cdi.c gdrom/gdi.c \ dreamcast.c dreamcast.h eventq.c eventq.h \ sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \ - sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \ + sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \ sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \ sh4/xltcache.c sh4/xltcache.h \ aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \ @@ -222,35 +226,31 @@ drivers/audio_null.c drivers/video_null.c \ drivers/gl_common.c drivers/gl_common.h drivers/gl_fbo.c \ drivers/gl_sl.c drivers/gl_slsrc.c\ -$(am__append_1) $(am__append_2) $(am__append_3) $(am__append_4) $(am__append_5) +$(am__append_1) $(am__append_3) $(am__append_4) $(am__append_5) $(am__append_6) + +@BUILD_SH4X86_TRUE@test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \ +@BUILD_SH4X86_TRUE@ x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \ +@BUILD_SH4X86_TRUE@ x86dasm/dis-buf.c \ +@BUILD_SH4X86_TRUE@ sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \ +@BUILD_SH4X86_TRUE@ sh4/xltcache.h mem.c util.c + +@BUILD_SH4X86_TRUE@test_testsh4x86_LDADD = @GTK_LIBS@ lxdream_LDADD = @GTK_LIBS@ @LIBPNG_LIBS@ @ESOUND_LIBS@ $(INTLLIBS) gendec_LDADD = @GTK_LIBS@ $(INTLLIBS) genglsl_LDADD = @GTK_LIBS@ $(INTLLIBS) -TESTS = test/testxlt - -check_PROGRAMS = test/testxlt test/testsh4x86 - test_testxlt_SOURCES = test/testxlt.c sh4/xltcache.c sh4/xltcache.h - -test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \ - x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \ - x86dasm/dis-buf.c \ - sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \ - sh4/xltcache.h mem.c util.c - -test_testsh4x86_LDADD = @PACKAGE_LIBS@ - -AM_CFLAGS = -D_ISOC99_SOURCE -D_BSD_SOURCE subdir = src ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = bin_PROGRAMS = lxdream$(EXEEXT) -check_PROGRAMS = test/testxlt$(EXEEXT) test/testsh4x86$(EXEEXT) +@BUILD_SH4X86_TRUE@check_PROGRAMS = test/testxlt$(EXEEXT) \ +@BUILD_SH4X86_TRUE@ test/testsh4x86$(EXEEXT) +@BUILD_SH4X86_FALSE@check_PROGRAMS = test/testxlt$(EXEEXT) noinst_PROGRAMS = gendec$(EXEEXT) genglsl$(EXEEXT) PROGRAMS = $(bin_PROGRAMS) $(noinst_PROGRAMS) @@ -268,12 +268,12 @@ gdrom/ide.c gdrom/ide.h gdrom/packet.h gdrom/gdimage.c \ gdrom/gdrom.c gdrom/gdrom.h gdrom/nrg.c gdrom/cdi.c gdrom/gdi.c \ dreamcast.c dreamcast.h eventq.c eventq.h sh4/sh4.c sh4/intc.c \ - sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c sh4/sh4core.c \ - sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h sh4/sh4mmio.c \ - sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \ - sh4/xltcache.c sh4/xltcache.h aica/armcore.c aica/armcore.h \ - aica/armdasm.c aica/armmem.c aica/aica.c aica/aica.h \ - aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \ + sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c sh4/mmu.c \ + sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \ + sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c \ + sh4/sh4stat.h sh4/xltcache.c sh4/xltcache.h aica/armcore.c \ + aica/armcore.h aica/armdasm.c aica/armmem.c aica/aica.c \ + aica/aica.h aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \ pvr2/pvr2mem.c pvr2/tacore.c pvr2/render.c pvr2/rendcore.c \ pvr2/rendbkg.c pvr2/rendsort.c pvr2/texcache.c pvr2/yuv.c \ pvr2/rendsave.c maple/maple.c maple/maple.h maple/controller.c \ @@ -308,28 +308,35 @@ gdrom.$(OBJEXT) nrg.$(OBJEXT) cdi.$(OBJEXT) gdi.$(OBJEXT) \ dreamcast.$(OBJEXT) eventq.$(OBJEXT) sh4.$(OBJEXT) \ intc.$(OBJEXT) sh4mem.$(OBJEXT) timer.$(OBJEXT) dmac.$(OBJEXT) \ - sh4core.$(OBJEXT) sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) \ - scif.$(OBJEXT) sh4stat.$(OBJEXT) xltcache.$(OBJEXT) \ - armcore.$(OBJEXT) armdasm.$(OBJEXT) armmem.$(OBJEXT) \ - aica.$(OBJEXT) audio.$(OBJEXT) pvr2.$(OBJEXT) pvr2mem.$(OBJEXT) \ - tacore.$(OBJEXT) render.$(OBJEXT) rendcore.$(OBJEXT) \ - rendbkg.$(OBJEXT) rendsort.$(OBJEXT) texcache.$(OBJEXT) \ - yuv.$(OBJEXT) rendsave.$(OBJEXT) maple.$(OBJEXT) \ - controller.$(OBJEXT) loader.$(OBJEXT) bootstrap.$(OBJEXT) \ - util.$(OBJEXT) display.$(OBJEXT) audio_null.$(OBJEXT) \ - video_null.$(OBJEXT) gl_common.$(OBJEXT) gl_fbo.$(OBJEXT) \ - gl_sl.$(OBJEXT) gl_slsrc.$(OBJEXT) $(am__objects_1) \ - $(am__objects_2) $(am__objects_3) $(am__objects_4) \ - $(am__objects_5) + mmu.$(OBJEXT) sh4core.$(OBJEXT) sh4dasm.$(OBJEXT) \ + sh4mmio.$(OBJEXT) scif.$(OBJEXT) sh4stat.$(OBJEXT) \ + xltcache.$(OBJEXT) armcore.$(OBJEXT) armdasm.$(OBJEXT) \ + armmem.$(OBJEXT) aica.$(OBJEXT) audio.$(OBJEXT) pvr2.$(OBJEXT) \ + pvr2mem.$(OBJEXT) tacore.$(OBJEXT) render.$(OBJEXT) \ + rendcore.$(OBJEXT) rendbkg.$(OBJEXT) rendsort.$(OBJEXT) \ + texcache.$(OBJEXT) yuv.$(OBJEXT) rendsave.$(OBJEXT) \ + maple.$(OBJEXT) controller.$(OBJEXT) loader.$(OBJEXT) \ + bootstrap.$(OBJEXT) util.$(OBJEXT) display.$(OBJEXT) \ + audio_null.$(OBJEXT) video_null.$(OBJEXT) gl_common.$(OBJEXT) \ + gl_fbo.$(OBJEXT) gl_sl.$(OBJEXT) gl_slsrc.$(OBJEXT) \ + $(am__objects_1) $(am__objects_2) $(am__objects_3) \ + $(am__objects_4) $(am__objects_5) lxdream_OBJECTS = $(am_lxdream_OBJECTS) lxdream_DEPENDENCIES = lxdream_LDFLAGS = -am_test_testsh4x86_OBJECTS = testsh4x86.$(OBJEXT) x86dasm.$(OBJEXT) \ - i386-dis.$(OBJEXT) dis-init.$(OBJEXT) dis-buf.$(OBJEXT) \ - sh4dasm.$(OBJEXT) sh4trans.$(OBJEXT) sh4x86.$(OBJEXT) \ - xltcache.$(OBJEXT) mem.$(OBJEXT) util.$(OBJEXT) +am__test_testsh4x86_SOURCES_DIST = test/testsh4x86.c x86dasm/x86dasm.c \ + x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \ + x86dasm/dis-buf.c sh4/sh4dasm.c sh4/sh4trans.c sh4/sh4x86.c \ + sh4/xltcache.c sh4/xltcache.h mem.c util.c +@BUILD_SH4X86_TRUE@am_test_testsh4x86_OBJECTS = testsh4x86.$(OBJEXT) \ +@BUILD_SH4X86_TRUE@ x86dasm.$(OBJEXT) i386-dis.$(OBJEXT) \ +@BUILD_SH4X86_TRUE@ dis-init.$(OBJEXT) dis-buf.$(OBJEXT) \ +@BUILD_SH4X86_TRUE@ sh4dasm.$(OBJEXT) sh4trans.$(OBJEXT) \ +@BUILD_SH4X86_TRUE@ sh4x86.$(OBJEXT) xltcache.$(OBJEXT) \ +@BUILD_SH4X86_TRUE@ mem.$(OBJEXT) util.$(OBJEXT) test_testsh4x86_OBJECTS = $(am_test_testsh4x86_OBJECTS) -test_testsh4x86_DEPENDENCIES = +@BUILD_SH4X86_TRUE@test_testsh4x86_DEPENDENCIES = +@BUILD_SH4X86_FALSE@test_testsh4x86_DEPENDENCIES = test_testsh4x86_LDFLAGS = am__dirstamp = $(am__leading_dot)dirstamp am_test_testxlt_OBJECTS = testxlt.$(OBJEXT) xltcache.$(OBJEXT) @@ -365,28 +372,29 @@ @AMDEP_TRUE@ ./$(DEPDIR)/loader.Po ./$(DEPDIR)/main.Po \ @AMDEP_TRUE@ ./$(DEPDIR)/main_win.Po ./$(DEPDIR)/maple.Po \ @AMDEP_TRUE@ ./$(DEPDIR)/mem.Po ./$(DEPDIR)/mmio_win.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/nrg.Po ./$(DEPDIR)/path_dlg.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/pvr2.Po ./$(DEPDIR)/pvr2mem.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/rendbkg.Po ./$(DEPDIR)/rendcore.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/render.Po ./$(DEPDIR)/rendsave.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/rendsort.Po ./$(DEPDIR)/scif.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/sh4.Po ./$(DEPDIR)/sh4core.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/sh4dasm.Po ./$(DEPDIR)/sh4mem.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/sh4mmio.Po ./$(DEPDIR)/sh4stat.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/sh4trans.Po ./$(DEPDIR)/sh4x86.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/syscall.Po ./$(DEPDIR)/tacore.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/testsh4x86.Po ./$(DEPDIR)/testxlt.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/texcache.Po ./$(DEPDIR)/timer.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/util.Po ./$(DEPDIR)/video_glx.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/video_gtk.Po ./$(DEPDIR)/video_null.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/watch.Po ./$(DEPDIR)/x86dasm.Po \ -@AMDEP_TRUE@ ./$(DEPDIR)/xltcache.Po ./$(DEPDIR)/yuv.Po +@AMDEP_TRUE@ ./$(DEPDIR)/mmu.Po ./$(DEPDIR)/nrg.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/path_dlg.Po ./$(DEPDIR)/pvr2.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/pvr2mem.Po ./$(DEPDIR)/rendbkg.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/rendcore.Po ./$(DEPDIR)/render.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/rendsave.Po ./$(DEPDIR)/rendsort.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/scif.Po ./$(DEPDIR)/sh4.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/sh4core.Po ./$(DEPDIR)/sh4dasm.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/sh4mem.Po ./$(DEPDIR)/sh4mmio.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/sh4stat.Po ./$(DEPDIR)/sh4trans.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/sh4x86.Po ./$(DEPDIR)/syscall.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/tacore.Po ./$(DEPDIR)/testsh4x86.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/testxlt.Po ./$(DEPDIR)/texcache.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/timer.Po ./$(DEPDIR)/util.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/video_glx.Po ./$(DEPDIR)/video_gtk.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/video_null.Po ./$(DEPDIR)/watch.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/x86dasm.Po ./$(DEPDIR)/xltcache.Po \ +@AMDEP_TRUE@ ./$(DEPDIR)/yuv.Po COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) CCLD = $(CC) LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@ DIST_SOURCES = $(gendec_SOURCES) $(genglsl_SOURCES) \ - $(am__lxdream_SOURCES_DIST) $(test_testsh4x86_SOURCES) \ + $(am__lxdream_SOURCES_DIST) $(am__test_testsh4x86_SOURCES_DIST) \ $(test_testxlt_SOURCES) DIST_COMMON = $(srcdir)/Makefile.in Makefile.am SOURCES = $(gendec_SOURCES) $(genglsl_SOURCES) $(lxdream_SOURCES) $(test_testsh4x86_SOURCES) $(test_testxlt_SOURCES) @@ -504,6 +512,7 @@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/maple.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mem.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mmio_win.Po@am__quote@ +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/mmu.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/nrg.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/path_dlg.Po@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/pvr2.Po@am__quote@ @@ -889,6 +898,28 @@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o dmac.obj `if test -f 'sh4/dmac.c'; then $(CYGPATH_W) 'sh4/dmac.c'; else $(CYGPATH_W) '$(srcdir)/sh4/dmac.c'; fi` +mmu.o: sh4/mmu.c +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT mmu.o -MD -MP -MF "$(DEPDIR)/mmu.Tpo" \ +@am__fastdepCC_TRUE@ -c -o mmu.o `test -f 'sh4/mmu.c' || echo '$(srcdir)/'`sh4/mmu.c; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/mmu.Tpo" "$(DEPDIR)/mmu.Po"; \ +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/mmu.Tpo"; exit 1; \ +@am__fastdepCC_TRUE@ fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/mmu.c' object='mmu.o' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/mmu.Po' tmpdepfile='$(DEPDIR)/mmu.TPo' @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o mmu.o `test -f 'sh4/mmu.c' || echo '$(srcdir)/'`sh4/mmu.c + +mmu.obj: sh4/mmu.c +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT mmu.obj -MD -MP -MF "$(DEPDIR)/mmu.Tpo" \ +@am__fastdepCC_TRUE@ -c -o mmu.obj `if test -f 'sh4/mmu.c'; then $(CYGPATH_W) 'sh4/mmu.c'; else $(CYGPATH_W) '$(srcdir)/sh4/mmu.c'; fi`; \ +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/mmu.Tpo" "$(DEPDIR)/mmu.Po"; \ +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/mmu.Tpo"; exit 1; \ +@am__fastdepCC_TRUE@ fi +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/mmu.c' object='mmu.obj' libtool=no @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/mmu.Po' tmpdepfile='$(DEPDIR)/mmu.TPo' @AMDEPBACKSLASH@ +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o mmu.obj `if test -f 'sh4/mmu.c'; then $(CYGPATH_W) 'sh4/mmu.c'; else $(CYGPATH_W) '$(srcdir)/sh4/mmu.c'; fi` + sh4core.o: sh4/sh4core.c @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT sh4core.o -MD -MP -MF "$(DEPDIR)/sh4core.Tpo" \ @am__fastdepCC_TRUE@ -c -o sh4core.o `test -f 'sh4/sh4core.c' || echo '$(srcdir)/'`sh4/sh4core.c; \ --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/src/sh4/mmu.c Thu Dec 06 10:43:30 2007 +0000 @@ -0,0 +1,333 @@ +/** + * $Id: mmu.c,v 1.15 2007-11-08 11:54:16 nkeynes Exp $ + * + * MMU implementation + * + * Copyright (c) 2005 Nathan Keynes. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#define MODULE sh4_module + +#include +#include "sh4/sh4mmio.h" +#include "sh4/sh4core.h" +#include "mem.h" + +#define OCRAM_START (0x1C000000>>PAGE_BITS) +#define OCRAM_END (0x20000000>>PAGE_BITS) + +#define ITLB_ENTRY_COUNT 4 +#define UTLB_ENTRY_COUNT 64 + +/* Entry address */ +#define TLB_VALID 0x00000100 +#define TLB_USERMODE 0x00000040 +#define TLB_WRITABLE 0x00000020 +#define TLB_SIZE_MASK 0x00000090 +#define TLB_SIZE_1K 0x00000000 +#define TLB_SIZE_4K 0x00000010 +#define TLB_SIZE_64K 0x00000080 +#define TLB_SIZE_1M 0x00000090 +#define TLB_CACHEABLE 0x00000008 +#define TLB_DIRTY 0x00000004 +#define TLB_SHARE 0x00000002 +#define TLB_WRITETHRU 0x00000001 + + +struct itlb_entry { + sh4addr_t vpn; // Virtual Page Number + uint32_t asid; // Process ID + sh4addr_t ppn; // Physical Page Number + uint32_t flags; +}; + +struct utlb_entry { + sh4addr_t vpn; // Virtual Page Number + uint32_t asid; // Process ID + sh4addr_t ppn; // Physical Page Number + uint32_t flags; + uint32_t pcmcia; // extra pcmcia data - not used +}; + +static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT]; +static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT]; +static uint32_t mmu_urc; +static uint32_t mmu_urb; +static uint32_t mmu_lrui; + +static sh4ptr_t cache = NULL; + +static void mmu_invalidate_tlb(); + + +int32_t mmio_region_MMU_read( uint32_t reg ) +{ + switch( reg ) { + case MMUCR: + return MMIO_READ( MMU, MMUCR) | (mmu_urc<<10) | (mmu_urb<<18) | (mmu_lrui<<26); + default: + return MMIO_READ( MMU, reg ); + } +} + +void mmio_region_MMU_write( uint32_t reg, uint32_t val ) +{ + switch(reg) { + case PTEH: + val &= 0xFFFFFCFF; + break; + case PTEL: + val &= 0x1FFFFDFF; + break; + case PTEA: + val &= 0x0000000F; + break; + case MMUCR: + if( val & MMUCR_TI ) { + mmu_invalidate_tlb(); + } + mmu_urc = (val >> 10) & 0x3F; + mmu_urb = (val >> 18) & 0x3F; + mmu_lrui = (val >> 26) & 0x3F; + val &= 0x00000301; + break; + case CCR: + mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) ); + break; + default: + break; + } + MMIO_WRITE( MMU, reg, val ); +} + + +void MMU_init() +{ + cache = mem_alloc_pages(2); +} + +void MMU_reset() +{ + mmio_region_MMU_write( CCR, 0 ); +} + +void MMU_save_state( FILE *f ) +{ + fwrite( cache, 4096, 2, f ); + fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f ); + fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f ); +} + +int MMU_load_state( FILE *f ) +{ + /* Setup the cache mode according to the saved register value + * (mem_load runs before this point to load all MMIO data) + */ + mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) ); + if( fread( cache, 4096, 2, f ) != 2 ) { + return 1; + } + if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) { + return 1; + } + if( fread( &mmu_utlb, sizeof(mmu_utlb), 1, f ) != 1 ) { + return 1; + } + return 0; +} + +void mmu_set_cache_mode( int mode ) +{ + uint32_t i; + switch( mode ) { + case MEM_OC_INDEX0: /* OIX=0 */ + for( i=OCRAM_START; i>(25-PAGE_BITS)); + break; + default: /* disabled */ + for( i=OCRAM_START; i>7)&0x03) + +int32_t mmu_itlb_addr_read( sh4addr_t addr ) +{ + struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)]; + return ent->vpn | ent->asid | (ent->flags & TLB_VALID); +} +int32_t mmu_itlb_data_read( sh4addr_t addr ) +{ + struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)]; + return ent->ppn | ent->flags; +} + +void mmu_itlb_addr_write( sh4addr_t addr, uint32_t val ) +{ + struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)]; + ent->vpn = val & 0xFFFFFC00; + ent->asid = val & 0x000000FF; + ent->flags = (ent->flags & ~(TLB_VALID)) | (val&TLB_VALID); +} + +void mmu_itlb_data_write( sh4addr_t addr, uint32_t val ) +{ + struct itlb_entry *ent = &mmu_itlb[ITLB_ENTRY(addr)]; + ent->ppn = val & 0x1FFFFC00; + ent->flags = val & 0x00001DA; +} + +#define UTLB_ENTRY(addr) ((addr>>8)&0x3F) +#define UTLB_ASSOC(addr) (addr&0x80) +#define UTLB_DATA2(addr) (addr&0x00800000) + +int32_t mmu_utlb_addr_read( sh4addr_t addr ) +{ + struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)]; + return ent->vpn | ent->asid | (ent->flags & TLB_VALID) | + ((ent->flags & TLB_DIRTY)<<7); +} +int32_t mmu_utlb_data_read( sh4addr_t addr ) +{ + struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)]; + if( UTLB_DATA2(addr) ) { + return ent->pcmcia; + } else { + return ent->ppn | ent->flags; + } +} + +void mmu_utlb_addr_write( sh4addr_t addr, uint32_t val ) +{ + if( UTLB_ASSOC(addr) ) { + } else { + struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)]; + ent->vpn = (val & 0xFFFFFC00); + ent->asid = (val & 0xFF); + ent->flags = (ent->flags & ~(TLB_DIRTY|TLB_VALID)); + ent->flags |= (val & TLB_VALID); + ent->flags |= ((val & 0x200)>>7); + } +} + +void mmu_utlb_data_write( sh4addr_t addr, uint32_t val ) +{ + struct utlb_entry *ent = &mmu_utlb[UTLB_ENTRY(addr)]; + if( UTLB_DATA2(addr) ) { + ent->pcmcia = val & 0x0000000F; + } else { + ent->ppn = (val & 0x1FFFFC00); + ent->flags = (val & 0x000001FF); + } +} + +/* Cache access - not implemented */ + +int32_t mmu_icache_addr_read( sh4addr_t addr ) +{ + return 0; // not implemented +} +int32_t mmu_icache_data_read( sh4addr_t addr ) +{ + return 0; // not implemented +} +int32_t mmu_ocache_addr_read( sh4addr_t addr ) +{ + return 0; // not implemented +} +int32_t mmu_ocache_data_read( sh4addr_t addr ) +{ + return 0; // not implemented +} + +void mmu_icache_addr_write( sh4addr_t addr, uint32_t val ) +{ +} + +void mmu_icache_data_write( sh4addr_t addr, uint32_t val ) +{ +} + +void mmu_ocache_addr_write( sh4addr_t addr, uint32_t val ) +{ +} + +void mmu_ocache_data_write( sh4addr_t addr, uint32_t val ) +{ +} --- a/src/sh4/sh4core.c Thu Dec 06 10:40:27 2007 +0000 +++ b/src/sh4/sh4core.c Thu Dec 06 10:43:30 2007 +0000 @@ -1,5 +1,5 @@ /** - * $Id: sh4core.c,v 1.50 2007-11-04 08:49:18 nkeynes Exp $ + * $Id: sh4core.in,v 1.10 2007-11-04 08:49:18 nkeynes Exp $ * * SH4 emulation core, and parent module for all the SH4 peripheral * modules. @@ -417,7 +417,7 @@ break; case 0x3: { /* LDTLB */ - /* TODO */ + MMU_ldtlb(); } break; case 0x4: --- a/src/sh4/sh4core.h Thu Dec 06 10:40:27 2007 +0000 +++ b/src/sh4/sh4core.h Thu Dec 06 10:43:30 2007 +0000 @@ -151,6 +151,7 @@ void MMU_reset( void ); void MMU_save_state( FILE *f ); int MMU_load_state( FILE *f ); +void MMU_ldtlb(); void SCIF_update_line_speed(void); #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28) --- a/src/sh4/sh4core.in Thu Dec 06 10:40:27 2007 +0000 +++ b/src/sh4/sh4core.in Thu Dec 06 10:43:30 2007 +0000 @@ -336,7 +336,7 @@ CLRT {: sh4r.t = 0; :} SETT {: sh4r.t = 1; :} CLRMAC {: sh4r.mac = 0; :} -LDTLB {: /* TODO */ :} +LDTLB {: MMU_ldtlb(); :} CLRS {: sh4r.s = 0; :} SETS {: sh4r.s = 1; :} MOVT Rn {: sh4r.r[Rn] = sh4r.t; :} --- a/src/sh4/sh4mem.c Thu Dec 06 10:40:27 2007 +0000 +++ b/src/sh4/sh4mem.c Thu Dec 06 10:43:30 2007 +0000 @@ -17,6 +17,7 @@ */ #define MODULE sh4_module +#define ENABLE_TRACE_IO 1 #include #include @@ -73,12 +74,23 @@ { struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19]; if( !io ) { - if( (addr & 0xFF000000) != 0xF4000000 ) { - /* OC address cache isn't implemented, but don't complain about it. - * Complain about anything else though */ - WARN( "Attempted read from unknown P4 region: %08X", addr ); + switch( addr & 0x1F000000 ) { + case 0x00000000: case 0x01000000: case 0x02000000: case 0x03000000: + /* Store queue - readable? */ + return 0; + break; + case 0x10000000: return mmu_icache_addr_read( addr ); + case 0x11000000: return mmu_icache_data_read( addr ); + case 0x12000000: return mmu_itlb_addr_read( addr ); + case 0x13000000: return mmu_itlb_data_read( addr ); + case 0x14000000: return mmu_ocache_addr_read( addr ); + case 0x15000000: return mmu_ocache_data_read( addr ); + case 0x16000000: return mmu_utlb_addr_read( addr ); + case 0x17000000: return mmu_utlb_data_read( addr ); + default: + WARN( "Attempted read from unknown or invalid P4 region: %08X", addr ); + return 0; } - return 0; } else { int32_t val = io->io_read( addr&0xFFF ); TRACE_P4IO( "Long read %08X <= %08X", io, (addr&0xFFF), val, addr ); @@ -90,12 +102,20 @@ { struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19]; if( !io ) { - if( (addr & 0xFC000000) == 0xE0000000 ) { + switch( addr & 0x1F000000 ) { + case 0x00000000: case 0x01000000: case 0x02000000: case 0x03000000: /* Store queue */ SH4_WRITE_STORE_QUEUE( addr, val ); - } else if( (addr & 0xFF000000) != 0xF4000000 ) { - /* OC address cache isn't implemented, but don't complain about it. - * Complain about anything else though */ + break; + case 0x10000000: mmu_icache_addr_write( addr, val ); break; + case 0x11000000: mmu_icache_data_write( addr, val ); break; + case 0x12000000: mmu_itlb_addr_write( addr, val ); break; + case 0x13000000: mmu_itlb_data_write( addr, val ); break; + case 0x14000000: mmu_ocache_addr_write( addr, val ); break; + case 0x15000000: mmu_ocache_data_write( addr, val ); break; + case 0x16000000: mmu_utlb_addr_write( addr, val ); break; + case 0x17000000: mmu_utlb_data_write( addr, val ); break; + default: WARN( "Attempted write to unknown P4 region: %08X", addr ); } } else { --- a/src/sh4/sh4mmio.c Thu Dec 06 10:40:27 2007 +0000 +++ b/src/sh4/sh4mmio.c Thu Dec 06 10:43:30 2007 +0000 @@ -28,81 +28,6 @@ #define MMIO_IMPL #include "sh4/sh4mmio.h" -/********************************* MMU *************************************/ - -MMIO_REGION_READ_DEFFN( MMU ) - -#define OCRAM_START (0x1C000000>>PAGE_BITS) -#define OCRAM_END (0x20000000>>PAGE_BITS) - -static sh4ptr_t cache = NULL; - -void mmio_region_MMU_write( uint32_t reg, uint32_t val ) -{ - switch(reg) { - case MMUCR: - if( val & MMUCR_AT ) { - ERROR( "MMU Address translation not implemented!" ); - dreamcast_stop(); - } - break; - case CCR: - mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA) ); - break; - default: - break; - } - MMIO_WRITE( MMU, reg, val ); -} - - -void MMU_init() -{ - cache = mem_alloc_pages(2); -} - -void MMU_reset() -{ - mmio_region_MMU_write( CCR, 0 ); -} - -void MMU_save_state( FILE *f ) -{ - fwrite( cache, 4096, 2, f ); -} - -int MMU_load_state( FILE *f ) -{ - /* Setup the cache mode according to the saved register value - * (mem_load runs before this point to load all MMIO data) - */ - mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) ); - if( fread( cache, 4096, 2, f ) != 2 ) { - return 1; - } - return 0; -} - -void mmu_set_cache_mode( int mode ) -{ - uint32_t i; - switch( mode ) { - case MEM_OC_INDEX0: /* OIX=0 */ - for( i=OCRAM_START; i>(25-PAGE_BITS)); - break; - default: /* disabled */ - for( i=OCRAM_START; i +#include +#include "lib.h" + +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define PTEA 0xFF000034 + +#define ITLB_ADDR(entry) (0xF2000000 + (entry<<8)) +#define ITLB_DATA(entry) (0xF3000000 + (entry<<8)) +#define UTLB_ADDR(entry) (0xF6000000 + (entry<<8)) +#define UTLB_DATA1(entry) (0xF7000000 + (entry<<8)) +#define UTLB_DATA2(entry) (0xF7800000 + (entry<<8)) + +/* Bang on the mmio side of the TLBs to make sure the bits + * respond appropriately (with AT disabled so we don't risk + * doing a hard crash) */ +void test_tlb_mmio() +{ + int entry; + for( entry=0; entry<64; entry++ ) { + long_write( UTLB_DATA1(entry), 0 ); + long_write( UTLB_ADDR(entry), 0xFFFFFFFF ); + assert( long_read( UTLB_ADDR(entry) ) == 0xFFFFFFFF ); + assert( long_read( UTLB_DATA1(entry) ) == 0x00000104 ); + long_write( UTLB_ADDR(entry), 0x00000000 ); + assert( long_read( UTLB_ADDR(entry) ) == 0x00000000 ); + assert( long_read( UTLB_DATA1(entry) ) == 0x00000000 ); + long_write( UTLB_DATA1(entry), 0xFFFFFFFF ); + assert( long_read( UTLB_DATA1(entry) ) == 0x1FFFFDFF ); + assert( long_read( UTLB_ADDR(entry) ) == 0x00000300 ); + long_write( UTLB_DATA1(entry), 0x00000000 ); + assert( long_read( UTLB_DATA1(entry) ) == 0x00000000 ); + assert( long_read( UTLB_ADDR(entry) ) == 0x00000000 ); + long_write( UTLB_DATA2(entry), 0xFFFFFFFF ); + assert( long_read( UTLB_DATA2(entry) ) == 0x0000000F ); + long_write( UTLB_DATA2(entry), 0x00000000 ); + assert( long_read( UTLB_DATA2(entry) ) == 0x00000000 ); + } + + for( entry=0; entry<4; entry++ ) { + long_write( ITLB_DATA(entry), 0 ); + long_write( ITLB_ADDR(entry), 0xFFFFFFFF ); + assert( long_read( ITLB_ADDR(entry) ) == 0xFFFFFDFF ); + assert( long_read( ITLB_DATA(entry) ) == 0x00000100 ); + long_write( ITLB_ADDR(entry), 0x00000000 ); + assert( long_read( ITLB_ADDR(entry) ) == 0x00000000 ); + assert( long_read( ITLB_DATA(entry) ) == 0x00000000 ); + long_write( ITLB_DATA(entry), 0xFFFFFFFF ); + assert( long_read( ITLB_DATA(entry) ) == 0x1FFFFDDA ); + assert( long_read( ITLB_ADDR(entry) ) == 0x00000100 ); + long_write( ITLB_DATA(entry), 0x00000000 ); + assert( long_read( ITLB_DATA(entry) ) == 0x00000000 ); + assert( long_read( ITLB_ADDR(entry) ) == 0x00000000 ); + + } +} + +int main( int argc, char *argv[] ) +{ + test_tlb_mmio(); +}