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lxdream.org :: lxdream :: r92:108450d84ce8
lxdream 0.9.1
released Jun 29
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changeset92:108450d84ce8
parent91:61bb3ee00cf8
child93:bb1def61e901
authornkeynes
dateSun Feb 05 04:02:57 2006 +0000 (14 years ago)
Comment out some more info lines
src/sh4/sh4core.c
src/sh4/sh4mmio.c
1.1 --- a/src/sh4/sh4core.c Sun Feb 05 04:01:55 2006 +0000
1.2 +++ b/src/sh4/sh4core.c Sun Feb 05 04:02:57 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4core.c,v 1.18 2006-01-21 11:38:36 nkeynes Exp $
1.6 + * $Id: sh4core.c,v 1.19 2006-02-05 04:02:57 nkeynes Exp $
1.7 *
1.8 * SH4 emulation core, and parent module for all the SH4 peripheral
1.9 * modules.
1.10 @@ -288,7 +288,7 @@
1.11 MMIO_WRITE( MMU, INTEVT, code );
1.12 sh4r.pc = sh4r.vbr + 0x600;
1.13 sh4r.new_pc = sh4r.pc + 2;
1.14 - WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
1.15 + // WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
1.16 }
1.17
1.18 gboolean sh4_execute_instruction( void )
1.19 @@ -399,8 +399,9 @@
1.20 uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
1.21 uint32_t target = tmp&0x03FFFFE0 | hi;
1.22 mem_copy_to_sh4( target, src, 32 );
1.23 - // WARN( "Executed SQ%c => %08X",
1.24 - // (queue == 0 ? '0' : '1'), target );
1.25 + //if( (target &0xFF000000) != 0x04000000 )
1.26 + // WARN( "Executed SQ%c => %08X",
1.27 + // (queue == 0 ? '0' : '1'), target );
1.28 }
1.29 break;
1.30 case 9: /* OCBI [Rn] */
2.1 --- a/src/sh4/sh4mmio.c Sun Feb 05 04:01:55 2006 +0000
2.2 +++ b/src/sh4/sh4mmio.c Sun Feb 05 04:02:57 2006 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: sh4mmio.c,v 1.7 2006-01-01 08:08:40 nkeynes Exp $
2.6 + * $Id: sh4mmio.c,v 1.8 2006-02-05 04:02:57 nkeynes Exp $
2.7 *
2.8 * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
2.9 * responsible for including the IMPL side of the SH4 MMIO pages.
2.10 @@ -29,7 +29,7 @@
2.11
2.12 /********************************* MMU *************************************/
2.13
2.14 -MMIO_REGION_READ_STUBFN( MMU )
2.15 +MMIO_REGION_READ_DEFFN( MMU )
2.16
2.17 #define OCRAM_START (0x1C000000>>PAGE_BITS)
2.18 #define OCRAM_END (0x20000000>>PAGE_BITS)
.