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lxdream.org :: lxdream :: r305:1191085c5988
lxdream 0.9.1
released Jun 29
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changeset305:1191085c5988
parent304:2855cf8709a5
child306:818c11570593
authornkeynes
dateThu Jan 18 11:14:01 2007 +0000 (13 years ago)
Rearrange asic cascade events
src/asic.c
src/asic.h
src/pvr2/tacore.c
1.1 --- a/src/asic.c Thu Jan 18 11:13:12 2007 +0000
1.2 +++ b/src/asic.c Thu Jan 18 11:14:01 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.c,v 1.24 2007-01-17 21:27:20 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.25 2007-01-18 11:14:01 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA).
1.10 @@ -217,13 +217,27 @@
1.11 intc_raise_interrupt( INT_IRQ11 );
1.12 if( result & MMIO_READ(ASIC, IRQC0 + offset) )
1.13 intc_raise_interrupt( INT_IRQ9 );
1.14 +
1.15 + if( event >= 64 ) { /* Third word */
1.16 + asic_event( EVENT_CASCADE2 );
1.17 + } else if( event >= 32 ) { /* Second word */
1.18 + asic_event( EVENT_CASCADE1 );
1.19 + }
1.20 }
1.21
1.22 void asic_clear_event( int event ) {
1.23 int offset = ((event&0x60)>>3);
1.24 uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
1.25 MMIO_WRITE( ASIC, PIRQ0 + offset, result );
1.26 -
1.27 + if( result == 0 ) {
1.28 + /* clear cascades if necessary */
1.29 + if( event >= 64 ) {
1.30 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
1.31 + } else if( event >= 32 ) {
1.32 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0xBFFFFFFF );
1.33 + }
1.34 + }
1.35 +
1.36 asic_check_cleared_events();
1.37 }
1.38
1.39 @@ -297,12 +311,19 @@
1.40 {
1.41 switch( reg ) {
1.42 case PIRQ1:
1.43 - val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
1.44 - /* fallthrough */
1.45 + break; /* Treat this as read-only for the moment */
1.46 case PIRQ0:
1.47 + val = val & 0x3FFFFFFF; /* Top two bits aren't clearable */
1.48 + MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.49 + asic_check_cleared_events();
1.50 + break;
1.51 case PIRQ2:
1.52 - /* Clear any interrupts */
1.53 - MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.54 + /* Clear any events */
1.55 + val = MMIO_READ(ASIC, reg)&(~val);
1.56 + MMIO_WRITE( ASIC, reg, val );
1.57 + if( val == 0 ) { /* all clear - clear the cascade bit */
1.58 + MMIO_WRITE( ASIC, PIRQ0, MMIO_READ( ASIC, PIRQ0 ) & 0x7FFFFFFF );
1.59 + }
1.60 asic_check_cleared_events();
1.61 break;
1.62 case SYSRESET:
2.1 --- a/src/asic.h Thu Jan 18 11:13:12 2007 +0000
2.2 +++ b/src/asic.h Thu Jan 18 11:14:01 2007 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: asic.h,v 1.17 2007-01-17 21:27:20 nkeynes Exp $
2.6 + * $Id: asic.h,v 1.18 2007-01-18 11:14:01 nkeynes Exp $
2.7 *
2.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
2.9 * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions,
2.10 @@ -175,7 +175,7 @@
2.11 #define EVENT_PVR_RENDER_DONE 2
2.12 #define EVENT_SCANLINE2 3
2.13 #define EVENT_SCANLINE1 4
2.14 -#define EVENT_RETRACE 5
2.15 +#define EVENT_HPOS 5
2.16 #define EVENT_PVR_YUV_DONE 6
2.17 #define EVENT_PVR_OPAQUE_DONE 7
2.18 #define EVENT_PVR_OPAQUEMOD_DONE 8
2.19 @@ -190,8 +190,9 @@
2.20 #define EVENT_G2_DMA3 18
2.21 #define EVENT_PVR_DMA 19
2.22 #define EVENT_PVR_PUNCHOUT_DONE 21
2.23 +#define EVENT_CASCADE1 30 /* Set if something in the second word is active */
2.24 +#define EVENT_CASCADE2 31 /* Set if something in the third word is active */
2.25
2.26 -#define EVENT_TA_ERROR 31
2.27 #define EVENT_IDE 32
2.28 #define EVENT_AICA 33
2.29
3.1 --- a/src/pvr2/tacore.c Thu Jan 18 11:13:12 2007 +0000
3.2 +++ b/src/pvr2/tacore.c Thu Jan 18 11:14:01 2007 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: tacore.c,v 1.9 2006-08-18 12:43:24 nkeynes Exp $
3.6 + * $Id: tacore.c,v 1.10 2007-01-18 11:14:01 nkeynes Exp $
3.7 *
3.8 * PVR2 Tile Accelerator implementation
3.9 *
3.10 @@ -327,7 +327,6 @@
3.11 }
3.12
3.13 static void ta_bad_input_error() {
3.14 - asic_event( EVENT_TA_ERROR );
3.15 asic_event( EVENT_PVR_BAD_INPUT );
3.16 }
3.17
3.18 @@ -347,7 +346,6 @@
3.19 for( rv=0; rv < length; rv++ ) {
3.20 if( posn == end ) {
3.21 asic_event( EVENT_PVR_PRIM_ALLOC_FAIL );
3.22 - asic_event( EVENT_TA_ERROR );
3.23 // ta_status.state = STATE_ERROR;
3.24 break;
3.25 }
3.26 @@ -383,7 +381,6 @@
3.27 return TA_NO_ALLOC;
3.28 } else if( newposn <= limit ) {
3.29 } else if( newposn <= (limit + ta_status.tilelist_size) ) {
3.30 - asic_event( EVENT_TA_ERROR );
3.31 asic_event( EVENT_PVR_MATRIX_ALLOC_FAIL );
3.32 MMIO_WRITE( PVR2, TA_LISTPOS, newposn );
3.33 } else {
3.34 @@ -402,7 +399,6 @@
3.35 return TA_NO_ALLOC;
3.36 } else if( newposn >= limit ) {
3.37 } else if( newposn >= (limit - ta_status.tilelist_size) ) {
3.38 - asic_event( EVENT_TA_ERROR );
3.39 asic_event( EVENT_PVR_MATRIX_ALLOC_FAIL );
3.40 MMIO_WRITE( PVR2, TA_LISTPOS, newposn );
3.41 } else {
.