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revision 391:16afb90b5d47
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changeset391:16afb90b5d47
parent390:d066209999f1
child392:39e596b3b6dd
authornkeynes
dateTue Sep 18 09:14:20 2007 +0000 (16 years ago)
Add sh4_raise_trap() routine
Share the new fsca/ftrv code between core + trans
src/sh4/sh4core.cview | annotate | diff | log
src/sh4/sh4core.hview | annotate | diff | log
src/sh4/sh4core.inview | annotate | diff | log
     1.1 --- a/src/sh4/sh4core.c	Tue Sep 18 09:12:30 2007 +0000

     1.2 +++ b/src/sh4/sh4core.c	Tue Sep 18 09:14:20 2007 +0000

     1.3 @@ -1,5 +1,5 @@

     1.4  /**

     1.5 - * $Id: sh4core.c,v 1.46 2007-09-16 07:01:07 nkeynes Exp $

     1.6 + * $Id: sh4core.c,v 1.47 2007-09-18 09:14:20 nkeynes Exp $

     1.7   * 

     1.8   * SH4 emulation core, and parent module for all the SH4 peripheral

     1.9   * modules.

    1.10 @@ -42,8 +42,8 @@

    1.11  

    1.12  uint32_t sh4_run_slice( uint32_t );

    1.13  

    1.14 -static uint16_t *sh4_icache = NULL;

    1.15 -static uint32_t sh4_icache_addr = 0;

    1.16 +uint16_t *sh4_icache = NULL;

    1.17 +uint32_t sh4_icache_addr = 0;

    1.18  

    1.19  uint32_t sh4_run_slice( uint32_t nanosecs ) 

    1.20  {

    1.21 @@ -68,6 +68,7 @@

    1.22  		    sh4_accept_interrupt();

    1.23  		}

    1.24  	    }

    1.25 +	    //	    sh4_stats_add( sh4r.pc );

    1.26  	    if( !sh4_execute_instruction() ) {

    1.27  		break;

    1.28  	    }

    1.29 @@ -286,6 +287,12 @@

    1.30      RAISE( code, EXV_EXCEPTION );

    1.31  }

    1.32  

    1.33 +gboolean sh4_raise_trap( int trap )

    1.34 +{

    1.35 +    MMIO_WRITE( MMU, TRA, trap<<2 );

    1.36 +    return sh4_raise_exception( EXC_TRAP );

    1.37 +}

    1.38 +

    1.39  gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {

    1.40      if( sh4r.in_delay_slot ) {

    1.41  	return sh4_raise_exception(slot_code);

    1.42 @@ -2163,9 +2170,12 @@

    1.43                                          uint32_t FRn = ((ir>>9)&0x7)<<1; 

    1.44                                          CHECKFPUEN();

    1.45                                          if( !IS_FPU_DOUBLEPREC() ) {

    1.46 +                                    	sh4_fsca( FPULi, &(DRF(FRn>>1)) );

    1.47 +                                    	/*

    1.48                                              float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;

    1.49                                              FR(FRn) = sinf(angle);

    1.50                                              FR((FRn)+1) = cosf(angle);

    1.51 +                                    	*/

    1.52                                          }

    1.53                                          }

    1.54                                          break;

    1.55 @@ -2176,6 +2186,8 @@

    1.56                                                  uint32_t FVn = ((ir>>10)&0x3); 

    1.57                                                  CHECKFPUEN();

    1.58                                                  if( !IS_FPU_DOUBLEPREC() ) {

    1.59 +                                            	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);

    1.60 +                                            	/*

    1.61                                                      tmp = FVn<<2;

    1.62                                              	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];

    1.63                                                      float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };

    1.64 @@ -2187,6 +2199,7 @@

    1.65                                              	    xf[11]*fv[2] + xf[15]*fv[3];

    1.66                                                      FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +

    1.67                                              	    xf[10]*fv[2] + xf[14]*fv[3];

    1.68 +                                            	*/

    1.69                                                  }

    1.70                                                  }

    1.71                                                  break;

     2.1 --- a/src/sh4/sh4core.h	Tue Sep 18 09:12:30 2007 +0000

     2.2 +++ b/src/sh4/sh4core.h	Tue Sep 18 09:14:20 2007 +0000

     2.3 @@ -1,5 +1,5 @@

     2.4  /**

     2.5 - * $Id: sh4core.h,v 1.23 2007-09-12 09:20:38 nkeynes Exp $

     2.6 + * $Id: sh4core.h,v 1.24 2007-09-18 09:14:20 nkeynes Exp $

     2.7   * 

     2.8   * This file defines the internal functions exported/used by the SH4 core, 

     2.9   * except for disassembly functions defined in sh4dasm.h

    2.10 @@ -98,6 +98,7 @@

    2.11  

    2.12  gboolean sh4_execute_instruction( void );

    2.13  gboolean sh4_raise_exception( int );

    2.14 +gboolean sh4_raise_trap( int );

    2.15  gboolean sh4_raise_slot_exception( int, int );

    2.16  gboolean sh4_raise_tlb_exception( int );

    2.17  void sh4_set_breakpoint( uint32_t pc, int type );

     3.1 --- a/src/sh4/sh4core.in	Tue Sep 18 09:12:30 2007 +0000

     3.2 +++ b/src/sh4/sh4core.in	Tue Sep 18 09:14:20 2007 +0000

     3.3 @@ -1,5 +1,5 @@

     3.4  /**

     3.5 - * $Id: sh4core.in,v 1.6 2007-09-16 07:01:07 nkeynes Exp $

     3.6 + * $Id: sh4core.in,v 1.7 2007-09-18 09:14:20 nkeynes Exp $

     3.7   * 

     3.8   * SH4 emulation core, and parent module for all the SH4 peripheral

     3.9   * modules.

    3.10 @@ -42,8 +42,8 @@

    3.11  

    3.12  uint32_t sh4_run_slice( uint32_t );

    3.13  

    3.14 -static uint16_t *sh4_icache = NULL;

    3.15 -static uint32_t sh4_icache_addr = 0;

    3.16 +uint16_t *sh4_icache = NULL;

    3.17 +uint32_t sh4_icache_addr = 0;

    3.18  

    3.19  uint32_t sh4_run_slice( uint32_t nanosecs ) 

    3.20  {

    3.21 @@ -68,6 +68,7 @@

    3.22  		    sh4_accept_interrupt();

    3.23  		}

    3.24  	    }

    3.25 +	    //	    sh4_stats_add( sh4r.pc );

    3.26  	    if( !sh4_execute_instruction() ) {

    3.27  		break;

    3.28  	    }

    3.29 @@ -286,6 +287,12 @@

    3.30      RAISE( code, EXV_EXCEPTION );

    3.31  }

    3.32  

    3.33 +gboolean sh4_raise_trap( int trap )

    3.34 +{

    3.35 +    MMIO_WRITE( MMU, TRA, trap<<2 );

    3.36 +    return sh4_raise_exception( EXC_TRAP );

    3.37 +}

    3.38 +

    3.39  gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {

    3.40      if( sh4r.in_delay_slot ) {

    3.41  	return sh4_raise_exception(slot_code);

    3.42 @@ -1204,14 +1211,19 @@

    3.43  FSCA FPUL, FRn {:

    3.44      CHECKFPUEN();

    3.45      if( !IS_FPU_DOUBLEPREC() ) {

    3.46 +	sh4_fsca( FPULi, &(DRF(FRn>>1)) );

    3.47 +	/*

    3.48          float angle = (((float)(FPULi&0xFFFF))/65536.0) * 2 * M_PI;

    3.49          FR(FRn) = sinf(angle);

    3.50          FR((FRn)+1) = cosf(angle);

    3.51 +	*/

    3.52      }

    3.53  :}

    3.54  FTRV XMTRX, FVn {:

    3.55      CHECKFPUEN();

    3.56      if( !IS_FPU_DOUBLEPREC() ) {

    3.57 +	sh4_ftrv(&(DRF(FVn<<1)), &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0]);

    3.58 +	/*

    3.59          tmp = FVn<<2;

    3.60  	float *xf = &sh4r.fr[((~sh4r.fpscr)&FPSCR_FR)>>21][0];

    3.61          float fv[4] = { FR(tmp), FR(tmp+1), FR(tmp+2), FR(tmp+3) };

    3.62 @@ -1223,6 +1235,7 @@

    3.63  	    xf[11]*fv[2] + xf[15]*fv[3];

    3.64          FR(tmp+3) = xf[2] * fv[0] + xf[6]*fv[1] +

    3.65  	    xf[10]*fv[2] + xf[14]*fv[3];

    3.66 +	*/

    3.67      }

    3.68  :}

    3.69  UNDEF {:
.