1.1 --- a/src/Makefile.am	Thu Dec 22 13:57:26 2005 +0000
     1.2 +++ b/src/Makefile.am	Fri Dec 23 11:44:55 2005 +0000
     1.3 @@ -18,7 +18,7 @@
     1.4          asic.c asic.h pvr2.c pvr2.h ide.c ide.h \
     1.5          video.c dreamcast.c dreamcast.h \
     1.6          maple.c maple.h maple/controller.c maple/controller.h \
     1.7 -        sh4/intc.c sh4/intc.h sh4/sh4mem.c \
     1.8 +        sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c \
     1.9          sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
    1.10          sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/watch.c \
    1.11          aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \

     2.1 --- a/src/Makefile.in	Thu Dec 22 13:57:26 2005 +0000
     2.2 +++ b/src/Makefile.in	Fri Dec 23 11:44:55 2005 +0000
     2.3 @@ -145,7 +145,7 @@
     2.4          asic.c asic.h pvr2.c pvr2.h ide.c ide.h \
     2.5          video.c dreamcast.c dreamcast.h \
     2.6          maple.c maple.h maple/controller.c maple/controller.h \
     2.7 -        sh4/intc.c sh4/intc.h sh4/sh4mem.c \
     2.8 +        sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c \
     2.9          sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
    2.10          sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/watch.c \
    2.11          aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \
    2.12 @@ -169,11 +169,11 @@
    2.13  	debug_win.$(OBJEXT) dump_win.$(OBJEXT) mem.$(OBJEXT) \
    2.14  	asic.$(OBJEXT) pvr2.$(OBJEXT) ide.$(OBJEXT) video.$(OBJEXT) \
    2.15  	dreamcast.$(OBJEXT) maple.$(OBJEXT) controller.$(OBJEXT) \
    2.16 -	intc.$(OBJEXT) sh4mem.$(OBJEXT) sh4core.$(OBJEXT) \
    2.17 -	sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) scif.$(OBJEXT) \
    2.18 -	watch.$(OBJEXT) armcore.$(OBJEXT) armdasm.$(OBJEXT) \
    2.19 -	armmem.$(OBJEXT) aica.$(OBJEXT) fileio.$(OBJEXT) \
    2.20 -	ipbin.$(OBJEXT) util.$(OBJEXT)
    2.21 +	intc.$(OBJEXT) sh4mem.$(OBJEXT) timer.$(OBJEXT) \
    2.22 +	sh4core.$(OBJEXT) sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) \
    2.23 +	scif.$(OBJEXT) watch.$(OBJEXT) armcore.$(OBJEXT) \
    2.24 +	armdasm.$(OBJEXT) armmem.$(OBJEXT) aica.$(OBJEXT) \
    2.25 +	fileio.$(OBJEXT) ipbin.$(OBJEXT) util.$(OBJEXT)
    2.26  dream_OBJECTS = $(am_dream_OBJECTS)
    2.27  dream_DEPENDENCIES =
    2.28  dream_LDFLAGS =
    2.29 @@ -194,8 +194,9 @@
    2.30  @AMDEP_TRUE@	./$(DEPDIR)/pvr2.Po ./$(DEPDIR)/scif.Po \
    2.31  @AMDEP_TRUE@	./$(DEPDIR)/sh4core.Po ./$(DEPDIR)/sh4dasm.Po \
    2.32  @AMDEP_TRUE@	./$(DEPDIR)/sh4mem.Po ./$(DEPDIR)/sh4mmio.Po \
    2.33 -@AMDEP_TRUE@	./$(DEPDIR)/support.Po ./$(DEPDIR)/util.Po \
    2.34 -@AMDEP_TRUE@	./$(DEPDIR)/video.Po ./$(DEPDIR)/watch.Po
    2.35 +@AMDEP_TRUE@	./$(DEPDIR)/support.Po ./$(DEPDIR)/timer.Po \
    2.36 +@AMDEP_TRUE@	./$(DEPDIR)/util.Po ./$(DEPDIR)/video.Po \
    2.37 +@AMDEP_TRUE@	./$(DEPDIR)/watch.Po
    2.38  COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \
    2.39  	$(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)
    2.40  CCLD = $(CC)
    2.41 @@ -274,6 +275,7 @@
    2.42  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4mem.Po@am__quote@
    2.43  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4mmio.Po@am__quote@
    2.44  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/support.Po@am__quote@
    2.45 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/timer.Po@am__quote@
    2.46  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/util.Po@am__quote@
    2.47  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/video.Po@am__quote@
    2.48  @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/watch.Po@am__quote@
    2.49 @@ -366,6 +368,28 @@
    2.50  @AMDEP_TRUE@@am__fastdepCC_FALSE@	$(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
    2.51  @am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o sh4mem.obj `if test -f 'sh4/sh4mem.c'; then $(CYGPATH_W) 'sh4/sh4mem.c'; else $(CYGPATH_W) '$(srcdir)/sh4/sh4mem.c'; fi`
    2.52  
    2.53 +timer.o: sh4/timer.c
    2.54 +@am__fastdepCC_TRUE@	if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT timer.o -MD -MP -MF "$(DEPDIR)/timer.Tpo" \
    2.55 +@am__fastdepCC_TRUE@	  -c -o timer.o `test -f 'sh4/timer.c' || echo '$(srcdir)/'`sh4/timer.c; \
    2.56 +@am__fastdepCC_TRUE@	then mv -f "$(DEPDIR)/timer.Tpo" "$(DEPDIR)/timer.Po"; \
    2.57 +@am__fastdepCC_TRUE@	else rm -f "$(DEPDIR)/timer.Tpo"; exit 1; \
    2.58 +@am__fastdepCC_TRUE@	fi
    2.59 +@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='sh4/timer.c' object='timer.o' libtool=no @AMDEPBACKSLASH@
    2.60 +@AMDEP_TRUE@@am__fastdepCC_FALSE@	depfile='$(DEPDIR)/timer.Po' tmpdepfile='$(DEPDIR)/timer.TPo' @AMDEPBACKSLASH@
    2.61 +@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
    2.62 +@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o timer.o `test -f 'sh4/timer.c' || echo '$(srcdir)/'`sh4/timer.c
    2.63 +
    2.64 +timer.obj: sh4/timer.c
    2.65 +@am__fastdepCC_TRUE@	if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT timer.obj -MD -MP -MF "$(DEPDIR)/timer.Tpo" \
    2.66 +@am__fastdepCC_TRUE@	  -c -o timer.obj `if test -f 'sh4/timer.c'; then $(CYGPATH_W) 'sh4/timer.c'; else $(CYGPATH_W) '$(srcdir)/sh4/timer.c'; fi`; \
    2.67 +@am__fastdepCC_TRUE@	then mv -f "$(DEPDIR)/timer.Tpo" "$(DEPDIR)/timer.Po"; \
    2.68 +@am__fastdepCC_TRUE@	else rm -f "$(DEPDIR)/timer.Tpo"; exit 1; \
    2.69 +@am__fastdepCC_TRUE@	fi
    2.70 +@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='sh4/timer.c' object='timer.obj' libtool=no @AMDEPBACKSLASH@
    2.71 +@AMDEP_TRUE@@am__fastdepCC_FALSE@	depfile='$(DEPDIR)/timer.Po' tmpdepfile='$(DEPDIR)/timer.TPo' @AMDEPBACKSLASH@
    2.72 +@AMDEP_TRUE@@am__fastdepCC_FALSE@	$(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
    2.73 +@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o timer.obj `if test -f 'sh4/timer.c'; then $(CYGPATH_W) 'sh4/timer.c'; else $(CYGPATH_W) '$(srcdir)/sh4/timer.c'; fi`
    2.74 +
    2.75  sh4core.o: sh4/sh4core.c
    2.76  @am__fastdepCC_TRUE@	if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT sh4core.o -MD -MP -MF "$(DEPDIR)/sh4core.Tpo" \
    2.77  @am__fastdepCC_TRUE@	  -c -o sh4core.o `test -f 'sh4/sh4core.c' || echo '$(srcdir)/'`sh4/sh4core.c; \

     3.1 --- a/src/aica/aica.c	Thu Dec 22 13:57:26 2005 +0000
     3.2 +++ b/src/aica/aica.c	Fri Dec 23 11:44:55 2005 +0000
     3.3 @@ -1,5 +1,5 @@
     3.4  /**
     3.5 - * $Id: aica.c,v 1.3 2005-12-13 12:17:26 nkeynes Exp $
     3.6 + * $Id: aica.c,v 1.4 2005-12-23 11:44:55 nkeynes Exp $
     3.7   * 
     3.8   * This is the core sound system (ie the bit which does the actual work)
     3.9   *
    3.10 @@ -27,8 +27,16 @@
    3.11  MMIO_REGION_READ_DEFFN( AICA1 )
    3.12  MMIO_REGION_READ_DEFFN( AICA2 )
    3.13  
    3.14 -struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset, NULL, NULL,
    3.15 -					NULL, NULL };
    3.16 +void aica_init( void );
    3.17 +void aica_reset( void );
    3.18 +void aica_start( void );
    3.19 +void aica_stop( void );
    3.20 +void aica_run_slice( int );
    3.21 +
    3.22 +
    3.23 +struct dreamcast_module aica_module = { "AICA", aica_init, aica_reset, 
    3.24 +					aica_start, aica_run_slice, aica_stop,
    3.25 +					NULL, NULL, NULL };
    3.26  
    3.27  /**
    3.28   * Initialize the AICA subsystem. Note requires that 
    3.29 @@ -46,6 +54,22 @@
    3.30  
    3.31  }
    3.32  
    3.33 +void aica_start( void )
    3.34 +{
    3.35 +
    3.36 +}
    3.37 +
    3.38 +void aica_run_slice( int microsecs )
    3.39 +{
    3.40 +    /* Run arm instructions */
    3.41 +    /* Generate audio buffer */
    3.42 +}
    3.43 +
    3.44 +void aica_stop( void )
    3.45 +{
    3.46 +
    3.47 +}
    3.48 +
    3.49  /** Channel register structure:
    3.50   * 00
    3.51   * 04

     4.1 --- a/src/asic.c	Thu Dec 22 13:57:26 2005 +0000
     4.2 +++ b/src/asic.c	Fri Dec 23 11:44:55 2005 +0000
     4.3 @@ -20,7 +20,7 @@
     4.4   */
     4.5  
     4.6  struct dreamcast_module asic_module = { "ASIC", asic_init, NULL, NULL, NULL,
     4.7 -					NULL, NULL };
     4.8 +					NULL, NULL, NULL };
     4.9  
    4.10  void asic_check_cleared_events( void );
    4.11  

     5.1 --- a/src/clock.h	Thu Dec 22 13:57:26 2005 +0000
     5.2 +++ b/src/clock.h	Fri Dec 23 11:44:55 2005 +0000
     5.3 @@ -1,5 +1,5 @@
     5.4  /**
     5.5 - * $Id: clock.h,v 1.1 2005-12-22 07:38:06 nkeynes Exp $
     5.6 + * $Id: clock.h,v 1.2 2005-12-23 11:44:50 nkeynes Exp $
     5.7   * External interface to the dreamcast serial port, implemented by 
     5.8   * sh4/scif.c
     5.9   *
    5.10 @@ -24,15 +24,14 @@
    5.11  extern "C" {
    5.12  #endif
    5.13  
    5.14 -#define MHZ * 1000000
    5.15 -
    5.16 +#define MHZ
    5.17  #define SH4_BASE_RATE 200 MHZ
    5.18  #define ARM_BASE_RATE 33 MHZ
    5.19  
    5.20 -    extern uint32_t sh4_freq;
    5.21 -    extern uint32_t sh4_peripheral_freq;
    5.22 -    extern uint32_t sh4_bus_freq;
    5.23 -    extern uint32_t arm_freq;
    5.24 +extern uint32_t sh4_freq;
    5.25 +extern uint32_t sh4_peripheral_freq;
    5.26 +extern uint32_t sh4_bus_freq;
    5.27 +extern uint32_t arm_freq;
    5.28  
    5.29  #ifdef __cplusplus
    5.30  }

     6.1 --- a/src/dreamcast.c	Thu Dec 22 13:57:26 2005 +0000
     6.2 +++ b/src/dreamcast.c	Fri Dec 23 11:44:55 2005 +0000
     6.3 @@ -16,6 +16,13 @@
     6.4  static char *dreamcast_config = "DEFAULT";
     6.5  dreamcast_module_t modules[MAX_MODULES];
     6.6  
     6.7 +struct save_state_header {
     6.8 +    char magic[16];
     6.9 +    uint32_t version;
    6.10 +    uint32_t module_count;
    6.11 +};
    6.12 +
    6.13 +
    6.14  /**
    6.15   * This function is responsible for defining how all the pieces of the
    6.16   * dreamcast actually fit together. Among other things, this lets us
    6.17 @@ -64,6 +71,7 @@
    6.18  void dreamcast_init( void )
    6.19  {
    6.20      dreamcast_configure();
    6.21 +    dreamcast_state = STATE_STOPPED;
    6.22  }
    6.23  
    6.24  void dreamcast_reset( void )
    6.25 @@ -75,29 +83,37 @@
    6.26      }
    6.27  }
    6.28  
    6.29 -void dreamcast_start( void )
    6.30 +void dreamcast_run( void )
    6.31  {
    6.32      int i;
    6.33 -    for( i=0; i<num_modules; i++ ) {
    6.34 -	if( modules[i]->start != NULL )
    6.35 -	    modules[i]->start();
    6.36 +    if( dreamcast_state != STATE_RUNNING ) {
    6.37 +	for( i=0; i<num_modules; i++ ) {
    6.38 +	    if( modules[i]->start != NULL )
    6.39 +		modules[i]->start();
    6.40 +	}
    6.41      }
    6.42 -}
    6.43 -void dreamcast_stop( void )
    6.44 -{
    6.45 -    int i;
    6.46 +    dreamcast_state = STATE_RUNNING;
    6.47 +    while( dreamcast_state == STATE_RUNNING ) {
    6.48 +	for( i=0; i<num_modules; i++ ) {
    6.49 +	    if( modules[i]->run_time_slice != NULL )
    6.50 +		modules[i]->run_time_slice( TIMESLICE_LENGTH );
    6.51 +	}
    6.52 +
    6.53 +    }
    6.54 +
    6.55      for( i=0; i<num_modules; i++ ) {
    6.56  	if( modules[i]->stop != NULL )
    6.57  	    modules[i]->stop();
    6.58      }
    6.59 +    dreamcast_state = STATE_STOPPED;
    6.60 +    update_gui();
    6.61  }
    6.62  
    6.63 -struct save_state_header {
    6.64 -    char magic[16];
    6.65 -    uint32_t version;
    6.66 -    uint32_t module_count;
    6.67 -};
    6.68 -
    6.69 +void dreamcast_stop( void )
    6.70 +{
    6.71 +    if( dreamcast_state == STATE_RUNNING )
    6.72 +	dreamcast_state = STATE_STOPPING;
    6.73 +}
    6.74  
    6.75  int dreamcast_load_state( const gchar *filename )
    6.76  {

     7.1 --- a/src/dreamcast.h	Thu Dec 22 13:57:26 2005 +0000
     7.2 +++ b/src/dreamcast.h	Fri Dec 23 11:44:55 2005 +0000
     7.3 @@ -10,13 +10,20 @@
     7.4  extern "C" {
     7.5  #endif
     7.6  
     7.7 +#define DREAMCAST_SAVE_MAGIC "%!-DreamOn!Save\0"
     7.8 +#define DREAMCAST_SAVE_VERSION 0x00010000
     7.9 +
    7.10 +#define TIMESLICE_LENGTH 1000 /* microseconds */
    7.11 +
    7.12 +#define STATE_RUNNING 1
    7.13 +#define STATE_STOPPING 2
    7.14 +#define STATE_STOPPED 3 
    7.15 +
    7.16  void dreamcast_init(void);
    7.17  void dreamcast_reset(void);
    7.18 +void dreamcast_run(void);
    7.19  void dreamcast_stop(void);
    7.20  
    7.21 -#define DREAMCAST_SAVE_MAGIC "%!-DreamOn!Save\0"
    7.22 -#define DREAMCAST_SAVE_VERSION 0x00010000
    7.23 -
    7.24  int dreamcast_save_state( const gchar *filename );
    7.25  int dreamcast_load_state( const gchar *filename );
    7.26  

     8.1 --- a/src/gdrom/ide.c	Thu Dec 22 13:57:26 2005 +0000
     8.2 +++ b/src/gdrom/ide.c	Fri Dec 23 11:44:55 2005 +0000
     8.3 @@ -14,7 +14,7 @@
     8.4  void ide_init( void );
     8.5  
     8.6  struct dreamcast_module ide_module = { "IDE", ide_init, ide_reset, NULL, NULL,
     8.7 -				       NULL, NULL };
     8.8 +				       NULL, NULL, NULL };
     8.9  
    8.10  struct ide_registers idereg;
    8.11  

     9.1 --- a/src/gui/callbacks.c	Thu Dec 22 13:57:26 2005 +0000
     9.2 +++ b/src/gui/callbacks.c	Fri Dec 23 11:44:55 2005 +0000
     9.3 @@ -107,29 +107,12 @@
     9.4  }
     9.5  
     9.6  
     9.7 -void run( debug_info_t data, uint32_t target ) {
     9.8 -    if( ! sh4_isrunning() ) {
     9.9 -        do {
    9.10 -            if( target == -1 )
    9.11 -                sh4_runfor(1000000);
    9.12 -            else
    9.13 -                sh4_runto(target, 1000000);
    9.14 -            update_icount(data);
    9.15 -            run_timers(1000000);
    9.16 -	    SCIF_clock_tick();
    9.17 -            while( gtk_events_pending() )
    9.18 -                gtk_main_iteration();
    9.19 -            pvr2_next_frame();
    9.20 -        } while( sh4_isrunning() );
    9.21 -        update_gui();
    9.22 -    }    
    9.23 -}
    9.24  void
    9.25  on_run_btn_clicked                     (GtkButton       *button,
    9.26                                          gpointer         user_data)
    9.27  {
    9.28      debug_info_t data = get_debug_info(GTK_WIDGET(button));
    9.29 -    run(data,-1);
    9.30 +    dreamcast_run();
    9.31  }
    9.32  
    9.33  
    9.34 @@ -142,7 +125,8 @@
    9.35          WARN( "No address selected, so can't run to it", NULL );
    9.36      else {
    9.37          INFO( "Running until %08X...", selected_pc );
    9.38 -        run( data, selected_pc );
    9.39 +	sh4_set_breakpoint( selected_pc, BREAK_ONESHOT );
    9.40 +	dreamcast_run();
    9.41      }
    9.42  }
    9.43  

    10.1 --- a/src/gui/gui.c	Thu Dec 22 13:57:26 2005 +0000
    10.2 +++ b/src/gui/gui.c	Fri Dec 23 11:44:55 2005 +0000
    10.3 @@ -43,6 +43,13 @@
    10.4      fixed_list_font = pango_font_description_from_string("Courier 10");
    10.5  }
    10.6  
    10.7 +void gui_run_slice( int millisecs ) 
    10.8 +{
    10.9 +    while( gtk_events_pending() )
   10.10 +	gtk_main_iteration();
   10.11 +    update_icount(main_debug);
   10.12 +}
   10.13 +
   10.14  void update_gui(void) {
   10.15      update_registers(main_debug);
   10.16      update_icount(main_debug);

    11.1 --- a/src/maple/maple.c	Thu Dec 22 13:57:26 2005 +0000
    11.2 +++ b/src/maple/maple.c	Fri Dec 23 11:44:55 2005 +0000
    11.3 @@ -8,7 +8,7 @@
    11.4  void maple_init( void );
    11.5  
    11.6  struct dreamcast_module maple_module = { "Maple", maple_init, NULL, NULL, NULL,
    11.7 -					 NULL, NULL };
    11.8 +					 NULL, NULL, NULL };
    11.9  
   11.10  void maple_init( void )
   11.11  {

    12.1 --- a/src/mem.c	Thu Dec 22 13:57:26 2005 +0000
    12.2 +++ b/src/mem.c	Fri Dec 23 11:44:55 2005 +0000
    12.3 @@ -1,5 +1,5 @@
    12.4  /**
    12.5 - * $Id: mem.c,v 1.6 2005-12-22 07:38:06 nkeynes Exp $
    12.6 + * $Id: mem.c,v 1.7 2005-12-23 11:44:51 nkeynes Exp $
    12.7   * mem.c is responsible for creating and maintaining the overall system memory
    12.8   * map, as visible from the SH4 processor. 
    12.9   *
   12.10 @@ -38,7 +38,7 @@
   12.11  int mem_load(FILE *f);
   12.12  void mem_save(FILE *f);
   12.13  struct dreamcast_module mem_module =
   12.14 -    { "MEM", mem_init, mem_reset, NULL, NULL, mem_save, mem_load };
   12.15 +    { "MEM", mem_init, mem_reset, NULL, NULL, NULL, mem_save, mem_load };
   12.16  
   12.17  struct mem_region mem_rgn[MAX_MEM_REGIONS];
   12.18  struct mmio_region *io_rgn[MAX_IO_REGIONS];

    13.1 --- a/src/modules.h	Thu Dec 22 13:57:26 2005 +0000
    13.2 +++ b/src/modules.h	Fri Dec 23 11:44:55 2005 +0000
    13.3 @@ -30,6 +30,11 @@
    13.4       */
    13.5      void (*start)();
    13.6      /**
    13.7 +     * Execute one time-slice worth of operations, for the given number of
    13.8 +     * micro-seconds.
    13.9 +     */
   13.10 +    void (*run_time_slice)( int microsecs );
   13.11 +    /**
   13.12       * Set the module into a stopped state (may be NULL)
   13.13       */
   13.14      void (*stop)();

    14.1 --- a/src/pvr2/pvr2.c	Thu Dec 22 13:57:26 2005 +0000
    14.2 +++ b/src/pvr2/pvr2.c	Fri Dec 23 11:44:55 2005 +0000
    14.3 @@ -10,8 +10,11 @@
    14.4  char *video_base;
    14.5  
    14.6  void pvr2_init( void );
    14.7 +void pvr2_run_slice( int );
    14.8 +void pvr2_next_frame( void );
    14.9  
   14.10 -struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, NULL,
   14.11 +struct dreamcast_module pvr2_module = { "PVR2", pvr2_init, NULL, NULL, 
   14.12 +					pvr2_run_slice, NULL,
   14.13  					NULL, NULL };
   14.14  
   14.15  void pvr2_init( void )
   14.16 @@ -20,6 +23,18 @@
   14.17      video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   14.18  }
   14.19  
   14.20 +uint32_t pvr2_time_counter = 0;
   14.21 +uint32_t pvr2_time_per_frame = 20000;
   14.22 +
   14.23 +void pvr2_run_slice( int microsecs ) 
   14.24 +{
   14.25 +    pvr2_time_counter += microsecs;
   14.26 +    if( pvr2_time_counter >= pvr2_time_per_frame ) {
   14.27 +	pvr2_next_frame();
   14.28 +	pvr2_time_counter -= pvr2_time_per_frame;
   14.29 +    }
   14.30 +}
   14.31 +
   14.32  uint32_t vid_stride, vid_lpf, vid_ppl, vid_hres, vid_vres, vid_col;
   14.33  int interlaced, bChanged = 1, bEnabled = 0, vid_size = 0;
   14.34  char *frame_start; /* current video start address (in real memory) */

    15.1 --- a/src/sh4/scif.c	Thu Dec 22 13:57:26 2005 +0000
    15.2 +++ b/src/sh4/scif.c	Fri Dec 23 11:44:55 2005 +0000
    15.3 @@ -1,5 +1,5 @@
    15.4  /**
    15.5 - * $Id: scif.c,v 1.3 2005-12-22 13:57:26 nkeynes Exp $
    15.6 + * $Id: scif.c,v 1.4 2005-12-23 11:44:55 nkeynes Exp $
    15.7   * SCIF (Serial Communication Interface with FIFO) implementation - part of the 
    15.8   * SH4 standard on-chip peripheral set. The SCIF is hooked up to the DCs
    15.9   * external serial port
   15.10 @@ -609,3 +609,9 @@
   15.11      }
   15.12      SCIF_rcvd_last_tick = rcvd;
   15.13  }
   15.14 +
   15.15 +void SCIF_run_slice( int microsecs ) 
   15.16 +{
   15.17 +    /* TODO */
   15.18 +    SCIF_clock_tick();
   15.19 +}

    16.1 --- a/src/sh4/sh4core.c	Thu Dec 22 13:57:26 2005 +0000
    16.2 +++ b/src/sh4/sh4core.c	Fri Dec 23 11:44:55 2005 +0000
    16.3 @@ -1,17 +1,48 @@
    16.4 +/**
    16.5 + * $Id: sh4core.c,v 1.9 2005-12-23 11:44:55 nkeynes Exp $
    16.6 + * 
    16.7 + * SH4 emulation core, and parent module for all the SH4 peripheral
    16.8 + * modules.
    16.9 + *
   16.10 + * Copyright (c) 2005 Nathan Keynes.
   16.11 + *
   16.12 + * This program is free software; you can redistribute it and/or modify
   16.13 + * it under the terms of the GNU General Public License as published by
   16.14 + * the Free Software Foundation; either version 2 of the License, or
   16.15 + * (at your option) any later version.
   16.16 + *
   16.17 + * This program is distributed in the hope that it will be useful,
   16.18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
   16.19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   16.20 + * GNU General Public License for more details.
   16.21 + */
   16.22 +
   16.23  #include <math.h>
   16.24  #include "dream.h"
   16.25  #include "modules.h"
   16.26  #include "sh4core.h"
   16.27  #include "sh4mmio.h"
   16.28  #include "mem.h"
   16.29 +#include "clock.h"
   16.30  #include "intc.h"
   16.31  
   16.32 -void sh4_save( FILE *f );
   16.33 -int sh4_load( FILE *f );
   16.34 +uint32_t sh4_freq = SH4_BASE_RATE;
   16.35 +uint32_t sh4_bus_freq = SH4_BASE_RATE;
   16.36 +uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
   16.37 +
   16.38 +/********************** SH4 Module Definition ****************************/
   16.39 +
   16.40 +void sh4_init( void );
   16.41 +void sh4_reset( void );
   16.42 +void sh4_run_slice( int );
   16.43 +void sh4_start( void );
   16.44 +void sh4_stop( void );
   16.45 +void sh4_save_state( FILE *f );
   16.46 +int sh4_load_state( FILE *f );
   16.47  
   16.48  struct dreamcast_module sh4_module = { "SH4", sh4_init, sh4_reset, 
   16.49 -				       NULL, sh4_stop,
   16.50 -				       sh4_save, sh4_load };
   16.51 +				       NULL, sh4_run_slice, sh4_stop,
   16.52 +				       sh4_save_state, sh4_load_state };
   16.53  
   16.54  struct sh4_registers sh4r;
   16.55  static int running = 0;
   16.56 @@ -34,10 +65,16 @@
   16.57      intc_reset();
   16.58  }
   16.59  
   16.60 -void sh4_set_pc( int pc )
   16.61 +void sh4_run_slice( int microsecs ) 
   16.62  {
   16.63 -    sh4r.pc = pc;
   16.64 -    sh4r.new_pc = pc+2;
   16.65 +    int count = sh4_freq * microsecs;
   16.66 +    int i;
   16.67 +
   16.68 +    for( i=0; i<count; i++ ) {
   16.69 +	sh4_execute_instruction();
   16.70 +    }
   16.71 +    TMU_run_slice( microsecs );
   16.72 +    SCIF_run_slice( microsecs );
   16.73  }
   16.74  
   16.75  void sh4_stop(void)
   16.76 @@ -45,16 +82,16 @@
   16.77      running = 0;
   16.78  }
   16.79  
   16.80 -void sh4_save( FILE *f )
   16.81 +void sh4_save_state( FILE *f )
   16.82  {
   16.83      fwrite( &sh4r, sizeof(sh4r), 1, f );
   16.84 -    /* Save all additional on-board MMIO state */
   16.85 +    SCIF_save_state( f );
   16.86  }
   16.87  
   16.88 -int sh4_load( FILE * f )
   16.89 +int sh4_load_state( FILE * f )
   16.90  {
   16.91      fread( &sh4r, sizeof(sh4r), 1, f );
   16.92 -    return 0;
   16.93 +    return SCIF_load_state( f );
   16.94  }
   16.95  
   16.96  void sh4_run(void)
   16.97 @@ -65,6 +102,19 @@
   16.98      }
   16.99  }
  16.100  
  16.101 +/********************** SH4 emulation core  ****************************/
  16.102 +
  16.103 +void sh4_set_pc( int pc )
  16.104 +{
  16.105 +    sh4r.pc = pc;
  16.106 +    sh4r.new_pc = pc+2;
  16.107 +}
  16.108 +
  16.109 +void sh4_set_breakpoint( uint32_t pc, int type )
  16.110 +{
  16.111 +
  16.112 +}
  16.113 +
  16.114  void sh4_runfor(uint32_t count)
  16.115  {
  16.116      running = 1;

    17.1 --- a/src/sh4/sh4core.h	Thu Dec 22 13:57:26 2005 +0000
    17.2 +++ b/src/sh4/sh4core.h	Fri Dec 23 11:44:55 2005 +0000
    17.3 @@ -1,5 +1,5 @@
    17.4  /**
    17.5 - * $Id: sh4core.h,v 1.3 2005-12-11 05:15:36 nkeynes Exp $
    17.6 + * $Id: sh4core.h,v 1.4 2005-12-23 11:44:55 nkeynes Exp $
    17.7   * 
    17.8   * This file defines the public functions exported by the SH4 core, except
    17.9   * for disassembly functions defined in sh4dasm.h
   17.10 @@ -20,6 +20,7 @@
   17.11  #define sh4core_H 1
   17.12  
   17.13  #include <stdint.h>
   17.14 +#include <stdio.h>
   17.15  
   17.16  #ifdef __cplusplus
   17.17  extern "C" {
   17.18 @@ -60,6 +61,10 @@
   17.19  void sh4_set_pc( int );
   17.20  void sh4_execute_instruction( void );
   17.21  void sh4_raise_exception( int, int );
   17.22 +void sh4_set_breakpoint( uint32_t pc, int type );
   17.23 +
   17.24 +#define BREAK_ONESHOT 1
   17.25 +#define BREAK_PERM 2
   17.26  
   17.27  /* SH4 Memory */
   17.28  int32_t sh4_read_long( uint32_t addr );
   17.29 @@ -70,7 +75,12 @@
   17.30  void sh4_write_byte( uint32_t addr, uint32_t val );
   17.31  int32_t sh4_read_phys_word( uint32_t addr );
   17.32  
   17.33 -void run_timers( int );
   17.34 +/* Peripheral functions */
   17.35 +void DMAC_run_slice( int );
   17.36 +void TMU_run_slice( int );
   17.37 +void SCIF_run_slice( int );
   17.38 +void SCIF_save_state( FILE *f );
   17.39 +int SCIF_load_state( FILE *f );
   17.40  
   17.41  #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
   17.42  #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))

    18.1 --- a/src/sh4/sh4mmio.c	Thu Dec 22 13:57:26 2005 +0000
    18.2 +++ b/src/sh4/sh4mmio.c	Fri Dec 23 11:44:55 2005 +0000
    18.3 @@ -134,97 +134,12 @@
    18.4  
    18.5  MMIO_REGION_STUBFNS( UBC )
    18.6  
    18.7 -/********************************* CPG *************************************/
    18.8 -
    18.9 -uint32_t sh4_freq = SH4_BASE_RATE;
   18.10 -uint32_t sh4_bus_freq = SH4_BASE_RATE;
   18.11 -uint32_t sh4_peripheral_freq = SH4_BASE_RATE / 2;
   18.12 -
   18.13 -
   18.14 -MMIO_REGION_STUBFNS( CPG )
   18.15  
   18.16  /********************************* DMAC *************************************/
   18.17  
   18.18  MMIO_REGION_STUBFNS( DMAC )
   18.19  
   18.20 -/********************************** RTC *************************************/
   18.21  
   18.22 -MMIO_REGION_STUBFNS( RTC )
   18.23 -
   18.24 -/********************************** TMU *************************************/
   18.25 -
   18.26 -int timer_divider[3] = {16,16,16};
   18.27 -MMIO_REGION_READ_DEFFN( TMU )
   18.28 -
   18.29 -int get_timer_div( int val )
   18.30 -{
   18.31 -    switch( val & 0x07 ) {
   18.32 -        case 0: return 16; /* assume peripheral clock is IC/4 */
   18.33 -        case 1: return 64;
   18.34 -        case 2: return 256;
   18.35 -        case 3: return 1024;
   18.36 -        case 4: return 4096;
   18.37 -    }
   18.38 -    return 1;
   18.39 -}
   18.40 -
   18.41 -void mmio_region_TMU_write( uint32_t reg, uint32_t val )
   18.42 -{
   18.43 -    switch( reg ) {
   18.44 -        case TCR0:
   18.45 -            timer_divider[0] = get_timer_div(val);
   18.46 -            break;
   18.47 -        case TCR1:
   18.48 -            timer_divider[1] = get_timer_div(val);
   18.49 -            break;
   18.50 -        case TCR2:
   18.51 -            timer_divider[2] = get_timer_div(val);
   18.52 -            break;
   18.53 -    }
   18.54 -    MMIO_WRITE( TMU, reg, val );
   18.55 -}
   18.56 -
   18.57 -void run_timers( int cycles )
   18.58 -{
   18.59 -    int tcr = MMIO_READ( TMU, TSTR );
   18.60 -    cycles *= 16;
   18.61 -    if( tcr & 0x01 ) {
   18.62 -        int count = cycles / timer_divider[0];
   18.63 -        int *val = MMIO_REG( TMU, TCNT0 );
   18.64 -        if( *val < count ) {
   18.65 -            MMIO_READ( TMU, TCR0 ) |= 0x100;
   18.66 -            /* interrupt goes here */
   18.67 -            count -= *val;
   18.68 -            *val = MMIO_READ( TMU, TCOR0 ) - count;
   18.69 -        } else {
   18.70 -            *val -= count;
   18.71 -        }
   18.72 -    }
   18.73 -    if( tcr & 0x02 ) {
   18.74 -        int count = cycles / timer_divider[1];
   18.75 -        int *val = MMIO_REG( TMU, TCNT1 );
   18.76 -        if( *val < count ) {
   18.77 -            MMIO_READ( TMU, TCR1 ) |= 0x100;
   18.78 -            /* interrupt goes here */
   18.79 -            count -= *val;
   18.80 -            *val = MMIO_READ( TMU, TCOR1 ) - count;
   18.81 -        } else {
   18.82 -            *val -= count;
   18.83 -        }
   18.84 -    }
   18.85 -    if( tcr & 0x04 ) {
   18.86 -        int count = cycles / timer_divider[2];
   18.87 -        int *val = MMIO_REG( TMU, TCNT2 );
   18.88 -        if( *val < count ) {
   18.89 -            MMIO_READ( TMU, TCR2 ) |= 0x100;
   18.90 -            /* interrupt goes here */
   18.91 -            count -= *val;
   18.92 -            *val = MMIO_READ( TMU, TCOR2 ) - count;
   18.93 -        } else {
   18.94 -            *val -= count;
   18.95 -        }
   18.96 -    }
   18.97 -}
   18.98  
   18.99  /********************************** SCI *************************************/
  18.100  

    19.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.2 +++ b/src/sh4/timer.c	Fri Dec 23 11:44:55 2005 +0000
    19.3 @@ -0,0 +1,128 @@
    19.4 +/**
    19.5 + * $Id: timer.c,v 1.1 2005-12-23 11:44:55 nkeynes Exp $
    19.6 + * 
    19.7 + * SH4 Timer/Clock peripheral modules (CPG, TMU, RTC), combined together to
    19.8 + * keep things simple (they intertwine a bit).
    19.9 + *
   19.10 + * Copyright (c) 2005 Nathan Keynes.
   19.11 + *
   19.12 + * This program is free software; you can redistribute it and/or modify
   19.13 + * it under the terms of the GNU General Public License as published by
   19.14 + * the Free Software Foundation; either version 2 of the License, or
   19.15 + * (at your option) any later version.
   19.16 + *
   19.17 + * This program is distributed in the hope that it will be useful,
   19.18 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
   19.19 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   19.20 + * GNU General Public License for more details.
   19.21 + */
   19.22 +
   19.23 +#include "dream.h"
   19.24 +#include "mem.h"
   19.25 +#include "clock.h"
   19.26 +#include "sh4core.h"
   19.27 +#include "sh4mmio.h"
   19.28 +
   19.29 +/********************************* CPG *************************************/
   19.30 +
   19.31 +int32_t mmio_region_CPG_read( uint32_t reg )
   19.32 +{
   19.33 +    return MMIO_READ( CPG, reg );
   19.34 +}
   19.35 +
   19.36 +void mmio_region_CPG_write( uint32_t reg, uint32_t val )
   19.37 +{
   19.38 +    MMIO_WRITE( CPG, reg, val );
   19.39 +}
   19.40 +
   19.41 +/********************************** RTC *************************************/
   19.42 +
   19.43 +int32_t mmio_region_RTC_read( uint32_t reg )
   19.44 +{
   19.45 +    return MMIO_READ( RTC, reg );
   19.46 +}
   19.47 +
   19.48 +void mmio_region_RTC_write( uint32_t reg, uint32_t val )
   19.49 +{
   19.50 +    MMIO_WRITE( RTC, reg, val );
   19.51 +}
   19.52 +
   19.53 +/********************************** TMU *************************************/
   19.54 +
   19.55 +int timer_divider[3] = {16,16,16};
   19.56 +
   19.57 +int32_t mmio_region_TMU_read( uint32_t reg )
   19.58 +{
   19.59 +    return MMIO_READ( TMU, reg );
   19.60 +}
   19.61 +
   19.62 +
   19.63 +int get_timer_div( int val )
   19.64 +{
   19.65 +    switch( val & 0x07 ) {
   19.66 +        case 0: return 16; /* assume peripheral clock is IC/4 */
   19.67 +        case 1: return 64;
   19.68 +        case 2: return 256;
   19.69 +        case 3: return 1024;
   19.70 +        case 4: return 4096;
   19.71 +    }
   19.72 +    return 1;
   19.73 +}
   19.74 +
   19.75 +void mmio_region_TMU_write( uint32_t reg, uint32_t val )
   19.76 +{
   19.77 +    switch( reg ) {
   19.78 +        case TCR0:
   19.79 +            timer_divider[0] = get_timer_div(val);
   19.80 +            break;
   19.81 +        case TCR1:
   19.82 +            timer_divider[1] = get_timer_div(val);
   19.83 +            break;
   19.84 +        case TCR2:
   19.85 +            timer_divider[2] = get_timer_div(val);
   19.86 +            break;
   19.87 +    }
   19.88 +    MMIO_WRITE( TMU, reg, val );
   19.89 +}
   19.90 +
   19.91 +void TMU_run_slice( int microsecs )
   19.92 +{
   19.93 +    int tcr = MMIO_READ( TMU, TSTR );
   19.94 +    int cycles = microsecs * 16 * 200;
   19.95 +    if( tcr & 0x01 ) {
   19.96 +        int count = cycles / timer_divider[0];
   19.97 +        int *val = MMIO_REG( TMU, TCNT0 );
   19.98 +        if( *val < count ) {
   19.99 +            MMIO_READ( TMU, TCR0 ) |= 0x100;
  19.100 +            /* interrupt goes here */
  19.101 +            count -= *val;
  19.102 +            *val = MMIO_READ( TMU, TCOR0 ) - count;
  19.103 +        } else {
  19.104 +            *val -= count;
  19.105 +        }
  19.106 +    }
  19.107 +    if( tcr & 0x02 ) {
  19.108 +        int count = cycles / timer_divider[1];
  19.109 +        int *val = MMIO_REG( TMU, TCNT1 );
  19.110 +        if( *val < count ) {
  19.111 +            MMIO_READ( TMU, TCR1 ) |= 0x100;
  19.112 +            /* interrupt goes here */
  19.113 +            count -= *val;
  19.114 +            *val = MMIO_READ( TMU, TCOR1 ) - count;
  19.115 +        } else {
  19.116 +            *val -= count;
  19.117 +        }
  19.118 +    }
  19.119 +    if( tcr & 0x04 ) {
  19.120 +        int count = cycles / timer_divider[2];
  19.121 +        int *val = MMIO_REG( TMU, TCNT2 );
  19.122 +        if( *val < count ) {
  19.123 +            MMIO_READ( TMU, TCR2 ) |= 0x100;
  19.124 +            /* interrupt goes here */
  19.125 +            count -= *val;
  19.126 +            *val = MMIO_READ( TMU, TCOR2 ) - count;
  19.127 +        } else {
  19.128 +            *val -= count;
  19.129 +        }
  19.130 +    }
  19.131 +}