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lxdream.org :: lxdream :: r753:1fe39c3a9bbc
lxdream 0.9.1
released Jun 29
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changeset753:1fe39c3a9bbc
parent752:9458edce8861
child754:35c496703380
authornkeynes
dateSun Jul 20 11:36:48 2008 +0000 (11 years ago)
Initial implementation for sort-dma channel
src/asic.c
src/asic.h
src/pvr2/pvr2.h
src/pvr2/tacore.c
test/Makefile.in
test/asic.c
test/asic.h
test/dmac.c
test/testsort.data
1.1 --- a/src/asic.c Sat Jul 19 02:48:50 2008 +0000
1.2 +++ b/src/asic.c Sun Jul 20 11:36:48 2008 +0000
1.3 @@ -355,9 +355,42 @@
1.4 sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
1.5 sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );
1.6 int table_size = MMIO_READ( ASIC, SORTDMATSIZ );
1.7 - int data_size = MMIO_READ( ASIC, SORTDMADSIZ );
1.8 + int addr_shift = MMIO_READ( ASIC, SORTDMAASIZ ) ? 5 : 0;
1.9 + int count = 1;
1.10
1.11 - WARN( "Sort DMA not implemented" );
1.12 + uint32_t *table32 = (uint32_t *)mem_get_region( table_addr );
1.13 + uint16_t *table16 = (uint16_t *)table32;
1.14 + uint32_t next = table_size ? (*table32++) : (uint32_t)(*table16++);
1.15 + while(1) {
1.16 + next &= 0x07FFFFFF;
1.17 + if( next == 1 ) {
1.18 + next = table_size ? (*table32++) : (uint32_t)(*table16++);
1.19 + count++;
1.20 + continue;
1.21 + } else if( next == 2 ) {
1.22 + asic_event( EVENT_SORT_DMA );
1.23 + break;
1.24 + }
1.25 + uint32_t *data = (uint32_t *)mem_get_region(data_addr + (next<<addr_shift));
1.26 + if( data == NULL ) {
1.27 + break;
1.28 + }
1.29 +
1.30 + uint32_t *poly = pvr2_ta_find_polygon_context(data, 128);
1.31 + if( poly == NULL ) {
1.32 + asic_event( EVENT_SORT_DMA_ERR );
1.33 + break;
1.34 + }
1.35 + uint32_t size = poly[6] & 0xFF;
1.36 + if( size == 0 ) {
1.37 + size = 0x100;
1.38 + }
1.39 + next = poly[7];
1.40 + pvr2_ta_write( (unsigned char *)data, size<<5 );
1.41 + }
1.42 +
1.43 + MMIO_WRITE( ASIC, SORTDMACNT, count );
1.44 + MMIO_WRITE( ASIC, SORTDMACTL, 0 );
1.45 }
1.46
1.47 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
1.48 @@ -422,7 +455,7 @@
1.49 case SORTDMATBL: case SORTDMADATA:
1.50 MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );
1.51 break;
1.52 - case SORTDMATSIZ: case SORTDMADSIZ:
1.53 + case SORTDMATSIZ: case SORTDMAASIZ:
1.54 MMIO_WRITE( ASIC, reg, (val & 1) );
1.55 break;
1.56 case SORTDMACTL:
2.1 --- a/src/asic.h Sat Jul 19 02:48:50 2008 +0000
2.2 +++ b/src/asic.h Sun Jul 20 11:36:48 2008 +0000
2.3 @@ -32,12 +32,13 @@
2.4 LONG_PORT( 0x810, SORTDMATBL, PORT_MRW, 0, "Sort DMA Table address" )
2.5 LONG_PORT( 0x814, SORTDMADATA, PORT_MRW, 0, "Sort DMA Data base address" )
2.6 LONG_PORT( 0x818, SORTDMATSIZ, PORT_MRW, 0, "Sort DMA Table entry size" )
2.7 - LONG_PORT( 0x81C, SORTDMADSIZ, PORT_MRW, 0, "Sort DMA Data size" )
2.8 + LONG_PORT( 0x81C, SORTDMAASIZ, PORT_MRW, 0, "Sort DMA Table address size" )
2.9 LONG_PORT( 0x820, SORTDMACTL, PORT_MRW, 0, "Sort DMA Control" )
2.10 LONG_PORT( 0x840, ASICUNK5, PORT_MRW, 0, "ASIC <unknown5>" )
2.11 LONG_PORT( 0x844, ASICUNK6, PORT_MRW, 0, "ASIC <unknown6>" )
2.12 LONG_PORT( 0x848, ASICUNK7, PORT_MRW, 0, "ASIC <unknown7>" )
2.13 LONG_PORT( 0x84C, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )
2.14 + LONG_PORT( 0x860, SORTDMACNT, PORT_MR, 0, "Sort DMA Transfer count" )
2.15 LONG_PORT( 0x884, PVRDMARGN1, PORT_MRW, 0, "PVR DMA Dest region 1" )
2.16 LONG_PORT( 0x888, PVRDMARGN2, PORT_MRW, 0, "PVR DMA Dest region 2" )
2.17 LONG_PORT( 0x88C, G2STATUS, PORT_MR|PORT_NOTRACE, 0x0E, "G2 Fifo status" )
2.18 @@ -189,6 +190,7 @@
2.19 #define EVENT_G2_DMA2 17
2.20 #define EVENT_G2_DMA3 18
2.21 #define EVENT_PVR_DMA 19
2.22 +#define EVENT_SORT_DMA 20
2.23 #define EVENT_PVR_PUNCHOUT_DONE 21
2.24 #define EVENT_CASCADE1 30 /* Set if something in the second word is active */
2.25 #define EVENT_CASCADE2 31 /* Set if something in the third word is active */
2.26 @@ -199,6 +201,7 @@
2.27 #define EVENT_PVR_PRIM_ALLOC_FAIL 66
2.28 #define EVENT_PVR_MATRIX_ALLOC_FAIL 67
2.29 #define EVENT_PVR_BAD_INPUT 68
2.30 +#define EVENT_SORT_DMA_ERR 92
2.31
2.32 #define IS_IDE_REGISTER(x) ( (x) <= IDEDMACTL2 )
2.33
3.1 --- a/src/pvr2/pvr2.h Sat Jul 19 02:48:50 2008 +0000
3.2 +++ b/src/pvr2/pvr2.h Sun Jul 20 11:36:48 2008 +0000
3.3 @@ -213,6 +213,12 @@
3.4 */
3.5 void pvr2_ta_write( unsigned char *buf, uint32_t length );
3.6
3.7 +/**
3.8 + * Find the first polygon or sprite context in the supplied buffer of TA
3.9 + * data.
3.10 + * @return A pointer to the context, or NULL if it cannot be found
3.11 + */
3.12 +uint32_t *pvr2_ta_find_polygon_context( uint32_t *buf, uint32_t length );
3.13
3.14 /**
3.15 * (Re)initialize the tile accelerator in preparation for the next scene.
4.1 --- a/src/pvr2/tacore.c Sat Jul 19 02:48:50 2008 +0000
4.2 +++ b/src/pvr2/tacore.c Sun Jul 20 11:36:48 2008 +0000
4.3 @@ -1161,7 +1161,22 @@
4.4
4.5 }
4.6
4.7 -
4.8 +/**
4.9 + * Find the first polygon or sprite context in the supplied buffer of TA
4.10 + * data.
4.11 + * @return A pointer to the context, or NULL if it cannot be found
4.12 + */
4.13 +uint32_t *pvr2_ta_find_polygon_context( uint32_t *buf, uint32_t length )
4.14 +{
4.15 + uint32_t *poly;
4.16 + for( poly = buf; poly < buf+(length>>2); poly += 8 ) {
4.17 + if( TA_CMD(*poly) == TA_CMD_POLYGON_CONTEXT ||
4.18 + TA_CMD(*poly) == TA_CMD_SPRITE_CONTEXT ) {
4.19 + return poly;
4.20 + }
4.21 + }
4.22 + return NULL;
4.23 +}
4.24
4.25 /**
4.26 * Write a block of data to the tile accelerator, adding the data to the
5.1 --- a/test/Makefile.in Sat Jul 19 02:48:50 2008 +0000
5.2 +++ b/test/Makefile.in Sun Jul 20 11:36:48 2008 +0000
5.3 @@ -66,6 +66,7 @@
5.4 $(RUNTEST) testmmu
5.5 $(RUNTEST) testregs
5.6 cat testta.data testta2.data testta3.data testta4.data testta5.data | $(RUNTEST) testta
5.7 + cat testsort.data | $(RUNTEST) testta
5.8 # $(RUNTEST) testide -d ../disc/test.nrg
5.9
5.10
6.1 --- a/test/asic.c Sat Jul 19 02:48:50 2008 +0000
6.2 +++ b/test/asic.c Sun Jul 20 11:36:48 2008 +0000
6.3 @@ -43,6 +43,28 @@
6.4 }
6.5
6.6 /**
6.7 + * Wait for either of 2 ASIC events.
6.8 + * @return the event id if the event occurred, otherwise -1 if the wait timed out.
6.9 + */
6.10 +int asic_wait2( int event1, int event2 )
6.11 +{
6.12 + int n1 = event1 >> 5;
6.13 + int n2 = event2 >> 5;
6.14 + unsigned int mask1 = (1<< (event1&0x1f));
6.15 + unsigned int mask2 = (1<< (event2&0x1f));
6.16 + int i;
6.17 + for( i=0; i<TIMEOUT; i++ ) {
6.18 + if( long_read(ASIC_PIRQ(n1)) & mask1 ) {
6.19 + return event1;
6.20 + }
6.21 + if( long_read(ASIC_PIRQ(n2)) & mask2 ) {
6.22 + return event2;
6.23 + }
6.24 + }
6.25 + return -1; /* Timeout */
6.26 +}
6.27 +
6.28 +/**
6.29 * Clear all asic events
6.30 */
6.31 void asic_clear()
7.1 --- a/test/asic.h Sat Jul 19 02:48:50 2008 +0000
7.2 +++ b/test/asic.h Sun Jul 20 11:36:48 2008 +0000
7.3 @@ -18,6 +18,7 @@
7.4 #define EVENT_SPU_DMA2 17
7.5 #define EVENT_SPU_DMA3 18
7.6 #define EVENT_PVR_DMA 19
7.7 +#define EVENT_SORT_DMA 20
7.8 #define EVENT_PVR_PUNCHOUT_DONE 21
7.9
7.10 #define EVENT_TA_ERROR 31
7.11 @@ -28,6 +29,8 @@
7.12 #define EVENT_PVR_MATRIX_ALLOC_FAIL 67
7.13 #define EVENT_PVR_BAD_INPUT 68
7.14
7.15 +#define EVENT_SORT_DMA_ERR 92
7.16 +
7.17 /**
7.18 * Wait for an ASIC event.
7.19 * @return 0 if the event occurred, otherwise -1 if the wait timed out.
7.20 @@ -35,6 +38,12 @@
7.21 int asic_wait( int event );
7.22
7.23 /**
7.24 + * Wait for either of a pair of events.
7.25 + * @return the event ID of the event that occured, or -1 if the wait timed out
7.26 + */
7.27 +int asic_wait2( int event1, int event2 );
7.28 +
7.29 +/**
7.30 * Check if an ASIC event is active (does not wait)
7.31 * @return 0 if inactive, nonzero if active.
7.32 */
8.1 --- a/test/dmac.c Sat Jul 19 02:48:50 2008 +0000
8.2 +++ b/test/dmac.c Sun Jul 20 11:36:48 2008 +0000
8.3 @@ -33,6 +33,13 @@
8.4 #define PVR_DMA_CTL (ASIC_BASE+0x808)
8.5 #define PVR_DMA_REGION (ASIC_BASE+0x884)
8.6
8.7 +#define SORT_DMA_TABLE (ASIC_BASE+0x810)
8.8 +#define SORT_DMA_DATA (ASIC_BASE+0x814)
8.9 +#define SORT_DMA_TABLEBITS (ASIC_BASE+0x818)
8.10 +#define SORT_DMA_DATASIZE (ASIC_BASE+0x81C)
8.11 +#define SORT_DMA_CTL (ASIC_BASE+0x820)
8.12 +#define SORT_DMA_COUNT (ASIC_BASE+0x860)
8.13 +
8.14 void dmac_dump_channel( FILE *f, unsigned int channel )
8.15 {
8.16 fprintf( f, "DMAC SAR: %08X Count: %08X Ctl: %08X OR: %08X\n",
8.17 @@ -124,3 +131,29 @@
8.18
8.19 return result;
8.20 }
8.21 +
8.22 +int sort_dma_write( char *sorttable, int tablelen, char *data, int datalen, int bitwidth, int datasize )
8.23 +{
8.24 + int result;
8.25 + uint32_t tableaddr = (uint32_t)sorttable;
8.26 + uint32_t dataaddr = (uint32_t)data;
8.27 +
8.28 + long_write( SORT_DMA_CTL, 0 );
8.29 + asic_clear();
8.30 +
8.31 + long_write( SORT_DMA_TABLE, tableaddr );
8.32 + long_write( SORT_DMA_DATA, dataaddr );
8.33 + long_write( SORT_DMA_TABLEBITS, bitwidth );
8.34 + long_write( SORT_DMA_DATASIZE, datasize );
8.35 + long_write( SORT_DMA_CTL, 1 );
8.36 + result = asic_wait2(EVENT_SORT_DMA, EVENT_SORT_DMA_ERR);
8.37 + if( result == -1 ) {
8.38 + fprintf( stderr, "SORT DMA failed (timeout)\n" );
8.39 + asic_dump(stderr);
8.40 + fprintf( stderr, "Table: %08X Count: %08X Ctl: %08X\n", long_read(SORT_DMA_TABLE), long_read(SORT_DMA_COUNT),
8.41 + long_read(SORT_DMA_CTL) );
8.42 + long_write( SORT_DMA_CTL, 0 );
8.43 + }
8.44 + CHECK_IEQUALS( 0, long_read(SORT_DMA_CTL) );
8.45 + return result;
8.46 +}
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
9.2 +++ b/test/testsort.data Sun Jul 20 11:36:48 2008 +0000
9.3 @@ -0,0 +1,233 @@
9.4 +#
9.5 +# Sort DMA tests
9.6 +#
9.7 +[1.1 Single object]
9.8 +sortconf = 00000001 00000001
9.9 +sorttab = 00000000
9.10 +input =
9.11 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000006 00000002
9.12 +E0000000 0.0 0.1 0.2 00000000 00000000 FF00FF00 FE010203
9.13 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.14 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.15 +F0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.16 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.17 +output =
9.18 +E0A00000 2083242D 00000000
9.19 +0.0 0.1 0.2 FF00FF00
9.20 +15.2 0.3 0.4 FF0000FF
9.21 +15.8 15.9 0.5 FFFFFFFF
9.22 +E0A00000 2083242D 00000000
9.23 +15.8 15.9 0.5 FFFFFFFF
9.24 +15.2 0.3 0.4 FF0000FF
9.25 +0.4 17.3 0.6 FF00FF00
9.26 +tile 1 =
9.27 +82204000
9.28 +
9.29 +[1.2 Two objects]
9.30 +sortconf = 00000001 00000001
9.31 +sorttab = 00000005 00000002
9.32 +input =
9.33 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000005 00000001
9.34 +E0000000 0.0 0.1 0.2 00000000 00000000 FF00FF00 FE010203
9.35 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.36 +F0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.37 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.38 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000004 00000000
9.39 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.40 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.41 +F0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.42 +output =
9.43 +E0A00000 2083242D 00000000
9.44 +15.8 15.9 0.5 FFFFFFFF
9.45 +15.2 0.3 0.4 FF0000FF
9.46 +0.4 17.3 0.6 FF00FF00
9.47 +E0A00000 2083242D 00000000
9.48 +0.0 0.1 0.2 FF00FF00
9.49 +15.2 0.3 0.4 FF0000FF
9.50 +15.8 15.9 0.5 FFFFFFFF
9.51 +tile 1 =
9.52 +82204000
9.53 +
9.54 +[1.3 Two single lists]
9.55 +sortconf = 00000001 00000001
9.56 +sorttab = 00000000 00000004 00000002
9.57 +input =
9.58 +80800002 E0000000 2083422D 00000000 00000000 00000000 00000004 00000001
9.59 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.60 +E0000000 0.0 0.1 0.2 00000000 00000000 FF00FF00 FE010203
9.61 +F0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.62 +80800002 E0000000 2083422D 00000000 00000000 00000000 00000005 00000001
9.63 +E0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.64 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.65 +F0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.66 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.67 +output =
9.68 +E0A00000 2083422D 00000000
9.69 +15.2 0.3 0.4 FF0000FF
9.70 +0.0 0.1 0.2 FF00FF00
9.71 +15.8 15.9 0.5 FFFFFFFF
9.72 +E0A00000 2083422D 00000000
9.73 +0.4 17.3 0.6 FF00FF00
9.74 +15.8 15.9 0.5 FFFFFFFF
9.75 +15.2 0.3 0.4 FF0000FF
9.76 +tile 1 =
9.77 +82204000
9.78 +
9.79 +[1.4 Repeating a list]
9.80 +sortconf = 00000001 00000001
9.81 +sorttab = 00000004 00000004 00000008
9.82 +input =
9.83 +80800002 E0000000 2083422D 00000000 00000000 00000000 00000004 00000001
9.84 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.85 +E0000000 0.0 0.1 0.2 00000000 00000000 FF00FF00 FE010203
9.86 +F0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.87 +80800002 E0000000 2083422D 00000000 00000000 00000000 00000004 00000000
9.88 +E0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.89 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.90 +F0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.91 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.92 +80800002 00000000 00000000 00000000 00000000 00000000 00000001 00000002
9.93 +
9.94 +output =
9.95 +E0A00000 2083422D 00000000
9.96 +0.4 17.3 0.6 FF00FF00
9.97 +15.8 15.9 0.5 FFFFFFFF
9.98 +15.2 0.3 0.4 FF0000FF
9.99 +E0A00000 2083422D 00000000
9.100 +15.2 0.3 0.4 FF0000FF
9.101 +0.0 0.1 0.2 FF00FF00
9.102 +15.8 15.9 0.5 FFFFFFFF
9.103 +E0A00000 2083422D 00000000
9.104 +0.4 17.3 0.6 FF00FF00
9.105 +15.8 15.9 0.5 FFFFFFFF
9.106 +15.2 0.3 0.4 FF0000FF
9.107 +E0A00000 2083422D 00000000
9.108 +15.2 0.3 0.4 FF0000FF
9.109 +0.0 0.1 0.2 FF00FF00
9.110 +15.8 15.9 0.5 FFFFFFFF
9.111 +tile 1 =
9.112 +86204000
9.113 +
9.114 +[1.5 Empty list]
9.115 +sortconf = 00000001 00000001
9.116 +sorttab = 00000002
9.117 +input =
9.118 +80800002 E0000000 2083422D 00000000 00000000 00000000 00000004 00000000
9.119 +F0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.120 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.121 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.122 +00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000002
9.123 +output =
9.124 +
9.125 +[1.6 Multiple params]
9.126 +sortconf = 00000001 00000001
9.127 +sorttab = 00000000
9.128 +input =
9.129 +20000000 00000000 00000000 00000000 00000000 00000000 0000000E 0000000E
9.130 +20000000 00000000 00000000 00000000 00000000 00000000 0000000E 0000000E
9.131 +20000000 00000000 00000000 00000000 00000000 00000000 0000000E 0000000E
9.132 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000008 00000002
9.133 +E0000000 0.0 0.1 0.2 00000000 00000000 FF00FF00 FE010203
9.134 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.135 +F0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.136 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.137 +output =
9.138 +E0A00000 2083242D 00000000
9.139 +0.0 0.1 0.2 FF00FF00
9.140 +15.2 0.3 0.4 FF0000FF
9.141 +15.8 15.9 0.5 FFFFFFFF
9.142 +tile 1 =
9.143 +80204000
9.144 +
9.145 +[1.7 Too many params]
9.146 +sortconf = 00000001 00000001
9.147 +sorttab = 00000000
9.148 +error = 1F 5C
9.149 +input =
9.150 +20000000 00000000 00000000 00000000 00000000 00000000 0000000E 0000000E
9.151 +20000000 00000000 00000000 00000000 00000000 00000000 0000000E 0000000E
9.152 +20000000 00000000 00000000 00000000 00000000 00000000 0000000E 0000000E
9.153 +20000000 00000000 00000000 00000000 00000000 00000000 0000000E 0000000E
9.154 +80800002 E0000000 2083422D 00000000 00000000 00000000 0000000A 00000002
9.155 +E0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.156 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.157 +F0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.158 +00000000 00000000 00000000 00000000 00000000 00000000 00000001 00000002
9.159 +output =
9.160 +
9.161 +[1.8 16-bit table]
9.162 +sortconf = 00000000 00000001
9.163 +sorttab = 00040000 00000002
9.164 +input =
9.165 +80800002 E0000000 2083422D 00000000 00000000 00000000 00000004 00000001
9.166 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.167 +E0000000 0.0 0.1 0.2 00000000 00000000 FF00FF00 FE010203
9.168 +F0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.169 +80800002 E0000000 2083422D 00000000 00000000 00000000 00000005 00000001
9.170 +E0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.171 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.172 +F0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.173 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.174 +output =
9.175 +E0A00000 2083422D 00000000
9.176 +15.2 0.3 0.4 FF0000FF
9.177 +0.0 0.1 0.2 FF00FF00
9.178 +15.8 15.9 0.5 FFFFFFFF
9.179 +E0A00000 2083422D 00000000
9.180 +0.4 17.3 0.6 FF00FF00
9.181 +15.8 15.9 0.5 FFFFFFFF
9.182 +15.2 0.3 0.4 FF0000FF
9.183 +tile 1 =
9.184 +82204000
9.185 +
9.186 +[1.9 Byte-size offsets]
9.187 +sortconf = 00000001 00000000
9.188 +sorttab = 000000C0 00000002
9.189 +input =
9.190 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.191 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000005 00000001
9.192 +E0000000 0.0 0.1 0.2 00000000 00000000 FF00FF00 FE010203
9.193 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.194 +F0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.195 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.196 +80800002 E0000000 2083242D 00000000 00000000 00000000 00000004 00000020
9.197 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.198 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.199 +F0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.200 +output =
9.201 +E0A00000 2083242D 00000000
9.202 +15.8 15.9 0.5 FFFFFFFF
9.203 +15.2 0.3 0.4 FF0000FF
9.204 +0.4 17.3 0.6 FF00FF00
9.205 +E0A00000 2083242D 00000000
9.206 +0.0 0.1 0.2 FF00FF00
9.207 +15.2 0.3 0.4 FF0000FF
9.208 +15.8 15.9 0.5 FFFFFFFF
9.209 +tile 1 =
9.210 +82204000
9.211 +
9.212 +[1.10 Word masks]
9.213 +sortconf = 00000001 00000001
9.214 +sorttab = F8000005 F8000002 00000005 00000002
9.215 +input =
9.216 +80800002 E0000000 2083242D 00000000 00000000 00000000 FFFFFF05 F8000001
9.217 +E0000000 0.0 0.1 0.2 00000000 00000000 FF00FF00 FE010203
9.218 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.219 +F0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.220 +00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
9.221 +80800002 E0000000 2083242D 00000000 00000000 00000000 01010104 F8000000
9.222 +E0000000 15.8 15.9 0.5 00000000 00000000 FFFFFFFF FB0A0B0C
9.223 +E0000000 15.2 0.3 0.4 00000000 00000000 FF0000FF FD040506
9.224 +F0000000 0.4 17.3 0.6 00000000 00000000 FF00FF00 FE010203
9.225 +output =
9.226 +E0A00000 2083242D 00000000
9.227 +15.8 15.9 0.5 FFFFFFFF
9.228 +15.2 0.3 0.4 FF0000FF
9.229 +0.4 17.3 0.6 FF00FF00
9.230 +E0A00000 2083242D 00000000
9.231 +0.0 0.1 0.2 FF00FF00
9.232 +15.2 0.3 0.4 FF0000FF
9.233 +15.8 15.9 0.5 FFFFFFFF
9.234 +tile 1 =
9.235 +82204000
9.236 +
.