revision 629:2811e8a2debf
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raw | bz2 | zip | gz changeset | 629:2811e8a2debf |
parent | 628:bd46e2c4c479 |
child | 630:50addb748df5 |
author | nkeynes |
date | Fri Feb 08 11:30:04 2008 +0000 (16 years ago) |
Bail out properly on read errors during a DMA cycle
src/gdrom/ide.c | view | annotate | diff | log |
1.1 --- a/src/gdrom/ide.c Fri Feb 08 00:59:15 2008 +00001.2 +++ b/src/gdrom/ide.c Fri Feb 08 11:30:04 2008 +00001.3 @@ -190,6 +190,7 @@1.4 idereg.count = 3;1.5 if( result != 0 ) {1.6 idereg.status = 0x51;1.7 + idereg.state = IDE_STATE_IDLE;1.8 ide_raise_interrupt();1.9 } else {1.10 idereg.status = idereg.status & ~(IDE_STATUS_BSY|IDE_STATUS_CHK);1.11 @@ -325,29 +326,27 @@1.12 uint32_t ide_read_data_dma( uint32_t addr, uint32_t length )1.13 {1.14 uint32_t xfercount = 0;1.15 - if( idereg.state == IDE_STATE_DMA_READ ) {1.16 - while( xfercount < length ) {1.17 - int xferlen = length - xfercount;1.18 - int remaining = idereg.data_length - idereg.data_offset;1.19 - if( xferlen > remaining ) {1.20 - xferlen = remaining;1.21 - }1.22 - mem_copy_to_sh4( addr, (data_buffer + idereg.data_offset), xferlen );1.23 - xfercount += xferlen;1.24 - addr += xferlen;1.25 - idereg.data_offset += xferlen;1.26 - if( idereg.data_offset >= idereg.data_length ) {1.27 - if( idereg.sectors_left > 0 ) {1.28 - ide_read_next_sector();1.29 - } else {1.30 - idereg.data_offset = -1;1.31 - idereg.state = IDE_STATE_IDLE;1.32 - idereg.status = 0x50;1.33 - idereg.count = 0x03;1.34 - ide_raise_interrupt();1.35 - asic_event( EVENT_IDE_DMA );1.36 - break;1.37 - }1.38 + while( xfercount < length && idereg.state == IDE_STATE_DMA_READ ) {1.39 + int xferlen = length - xfercount;1.40 + int remaining = idereg.data_length - idereg.data_offset;1.41 + if( xferlen > remaining ) {1.42 + xferlen = remaining;1.43 + }1.44 + mem_copy_to_sh4( addr, (data_buffer + idereg.data_offset), xferlen );1.45 + xfercount += xferlen;1.46 + addr += xferlen;1.47 + idereg.data_offset += xferlen;1.48 + if( idereg.data_offset >= idereg.data_length ) {1.49 + if( idereg.sectors_left > 0 ) {1.50 + ide_read_next_sector();1.51 + } else {1.52 + idereg.data_offset = -1;1.53 + idereg.state = IDE_STATE_IDLE;1.54 + idereg.status = 0x50;1.55 + idereg.count = 0x03;1.56 + ide_raise_interrupt();1.57 + asic_event( EVENT_IDE_DMA );1.58 + break;1.59 }1.60 }1.61 }
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