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lxdream.org :: lxdream :: r555:309c97260912
lxdream 0.9.1
released Jun 29
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changeset555:309c97260912 lxdream-mmu
parent554:cecd78cb06bd
child556:72dbf70344db
authornkeynes
dateTue Jan 01 04:32:01 2008 +0000 (12 years ago)
branchlxdream-mmu
Add initial TLB tests
test/Makefile.in
test/sh4/inc.s
test/sh4/testsh4.c
test/sh4/tlb.s
1.1 --- a/test/Makefile.in Tue Jan 01 02:47:20 2008 +0000
1.2 +++ b/test/Makefile.in Tue Jan 01 04:32:01 2008 +0000
1.3 @@ -78,7 +78,7 @@
1.4 sh4/mac.s \
1.5 sh4/rot.so sh4/shl.so sh4/shld.so sh4/sub.so sh4/subc.so \
1.6 sh4/trapa.so sh4/tas.so sh4/xtrct.so \
1.7 - sh4/excslot.so sh4/undef.so
1.8 + sh4/excslot.so sh4/undef.so sh4/tlb.so
1.9 $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
1.10 $(SH4OBJCOPY) testsh4 testsh4.bin
1.11
2.1 --- a/test/sh4/inc.s Tue Jan 01 02:47:20 2008 +0000
2.2 +++ b/test/sh4/inc.s Tue Jan 01 04:32:01 2008 +0000
2.3 @@ -240,6 +240,24 @@
2.4 L3:
2.5 .endm
2.6
2.7 +.macro assert_tlb_exc_caught testname, expectpc, expectvpn
2.8 +LOCAL L1, L2, L3
2.9 + mov.l L1, r3
2.10 + mov.l \testname, r4
2.11 + mov r12, r5
2.12 + mov.l L2, r6
2.13 + mov.l \expectvpn, r7
2.14 + jsr @r3
2.15 + nop
2.16 + add r0, r13
2.17 + bra L3
2.18 + nop
2.19 +.align 4
2.20 +L1: .long _assert_exception_caught
2.21 +L2: .long \expectpc
2.22 +L3:
2.23 +.endm
2.24 +
2.25 .align 2
2.26 assert_t_set_message:
2.27 .string "Expected T=1 but was 0"
3.1 --- a/test/sh4/testsh4.c Tue Jan 01 02:47:20 2008 +0000
3.2 +++ b/test/sh4/testsh4.c Tue Jan 01 04:32:01 2008 +0000
3.3 @@ -1,4 +1,5 @@
3.4 #include <stdio.h>
3.5 +#include "../lib.h"
3.6
3.7 int total_tests = 0;
3.8 int total_fails = 0;
3.9 @@ -42,6 +43,29 @@
3.10 }
3.11 }
3.12
3.13 +int assert_tlb_exception_caught( char *testname, int number, unsigned int expectedpc,
3.14 + unsigned int vpn )
3.15 +{
3.16 + if( assert_exception_caught(testname, number, expectedpc) == 1 ) {
3.17 + return 1;
3.18 + }
3.19 +
3.20 + unsigned int pteh = long_read(0xFF000000);
3.21 + if( (pteh & 0xFFFFFC00) != (vpn & 0xFFFFFC00) ) {
3.22 + fprintf(stderr, "%s: Test %d failed: Expected PTEH.VPN = %08X, but was %08X\n",
3.23 + testname, number, (vpn>>10), (pteh>>10) );
3.24 + return 1;
3.25 + }
3.26 +
3.27 + unsigned int tea = long_read(0xFF00000C);
3.28 + if( tea != vpn ) {
3.29 + fprintf(stderr, "%s: Test %d failed: Expected TEA = %08X, but was %08X\n",
3.30 + testname, number, vpn, tea );
3.31 + return 1;
3.32 + }
3.33 + return 0;
3.34 +}
3.35 +
3.36 int main()
3.37 {
3.38 fprintf( stdout, "Instruction tests...\n" );
3.39 @@ -77,6 +101,7 @@
3.40 fprintf( stdout, "Exception tests...\n" );
3.41 test_slot_illegal();
3.42 test_undefined();
3.43 + test_tlb();
3.44 remove_interrupt_handler();
3.45
3.46 fprintf( stdout, "Total: %d/%d tests passed (%d%%)\n", total_tests-total_fails,
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/test/sh4/tlb.s Tue Jan 01 04:32:01 2008 +0000
4.3 @@ -0,0 +1,165 @@
4.4 +.section .text
4.5 +.include "sh4/inc.s"
4.6 +!
4.7 +! Test for correct UTLB operation.
4.8 +!
4.9 +! Note we don't test triggering a TLB multiple-hit exception - it's a reset
4.10 +! rather than a regular exception.
4.11 +
4.12 +.global _test_tlb
4.13 +_test_tlb:
4.14 + start_test
4.15 +
4.16 +! Turn on AT, and flush the current TLB (if any)
4.17 +! Initialize to SV=0, SQMD=0, URB=URC=LRUI=0
4.18 + mov.l test_tlb_mmucr, r0
4.19 + mov #5, r1
4.20 + mov.l r1, @r0
4.21 +
4.22 +! Privileged mode tests first (much easier)
4.23 + add #1, r12
4.24 + mov.l test_tlb1_pteh, r1
4.25 + mov.l test_tlb_pteh, r2
4.26 + mov.l r1, @r2
4.27 + mov.l test_tlb1_ptel, r1
4.28 + mov.l test_tlb_ptel, r2
4.29 + mov.l r1, @r2
4.30 + ldtlb
4.31 +
4.32 +! Simple read
4.33 + mov.l test_tlb1_direct, r3
4.34 + mov #42, r2
4.35 + mov.l r2, @r3
4.36 + mov.l test_tlb1_mmu, r0
4.37 + mov.l @r0, r1
4.38 + cmp/eq r1, r2
4.39 + bt test_tlb_2
4.40 + fail test_tlb_str_k
4.41 + bra test_tlb_2
4.42 + nop
4.43 +test_tlb1_pteh:
4.44 + .long 0x12345012
4.45 +test_tlb1_ptel:
4.46 + .long 0x005F8120
4.47 +
4.48 +test_tlb_2:
4.49 + ! Trigger an initial-page-write exception
4.50 + add #1, r12
4.51 + expect_exc 0x00000080
4.52 + mov.l test_tlb1_mmu, r0
4.53 +test_tlb2_exc:
4.54 + mov.l r0, @r0
4.55 + assert_tlb_exc_caught test_tlb_str_k test_tlb2_exc test_tlb1_mmu
4.56 +
4.57 +test_tlb_3:
4.58 + ! Trigger a missing page read exception by invalidation
4.59 + add #1, r12
4.60 + mov.l test_tlb3_addr, r1
4.61 + mov.l test_tlb3_data, r2
4.62 + mov.l r2, @r1
4.63 +
4.64 + expect_exc 0x00000040
4.65 + mov.l test_tlb1_mmu, r0
4.66 +test_tlb3_exc:
4.67 + mov.l @r0, r2
4.68 + assert_tlb_exc_caught test_tlb_str_k, test_tlb3_exc, test_tlb1_mmu
4.69 + bra test_tlb_4
4.70 + nop
4.71 +
4.72 +test_tlb3_addr:
4.73 + .long 0xF6000F80
4.74 +test_tlb3_data:
4.75 + .long 0x12345212
4.76 +
4.77 +test_tlb_4:
4.78 + ! Test missing page write exception on the same page
4.79 + add #1, r12
4.80 + expect_exc 0x00000060
4.81 + mov.l test_tlb1_mmu, r0
4.82 +test_tlb4_exc:
4.83 + mov.l r2, @r0
4.84 + assert_tlb_exc_caught test_tlb_str_k, test_tlb4_exc, test_tlb1_mmu
4.85 +
4.86 +test_tlb_5: ! Test initial write exception
4.87 + add #1, r12
4.88 +
4.89 + mov.l test_tlb5_addr, r1
4.90 + mov.l test_tlb5_data, r2
4.91 + mov.l r2, @r1
4.92 +
4.93 + expect_exc 0x00000080
4.94 + mov.l test_tlb1_mmu, r0
4.95 + mov #63, r3
4.96 +test_tlb5_exc:
4.97 + mov.l r3, @r0
4.98 + assert_tlb_exc_caught test_tlb_str_k, test_tlb5_exc, test_tlb1_mmu
4.99 + mov.l test_tlb1_direct, r3
4.100 + mov.l @r3, r4
4.101 + mov #42, r2
4.102 + cmp/eq r2, r4
4.103 + bf test_tlb5_fail
4.104 + mov.l test_tlb1_mmu, r0
4.105 + mov.l @r0, r3
4.106 + cmp/eq r2, r3
4.107 + bt test_tlb_6
4.108 +test_tlb5_fail:
4.109 + fail test_tlb_str_k
4.110 +
4.111 +test_tlb5_addr:
4.112 + .long 0xF6000F80
4.113 +test_tlb5_data:
4.114 + .long 0x12345112
4.115 +
4.116 +test_tlb_6:! Test successful write.
4.117 + add #1, r12
4.118 +
4.119 + mov.l test_tlb6_addr, r1
4.120 + mov.l test_tlb6_data, r2
4.121 + mov.l r2, @r1
4.122 +
4.123 + mov.l test_tlb1_mmu, r0
4.124 + mov #77, r3
4.125 + mov.l r3, @r0
4.126 + mov.l test_tlb1_direct, r1
4.127 + mov.l @r1, r2
4.128 + cmp/eq r2, r3
4.129 + bt test_tlb_7
4.130 + fail test_tlb_str_k
4.131 + bra test_tlb_7
4.132 + nop
4.133 +
4.134 +test_tlb_7:
4.135 + bra test_tlb_end
4.136 + nop
4.137 +
4.138 +test_tlb6_addr:
4.139 + .long 0xF6000F80
4.140 +test_tlb6_data:
4.141 + .long 0x12345312
4.142 +
4.143 +
4.144 +test_tlb1_mmu:
4.145 + .long 0x12345040
4.146 +test_tlb1_direct:
4.147 + .long 0xA05F8040 ! Display border colour
4.148 +
4.149 +test_tlb_end:
4.150 + xor r0, r0
4.151 + mov.l test_tlb_mmucr, r1
4.152 + mov.l r0, @r1
4.153 +
4.154 + end_test test_tlb_str_k
4.155 +
4.156 +test_tlb_mmucr:
4.157 + .long 0xFF000010
4.158 +test_tlb_pteh:
4.159 + .long 0xFF000000
4.160 +test_tlb_ptel:
4.161 + .long 0xFF000004
4.162 +test_tlb_tea:
4.163 + .long 0xFF00000C
4.164 +test_tlb_str:
4.165 + .string "TLB"
4.166 +.align 4
4.167 +test_tlb_str_k:
4.168 + .long test_tlb_str
.