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lxdream.org :: lxdream :: r56:3224dceaf2a3
lxdream 0.9.1
released Jun 29
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changeset56:3224dceaf2a3
parent55:96323c198da3
child57:5648c0e0638b
authornkeynes
dateSun Jan 01 08:09:42 2006 +0000 (13 years ago)
Implement PVR DMA channel
src/asic.c
src/asic.h
src/pvr2/pvr2.c
src/pvr2/pvr2.h
1.1 --- a/src/asic.c Sun Jan 01 08:09:17 2006 +0000
1.2 +++ b/src/asic.c Sun Jan 01 08:09:42 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.c,v 1.9 2005-12-26 10:48:55 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.10 2006-01-01 08:09:42 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA).
1.10 @@ -23,6 +23,7 @@
1.11 #include "dream.h"
1.12 #include "mem.h"
1.13 #include "sh4/intc.h"
1.14 +#include "sh4/dmac.h"
1.15 #include "dreamcast.h"
1.16 #include "maple/maple.h"
1.17 #include "gdrom/ide.h"
1.18 @@ -55,27 +56,40 @@
1.19 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
1.20 {
1.21 switch( reg ) {
1.22 - case PIRQ0:
1.23 - case PIRQ1:
1.24 - case PIRQ2:
1.25 - /* Clear any interrupts */
1.26 - MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.27 - asic_check_cleared_events();
1.28 - break;
1.29 - case MAPLE_STATE:
1.30 - MMIO_WRITE( ASIC, reg, val );
1.31 - if( val & 1 ) {
1.32 - uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
1.33 - WARN( "Maple request initiated at %08X, halting", maple_addr );
1.34 - maple_handle_buffer( maple_addr );
1.35 - MMIO_WRITE( ASIC, reg, 0 );
1.36 -// dreamcast_stop();
1.37 - }
1.38 - break;
1.39 - default:
1.40 - MMIO_WRITE( ASIC, reg, val );
1.41 - WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
1.42 - reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
1.43 + case PIRQ0:
1.44 + case PIRQ1:
1.45 + case PIRQ2:
1.46 + /* Clear any interrupts */
1.47 + MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.48 + asic_check_cleared_events();
1.49 + break;
1.50 + case MAPLE_STATE:
1.51 + MMIO_WRITE( ASIC, reg, val );
1.52 + if( val & 1 ) {
1.53 + uint32_t maple_addr = MMIO_READ( ASIC, MAPLE_DMA) &0x1FFFFFE0;
1.54 + WARN( "Maple request initiated at %08X, halting", maple_addr );
1.55 + maple_handle_buffer( maple_addr );
1.56 + MMIO_WRITE( ASIC, reg, 0 );
1.57 + }
1.58 + break;
1.59 + case PVRDMACTL: /* Initiate PVR DMA transfer */
1.60 + if( val & 1 ) {
1.61 + uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;
1.62 + uint32_t count = MMIO_READ( ASIC, PVRDMACNT );
1.63 + char *data = alloca( count );
1.64 + uint32_t rcount = DMAC_get_buffer( 2, data, count );
1.65 + if( rcount != count )
1.66 + WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );
1.67 + if( (dest_addr &0xF0000000) == 0x10000000 ) { /* TA */
1.68 + pvr2ta_write( data, rcount );
1.69 + }
1.70 + asic_event( EVENT_PVR_DMA );
1.71 + }
1.72 + break;
1.73 + default:
1.74 + MMIO_WRITE( ASIC, reg, val );
1.75 + WARN( "Write to ASIC (%03X <= %08X) [%s: %s]",
1.76 + reg, val, MMIO_REGID(ASIC,reg), MMIO_REGDESC(ASIC,reg) );
1.77 }
1.78 }
1.79
1.80 @@ -177,14 +191,16 @@
1.81 ide_write_command( (uint8_t)val );
1.82 }
1.83 break;
1.84 -
1.85 default:
1.86 + WARN( "EXTDMA write %08X <= %08X", reg, val );
1.87 +
1.88 MMIO_WRITE( EXTDMA, reg, val );
1.89 }
1.90 }
1.91
1.92 MMIO_REGION_READ_FN( EXTDMA, reg )
1.93 {
1.94 + uint32_t val;
1.95 switch( reg ) {
1.96 case IDEALTSTATUS: return idereg.status;
1.97 case IDEDATA: return ide_read_data_pio( );
1.98 @@ -198,7 +214,9 @@
1.99 ide_clear_interrupt();
1.100 return idereg.status;
1.101 default:
1.102 - return MMIO_READ( EXTDMA, reg );
1.103 + val = MMIO_READ( EXTDMA, reg );
1.104 + DEBUG( "EXTDMA read %08X => %08X", reg, val );
1.105 + return val;
1.106 }
1.107 }
1.108
2.1 --- a/src/asic.h Sun Jan 01 08:09:17 2006 +0000
2.2 +++ b/src/asic.h Sun Jan 01 08:09:42 2006 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: asic.h,v 1.3 2005-12-25 08:24:07 nkeynes Exp $
2.6 + * $Id: asic.h,v 1.4 2006-01-01 08:09:42 nkeynes Exp $
2.7 *
2.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
2.9 * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions,
2.10 @@ -26,10 +26,20 @@
2.11 */
2.12
2.13 MMIO_REGION_BEGIN( 0x005F6000, ASIC, "System ASIC" )
2.14 - LONG_PORT( 0x884, ASICUNK1, PORT_MRW, 0, "ASIC <unknown1>" )
2.15 - LONG_PORT( 0x888, ASICUNK2, PORT_MRW, 0, "ASIC <unknown2>" )
2.16 + LONG_PORT( 0x800, PVRDMADEST, PORT_MRW, 0, "PVR DMA Dest Address" )
2.17 + LONG_PORT( 0x804, PVRDMACNT, PORT_MRW, 0, "PVR DMA Byte Count" )
2.18 + LONG_PORT( 0x808, PVRDMACTL, PORT_MRW, 0, "PVR DMA Control" )
2.19 + LONG_PORT( 0x810, ASICUNK1, PORT_MRW, 0, "ASIC <unknown1>" )
2.20 + LONG_PORT( 0x814, ASICUNK2, PORT_MRW, 0, "ASIC <unknown2>" )
2.21 + LONG_PORT( 0x818, ASICUNK3, PORT_MRW, 0, "ASIC <unknown3>" )
2.22 + LONG_PORT( 0x81C, ASICUNK4, PORT_MRW, 0, "ASIC <unknown4>" )
2.23 + LONG_PORT( 0x884, ASICUNK5, PORT_MRW, 0, "ASIC <unknown5>" )
2.24 + LONG_PORT( 0x888, ASICUNK6, PORT_MRW, 0, "ASIC <unknown6>" )
2.25 LONG_PORT( 0x88C, G2STATUS, PORT_MR, 0, "G2 Bus status" )
2.26 - LONG_PORT( 0x89C, ASICUNK3, PORT_MRW, 0xB, "Unknown, always 0xB?" )
2.27 + LONG_PORT( 0x89C, ASICUNK7, PORT_MRW, 0xB, "Unknown, always 0xB?" )
2.28 + LONG_PORT( 0x8A0, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )
2.29 + LONG_PORT( 0x8A4, ASICUNK9, PORT_MRW, 0, "ASIC <unknown9>" )
2.30 + LONG_PORT( 0x8AC, ASICUNKA, PORT_MRW, 0, "ASIC <unknownA>" )
2.31 LONG_PORT( 0x900, PIRQ0, PORT_MRW, 0, "Pending interrupts 0" )
2.32 LONG_PORT( 0x904, PIRQ1, PORT_MRW, 0, "Pending interrupts 1" )
2.33 LONG_PORT( 0x908, PIRQ2, PORT_MRW, 0, "Pending interrupts 2" )
2.34 @@ -52,7 +62,7 @@
2.35 * what any of it means (nor have I seen any of it accessed), they're not
2.36 * listed above.
2.37 */
2.38 -
2.39 +
2.40
2.41 LONG_PORT( 0xC04, MAPLE_DMA, PORT_MRW, UNDEFINED, "Maple DMA Address" )
2.42 LONG_PORT( 0xC10, MAPLE_RESET2, PORT_MRW, UNDEFINED, "Maple Reset 2" )
2.43 @@ -144,27 +154,35 @@
2.44 LONG_PORT( 0x8B4, SPUDMAUN9, PORT_MRW, 0, "SPU DMA <unknown9>" )
2.45 LONG_PORT( 0x8B8, SPUDMAUN10, PORT_MRW, 0, "SPU DMA <unknown10>" )
2.46 LONG_PORT( 0x8BC, SPUDMAUN11, PORT_MRW, 0, "SPU DMA <unknown11>" )
2.47 - LONG_PORT( 0xC00, PVRDMAEXT, PORT_MRW, 0, "PVR DMA External address" )
2.48 - LONG_PORT( 0xC04, PVRDMASH4, PORT_MRW, 0, "PVR DMA SH4 address" )
2.49 - LONG_PORT( 0xC08, PVRDMASIZ, PORT_MRW, 0, "PVR DMA Size" )
2.50 - LONG_PORT( 0xC0C, PVRDMADIR, PORT_MRW, 0, "PVR DMA Direction" )
2.51 - LONG_PORT( 0xC10, PVRDMAMOD, PORT_MRW, 0, "PVR DMA Mode" )
2.52 - LONG_PORT( 0xC14, PVRDMACTL1, PORT_MRW, 0, "PVR DMA Control 1" )
2.53 - LONG_PORT( 0xC18, PVRDMACTL2, PORT_MRW, 0, "PVR DMA Control 2" )
2.54 - LONG_PORT( 0xC80, PVRDMAUN1, PORT_MRW, 0, "PVR DMA <unknown1>" )
2.55 + LONG_PORT( 0xC00, PVRDMA2EXT, PORT_MRW, 0, "PVR DMA External address" )
2.56 + LONG_PORT( 0xC04, PVRDMA2SH4, PORT_MRW, 0, "PVR DMA SH4 address" )
2.57 + LONG_PORT( 0xC08, PVRDMA2SIZ, PORT_MRW, 0, "PVR DMA Size" )
2.58 + LONG_PORT( 0xC0C, PVRDMA2DIR, PORT_MRW, 0, "PVR DMA Direction" )
2.59 + LONG_PORT( 0xC10, PVRDMA2MOD, PORT_MRW, 0, "PVR DMA Mode" )
2.60 + LONG_PORT( 0xC14, PVRDMA2CTL1, PORT_MRW, 0, "PVR DMA Control 1" )
2.61 + LONG_PORT( 0xC18, PVRDMA2CTL2, PORT_MRW, 0, "PVR DMA Control 2" )
2.62 + LONG_PORT( 0xC80, PVRDMA2UN1, PORT_MRW, 0, "PVR DMA <unknown1>" )
2.63
2.64 MMIO_REGION_END
2.65
2.66 +#define EVENT_PVR_RENDER_DONE 2
2.67 #define EVENT_SCANLINE1 3
2.68 #define EVENT_SCANLINE2 4
2.69 #define EVENT_RETRACE 5
2.70 +#define EVENT_PVR_OPAQUE_DONE 7
2.71 +#define EVENT_PVR_OPAQUEMOD_DONE 8
2.72 +#define EVENT_PVR_TRANS_DONE 9
2.73 +#define EVENT_PVR_TRANSMODE_DONE 10
2.74 #define EVENT_MAPLE_DMA 12
2.75 #define EVENT_MAPLE_ERR 13 /* ??? */
2.76 #define EVENT_GDROM_DMA 14
2.77 -#define EVENT_SPU_DMA0 15 /* ??? */
2.78 +#define EVENT_SPU_DMA0 15
2.79 #define EVENT_SPU_DMA1 16
2.80 #define EVENT_SPU_DMA2 17
2.81 #define EVENT_SPU_DMA3 18
2.82 +#define EVENT_PVR_DMA 19
2.83 +#define EVENT_PVR_PUNCHOUT_DONE 21
2.84 +
2.85 #define EVENT_GDROM_CMD 32
2.86 #define EVENT_AICA 33
2.87
3.1 --- a/src/pvr2/pvr2.c Sun Jan 01 08:09:17 2006 +0000
3.2 +++ b/src/pvr2/pvr2.c Sun Jan 01 08:09:42 2006 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: pvr2.c,v 1.10 2005-12-26 03:54:52 nkeynes Exp $
3.6 + * $Id: pvr2.c,v 1.11 2006-01-01 08:09:42 nkeynes Exp $
3.7 *
3.8 * PVR2 (Video) MMIO and supporting functions.
3.9 *
3.10 @@ -22,6 +22,7 @@
3.11 #include "mem.h"
3.12 #include "asic.h"
3.13 #include "pvr2.h"
3.14 +#include "sh4/sh4core.h"
3.15 #define MMIO_IMPL
3.16 #include "pvr2.h"
3.17
3.18 @@ -38,6 +39,7 @@
3.19 void pvr2_init( void )
3.20 {
3.21 register_io_region( &mmio_region_PVR2 );
3.22 + register_io_region( &mmio_region_PVR2TA );
3.23 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
3.24 }
3.25
3.26 @@ -139,3 +141,21 @@
3.27 {
3.28 mmio_region_PVR2_write( DISPADDR1, base );
3.29 }
3.30 +
3.31 +
3.32 +int32_t mmio_region_PVR2TA_read( uint32_t reg )
3.33 +{
3.34 + return 0xFFFFFFFF;
3.35 +}
3.36 +
3.37 +char pvr2ta_remainder[8];
3.38 +
3.39 +void mmio_region_PVR2TA_write( uint32_t reg, uint32_t val )
3.40 +{
3.41 +
3.42 +}
3.43 +
3.44 +void pvr2ta_write( char *buf, uint32_t length )
3.45 +{
3.46 +
3.47 +}
4.1 --- a/src/pvr2/pvr2.h Sun Jan 01 08:09:17 2006 +0000
4.2 +++ b/src/pvr2/pvr2.h Sun Jan 01 08:09:42 2006 +0000
4.3 @@ -1,5 +1,5 @@
4.4 /**
4.5 - * $Id: pvr2.h,v 1.3 2005-12-25 08:24:07 nkeynes Exp $
4.6 + * $Id: pvr2.h,v 1.4 2006-01-01 08:09:42 nkeynes Exp $
4.7 *
4.8 * PVR2 (video chip) MMIO registers and functions.
4.9 *
4.10 @@ -36,7 +36,7 @@
4.11 LONG_PORT( 0x064, RENDADDR2, PORT_MRW, 0, "Rendering memory base 2" )
4.12 LONG_PORT( 0x068, HCLIP, PORT_MRW, 0, "Horizontal clipping area" )
4.13 LONG_PORT( 0x06C, VCLIP, PORT_MRW, 0, "Vertical clipping area" )
4.14 -LONG_PORT( 0x074, SHADOW, PORT_MRW, 0, "Shadowing" )
4.15 + LONG_PORT( 0x074, SHADOW, PORT_MRW, 0, "Shadowing" )
4.16 LONG_PORT( 0x078, OBJCLIP, PORT_MRW, 0, "Object clip distance (float32)" )
4.17 LONG_PORT( 0x084, TSPCLIP, PORT_MRW, 0, "Texture clip distance (float32)" )
4.18 LONG_PORT( 0x088, BGPLANEZ, PORT_MRW, 0, "Background plane depth (float32)" )
4.19 @@ -70,6 +70,9 @@
4.20 LONG_PORT( 0x164, TAOPLST, PORT_MRW, 0, "TA Object Pointer List start" )
4.21 MMIO_REGION_END
4.22
4.23 +MMIO_REGION_BEGIN( 0x10000000, PVR2TA, "Power VR/2 TA Command port" )
4.24 + LONG_PORT( 0x000, TACMD, PORT_MRW, 0, "TA Command port" )
4.25 +MMIO_REGION_END
4.26
4.27 #define DISPMODE_DE 0x00000001 /* Display enable */
4.28 #define DISPMODE_SD 0x00000002 /* Scan double */
4.29 @@ -98,3 +101,9 @@
4.30
4.31 void pvr2_next_frame( void );
4.32 void pvr2_set_base_address( uint32_t );
4.33 +
4.34 +/**
4.35 + * Process the data in the supplied buffer as an array of TA command lists.
4.36 + * Any excess bytes are held pending until a complete list is sent
4.37 + */
4.38 +void pvr2ta_write( char *buf, uint32_t length );
.