Search
lxdream.org :: lxdream :: r428:338966c8aed0
lxdream 0.9.1
released Jun 29
Download Now
changeset428:338966c8aed0
parent427:00270806b4cf
child429:e581b90c3fb3
authornkeynes
dateSun Oct 07 06:27:12 2007 +0000 (12 years ago)
Fix compilation warnings
src/sh4/scif.c
src/sh4/sh4mmio.c
src/sh4/xltcache.c
1.1 --- a/src/sh4/scif.c Sun Oct 07 06:21:14 2007 +0000
1.2 +++ b/src/sh4/scif.c Sun Oct 07 06:27:12 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: scif.c,v 1.8 2006-01-01 08:08:40 nkeynes Exp $
1.6 + * $Id: scif.c,v 1.9 2007-10-07 06:27:12 nkeynes Exp $
1.7 * SCIF (Serial Communication Interface with FIFO) implementation - part of the
1.8 * SH4 standard on-chip peripheral set. The SCIF is hooked up to the DCs
1.9 * external serial port
1.10 @@ -130,7 +130,7 @@
1.11 #define IS_RECEIVE_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RIE)
1.12 #define IS_RECEIVE_ERROR_IRQ_ENABLED() (MMIO_READ(SCIF,SCSCR2) & (SCSCR2_RIE|SCSCR2_REIE))
1.13 /* Receive is enabled if the RE bit is set in SCSCR2, and the ORER bit is cleared in SCLSR2 */
1.14 -#define IS_RECEIVE_ENABLED() ( (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RE) && (MMIO_READ(SCIF,SCLSR2) & SCLSR2_ORER == 0) )
1.15 +#define IS_RECEIVE_ENABLED() ( (MMIO_READ(SCIF,SCSCR2) & SCSCR2_RE) && ((MMIO_READ(SCIF,SCLSR2) & SCLSR2_ORER) == 0) )
1.16 /* Transmit is enabled if the TE bit is set in SCSCR2 */
1.17 #define IS_TRANSMIT_ENABLED() (MMIO_READ(SCIF,SCSCR2) & SCSCR2_TE)
1.18 #define IS_LOOPBACK_ENABLED() (MMIO_READ(SCIF,SCFCR2) & SCFCR2_LOOP)
1.19 @@ -393,7 +393,7 @@
1.20
1.21 if( sendq_size <= SCIF_sendq.trigger )
1.22 result |= SCFSR2_TDFE;
1.23 - else if( result & SCFSR2_TDFE == 0 && IS_TRANSMIT_IRQ_ENABLED() )
1.24 + else if( (result & SCFSR2_TDFE) == 0 && IS_TRANSMIT_IRQ_ENABLED() )
1.25 intc_clear_interrupt( INT_SCIF_TXI );
1.26
1.27 if( recvq_size >= SCIF_recvq.trigger )
1.28 @@ -481,7 +481,7 @@
1.29 serial_device->set_line_params( val );
1.30 }
1.31 tmp = MMIO_READ( SCIF, SCSMR2 );
1.32 - if( tmp & 0x03 != val & 0x03 ) {
1.33 + if( (tmp & 0x03) != (val & 0x03) ) {
1.34 /* Clock change */
1.35 SCIF_update_line_speed( );
1.36 }
1.37 @@ -502,11 +502,11 @@
1.38 */
1.39 val &= 0x00FA;
1.40 /* Clear any interrupts that just became disabled */
1.41 - if( val & SCSCR2_TIE == 0 )
1.42 + if( (val & SCSCR2_TIE) == 0 )
1.43 intc_clear_interrupt( INT_SCIF_TXI );
1.44 - if( val & SCSCR2_RIE == 0 )
1.45 + if( (val & SCSCR2_RIE) == 0 )
1.46 intc_clear_interrupt( INT_SCIF_RXI );
1.47 - if( val & (SCSCR2_RIE|SCSCR2_REIE) == 0 ) {
1.48 + if( (val & (SCSCR2_RIE|SCSCR2_REIE)) == 0 ) {
1.49 intc_clear_interrupt( INT_SCIF_ERI );
1.50 intc_clear_interrupt( INT_SCIF_BRI );
1.51 }
1.52 @@ -609,7 +609,7 @@
1.53 SCIF_recvq.head != SCIF_recvq.tail &&
1.54 SCIF_recvq_size() < SCIF_recvq.trigger ) {
1.55 uint32_t tmp = MMIO_READ( SCIF, SCFSR2 );
1.56 - if( tmp & SCFSR2_DR == 0 ) {
1.57 + if( (tmp & SCFSR2_DR) == 0 ) {
1.58 MMIO_WRITE( SCIF, SCFSR2, tmp | SCFSR2_DR );
1.59 if( IS_RECEIVE_IRQ_ENABLED() )
1.60 intc_raise_interrupt( INT_SCIF_RXI );
2.1 --- a/src/sh4/sh4mmio.c Sun Oct 07 06:21:14 2007 +0000
2.2 +++ b/src/sh4/sh4mmio.c Sun Oct 07 06:27:12 2007 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: sh4mmio.c,v 1.13 2007-10-02 08:48:27 nkeynes Exp $
2.6 + * $Id: sh4mmio.c,v 1.14 2007-10-07 06:27:12 nkeynes Exp $
2.7 *
2.8 * Miscellaneous and not-really-implemented SH4 peripheral modules. Also
2.9 * responsible for including the IMPL side of the SH4 MMIO pages.
2.10 @@ -20,12 +20,13 @@
2.11 #define MODULE sh4_module
2.12
2.13 #include "dream.h"
2.14 +#include "dreamcast.h"
2.15 #include "mem.h"
2.16 #include "clock.h"
2.17 -#include "sh4core.h"
2.18 -#include "sh4mmio.h"
2.19 +#include "sh4/sh4core.h"
2.20 +#include "sh4/sh4mmio.h"
2.21 #define MMIO_IMPL
2.22 -#include "sh4mmio.h"
2.23 +#include "sh4/sh4mmio.h"
2.24
2.25 /********************************* MMU *************************************/
2.26
2.27 @@ -149,7 +150,6 @@
2.28 int32_t mmio_region_BSC_read( uint32_t reg )
2.29 {
2.30 int32_t val;
2.31 - int i;
2.32 switch( reg ) {
2.33 case PDTRA:
2.34 val = bsc_read_pdtra();
3.1 --- a/src/sh4/xltcache.c Sun Oct 07 06:21:14 2007 +0000
3.2 +++ b/src/sh4/xltcache.c Sun Oct 07 06:27:12 2007 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: xltcache.c,v 1.8 2007-10-06 09:03:24 nkeynes Exp $
3.6 + * $Id: xltcache.c,v 1.9 2007-10-07 06:27:12 nkeynes Exp $
3.7 *
3.8 * Translation cache management. This part is architecture independent.
3.9 *
3.10 @@ -16,11 +16,13 @@
3.11 * GNU General Public License for more details.
3.12 */
3.13
3.14 -#include "sh4/xltcache.h"
3.15 -#include "dreamcast.h"
3.16 #include <sys/mman.h>
3.17 #include <assert.h>
3.18
3.19 +#include "dreamcast.h"
3.20 +#include "sh4/xltcache.h"
3.21 +#include "x86dasm/x86dasm.h"
3.22 +
3.23 #define XLAT_LUT_PAGE_BITS 12
3.24 #define XLAT_LUT_TOTAL_BITS 28
3.25 #define XLAT_LUT_PAGE(addr) (((addr)>>13) & 0xFFFF)
3.26 @@ -371,7 +373,7 @@
3.27 if( xlat_new_cache_ptr->size == 0 ) {
3.28 /* Migrate to the front of the cache to keep it contiguous */
3.29 xlat_new_create_ptr->active = 0;
3.30 - char *olddata = xlat_new_create_ptr->code;
3.31 + unsigned char *olddata = xlat_new_create_ptr->code;
3.32 int oldsize = xlat_new_create_ptr->size;
3.33 int size = oldsize + MIN_BLOCK_SIZE; /* minimum expansion */
3.34 void **lut_entry = xlat_new_create_ptr->lut_entry;
.