lxdream 0.9.1revision 387:38e9fddbf0e3
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raw | bz2 | zip | gz | changeset | 387:38e9fddbf0e3 |
| parent | 386:6fb10951326a |
| child | 388:13bae2fb0373 |
| author | nkeynes |
| date | Tue Sep 18 08:58:23 2007 +0000 (16 years ago) |
Add instruction statistics gathering module
 | src/Makefile.am | view | annotate | diff | log | |
| src/Makefile.in | view | annotate | diff | log | |
| src/sh4/sh4stat.c | view | annotate | diff | log | |
| src/sh4/sh4stat.h | view | annotate | diff | log | |
| src/sh4/sh4stat.in | view | annotate | diff | log |
1.1 --- a/src/Makefile.am Sun Sep 16 07:03:23 2007 +00001.2 +++ b/src/Makefile.am Tue Sep 18 08:58:23 2007 +00001.3 @@ -23,7 +23,7 @@1.4 sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \1.5 sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \1.6 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/xltcache.c sh4/xltcache.h \1.7 - sh4/sh4trans.c sh4/sh4trans.h sh4/sh4x86.c \1.8 + sh4/sh4trans.c sh4/sh4trans.h sh4/sh4x86.c sh4/sh4stat.c sh4/sh4stat.h \1.9 x86dasm/x86dasm.c x86dasm/x86dasm.h \1.10 x86dasm/i386-dis.c x86dasm/dis-init.c x86dasm/dis-buf.c \1.11 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \1.12 @@ -70,3 +70,5 @@1.13 ./gendec sh4/sh4.def sh4/sh4dasm.in -o sh4/sh4dasm.c1.14 sh4/sh4x86.c: gendec sh4/sh4.def sh4/sh4x86.in1.15 ./gendec sh4/sh4.def sh4/sh4x86.in -o sh4/sh4x86.c1.16 +sh4/sh4stat.c: gendec sh4/sh4.def sh4/sh4stat.in1.17 + ./gendec sh4/sh4.def sh4/sh4stat.in -o sh4/sh4stat.c
2.1 --- a/src/Makefile.in Sun Sep 16 07:03:23 2007 +00002.2 +++ b/src/Makefile.in Tue Sep 18 08:58:23 2007 +00002.3 @@ -157,7 +157,7 @@2.4 sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \2.5 sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \2.6 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/xltcache.c sh4/xltcache.h \2.7 - sh4/sh4trans.c sh4/sh4trans.h sh4/sh4x86.c \2.8 + sh4/sh4trans.c sh4/sh4trans.h sh4/sh4x86.c sh4/sh4stat.c sh4/sh4stat.h \2.9 x86dasm/x86dasm.c x86dasm/x86dasm.h \2.10 x86dasm/i386-dis.c x86dasm/dis-init.c x86dasm/dis-buf.c \2.11 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armmem.c \2.12 @@ -221,10 +221,10 @@2.13 intc.$(OBJEXT) sh4mem.$(OBJEXT) timer.$(OBJEXT) dmac.$(OBJEXT) \2.14 sh4core.$(OBJEXT) sh4dasm.$(OBJEXT) sh4mmio.$(OBJEXT) \2.15 scif.$(OBJEXT) xltcache.$(OBJEXT) sh4trans.$(OBJEXT) \2.16 - sh4x86.$(OBJEXT) x86dasm.$(OBJEXT) i386-dis.$(OBJEXT) \2.17 - dis-init.$(OBJEXT) dis-buf.$(OBJEXT) armcore.$(OBJEXT) \2.18 - armdasm.$(OBJEXT) armmem.$(OBJEXT) aica.$(OBJEXT) \2.19 - audio.$(OBJEXT) pvr2.$(OBJEXT) pvr2mem.$(OBJEXT) \2.20 + sh4x86.$(OBJEXT) sh4stat.$(OBJEXT) x86dasm.$(OBJEXT) \2.21 + i386-dis.$(OBJEXT) dis-init.$(OBJEXT) dis-buf.$(OBJEXT) \2.22 + armcore.$(OBJEXT) armdasm.$(OBJEXT) armmem.$(OBJEXT) \2.23 + aica.$(OBJEXT) audio.$(OBJEXT) pvr2.$(OBJEXT) pvr2mem.$(OBJEXT) \2.24 tacore.$(OBJEXT) render.$(OBJEXT) rendcore.$(OBJEXT) \2.25 rendbkg.$(OBJEXT) rendsort.$(OBJEXT) texcache.$(OBJEXT) \2.26 yuv.$(OBJEXT) rendsave.$(OBJEXT) maple.$(OBJEXT) \2.27 @@ -282,15 +282,15 @@2.28 @AMDEP_TRUE@ ./$(DEPDIR)/scif.Po ./$(DEPDIR)/sh4.Po \2.29 @AMDEP_TRUE@ ./$(DEPDIR)/sh4core.Po ./$(DEPDIR)/sh4dasm.Po \2.30 @AMDEP_TRUE@ ./$(DEPDIR)/sh4mem.Po ./$(DEPDIR)/sh4mmio.Po \2.31 -@AMDEP_TRUE@ ./$(DEPDIR)/sh4trans.Po ./$(DEPDIR)/sh4x86.Po \2.32 -@AMDEP_TRUE@ ./$(DEPDIR)/support.Po ./$(DEPDIR)/syscall.Po \2.33 -@AMDEP_TRUE@ ./$(DEPDIR)/tacore.Po ./$(DEPDIR)/testsh4x86.Po \2.34 -@AMDEP_TRUE@ ./$(DEPDIR)/testxlt.Po ./$(DEPDIR)/texcache.Po \2.35 -@AMDEP_TRUE@ ./$(DEPDIR)/timer.Po ./$(DEPDIR)/util.Po \2.36 -@AMDEP_TRUE@ ./$(DEPDIR)/video_gtk.Po ./$(DEPDIR)/video_null.Po \2.37 -@AMDEP_TRUE@ ./$(DEPDIR)/video_x11.Po ./$(DEPDIR)/watch.Po \2.38 -@AMDEP_TRUE@ ./$(DEPDIR)/x86dasm.Po ./$(DEPDIR)/xltcache.Po \2.39 -@AMDEP_TRUE@ ./$(DEPDIR)/yuv.Po2.40 +@AMDEP_TRUE@ ./$(DEPDIR)/sh4stat.Po ./$(DEPDIR)/sh4trans.Po \2.41 +@AMDEP_TRUE@ ./$(DEPDIR)/sh4x86.Po ./$(DEPDIR)/support.Po \2.42 +@AMDEP_TRUE@ ./$(DEPDIR)/syscall.Po ./$(DEPDIR)/tacore.Po \2.43 +@AMDEP_TRUE@ ./$(DEPDIR)/testsh4x86.Po ./$(DEPDIR)/testxlt.Po \2.44 +@AMDEP_TRUE@ ./$(DEPDIR)/texcache.Po ./$(DEPDIR)/timer.Po \2.45 +@AMDEP_TRUE@ ./$(DEPDIR)/util.Po ./$(DEPDIR)/video_gtk.Po \2.46 +@AMDEP_TRUE@ ./$(DEPDIR)/video_null.Po ./$(DEPDIR)/video_x11.Po \2.47 +@AMDEP_TRUE@ ./$(DEPDIR)/watch.Po ./$(DEPDIR)/x86dasm.Po \2.48 +@AMDEP_TRUE@ ./$(DEPDIR)/xltcache.Po ./$(DEPDIR)/yuv.Po2.49 COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \2.50 $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS)2.51 CCLD = $(CC)2.52 @@ -413,6 +413,7 @@2.53 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4dasm.Po@am__quote@2.54 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4mem.Po@am__quote@2.55 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4mmio.Po@am__quote@2.56 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4stat.Po@am__quote@2.57 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4trans.Po@am__quote@2.58 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/sh4x86.Po@am__quote@2.59 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/support.Po@am__quote@2.60 @@ -915,6 +916,28 @@2.61 @AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.62 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o sh4x86.obj `if test -f 'sh4/sh4x86.c'; then $(CYGPATH_W) 'sh4/sh4x86.c'; else $(CYGPATH_W) '$(srcdir)/sh4/sh4x86.c'; fi`2.64 +sh4stat.o: sh4/sh4stat.c2.65 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT sh4stat.o -MD -MP -MF "$(DEPDIR)/sh4stat.Tpo" \2.66 +@am__fastdepCC_TRUE@ -c -o sh4stat.o `test -f 'sh4/sh4stat.c' || echo '$(srcdir)/'`sh4/sh4stat.c; \2.67 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/sh4stat.Tpo" "$(DEPDIR)/sh4stat.Po"; \2.68 +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/sh4stat.Tpo"; exit 1; \2.69 +@am__fastdepCC_TRUE@ fi2.70 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/sh4stat.c' object='sh4stat.o' libtool=no @AMDEPBACKSLASH@2.71 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/sh4stat.Po' tmpdepfile='$(DEPDIR)/sh4stat.TPo' @AMDEPBACKSLASH@2.72 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.73 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o sh4stat.o `test -f 'sh4/sh4stat.c' || echo '$(srcdir)/'`sh4/sh4stat.c2.74 +2.75 +sh4stat.obj: sh4/sh4stat.c2.76 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT sh4stat.obj -MD -MP -MF "$(DEPDIR)/sh4stat.Tpo" \2.77 +@am__fastdepCC_TRUE@ -c -o sh4stat.obj `if test -f 'sh4/sh4stat.c'; then $(CYGPATH_W) 'sh4/sh4stat.c'; else $(CYGPATH_W) '$(srcdir)/sh4/sh4stat.c'; fi`; \2.78 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/sh4stat.Tpo" "$(DEPDIR)/sh4stat.Po"; \2.79 +@am__fastdepCC_TRUE@ else rm -f "$(DEPDIR)/sh4stat.Tpo"; exit 1; \2.80 +@am__fastdepCC_TRUE@ fi2.81 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/sh4stat.c' object='sh4stat.obj' libtool=no @AMDEPBACKSLASH@2.82 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ depfile='$(DEPDIR)/sh4stat.Po' tmpdepfile='$(DEPDIR)/sh4stat.TPo' @AMDEPBACKSLASH@2.83 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.84 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o sh4stat.obj `if test -f 'sh4/sh4stat.c'; then $(CYGPATH_W) 'sh4/sh4stat.c'; else $(CYGPATH_W) '$(srcdir)/sh4/sh4stat.c'; fi`2.85 +2.86 x86dasm.o: x86dasm/x86dasm.c2.87 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT x86dasm.o -MD -MP -MF "$(DEPDIR)/x86dasm.Tpo" \2.88 @am__fastdepCC_TRUE@ -c -o x86dasm.o `test -f 'x86dasm/x86dasm.c' || echo '$(srcdir)/'`x86dasm/x86dasm.c; \2.89 @@ -1991,6 +2014,8 @@2.90 ./gendec sh4/sh4.def sh4/sh4dasm.in -o sh4/sh4dasm.c2.91 sh4/sh4x86.c: gendec sh4/sh4.def sh4/sh4x86.in2.92 ./gendec sh4/sh4.def sh4/sh4x86.in -o sh4/sh4x86.c2.93 +sh4/sh4stat.c: gendec sh4/sh4.def sh4/sh4stat.in2.94 + ./gendec sh4/sh4.def sh4/sh4stat.in -o sh4/sh4stat.c2.95 # Tell versions [3.59,3.63) of GNU make to not export all variables.2.96 # Otherwise a system limit (for SysV at least) may be exceeded.2.97 .NOEXPORT:
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00003.2 +++ b/src/sh4/sh4stat.c Tue Sep 18 08:58:23 2007 +00003.3 @@ -0,0 +1,1670 @@3.4 +/**3.5 + * $Id: sh4stat.c,v 1.1 2007-09-18 08:58:23 nkeynes Exp $3.6 + *3.7 + * Support module for collecting instruction stats3.8 + *3.9 + * Copyright (c) 2005 Nathan Keynes.3.10 + *3.11 + * This program is free software; you can redistribute it and/or modify3.12 + * it under the terms of the GNU General Public License as published by3.13 + * the Free Software Foundation; either version 2 of the License, or3.14 + * (at your option) any later version.3.15 + *3.16 + * This program is distributed in the hope that it will be useful,3.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of3.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the3.19 + * GNU General Public License for more details.3.20 + */3.21 +3.22 +#include "dream.h"3.23 +#include "sh4stat.h"3.24 +#include "sh4core.h"3.25 +3.26 +static uint64_t sh4_stats[SH4_INSTRUCTION_COUNT+1];3.27 +static uint64_t sh4_stats_total;3.28 +static const char *sh4_stats_names[] = {3.29 + "???",3.30 +"ADD Rm, Rn",3.31 +"ADD #imm, Rn",3.32 +"ADDC Rm, Rn",3.33 +"ADDV Rm, Rn",3.34 +"AND Rm, Rn",3.35 +"AND #imm, R0",3.36 +"AND.B #imm, @(R0, GBR)",3.37 +"BF disp",3.38 +"BF/S disp",3.39 +"BRA disp",3.40 +"BRAF Rn",3.41 +"BSR disp",3.42 +"BSRF Rn",3.43 +"BT disp",3.44 +"BT/S disp",3.45 +"CLRMAC",3.46 +"CLRS",3.47 +"CLRT",3.48 +"CMP/EQ Rm, Rn",3.49 +"CMP/EQ #imm, R0",3.50 +"CMP/GE Rm, Rn",3.51 +"CMP/GT Rm, Rn",3.52 +"CMP/HI Rm, Rn",3.53 +"CMP/HS Rm, Rn",3.54 +"CMP/PL Rn",3.55 +"CMP/PZ Rn",3.56 +"CMP/STR Rm, Rn",3.57 +"DIV0S Rm, Rn",3.58 +"DIV0U",3.59 +"DIV1 Rm, Rn",3.60 +"DMULS.L Rm, Rn",3.61 +"DMULU.L Rm, Rn",3.62 +"DT Rn",3.63 +"EXTS.B Rm, Rn",3.64 +"EXTS.W Rm, Rn",3.65 +"EXTU.B Rm, Rn",3.66 +"EXTU.W Rm, Rn",3.67 +"FABS FRn",3.68 +"FADD FRm, FRn",3.69 +"FCMP/EQ FRm, FRn",3.70 +"FCMP/GT FRm, FRn",3.71 +"FCNVDS FRm, FPUL",3.72 +"FCNVSD FPUL, FRn",3.73 +"FDIV FRm, FRn",3.74 +"FIPR FVm, FVn",3.75 +"FLDS FRm, FPUL",3.76 +"FLDI0 FRn",3.77 +"FLDI1 FRn",3.78 +"FLOAT FPUL, FRn",3.79 +"FMAC FR0, FRm, FRn",3.80 +"FMOV FRm, FRn",3.81 +"FMOV FRm, @Rn",3.82 +"FMOV FRm, @-Rn",3.83 +"FMOV FRm, @(R0, Rn)",3.84 +"FMOV @Rm, FRn",3.85 +"FMOV @Rm+, FRn",3.86 +"FMOV @(R0, Rm), FRn",3.87 +"FMUL FRm, FRn",3.88 +"FNEG FRn",3.89 +"FRCHG",3.90 +"FSCA FPUL, FRn",3.91 +"FSCHG",3.92 +"FSQRT FRn",3.93 +"FSRRA FRn",3.94 +"FSTS FPUL, FRn",3.95 +"FSUB FRm, FRn",3.96 +"FTRC FRm, FPUL",3.97 +"FTRV XMTRX, FVn",3.98 +"JMP @Rn",3.99 +"JSR @Rn",3.100 +"LDC Rm, SR",3.101 +"LDC Rm, *",3.102 +"LDC.L @Rm+, SR",3.103 +"LDC.L @Rm+, *",3.104 +"LDS Rm, *",3.105 +"LDS.L @Rm+, *",3.106 +"LDTLB",3.107 +"MAC.L @Rm+, @Rn+",3.108 +"MAC.W @Rm+, @Rn+",3.109 +"MOV Rm, Rn",3.110 +"MOV #imm, Rn",3.111 +"MOV.B ...",3.112 +"MOV.L ...",3.113 +"MOV.L @(disp, PC)",3.114 +"MOV.W ...",3.115 +"MOVA @(disp, PC), R0",3.116 +"MOVCA.L R0, @Rn",3.117 +"MOVT Rn",3.118 +"MUL.L Rm, Rn",3.119 +"MULS.W Rm, Rn",3.120 +"MULU.W Rm, Rn",3.121 +"NEG Rm, Rn",3.122 +"NEGC Rm, Rn",3.123 +"NOP",3.124 +"NOT Rm, Rn",3.125 +"OCBI @Rn",3.126 +"OCBP @Rn",3.127 +"OCBWB @Rn",3.128 +"OR Rm, Rn",3.129 +"OR #imm, R0",3.130 +"OR.B #imm, @(R0, GBR)",3.131 +"PREF @Rn",3.132 +"ROTCL Rn",3.133 +"ROTCR Rn",3.134 +"ROTL Rn",3.135 +"ROTR Rn",3.136 +"RTE",3.137 +"RTS",3.138 +"SETS",3.139 +"SETT",3.140 +"SHAD Rm, Rn",3.141 +"SHAL Rn",3.142 +"SHAR Rn",3.143 +"SHLD Rm, Rn",3.144 +"SHLL* Rn",3.145 +"SHLR* Rn",3.146 +"SLEEP",3.147 +"STC SR, Rn",3.148 +"STC *, Rn",3.149 +"STC.L SR, @-Rn",3.150 +"STC.L *, @-Rn",3.151 +"STS *, Rn",3.152 +"STS.L *, @-Rn",3.153 +"SUB Rm, Rn",3.154 +"SUBC Rm, Rn",3.155 +"SUBV Rm, Rn",3.156 +"SWAP.B Rm, Rn",3.157 +"SWAP.W Rm, Rn",3.158 +"TAS.B @Rn",3.159 +"TRAPA #imm",3.160 +"TST Rm, Rn",3.161 +"TST #imm, R0",3.162 +"TST.B #imm, @(R0, GBR)",3.163 +"XOR Rm, Rn",3.164 +"XOR #imm, R0",3.165 +"XOR.B #imm, @(R0, GBR)",3.166 +"XTRCT Rm, Rn",3.167 +"UNDEF"3.168 +};3.169 +3.170 +void sh4_stats_reset( void )3.171 +{3.172 + int i;3.173 + for( i=0; i<= I_UNDEF; i++ ) {3.174 + sh4_stats[i] = 0;3.175 + }3.176 + sh4_stats_total = 0;3.177 +}3.178 +3.179 +void sh4_stats_print( FILE *out )3.180 +{3.181 + int i;3.182 + for( i=0; i<= I_UNDEF; i++ ) {3.183 + fprintf( out, "%-20s\t%d\t%.2f%\n", sh4_stats_names[i], (uint32_t)sh4_stats[i], ((double)sh4_stats[i])*100.0/(double)sh4_stats_total );3.184 + }3.185 + fprintf( out, "Total: %d\n", sh4_stats_total );3.186 +}3.187 +3.188 +void sh4_stats_add( uint32_t pc )3.189 +{3.190 + uint16_t ir = sh4_read_word(pc);3.191 +#define UNDEF() sh4_stats[0]++3.192 + switch( (ir&0xF000) >> 12 ) {3.193 + case 0x0:3.194 + switch( ir&0xF ) {3.195 + case 0x2:3.196 + switch( (ir&0x80) >> 7 ) {3.197 + case 0x0:3.198 + switch( (ir&0x70) >> 4 ) {3.199 + case 0x0:3.200 + { /* STC SR, Rn */3.201 + uint32_t Rn = ((ir>>8)&0xF);3.202 + sh4_stats[I_STCSR]++;3.203 + }3.204 + break;3.205 + case 0x1:3.206 + { /* STC GBR, Rn */3.207 + uint32_t Rn = ((ir>>8)&0xF);3.208 + sh4_stats[I_STC]++;3.209 + }3.210 + break;3.211 + case 0x2:3.212 + { /* STC VBR, Rn */3.213 + uint32_t Rn = ((ir>>8)&0xF);3.214 + sh4_stats[I_STC]++;3.215 + }3.216 + break;3.217 + case 0x3:3.218 + { /* STC SSR, Rn */3.219 + uint32_t Rn = ((ir>>8)&0xF);3.220 + sh4_stats[I_STC]++;3.221 + }3.222 + break;3.223 + case 0x4:3.224 + { /* STC SPC, Rn */3.225 + uint32_t Rn = ((ir>>8)&0xF);3.226 + sh4_stats[I_STC]++;3.227 + }3.228 + break;3.229 + default:3.230 + UNDEF();3.231 + break;3.232 + }3.233 + break;3.234 + case 0x1:3.235 + { /* STC Rm_BANK, Rn */3.236 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);3.237 + sh4_stats[I_STC]++;3.238 + }3.239 + break;3.240 + }3.241 + break;3.242 + case 0x3:3.243 + switch( (ir&0xF0) >> 4 ) {3.244 + case 0x0:3.245 + { /* BSRF Rn */3.246 + uint32_t Rn = ((ir>>8)&0xF);3.247 + sh4_stats[I_BSRF]++;3.248 + }3.249 + break;3.250 + case 0x2:3.251 + { /* BRAF Rn */3.252 + uint32_t Rn = ((ir>>8)&0xF);3.253 + sh4_stats[I_BRAF]++;3.254 + }3.255 + break;3.256 + case 0x8:3.257 + { /* PREF @Rn */3.258 + uint32_t Rn = ((ir>>8)&0xF);3.259 + sh4_stats[I_PREF]++;3.260 + }3.261 + break;3.262 + case 0x9:3.263 + { /* OCBI @Rn */3.264 + uint32_t Rn = ((ir>>8)&0xF);3.265 + sh4_stats[I_OCBI]++;3.266 + }3.267 + break;3.268 + case 0xA:3.269 + { /* OCBP @Rn */3.270 + uint32_t Rn = ((ir>>8)&0xF);3.271 + sh4_stats[I_OCBP]++;3.272 + }3.273 + break;3.274 + case 0xB:3.275 + { /* OCBWB @Rn */3.276 + uint32_t Rn = ((ir>>8)&0xF);3.277 + sh4_stats[I_OCBWB]++;3.278 + }3.279 + break;3.280 + case 0xC:3.281 + { /* MOVCA.L R0, @Rn */3.282 + uint32_t Rn = ((ir>>8)&0xF);3.283 + sh4_stats[I_MOVCA]++;3.284 + }3.285 + break;3.286 + default:3.287 + UNDEF();3.288 + break;3.289 + }3.290 + break;3.291 + case 0x4:3.292 + { /* MOV.B Rm, @(R0, Rn) */3.293 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.294 + sh4_stats[I_MOVB]++;3.295 + }3.296 + break;3.297 + case 0x5:3.298 + { /* MOV.W Rm, @(R0, Rn) */3.299 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.300 + sh4_stats[I_MOVW]++;3.301 + }3.302 + break;3.303 + case 0x6:3.304 + { /* MOV.L Rm, @(R0, Rn) */3.305 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.306 + sh4_stats[I_MOVL]++;3.307 + }3.308 + break;3.309 + case 0x7:3.310 + { /* MUL.L Rm, Rn */3.311 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.312 + sh4_stats[I_MULL]++;3.313 + }3.314 + break;3.315 + case 0x8:3.316 + switch( (ir&0xFF0) >> 4 ) {3.317 + case 0x0:3.318 + { /* CLRT */3.319 + sh4_stats[I_CLRT]++;3.320 + }3.321 + break;3.322 + case 0x1:3.323 + { /* SETT */3.324 + sh4_stats[I_SETT]++;3.325 + }3.326 + break;3.327 + case 0x2:3.328 + { /* CLRMAC */3.329 + sh4_stats[I_CLRMAC]++;3.330 + }3.331 + break;3.332 + case 0x3:3.333 + { /* LDTLB */3.334 + sh4_stats[I_LDTLB]++;3.335 + }3.336 + break;3.337 + case 0x4:3.338 + { /* CLRS */3.339 + sh4_stats[I_CLRS]++;3.340 + }3.341 + break;3.342 + case 0x5:3.343 + { /* SETS */3.344 + sh4_stats[I_SETS]++;3.345 + }3.346 + break;3.347 + default:3.348 + UNDEF();3.349 + break;3.350 + }3.351 + break;3.352 + case 0x9:3.353 + switch( (ir&0xF0) >> 4 ) {3.354 + case 0x0:3.355 + { /* NOP */3.356 + sh4_stats[I_NOP]++;3.357 + }3.358 + break;3.359 + case 0x1:3.360 + { /* DIV0U */3.361 + sh4_stats[I_DIV0U]++;3.362 + }3.363 + break;3.364 + case 0x2:3.365 + { /* MOVT Rn */3.366 + uint32_t Rn = ((ir>>8)&0xF);3.367 + sh4_stats[I_MOVT]++;3.368 + }3.369 + break;3.370 + default:3.371 + UNDEF();3.372 + break;3.373 + }3.374 + break;3.375 + case 0xA:3.376 + switch( (ir&0xF0) >> 4 ) {3.377 + case 0x0:3.378 + { /* STS MACH, Rn */3.379 + uint32_t Rn = ((ir>>8)&0xF);3.380 + sh4_stats[I_STS]++;3.381 + }3.382 + break;3.383 + case 0x1:3.384 + { /* STS MACL, Rn */3.385 + uint32_t Rn = ((ir>>8)&0xF);3.386 + sh4_stats[I_STS]++;3.387 + }3.388 + break;3.389 + case 0x2:3.390 + { /* STS PR, Rn */3.391 + uint32_t Rn = ((ir>>8)&0xF);3.392 + sh4_stats[I_STS]++;3.393 + }3.394 + break;3.395 + case 0x3:3.396 + { /* STC SGR, Rn */3.397 + uint32_t Rn = ((ir>>8)&0xF);3.398 + sh4_stats[I_STC]++;3.399 + }3.400 + break;3.401 + case 0x5:3.402 + { /* STS FPUL, Rn */3.403 + uint32_t Rn = ((ir>>8)&0xF);3.404 + sh4_stats[I_STS]++;3.405 + }3.406 + break;3.407 + case 0x6:3.408 + { /* STS FPSCR, Rn */3.409 + uint32_t Rn = ((ir>>8)&0xF);3.410 + sh4_stats[I_STS]++;3.411 + }3.412 + break;3.413 + case 0xF:3.414 + { /* STC DBR, Rn */3.415 + uint32_t Rn = ((ir>>8)&0xF);3.416 + sh4_stats[I_STC]++;3.417 + }3.418 + break;3.419 + default:3.420 + UNDEF();3.421 + break;3.422 + }3.423 + break;3.424 + case 0xB:3.425 + switch( (ir&0xFF0) >> 4 ) {3.426 + case 0x0:3.427 + { /* RTS */3.428 + sh4_stats[I_RTS]++;3.429 + }3.430 + break;3.431 + case 0x1:3.432 + { /* SLEEP */3.433 + sh4_stats[I_SLEEP]++;3.434 + }3.435 + break;3.436 + case 0x2:3.437 + { /* RTE */3.438 + sh4_stats[I_RTE]++;3.439 + }3.440 + break;3.441 + default:3.442 + UNDEF();3.443 + break;3.444 + }3.445 + break;3.446 + case 0xC:3.447 + { /* MOV.B @(R0, Rm), Rn */3.448 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.449 + sh4_stats[I_MOVB]++;3.450 + }3.451 + break;3.452 + case 0xD:3.453 + { /* MOV.W @(R0, Rm), Rn */3.454 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.455 + sh4_stats[I_MOVW]++;3.456 + }3.457 + break;3.458 + case 0xE:3.459 + { /* MOV.L @(R0, Rm), Rn */3.460 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.461 + sh4_stats[I_MOVL]++;3.462 + }3.463 + break;3.464 + case 0xF:3.465 + { /* MAC.L @Rm+, @Rn+ */3.466 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.467 + sh4_stats[I_MACL]++;3.468 + }3.469 + break;3.470 + default:3.471 + UNDEF();3.472 + break;3.473 + }3.474 + break;3.475 + case 0x1:3.476 + { /* MOV.L Rm, @(disp, Rn) */3.477 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;3.478 + sh4_stats[I_MOVL]++;3.479 + }3.480 + break;3.481 + case 0x2:3.482 + switch( ir&0xF ) {3.483 + case 0x0:3.484 + { /* MOV.B Rm, @Rn */3.485 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.486 + sh4_stats[I_MOVB]++;3.487 + }3.488 + break;3.489 + case 0x1:3.490 + { /* MOV.W Rm, @Rn */3.491 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.492 + sh4_stats[I_MOVW]++;3.493 + }3.494 + break;3.495 + case 0x2:3.496 + { /* MOV.L Rm, @Rn */3.497 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.498 + sh4_stats[I_MOVL]++;3.499 + }3.500 + break;3.501 + case 0x4:3.502 + { /* MOV.B Rm, @-Rn */3.503 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.504 + sh4_stats[I_MOVB]++;3.505 + }3.506 + break;3.507 + case 0x5:3.508 + { /* MOV.W Rm, @-Rn */3.509 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.510 + sh4_stats[I_MOVW]++;3.511 + }3.512 + break;3.513 + case 0x6:3.514 + { /* MOV.L Rm, @-Rn */3.515 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.516 + sh4_stats[I_MOVL]++;3.517 + }3.518 + break;3.519 + case 0x7:3.520 + { /* DIV0S Rm, Rn */3.521 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.522 + sh4_stats[I_DIV0S]++;3.523 + }3.524 + break;3.525 + case 0x8:3.526 + { /* TST Rm, Rn */3.527 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.528 + sh4_stats[I_TST]++;3.529 + }3.530 + break;3.531 + case 0x9:3.532 + { /* AND Rm, Rn */3.533 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.534 + sh4_stats[I_AND]++;3.535 + }3.536 + break;3.537 + case 0xA:3.538 + { /* XOR Rm, Rn */3.539 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.540 + sh4_stats[I_XOR]++;3.541 + }3.542 + break;3.543 + case 0xB:3.544 + { /* OR Rm, Rn */3.545 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.546 + sh4_stats[I_OR]++;3.547 + }3.548 + break;3.549 + case 0xC:3.550 + { /* CMP/STR Rm, Rn */3.551 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.552 + sh4_stats[I_CMPSTR]++;3.553 + }3.554 + break;3.555 + case 0xD:3.556 + { /* XTRCT Rm, Rn */3.557 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.558 + sh4_stats[I_XTRCT]++;3.559 + }3.560 + break;3.561 + case 0xE:3.562 + { /* MULU.W Rm, Rn */3.563 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.564 + sh4_stats[I_MULUW]++;3.565 + }3.566 + break;3.567 + case 0xF:3.568 + { /* MULS.W Rm, Rn */3.569 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.570 + sh4_stats[I_MULSW]++;3.571 + }3.572 + break;3.573 + default:3.574 + UNDEF();3.575 + break;3.576 + }3.577 + break;3.578 + case 0x3:3.579 + switch( ir&0xF ) {3.580 + case 0x0:3.581 + { /* CMP/EQ Rm, Rn */3.582 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.583 + sh4_stats[I_CMPEQ]++;3.584 + }3.585 + break;3.586 + case 0x2:3.587 + { /* CMP/HS Rm, Rn */3.588 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.589 + sh4_stats[I_CMPHS]++;3.590 + }3.591 + break;3.592 + case 0x3:3.593 + { /* CMP/GE Rm, Rn */3.594 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.595 + sh4_stats[I_CMPGE]++;3.596 + }3.597 + break;3.598 + case 0x4:3.599 + { /* DIV1 Rm, Rn */3.600 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.601 + sh4_stats[I_DIV1]++;3.602 + }3.603 + break;3.604 + case 0x5:3.605 + { /* DMULU.L Rm, Rn */3.606 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.607 + sh4_stats[I_DMULU]++;3.608 + }3.609 + break;3.610 + case 0x6:3.611 + { /* CMP/HI Rm, Rn */3.612 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.613 + sh4_stats[I_CMPHI]++;3.614 + }3.615 + break;3.616 + case 0x7:3.617 + { /* CMP/GT Rm, Rn */3.618 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.619 + sh4_stats[I_CMPGT]++;3.620 + }3.621 + break;3.622 + case 0x8:3.623 + { /* SUB Rm, Rn */3.624 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.625 + sh4_stats[I_SUB]++;3.626 + }3.627 + break;3.628 + case 0xA:3.629 + { /* SUBC Rm, Rn */3.630 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.631 + sh4_stats[I_SUBC]++;3.632 + }3.633 + break;3.634 + case 0xB:3.635 + { /* SUBV Rm, Rn */3.636 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.637 + sh4_stats[I_SUBV]++;3.638 + }3.639 + break;3.640 + case 0xC:3.641 + { /* ADD Rm, Rn */3.642 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.643 + sh4_stats[I_ADD]++;3.644 + }3.645 + break;3.646 + case 0xD:3.647 + { /* DMULS.L Rm, Rn */3.648 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.649 + sh4_stats[I_DMULS]++;3.650 + }3.651 + break;3.652 + case 0xE:3.653 + { /* ADDC Rm, Rn */3.654 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.655 + sh4_stats[I_ADDC]++;3.656 + }3.657 + break;3.658 + case 0xF:3.659 + { /* ADDV Rm, Rn */3.660 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.661 + sh4_stats[I_ADDV]++;3.662 + }3.663 + break;3.664 + default:3.665 + UNDEF();3.666 + break;3.667 + }3.668 + break;3.669 + case 0x4:3.670 + switch( ir&0xF ) {3.671 + case 0x0:3.672 + switch( (ir&0xF0) >> 4 ) {3.673 + case 0x0:3.674 + { /* SHLL Rn */3.675 + uint32_t Rn = ((ir>>8)&0xF);3.676 + sh4_stats[I_SHLL]++;3.677 + }3.678 + break;3.679 + case 0x1:3.680 + { /* DT Rn */3.681 + uint32_t Rn = ((ir>>8)&0xF);3.682 + sh4_stats[I_DT]++;3.683 + }3.684 + break;3.685 + case 0x2:3.686 + { /* SHAL Rn */3.687 + uint32_t Rn = ((ir>>8)&0xF);3.688 + sh4_stats[I_SHAL]++;3.689 + }3.690 + break;3.691 + default:3.692 + UNDEF();3.693 + break;3.694 + }3.695 + break;3.696 + case 0x1:3.697 + switch( (ir&0xF0) >> 4 ) {3.698 + case 0x0:3.699 + { /* SHLR Rn */3.700 + uint32_t Rn = ((ir>>8)&0xF);3.701 + sh4_stats[I_SHLR]++;3.702 + }3.703 + break;3.704 + case 0x1:3.705 + { /* CMP/PZ Rn */3.706 + uint32_t Rn = ((ir>>8)&0xF);3.707 + sh4_stats[I_CMPPZ]++;3.708 + }3.709 + break;3.710 + case 0x2:3.711 + { /* SHAR Rn */3.712 + uint32_t Rn = ((ir>>8)&0xF);3.713 + sh4_stats[I_SHAR]++;3.714 + }3.715 + break;3.716 + default:3.717 + UNDEF();3.718 + break;3.719 + }3.720 + break;3.721 + case 0x2:3.722 + switch( (ir&0xF0) >> 4 ) {3.723 + case 0x0:3.724 + { /* STS.L MACH, @-Rn */3.725 + uint32_t Rn = ((ir>>8)&0xF);3.726 + sh4_stats[I_STSM]++;3.727 + }3.728 + break;3.729 + case 0x1:3.730 + { /* STS.L MACL, @-Rn */3.731 + uint32_t Rn = ((ir>>8)&0xF);3.732 + sh4_stats[I_STSM]++;3.733 + }3.734 + break;3.735 + case 0x2:3.736 + { /* STS.L PR, @-Rn */3.737 + uint32_t Rn = ((ir>>8)&0xF);3.738 + sh4_stats[I_STSM]++;3.739 + }3.740 + break;3.741 + case 0x3:3.742 + { /* STC.L SGR, @-Rn */3.743 + uint32_t Rn = ((ir>>8)&0xF);3.744 + sh4_stats[I_STCM]++;3.745 + }3.746 + break;3.747 + case 0x5:3.748 + { /* STS.L FPUL, @-Rn */3.749 + uint32_t Rn = ((ir>>8)&0xF);3.750 + sh4_stats[I_STSM]++;3.751 + }3.752 + break;3.753 + case 0x6:3.754 + { /* STS.L FPSCR, @-Rn */3.755 + uint32_t Rn = ((ir>>8)&0xF);3.756 + sh4_stats[I_STSM]++;3.757 + }3.758 + break;3.759 + case 0xF:3.760 + { /* STC.L DBR, @-Rn */3.761 + uint32_t Rn = ((ir>>8)&0xF);3.762 + sh4_stats[I_STCM]++;3.763 + }3.764 + break;3.765 + default:3.766 + UNDEF();3.767 + break;3.768 + }3.769 + break;3.770 + case 0x3:3.771 + switch( (ir&0x80) >> 7 ) {3.772 + case 0x0:3.773 + switch( (ir&0x70) >> 4 ) {3.774 + case 0x0:3.775 + { /* STC.L SR, @-Rn */3.776 + uint32_t Rn = ((ir>>8)&0xF);3.777 + sh4_stats[I_STCSRM]++;3.778 + }3.779 + break;3.780 + case 0x1:3.781 + { /* STC.L GBR, @-Rn */3.782 + uint32_t Rn = ((ir>>8)&0xF);3.783 + sh4_stats[I_STCM]++;3.784 + }3.785 + break;3.786 + case 0x2:3.787 + { /* STC.L VBR, @-Rn */3.788 + uint32_t Rn = ((ir>>8)&0xF);3.789 + sh4_stats[I_STCM]++;3.790 + }3.791 + break;3.792 + case 0x3:3.793 + { /* STC.L SSR, @-Rn */3.794 + uint32_t Rn = ((ir>>8)&0xF);3.795 + sh4_stats[I_STCM]++;3.796 + }3.797 + break;3.798 + case 0x4:3.799 + { /* STC.L SPC, @-Rn */3.800 + uint32_t Rn = ((ir>>8)&0xF);3.801 + sh4_stats[I_STCM]++;3.802 + }3.803 + break;3.804 + default:3.805 + UNDEF();3.806 + break;3.807 + }3.808 + break;3.809 + case 0x1:3.810 + { /* STC.L Rm_BANK, @-Rn */3.811 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm_BANK = ((ir>>4)&0x7);3.812 + sh4_stats[I_STCM]++;3.813 + }3.814 + break;3.815 + }3.816 + break;3.817 + case 0x4:3.818 + switch( (ir&0xF0) >> 4 ) {3.819 + case 0x0:3.820 + { /* ROTL Rn */3.821 + uint32_t Rn = ((ir>>8)&0xF);3.822 + sh4_stats[I_ROTL]++;3.823 + }3.824 + break;3.825 + case 0x2:3.826 + { /* ROTCL Rn */3.827 + uint32_t Rn = ((ir>>8)&0xF);3.828 + sh4_stats[I_ROTCL]++;3.829 + }3.830 + break;3.831 + default:3.832 + UNDEF();3.833 + break;3.834 + }3.835 + break;3.836 + case 0x5:3.837 + switch( (ir&0xF0) >> 4 ) {3.838 + case 0x0:3.839 + { /* ROTR Rn */3.840 + uint32_t Rn = ((ir>>8)&0xF);3.841 + sh4_stats[I_ROTR]++;3.842 + }3.843 + break;3.844 + case 0x1:3.845 + { /* CMP/PL Rn */3.846 + uint32_t Rn = ((ir>>8)&0xF);3.847 + sh4_stats[I_CMPPL]++;3.848 + }3.849 + break;3.850 + case 0x2:3.851 + { /* ROTCR Rn */3.852 + uint32_t Rn = ((ir>>8)&0xF);3.853 + sh4_stats[I_ROTCR]++;3.854 + }3.855 + break;3.856 + default:3.857 + UNDEF();3.858 + break;3.859 + }3.860 + break;3.861 + case 0x6:3.862 + switch( (ir&0xF0) >> 4 ) {3.863 + case 0x0:3.864 + { /* LDS.L @Rm+, MACH */3.865 + uint32_t Rm = ((ir>>8)&0xF);3.866 + sh4_stats[I_LDSM]++;3.867 + }3.868 + break;3.869 + case 0x1:3.870 + { /* LDS.L @Rm+, MACL */3.871 + uint32_t Rm = ((ir>>8)&0xF);3.872 + sh4_stats[I_LDSM]++;3.873 + }3.874 + break;3.875 + case 0x2:3.876 + { /* LDS.L @Rm+, PR */3.877 + uint32_t Rm = ((ir>>8)&0xF);3.878 + sh4_stats[I_LDSM]++;3.879 + }3.880 + break;3.881 + case 0x3:3.882 + { /* LDC.L @Rm+, SGR */3.883 + uint32_t Rm = ((ir>>8)&0xF);3.884 + sh4_stats[I_LDCM]++;3.885 + }3.886 + break;3.887 + case 0x5:3.888 + { /* LDS.L @Rm+, FPUL */3.889 + uint32_t Rm = ((ir>>8)&0xF);3.890 + sh4_stats[I_LDSM]++;3.891 + }3.892 + break;3.893 + case 0x6:3.894 + { /* LDS.L @Rm+, FPSCR */3.895 + uint32_t Rm = ((ir>>8)&0xF);3.896 + sh4_stats[I_LDSM]++;3.897 + }3.898 + break;3.899 + case 0xF:3.900 + { /* LDC.L @Rm+, DBR */3.901 + uint32_t Rm = ((ir>>8)&0xF);3.902 + sh4_stats[I_LDCM]++;3.903 + }3.904 + break;3.905 + default:3.906 + UNDEF();3.907 + break;3.908 + }3.909 + break;3.910 + case 0x7:3.911 + switch( (ir&0x80) >> 7 ) {3.912 + case 0x0:3.913 + switch( (ir&0x70) >> 4 ) {3.914 + case 0x0:3.915 + { /* LDC.L @Rm+, SR */3.916 + uint32_t Rm = ((ir>>8)&0xF);3.917 + sh4_stats[I_LDCSRM]++;3.918 + }3.919 + break;3.920 + case 0x1:3.921 + { /* LDC.L @Rm+, GBR */3.922 + uint32_t Rm = ((ir>>8)&0xF);3.923 + sh4_stats[I_LDCM]++;3.924 + }3.925 + break;3.926 + case 0x2:3.927 + { /* LDC.L @Rm+, VBR */3.928 + uint32_t Rm = ((ir>>8)&0xF);3.929 + sh4_stats[I_LDCM]++;3.930 + }3.931 + break;3.932 + case 0x3:3.933 + { /* LDC.L @Rm+, SSR */3.934 + uint32_t Rm = ((ir>>8)&0xF);3.935 + sh4_stats[I_LDCM]++;3.936 + }3.937 + break;3.938 + case 0x4:3.939 + { /* LDC.L @Rm+, SPC */3.940 + uint32_t Rm = ((ir>>8)&0xF);3.941 + sh4_stats[I_LDCM]++;3.942 + }3.943 + break;3.944 + default:3.945 + UNDEF();3.946 + break;3.947 + }3.948 + break;3.949 + case 0x1:3.950 + { /* LDC.L @Rm+, Rn_BANK */3.951 + uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);3.952 + sh4_stats[I_LDCM]++;3.953 + }3.954 + break;3.955 + }3.956 + break;3.957 + case 0x8:3.958 + switch( (ir&0xF0) >> 4 ) {3.959 + case 0x0:3.960 + { /* SHLL2 Rn */3.961 + uint32_t Rn = ((ir>>8)&0xF);3.962 + sh4_stats[I_SHLL]++;3.963 + }3.964 + break;3.965 + case 0x1:3.966 + { /* SHLL8 Rn */3.967 + uint32_t Rn = ((ir>>8)&0xF);3.968 + sh4_stats[I_SHLL]++;3.969 + }3.970 + break;3.971 + case 0x2:3.972 + { /* SHLL16 Rn */3.973 + uint32_t Rn = ((ir>>8)&0xF);3.974 + sh4_stats[I_SHLL]++;3.975 + }3.976 + break;3.977 + default:3.978 + UNDEF();3.979 + break;3.980 + }3.981 + break;3.982 + case 0x9:3.983 + switch( (ir&0xF0) >> 4 ) {3.984 + case 0x0:3.985 + { /* SHLR2 Rn */3.986 + uint32_t Rn = ((ir>>8)&0xF);3.987 + sh4_stats[I_SHLR]++;3.988 + }3.989 + break;3.990 + case 0x1:3.991 + { /* SHLR8 Rn */3.992 + uint32_t Rn = ((ir>>8)&0xF);3.993 + sh4_stats[I_SHLR]++;3.994 + }3.995 + break;3.996 + case 0x2:3.997 + { /* SHLR16 Rn */3.998 + uint32_t Rn = ((ir>>8)&0xF);3.999 + sh4_stats[I_SHLR]++;3.1000 + }3.1001 + break;3.1002 + default:3.1003 + UNDEF();3.1004 + break;3.1005 + }3.1006 + break;3.1007 + case 0xA:3.1008 + switch( (ir&0xF0) >> 4 ) {3.1009 + case 0x0:3.1010 + { /* LDS Rm, MACH */3.1011 + uint32_t Rm = ((ir>>8)&0xF);3.1012 + sh4_stats[I_LDS]++;3.1013 + }3.1014 + break;3.1015 + case 0x1:3.1016 + { /* LDS Rm, MACL */3.1017 + uint32_t Rm = ((ir>>8)&0xF);3.1018 + sh4_stats[I_LDS]++;3.1019 + }3.1020 + break;3.1021 + case 0x2:3.1022 + { /* LDS Rm, PR */3.1023 + uint32_t Rm = ((ir>>8)&0xF);3.1024 + sh4_stats[I_LDS]++;3.1025 + }3.1026 + break;3.1027 + case 0x3:3.1028 + { /* LDC Rm, SGR */3.1029 + uint32_t Rm = ((ir>>8)&0xF);3.1030 + sh4_stats[I_LDC]++;3.1031 + }3.1032 + break;3.1033 + case 0x5:3.1034 + { /* LDS Rm, FPUL */3.1035 + uint32_t Rm = ((ir>>8)&0xF);3.1036 + sh4_stats[I_LDS]++;3.1037 + }3.1038 + break;3.1039 + case 0x6:3.1040 + { /* LDS Rm, FPSCR */3.1041 + uint32_t Rm = ((ir>>8)&0xF);3.1042 + sh4_stats[I_LDS]++;3.1043 + }3.1044 + break;3.1045 + case 0xF:3.1046 + { /* LDC Rm, DBR */3.1047 + uint32_t Rm = ((ir>>8)&0xF);3.1048 + sh4_stats[I_LDC]++;3.1049 + }3.1050 + break;3.1051 + default:3.1052 + UNDEF();3.1053 + break;3.1054 + }3.1055 + break;3.1056 + case 0xB:3.1057 + switch( (ir&0xF0) >> 4 ) {3.1058 + case 0x0:3.1059 + { /* JSR @Rn */3.1060 + uint32_t Rn = ((ir>>8)&0xF);3.1061 + sh4_stats[I_JSR]++;3.1062 + }3.1063 + break;3.1064 + case 0x1:3.1065 + { /* TAS.B @Rn */3.1066 + uint32_t Rn = ((ir>>8)&0xF);3.1067 + sh4_stats[I_TASB]++;3.1068 + }3.1069 + break;3.1070 + case 0x2:3.1071 + { /* JMP @Rn */3.1072 + uint32_t Rn = ((ir>>8)&0xF);3.1073 + sh4_stats[I_JMP]++;3.1074 + }3.1075 + break;3.1076 + default:3.1077 + UNDEF();3.1078 + break;3.1079 + }3.1080 + break;3.1081 + case 0xC:3.1082 + { /* SHAD Rm, Rn */3.1083 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1084 + sh4_stats[I_SHAD]++;3.1085 + }3.1086 + break;3.1087 + case 0xD:3.1088 + { /* SHLD Rm, Rn */3.1089 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1090 + sh4_stats[I_SHLD]++;3.1091 + }3.1092 + break;3.1093 + case 0xE:3.1094 + switch( (ir&0x80) >> 7 ) {3.1095 + case 0x0:3.1096 + switch( (ir&0x70) >> 4 ) {3.1097 + case 0x0:3.1098 + { /* LDC Rm, SR */3.1099 + uint32_t Rm = ((ir>>8)&0xF);3.1100 + sh4_stats[I_LDCSR]++;3.1101 + }3.1102 + break;3.1103 + case 0x1:3.1104 + { /* LDC Rm, GBR */3.1105 + uint32_t Rm = ((ir>>8)&0xF);3.1106 + sh4_stats[I_LDC]++;3.1107 + }3.1108 + break;3.1109 + case 0x2:3.1110 + { /* LDC Rm, VBR */3.1111 + uint32_t Rm = ((ir>>8)&0xF);3.1112 + sh4_stats[I_LDC]++;3.1113 + }3.1114 + break;3.1115 + case 0x3:3.1116 + { /* LDC Rm, SSR */3.1117 + uint32_t Rm = ((ir>>8)&0xF);3.1118 + sh4_stats[I_LDC]++;3.1119 + }3.1120 + break;3.1121 + case 0x4:3.1122 + { /* LDC Rm, SPC */3.1123 + uint32_t Rm = ((ir>>8)&0xF);3.1124 + sh4_stats[I_LDC]++;3.1125 + }3.1126 + break;3.1127 + default:3.1128 + UNDEF();3.1129 + break;3.1130 + }3.1131 + break;3.1132 + case 0x1:3.1133 + { /* LDC Rm, Rn_BANK */3.1134 + uint32_t Rm = ((ir>>8)&0xF); uint32_t Rn_BANK = ((ir>>4)&0x7);3.1135 + sh4_stats[I_LDC]++;3.1136 + }3.1137 + break;3.1138 + }3.1139 + break;3.1140 + case 0xF:3.1141 + { /* MAC.W @Rm+, @Rn+ */3.1142 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1143 + sh4_stats[I_MACW]++;3.1144 + }3.1145 + break;3.1146 + }3.1147 + break;3.1148 + case 0x5:3.1149 + { /* MOV.L @(disp, Rm), Rn */3.1150 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<2;3.1151 + sh4_stats[I_MOVL]++;3.1152 + }3.1153 + break;3.1154 + case 0x6:3.1155 + switch( ir&0xF ) {3.1156 + case 0x0:3.1157 + { /* MOV.B @Rm, Rn */3.1158 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1159 + sh4_stats[I_MOVB]++;3.1160 + }3.1161 + break;3.1162 + case 0x1:3.1163 + { /* MOV.W @Rm, Rn */3.1164 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1165 + sh4_stats[I_MOVW]++;3.1166 + }3.1167 + break;3.1168 + case 0x2:3.1169 + { /* MOV.L @Rm, Rn */3.1170 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1171 + sh4_stats[I_MOVL]++;3.1172 + }3.1173 + break;3.1174 + case 0x3:3.1175 + { /* MOV Rm, Rn */3.1176 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1177 + sh4_stats[I_MOV]++;3.1178 + }3.1179 + break;3.1180 + case 0x4:3.1181 + { /* MOV.B @Rm+, Rn */3.1182 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1183 + sh4_stats[I_MOVB]++;3.1184 + }3.1185 + break;3.1186 + case 0x5:3.1187 + { /* MOV.W @Rm+, Rn */3.1188 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1189 + sh4_stats[I_MOVW]++;3.1190 + }3.1191 + break;3.1192 + case 0x6:3.1193 + { /* MOV.L @Rm+, Rn */3.1194 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1195 + sh4_stats[I_MOVL]++;3.1196 + }3.1197 + break;3.1198 + case 0x7:3.1199 + { /* NOT Rm, Rn */3.1200 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1201 + sh4_stats[I_NOT]++;3.1202 + }3.1203 + break;3.1204 + case 0x8:3.1205 + { /* SWAP.B Rm, Rn */3.1206 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1207 + sh4_stats[I_SWAPB]++;3.1208 + }3.1209 + break;3.1210 + case 0x9:3.1211 + { /* SWAP.W Rm, Rn */3.1212 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1213 + sh4_stats[I_SWAPW]++;3.1214 + }3.1215 + break;3.1216 + case 0xA:3.1217 + { /* NEGC Rm, Rn */3.1218 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1219 + sh4_stats[I_NEGC]++;3.1220 + }3.1221 + break;3.1222 + case 0xB:3.1223 + { /* NEG Rm, Rn */3.1224 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1225 + sh4_stats[I_NEG]++;3.1226 + }3.1227 + break;3.1228 + case 0xC:3.1229 + { /* EXTU.B Rm, Rn */3.1230 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1231 + sh4_stats[I_EXTUB]++;3.1232 + }3.1233 + break;3.1234 + case 0xD:3.1235 + { /* EXTU.W Rm, Rn */3.1236 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1237 + sh4_stats[I_EXTUW]++;3.1238 + }3.1239 + break;3.1240 + case 0xE:3.1241 + { /* EXTS.B Rm, Rn */3.1242 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1243 + sh4_stats[I_EXTSB]++;3.1244 + }3.1245 + break;3.1246 + case 0xF:3.1247 + { /* EXTS.W Rm, Rn */3.1248 + uint32_t Rn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1249 + sh4_stats[I_EXTSW]++;3.1250 + }3.1251 + break;3.1252 + }3.1253 + break;3.1254 + case 0x7:3.1255 + { /* ADD #imm, Rn */3.1256 + uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);3.1257 + sh4_stats[I_ADDI]++;3.1258 + }3.1259 + break;3.1260 + case 0x8:3.1261 + switch( (ir&0xF00) >> 8 ) {3.1262 + case 0x0:3.1263 + { /* MOV.B R0, @(disp, Rn) */3.1264 + uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);3.1265 + sh4_stats[I_MOVB]++;3.1266 + }3.1267 + break;3.1268 + case 0x1:3.1269 + { /* MOV.W R0, @(disp, Rn) */3.1270 + uint32_t Rn = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;3.1271 + sh4_stats[I_MOVW]++;3.1272 + }3.1273 + break;3.1274 + case 0x4:3.1275 + { /* MOV.B @(disp, Rm), R0 */3.1276 + uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF);3.1277 + sh4_stats[I_MOVB]++;3.1278 + }3.1279 + break;3.1280 + case 0x5:3.1281 + { /* MOV.W @(disp, Rm), R0 */3.1282 + uint32_t Rm = ((ir>>4)&0xF); uint32_t disp = (ir&0xF)<<1;3.1283 + sh4_stats[I_MOVW]++;3.1284 + }3.1285 + break;3.1286 + case 0x8:3.1287 + { /* CMP/EQ #imm, R0 */3.1288 + int32_t imm = SIGNEXT8(ir&0xFF);3.1289 + sh4_stats[I_CMPEQI]++;3.1290 + }3.1291 + break;3.1292 + case 0x9:3.1293 + { /* BT disp */3.1294 + int32_t disp = SIGNEXT8(ir&0xFF)<<1;3.1295 + sh4_stats[I_BT]++;3.1296 + }3.1297 + break;3.1298 + case 0xB:3.1299 + { /* BF disp */3.1300 + int32_t disp = SIGNEXT8(ir&0xFF)<<1;3.1301 + sh4_stats[I_BF]++;3.1302 + }3.1303 + break;3.1304 + case 0xD:3.1305 + { /* BT/S disp */3.1306 + int32_t disp = SIGNEXT8(ir&0xFF)<<1;3.1307 + sh4_stats[I_BTS]++;3.1308 + }3.1309 + break;3.1310 + case 0xF:3.1311 + { /* BF/S disp */3.1312 + int32_t disp = SIGNEXT8(ir&0xFF)<<1;3.1313 + sh4_stats[I_BFS]++;3.1314 + }3.1315 + break;3.1316 + default:3.1317 + UNDEF();3.1318 + break;3.1319 + }3.1320 + break;3.1321 + case 0x9:3.1322 + { /* MOV.W @(disp, PC), Rn */3.1323 + uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<1;3.1324 + sh4_stats[I_MOVW]++;3.1325 + }3.1326 + break;3.1327 + case 0xA:3.1328 + { /* BRA disp */3.1329 + int32_t disp = SIGNEXT12(ir&0xFFF)<<1;3.1330 + sh4_stats[I_BRA]++;3.1331 + }3.1332 + break;3.1333 + case 0xB:3.1334 + { /* BSR disp */3.1335 + int32_t disp = SIGNEXT12(ir&0xFFF)<<1;3.1336 + sh4_stats[I_BSR]++;3.1337 + }3.1338 + break;3.1339 + case 0xC:3.1340 + switch( (ir&0xF00) >> 8 ) {3.1341 + case 0x0:3.1342 + { /* MOV.B R0, @(disp, GBR) */3.1343 + uint32_t disp = (ir&0xFF);3.1344 + sh4_stats[I_MOVB]++;3.1345 + }3.1346 + break;3.1347 + case 0x1:3.1348 + { /* MOV.W R0, @(disp, GBR) */3.1349 + uint32_t disp = (ir&0xFF)<<1;3.1350 + sh4_stats[I_MOVW]++;3.1351 + }3.1352 + break;3.1353 + case 0x2:3.1354 + { /* MOV.L R0, @(disp, GBR) */3.1355 + uint32_t disp = (ir&0xFF)<<2;3.1356 + sh4_stats[I_MOVL]++;3.1357 + }3.1358 + break;3.1359 + case 0x3:3.1360 + { /* TRAPA #imm */3.1361 + uint32_t imm = (ir&0xFF);3.1362 + sh4_stats[I_TRAPA]++;3.1363 + }3.1364 + break;3.1365 + case 0x4:3.1366 + { /* MOV.B @(disp, GBR), R0 */3.1367 + uint32_t disp = (ir&0xFF);3.1368 + sh4_stats[I_MOVB]++;3.1369 + }3.1370 + break;3.1371 + case 0x5:3.1372 + { /* MOV.W @(disp, GBR), R0 */3.1373 + uint32_t disp = (ir&0xFF)<<1;3.1374 + sh4_stats[I_MOVW]++;3.1375 + }3.1376 + break;3.1377 + case 0x6:3.1378 + { /* MOV.L @(disp, GBR), R0 */3.1379 + uint32_t disp = (ir&0xFF)<<2;3.1380 + sh4_stats[I_MOVL]++;3.1381 + }3.1382 + break;3.1383 + case 0x7:3.1384 + { /* MOVA @(disp, PC), R0 */3.1385 + uint32_t disp = (ir&0xFF)<<2;3.1386 + sh4_stats[I_MOVA]++;3.1387 + }3.1388 + break;3.1389 + case 0x8:3.1390 + { /* TST #imm, R0 */3.1391 + uint32_t imm = (ir&0xFF);3.1392 + sh4_stats[I_TSTI]++;3.1393 + }3.1394 + break;3.1395 + case 0x9:3.1396 + { /* AND #imm, R0 */3.1397 + uint32_t imm = (ir&0xFF);3.1398 + sh4_stats[I_ANDI]++;3.1399 + }3.1400 + break;3.1401 + case 0xA:3.1402 + { /* XOR #imm, R0 */3.1403 + uint32_t imm = (ir&0xFF);3.1404 + sh4_stats[I_XORI]++;3.1405 + }3.1406 + break;3.1407 + case 0xB:3.1408 + { /* OR #imm, R0 */3.1409 + uint32_t imm = (ir&0xFF);3.1410 + sh4_stats[I_ORI]++;3.1411 + }3.1412 + break;3.1413 + case 0xC:3.1414 + { /* TST.B #imm, @(R0, GBR) */3.1415 + uint32_t imm = (ir&0xFF);3.1416 + sh4_stats[I_TSTB]++;3.1417 + }3.1418 + break;3.1419 + case 0xD:3.1420 + { /* AND.B #imm, @(R0, GBR) */3.1421 + uint32_t imm = (ir&0xFF);3.1422 + sh4_stats[I_ANDB]++;3.1423 + }3.1424 + break;3.1425 + case 0xE:3.1426 + { /* XOR.B #imm, @(R0, GBR) */3.1427 + uint32_t imm = (ir&0xFF);3.1428 + sh4_stats[I_XORB]++;3.1429 + }3.1430 + break;3.1431 + case 0xF:3.1432 + { /* OR.B #imm, @(R0, GBR) */3.1433 + uint32_t imm = (ir&0xFF);3.1434 + sh4_stats[I_ORB]++;3.1435 + }3.1436 + break;3.1437 + }3.1438 + break;3.1439 + case 0xD:3.1440 + { /* MOV.L @(disp, PC), Rn */3.1441 + uint32_t Rn = ((ir>>8)&0xF); uint32_t disp = (ir&0xFF)<<2;3.1442 + sh4_stats[I_MOVLPC]++;3.1443 + }3.1444 + break;3.1445 + case 0xE:3.1446 + { /* MOV #imm, Rn */3.1447 + uint32_t Rn = ((ir>>8)&0xF); int32_t imm = SIGNEXT8(ir&0xFF);3.1448 + sh4_stats[I_MOVI]++;3.1449 + }3.1450 + break;3.1451 + case 0xF:3.1452 + switch( ir&0xF ) {3.1453 + case 0x0:3.1454 + { /* FADD FRm, FRn */3.1455 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1456 + sh4_stats[I_FADD]++;3.1457 + }3.1458 + break;3.1459 + case 0x1:3.1460 + { /* FSUB FRm, FRn */3.1461 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1462 + sh4_stats[I_FSUB]++;3.1463 + }3.1464 + break;3.1465 + case 0x2:3.1466 + { /* FMUL FRm, FRn */3.1467 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1468 + sh4_stats[I_FMUL]++;3.1469 + }3.1470 + break;3.1471 + case 0x3:3.1472 + { /* FDIV FRm, FRn */3.1473 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1474 + sh4_stats[I_FDIV]++;3.1475 + }3.1476 + break;3.1477 + case 0x4:3.1478 + { /* FCMP/EQ FRm, FRn */3.1479 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1480 + sh4_stats[I_FCMPEQ]++;3.1481 + }3.1482 + break;3.1483 + case 0x5:3.1484 + { /* FCMP/GT FRm, FRn */3.1485 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1486 + sh4_stats[I_FCMPGT]++;3.1487 + }3.1488 + break;3.1489 + case 0x6:3.1490 + { /* FMOV @(R0, Rm), FRn */3.1491 + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1492 + sh4_stats[I_FMOV7]++;3.1493 + }3.1494 + break;3.1495 + case 0x7:3.1496 + { /* FMOV FRm, @(R0, Rn) */3.1497 + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1498 + sh4_stats[I_FMOV4]++;3.1499 + }3.1500 + break;3.1501 + case 0x8:3.1502 + { /* FMOV @Rm, FRn */3.1503 + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1504 + sh4_stats[I_FMOV5]++;3.1505 + }3.1506 + break;3.1507 + case 0x9:3.1508 + { /* FMOV @Rm+, FRn */3.1509 + uint32_t FRn = ((ir>>8)&0xF); uint32_t Rm = ((ir>>4)&0xF);3.1510 + sh4_stats[I_FMOV6]++;3.1511 + }3.1512 + break;3.1513 + case 0xA:3.1514 + { /* FMOV FRm, @Rn */3.1515 + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1516 + sh4_stats[I_FMOV2]++;3.1517 + }3.1518 + break;3.1519 + case 0xB:3.1520 + { /* FMOV FRm, @-Rn */3.1521 + uint32_t Rn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1522 + sh4_stats[I_FMOV3]++;3.1523 + }3.1524 + break;3.1525 + case 0xC:3.1526 + { /* FMOV FRm, FRn */3.1527 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1528 + sh4_stats[I_FMOV1]++;3.1529 + }3.1530 + break;3.1531 + case 0xD:3.1532 + switch( (ir&0xF0) >> 4 ) {3.1533 + case 0x0:3.1534 + { /* FSTS FPUL, FRn */3.1535 + uint32_t FRn = ((ir>>8)&0xF);3.1536 + sh4_stats[I_FSTS]++;3.1537 + }3.1538 + break;3.1539 + case 0x1:3.1540 + { /* FLDS FRm, FPUL */3.1541 + uint32_t FRm = ((ir>>8)&0xF);3.1542 + sh4_stats[I_FLDS]++;3.1543 + }3.1544 + break;3.1545 + case 0x2:3.1546 + { /* FLOAT FPUL, FRn */3.1547 + uint32_t FRn = ((ir>>8)&0xF);3.1548 + sh4_stats[I_FLOAT]++;3.1549 + }3.1550 + break;3.1551 + case 0x3:3.1552 + { /* FTRC FRm, FPUL */3.1553 + uint32_t FRm = ((ir>>8)&0xF);3.1554 + sh4_stats[I_FTRC]++;3.1555 + }3.1556 + break;3.1557 + case 0x4:3.1558 + { /* FNEG FRn */3.1559 + uint32_t FRn = ((ir>>8)&0xF);3.1560 + sh4_stats[I_FNEG]++;3.1561 + }3.1562 + break;3.1563 + case 0x5:3.1564 + { /* FABS FRn */3.1565 + uint32_t FRn = ((ir>>8)&0xF);3.1566 + sh4_stats[I_FABS]++;3.1567 + }3.1568 + break;3.1569 + case 0x6:3.1570 + { /* FSQRT FRn */3.1571 + uint32_t FRn = ((ir>>8)&0xF);3.1572 + sh4_stats[I_FSQRT]++;3.1573 + }3.1574 + break;3.1575 + case 0x7:3.1576 + { /* FSRRA FRn */3.1577 + uint32_t FRn = ((ir>>8)&0xF);3.1578 + sh4_stats[I_FSRRA]++;3.1579 + }3.1580 + break;3.1581 + case 0x8:3.1582 + { /* FLDI0 FRn */3.1583 + uint32_t FRn = ((ir>>8)&0xF);3.1584 + sh4_stats[I_FLDI0]++;3.1585 + }3.1586 + break;3.1587 + case 0x9:3.1588 + { /* FLDI1 FRn */3.1589 + uint32_t FRn = ((ir>>8)&0xF);3.1590 + sh4_stats[I_FLDI1]++;3.1591 + }3.1592 + break;3.1593 + case 0xA:3.1594 + { /* FCNVSD FPUL, FRn */3.1595 + uint32_t FRn = ((ir>>8)&0xF);3.1596 + sh4_stats[I_FCNVSD]++;3.1597 + }3.1598 + break;3.1599 + case 0xB:3.1600 + { /* FCNVDS FRm, FPUL */3.1601 + uint32_t FRm = ((ir>>8)&0xF);3.1602 + sh4_stats[I_FCNVDS]++;3.1603 + }3.1604 + break;3.1605 + case 0xE:3.1606 + { /* FIPR FVm, FVn */3.1607 + uint32_t FVn = ((ir>>10)&0x3); uint32_t FVm = ((ir>>8)&0x3);3.1608 + sh4_stats[I_FIPR]++;3.1609 + }3.1610 + break;3.1611 + case 0xF:3.1612 + switch( (ir&0x100) >> 8 ) {3.1613 + case 0x0:3.1614 + { /* FSCA FPUL, FRn */3.1615 + uint32_t FRn = ((ir>>9)&0x7)<<1;3.1616 + sh4_stats[I_FSCA]++;3.1617 + }3.1618 + break;3.1619 + case 0x1:3.1620 + switch( (ir&0x200) >> 9 ) {3.1621 + case 0x0:3.1622 + { /* FTRV XMTRX, FVn */3.1623 + uint32_t FVn = ((ir>>10)&0x3);3.1624 + sh4_stats[I_FTRV]++;3.1625 + }3.1626 + break;3.1627 + case 0x1:3.1628 + switch( (ir&0xC00) >> 10 ) {3.1629 + case 0x0:3.1630 + { /* FSCHG */3.1631 + sh4_stats[I_FSCHG]++;3.1632 + }3.1633 + break;3.1634 + case 0x2:3.1635 + { /* FRCHG */3.1636 + sh4_stats[I_FRCHG]++;3.1637 + }3.1638 + break;3.1639 + case 0x3:3.1640 + { /* UNDEF */3.1641 + sh4_stats[I_UNDEF]++;3.1642 + }3.1643 + break;3.1644 + default:3.1645 + UNDEF();3.1646 + break;3.1647 + }3.1648 + break;3.1649 + }3.1650 + break;3.1651 + }3.1652 + break;3.1653 + default:3.1654 + UNDEF();3.1655 + break;3.1656 + }3.1657 + break;3.1658 + case 0xE:3.1659 + { /* FMAC FR0, FRm, FRn */3.1660 + uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);3.1661 + sh4_stats[I_FMAC]++;3.1662 + }3.1663 + break;3.1664 + default:3.1665 + UNDEF();3.1666 + break;3.1667 + }3.1668 + break;3.1669 + }3.1670 +3.1671 +3.1672 +sh4_stats_total++;3.1673 +}
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00004.2 +++ b/src/sh4/sh4stat.h Tue Sep 18 08:58:23 2007 +00004.3 @@ -0,0 +1,56 @@4.4 +/**4.5 + * $Id: sh4stat.h,v 1.1 2007-09-18 08:58:23 nkeynes Exp $4.6 + *4.7 + * Support module for collecting instruction stats4.8 + *4.9 + * Copyright (c) 2005 Nathan Keynes.4.10 + *4.11 + * This program is free software; you can redistribute it and/or modify4.12 + * it under the terms of the GNU General Public License as published by4.13 + * the Free Software Foundation; either version 2 of the License, or4.14 + * (at your option) any later version.4.15 + *4.16 + * This program is distributed in the hope that it will be useful,4.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of4.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the4.19 + * GNU General Public License for more details.4.20 + */4.21 +4.22 +enum sh4_inst_id {4.23 + I_UNKNOWN,4.24 + I_ADD, I_ADDI, I_ADDC, I_ADDV,4.25 + I_AND, I_ANDI, I_ANDB,4.26 + I_BF, I_BFS, I_BRA, I_BRAF, I_BSR, I_BSRF, I_BT, I_BTS,4.27 + I_CLRMAC, I_CLRS, I_CLRT,4.28 + I_CMPEQ, I_CMPEQI, I_CMPGE, I_CMPGT, I_CMPHI, I_CMPHS, I_CMPPL, I_CMPPZ, I_CMPSTR,4.29 + I_DIV0S, I_DIV0U, I_DIV1,4.30 + I_DMULS, I_DMULU, I_DT,4.31 + I_EXTSB, I_EXTSW, I_EXTUB, I_EXTUW, I_FABS,4.32 + I_FADD, I_FCMPEQ, I_FCMPGT, I_FCNVDS, I_FCNVSD, I_FDIV, I_FIPR, I_FLDS,4.33 + I_FLDI0, I_FLDI1, I_FLOAT, I_FMAC, I_FMOV1, I_FMOV2, I_FMOV3, I_FMOV4,4.34 + I_FMOV5, I_FMOV6, I_FMOV7, I_FMUL, I_FNEG, I_FRCHG, I_FSCA, I_FSCHG,4.35 + I_FSQRT, I_FSRRA, I_FSTS, I_FSUB, I_FTRC, I_FTRV,4.36 + I_JMP, I_JSR,4.37 + I_LDCSR, I_LDC, I_LDCSRM, I_LDCM, I_LDS, I_LDSM, I_LDTLB,4.38 + I_MACL, I_MACW,4.39 + I_MOV, I_MOVI, I_MOVB, I_MOVL, I_MOVLPC, I_MOVW, I_MOVA, I_MOVCA, I_MOVT,4.40 + I_MULL, I_MULSW, I_MULUW,4.41 + I_NEG, I_NEGC, I_NOP, I_NOT,4.42 + I_OCBI, I_OCBP, I_OCBWB,4.43 + I_OR, I_ORI, I_ORB,4.44 + I_PREF,4.45 + I_ROTCL, I_ROTCR, I_ROTL, I_ROTR,4.46 + I_RTE, I_RTS,4.47 + I_SETS, I_SETT,4.48 + I_SHAD, I_SHAL, I_SHAR, I_SHLD, I_SHLL, I_SHLR,4.49 + I_SLEEP,4.50 + I_STCSR, I_STC, I_STCSRM, I_STCM, I_STS, I_STSM,4.51 + I_SUB, I_SUBC, I_SUBV,4.52 + I_SWAPB, I_SWAPW, I_TASB,4.53 + I_TRAPA,4.54 + I_TST, I_TSTI, I_TSTB,4.55 + I_XOR, I_XORI, I_XORB,4.56 + I_XTRCT,4.57 + I_UNDEF };4.58 +4.59 +#define SH4_INSTRUCTION_COUNT I_UNDEF
5.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00005.2 +++ b/src/sh4/sh4stat.in Tue Sep 18 08:58:23 2007 +00005.3 @@ -0,0 +1,405 @@5.4 +/**5.5 + * $Id: sh4stat.in,v 1.1 2007-09-18 08:58:23 nkeynes Exp $5.6 + *5.7 + * Support module for collecting instruction stats5.8 + *5.9 + * Copyright (c) 2005 Nathan Keynes.5.10 + *5.11 + * This program is free software; you can redistribute it and/or modify5.12 + * it under the terms of the GNU General Public License as published by5.13 + * the Free Software Foundation; either version 2 of the License, or5.14 + * (at your option) any later version.5.15 + *5.16 + * This program is distributed in the hope that it will be useful,5.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of5.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the5.19 + * GNU General Public License for more details.5.20 + */5.21 +5.22 +#include "dream.h"5.23 +#include "sh4stat.h"5.24 +#include "sh4core.h"5.25 +5.26 +static uint64_t sh4_stats[SH4_INSTRUCTION_COUNT+1];5.27 +static uint64_t sh4_stats_total;5.28 +static const char *sh4_stats_names[] = {5.29 + "???",5.30 +"ADD Rm, Rn",5.31 +"ADD #imm, Rn",5.32 +"ADDC Rm, Rn",5.33 +"ADDV Rm, Rn",5.34 +"AND Rm, Rn",5.35 +"AND #imm, R0",5.36 +"AND.B #imm, @(R0, GBR)",5.37 +"BF disp",5.38 +"BF/S disp",5.39 +"BRA disp",5.40 +"BRAF Rn",5.41 +"BSR disp",5.42 +"BSRF Rn",5.43 +"BT disp",5.44 +"BT/S disp",5.45 +"CLRMAC",5.46 +"CLRS",5.47 +"CLRT",5.48 +"CMP/EQ Rm, Rn",5.49 +"CMP/EQ #imm, R0",5.50 +"CMP/GE Rm, Rn",5.51 +"CMP/GT Rm, Rn",5.52 +"CMP/HI Rm, Rn",5.53 +"CMP/HS Rm, Rn",5.54 +"CMP/PL Rn",5.55 +"CMP/PZ Rn",5.56 +"CMP/STR Rm, Rn",5.57 +"DIV0S Rm, Rn",5.58 +"DIV0U",5.59 +"DIV1 Rm, Rn",5.60 +"DMULS.L Rm, Rn",5.61 +"DMULU.L Rm, Rn",5.62 +"DT Rn",5.63 +"EXTS.B Rm, Rn",5.64 +"EXTS.W Rm, Rn",5.65 +"EXTU.B Rm, Rn",5.66 +"EXTU.W Rm, Rn",5.67 +"FABS FRn",5.68 +"FADD FRm, FRn",5.69 +"FCMP/EQ FRm, FRn",5.70 +"FCMP/GT FRm, FRn",5.71 +"FCNVDS FRm, FPUL",5.72 +"FCNVSD FPUL, FRn",5.73 +"FDIV FRm, FRn",5.74 +"FIPR FVm, FVn",5.75 +"FLDS FRm, FPUL",5.76 +"FLDI0 FRn",5.77 +"FLDI1 FRn",5.78 +"FLOAT FPUL, FRn",5.79 +"FMAC FR0, FRm, FRn",5.80 +"FMOV FRm, FRn",5.81 +"FMOV FRm, @Rn",5.82 +"FMOV FRm, @-Rn",5.83 +"FMOV FRm, @(R0, Rn)",5.84 +"FMOV @Rm, FRn",5.85 +"FMOV @Rm+, FRn",5.86 +"FMOV @(R0, Rm), FRn",5.87 +"FMUL FRm, FRn",5.88 +"FNEG FRn",5.89 +"FRCHG",5.90 +"FSCA FPUL, FRn",5.91 +"FSCHG",5.92 +"FSQRT FRn",5.93 +"FSRRA FRn",5.94 +"FSTS FPUL, FRn",5.95 +"FSUB FRm, FRn",5.96 +"FTRC FRm, FPUL",5.97 +"FTRV XMTRX, FVn",5.98 +"JMP @Rn",5.99 +"JSR @Rn",5.100 +"LDC Rm, SR",5.101 +"LDC Rm, *",5.102 +"LDC.L @Rm+, SR",5.103 +"LDC.L @Rm+, *",5.104 +"LDS Rm, *",5.105 +"LDS.L @Rm+, *",5.106 +"LDTLB",5.107 +"MAC.L @Rm+, @Rn+",5.108 +"MAC.W @Rm+, @Rn+",5.109 +"MOV Rm, Rn",5.110 +"MOV #imm, Rn",5.111 +"MOV.B ...",5.112 +"MOV.L ...",5.113 +"MOV.L @(disp, PC)",5.114 +"MOV.W ...",5.115 +"MOVA @(disp, PC), R0",5.116 +"MOVCA.L R0, @Rn",5.117 +"MOVT Rn",5.118 +"MUL.L Rm, Rn",5.119 +"MULS.W Rm, Rn",5.120 +"MULU.W Rm, Rn",5.121 +"NEG Rm, Rn",5.122 +"NEGC Rm, Rn",5.123 +"NOP",5.124 +"NOT Rm, Rn",5.125 +"OCBI @Rn",5.126 +"OCBP @Rn",5.127 +"OCBWB @Rn",5.128 +"OR Rm, Rn",5.129 +"OR #imm, R0",5.130 +"OR.B #imm, @(R0, GBR)",5.131 +"PREF @Rn",5.132 +"ROTCL Rn",5.133 +"ROTCR Rn",5.134 +"ROTL Rn",5.135 +"ROTR Rn",5.136 +"RTE",5.137 +"RTS",5.138 +"SETS",5.139 +"SETT",5.140 +"SHAD Rm, Rn",5.141 +"SHAL Rn",5.142 +"SHAR Rn",5.143 +"SHLD Rm, Rn",5.144 +"SHLL* Rn",5.145 +"SHLR* Rn",5.146 +"SLEEP",5.147 +"STC SR, Rn",5.148 +"STC *, Rn",5.149 +"STC.L SR, @-Rn",5.150 +"STC.L *, @-Rn",5.151 +"STS *, Rn",5.152 +"STS.L *, @-Rn",5.153 +"SUB Rm, Rn",5.154 +"SUBC Rm, Rn",5.155 +"SUBV Rm, Rn",5.156 +"SWAP.B Rm, Rn",5.157 +"SWAP.W Rm, Rn",5.158 +"TAS.B @Rn",5.159 +"TRAPA #imm",5.160 +"TST Rm, Rn",5.161 +"TST #imm, R0",5.162 +"TST.B #imm, @(R0, GBR)",5.163 +"XOR Rm, Rn",5.164 +"XOR #imm, R0",5.165 +"XOR.B #imm, @(R0, GBR)",5.166 +"XTRCT Rm, Rn",5.167 +"UNDEF"5.168 +};5.169 +5.170 +void sh4_stats_reset( void )5.171 +{5.172 + int i;5.173 + for( i=0; i<= I_UNDEF; i++ ) {5.174 + sh4_stats[i] = 0;5.175 + }5.176 + sh4_stats_total = 0;5.177 +}5.178 +5.179 +void sh4_stats_print( FILE *out )5.180 +{5.181 + int i;5.182 + for( i=0; i<= I_UNDEF; i++ ) {5.183 + fprintf( out, "%-20s\t%d\t%.2f%\n", sh4_stats_names[i], (uint32_t)sh4_stats[i], ((double)sh4_stats[i])*100.0/(double)sh4_stats_total );5.184 + }5.185 + fprintf( out, "Total: %d\n", sh4_stats_total );5.186 +}5.187 +5.188 +void sh4_stats_add( uint32_t pc )5.189 +{5.190 + uint16_t ir = sh4_read_word(pc);5.191 +#define UNDEF() sh4_stats[0]++5.192 +%%5.193 +ADD Rm, Rn {: sh4_stats[I_ADD]++; :}5.194 +ADD #imm, Rn {: sh4_stats[I_ADDI]++; :}5.195 +ADDC Rm, Rn {: sh4_stats[I_ADDC]++; :}5.196 +ADDV Rm, Rn {: sh4_stats[I_ADDV]++; :}5.197 +AND Rm, Rn {: sh4_stats[I_AND]++; :}5.198 +AND #imm, R0 {: sh4_stats[I_ANDI]++; :}5.199 +AND.B #imm, @(R0, GBR) {: sh4_stats[I_ANDB]++; :}5.200 +BF disp {: sh4_stats[I_BF]++; :}5.201 +BF/S disp {: sh4_stats[I_BFS]++; :}5.202 +BRA disp {: sh4_stats[I_BRA]++; :}5.203 +BRAF Rn {: sh4_stats[I_BRAF]++; :}5.204 +BSR disp {: sh4_stats[I_BSR]++; :}5.205 +BSRF Rn {: sh4_stats[I_BSRF]++; :}5.206 +BT disp {: sh4_stats[I_BT]++; :}5.207 +BT/S disp {: sh4_stats[I_BTS]++; :}5.208 +CLRMAC {: sh4_stats[I_CLRMAC]++; :}5.209 +CLRS {: sh4_stats[I_CLRS]++; :}5.210 +CLRT {: sh4_stats[I_CLRT]++; :}5.211 +CMP/EQ Rm, Rn {: sh4_stats[I_CMPEQ]++; :}5.212 +CMP/EQ #imm, R0 {: sh4_stats[I_CMPEQI]++; :}5.213 +CMP/GE Rm, Rn {: sh4_stats[I_CMPGE]++; :}5.214 +CMP/GT Rm, Rn {: sh4_stats[I_CMPGT]++; :}5.215 +CMP/HI Rm, Rn {: sh4_stats[I_CMPHI]++; :}5.216 +CMP/HS Rm, Rn {: sh4_stats[I_CMPHS]++; :}5.217 +CMP/PL Rn {: sh4_stats[I_CMPPL]++; :}5.218 +CMP/PZ Rn {: sh4_stats[I_CMPPZ]++; :}5.219 +CMP/STR Rm, Rn {: sh4_stats[I_CMPSTR]++; :}5.220 +DIV0S Rm, Rn {: sh4_stats[I_DIV0S]++; :}5.221 +DIV0U {: sh4_stats[I_DIV0U]++; :}5.222 +DIV1 Rm, Rn {: sh4_stats[I_DIV1]++; :}5.223 +DMULS.L Rm, Rn {: sh4_stats[I_DMULS]++; :}5.224 +DMULU.L Rm, Rn {: sh4_stats[I_DMULU]++; :}5.225 +DT Rn {: sh4_stats[I_DT]++; :}5.226 +EXTS.B Rm, Rn {: sh4_stats[I_EXTSB]++; :}5.227 +EXTS.W Rm, Rn {: sh4_stats[I_EXTSW]++; :}5.228 +EXTU.B Rm, Rn {: sh4_stats[I_EXTUB]++; :}5.229 +EXTU.W Rm, Rn {: sh4_stats[I_EXTUW]++; :}5.230 +FABS FRn {: sh4_stats[I_FABS]++; :}5.231 +FADD FRm, FRn {: sh4_stats[I_FADD]++; :}5.232 +FCMP/EQ FRm, FRn {: sh4_stats[I_FCMPEQ]++; :}5.233 +FCMP/GT FRm, FRn {: sh4_stats[I_FCMPGT]++; :}5.234 +FCNVDS FRm, FPUL {: sh4_stats[I_FCNVDS]++; :}5.235 +FCNVSD FPUL, FRn {: sh4_stats[I_FCNVSD]++; :}5.236 +FDIV FRm, FRn {: sh4_stats[I_FDIV]++; :}5.237 +FIPR FVm, FVn {: sh4_stats[I_FIPR]++; :}5.238 +FLDS FRm, FPUL {: sh4_stats[I_FLDS]++; :}5.239 +FLDI0 FRn {: sh4_stats[I_FLDI0]++; :}5.240 +FLDI1 FRn {: sh4_stats[I_FLDI1]++; :}5.241 +FLOAT FPUL, FRn {: sh4_stats[I_FLOAT]++; :}5.242 +FMAC FR0, FRm, FRn {: sh4_stats[I_FMAC]++; :}5.243 +FMOV FRm, FRn {: sh4_stats[I_FMOV1]++; :}5.244 +FMOV FRm, @Rn {: sh4_stats[I_FMOV2]++; :}5.245 +FMOV FRm, @-Rn {: sh4_stats[I_FMOV3]++; :}5.246 +FMOV FRm, @(R0, Rn) {: sh4_stats[I_FMOV4]++; :}5.247 +FMOV @Rm, FRn {: sh4_stats[I_FMOV5]++; :}5.248 +FMOV @Rm+, FRn {: sh4_stats[I_FMOV6]++; :}5.249 +FMOV @(R0, Rm), FRn {: sh4_stats[I_FMOV7]++; :}5.250 +FMUL FRm, FRn {: sh4_stats[I_FMUL]++; :}5.251 +FNEG FRn {: sh4_stats[I_FNEG]++; :}5.252 +FRCHG {: sh4_stats[I_FRCHG]++; :}5.253 +FSCA FPUL, FRn {: sh4_stats[I_FSCA]++; :}5.254 +FSCHG {: sh4_stats[I_FSCHG]++; :}5.255 +FSQRT FRn {: sh4_stats[I_FSQRT]++; :}5.256 +FSRRA FRn {: sh4_stats[I_FSRRA]++; :}5.257 +FSTS FPUL, FRn {: sh4_stats[I_FSTS]++; :}5.258 +FSUB FRm, FRn {: sh4_stats[I_FSUB]++; :}5.259 +FTRC FRm, FPUL {: sh4_stats[I_FTRC]++; :}5.260 +FTRV XMTRX, FVn {: sh4_stats[I_FTRV]++; :}5.261 +JMP @Rn {: sh4_stats[I_JMP]++; :}5.262 +JSR @Rn {: sh4_stats[I_JSR]++; :}5.263 +LDC Rm, GBR {: sh4_stats[I_LDC]++; :}5.264 +LDC Rm, SR {: sh4_stats[I_LDCSR]++; :}5.265 +LDC Rm, VBR {: sh4_stats[I_LDC]++; :}5.266 +LDC Rm, SSR {: sh4_stats[I_LDC]++; :}5.267 +LDC Rm, SGR {: sh4_stats[I_LDC]++; :}5.268 +LDC Rm, SPC {: sh4_stats[I_LDC]++; :}5.269 +LDC Rm, DBR {: sh4_stats[I_LDC]++; :}5.270 +LDC Rm, Rn_BANK {: sh4_stats[I_LDC]++; :}5.271 +LDC.L @Rm+, GBR {: sh4_stats[I_LDCM]++; :}5.272 +LDC.L @Rm+, SR {: sh4_stats[I_LDCSRM]++; :}5.273 +LDC.L @Rm+, VBR {: sh4_stats[I_LDCM]++; :}5.274 +LDC.L @Rm+, SSR {: sh4_stats[I_LDCM]++; :}5.275 +LDC.L @Rm+, SGR {: sh4_stats[I_LDCM]++; :}5.276 +LDC.L @Rm+, SPC {: sh4_stats[I_LDCM]++; :}5.277 +LDC.L @Rm+, DBR {: sh4_stats[I_LDCM]++; :}5.278 +LDC.L @Rm+, Rn_BANK {: sh4_stats[I_LDCM]++; :}5.279 +LDS Rm, FPSCR {: sh4_stats[I_LDS]++; :}5.280 +LDS.L @Rm+, FPSCR {: sh4_stats[I_LDSM]++; :}5.281 +LDS Rm, FPUL {: sh4_stats[I_LDS]++; :}5.282 +LDS.L @Rm+, FPUL {: sh4_stats[I_LDSM]++; :}5.283 +LDS Rm, MACH {: sh4_stats[I_LDS]++; :}5.284 +LDS.L @Rm+, MACH {: sh4_stats[I_LDSM]++; :}5.285 +LDS Rm, MACL {: sh4_stats[I_LDS]++; :}5.286 +LDS.L @Rm+, MACL {: sh4_stats[I_LDSM]++; :}5.287 +LDS Rm, PR {: sh4_stats[I_LDS]++; :}5.288 +LDS.L @Rm+, PR {: sh4_stats[I_LDSM]++; :}5.289 +LDTLB {: sh4_stats[I_LDTLB]++; :}5.290 +MAC.L @Rm+, @Rn+ {: sh4_stats[I_MACL]++; :}5.291 +MAC.W @Rm+, @Rn+ {: sh4_stats[I_MACW]++; :}5.292 +MOV Rm, Rn {: sh4_stats[I_MOV]++; :}5.293 +MOV #imm, Rn {: sh4_stats[I_MOVI]++; :}5.294 +MOV.B Rm, @Rn {: sh4_stats[I_MOVB]++; :}5.295 +MOV.B Rm, @-Rn {: sh4_stats[I_MOVB]++; :}5.296 +MOV.B Rm, @(R0, Rn) {: sh4_stats[I_MOVB]++; :}5.297 +MOV.B R0, @(disp, GBR) {: sh4_stats[I_MOVB]++; :}5.298 +MOV.B R0, @(disp, Rn) {: sh4_stats[I_MOVB]++; :}5.299 +MOV.B @Rm, Rn {: sh4_stats[I_MOVB]++; :}5.300 +MOV.B @Rm+, Rn {: sh4_stats[I_MOVB]++; :}5.301 +MOV.B @(R0, Rm), Rn {: sh4_stats[I_MOVB]++; :}5.302 +MOV.B @(disp, GBR), R0 {: sh4_stats[I_MOVB]++; :}5.303 +MOV.B @(disp, Rm), R0 {: sh4_stats[I_MOVB]++; :}5.304 +MOV.L Rm, @Rn {: sh4_stats[I_MOVL]++; :}5.305 +MOV.L Rm, @-Rn {: sh4_stats[I_MOVL]++; :}5.306 +MOV.L Rm, @(R0, Rn) {: sh4_stats[I_MOVL]++; :}5.307 +MOV.L R0, @(disp, GBR) {: sh4_stats[I_MOVL]++; :}5.308 +MOV.L Rm, @(disp, Rn) {: sh4_stats[I_MOVL]++; :}5.309 +MOV.L @Rm, Rn {: sh4_stats[I_MOVL]++; :}5.310 +MOV.L @Rm+, Rn {: sh4_stats[I_MOVL]++; :}5.311 +MOV.L @(R0, Rm), Rn {: sh4_stats[I_MOVL]++; :}5.312 +MOV.L @(disp, GBR), R0 {: sh4_stats[I_MOVL]++; :}5.313 +MOV.L @(disp, PC), Rn {: sh4_stats[I_MOVLPC]++; :}5.314 +MOV.L @(disp, Rm), Rn {: sh4_stats[I_MOVL]++; :}5.315 +MOV.W Rm, @Rn {: sh4_stats[I_MOVW]++; :}5.316 +MOV.W Rm, @-Rn {: sh4_stats[I_MOVW]++; :}5.317 +MOV.W Rm, @(R0, Rn) {: sh4_stats[I_MOVW]++; :}5.318 +MOV.W R0, @(disp, GBR) {: sh4_stats[I_MOVW]++; :}5.319 +MOV.W R0, @(disp, Rn) {: sh4_stats[I_MOVW]++; :}5.320 +MOV.W @Rm, Rn {: sh4_stats[I_MOVW]++; :}5.321 +MOV.W @Rm+, Rn {: sh4_stats[I_MOVW]++; :}5.322 +MOV.W @(R0, Rm), Rn {: sh4_stats[I_MOVW]++; :}5.323 +MOV.W @(disp, GBR), R0 {: sh4_stats[I_MOVW]++; :}5.324 +MOV.W @(disp, PC), Rn {: sh4_stats[I_MOVW]++; :}5.325 +MOV.W @(disp, Rm), R0 {: sh4_stats[I_MOVW]++; :}5.326 +MOVA @(disp, PC), R0 {: sh4_stats[I_MOVA]++; :}5.327 +MOVCA.L R0, @Rn {: sh4_stats[I_MOVCA]++; :}5.328 +MOVT Rn {: sh4_stats[I_MOVT]++; :}5.329 +MUL.L Rm, Rn {: sh4_stats[I_MULL]++; :}5.330 +MULS.W Rm, Rn {: sh4_stats[I_MULSW]++; :}5.331 +MULU.W Rm, Rn {: sh4_stats[I_MULUW]++; :}5.332 +NEG Rm, Rn {: sh4_stats[I_NEG]++; :}5.333 +NEGC Rm, Rn {: sh4_stats[I_NEGC]++; :}5.334 +NOP {: sh4_stats[I_NOP]++; :}5.335 +NOT Rm, Rn {: sh4_stats[I_NOT]++; :}5.336 +OCBI @Rn {: sh4_stats[I_OCBI]++; :}5.337 +OCBP @Rn {: sh4_stats[I_OCBP]++; :}5.338 +OCBWB @Rn {: sh4_stats[I_OCBWB]++; :}5.339 +OR Rm, Rn {: sh4_stats[I_OR]++; :}5.340 +OR #imm, R0 {: sh4_stats[I_ORI]++; :}5.341 +OR.B #imm, @(R0, GBR) {: sh4_stats[I_ORB]++; :}5.342 +PREF @Rn {: sh4_stats[I_PREF]++; :}5.343 +ROTCL Rn {: sh4_stats[I_ROTCL]++; :}5.344 +ROTCR Rn {: sh4_stats[I_ROTCR]++; :}5.345 +ROTL Rn {: sh4_stats[I_ROTL]++; :}5.346 +ROTR Rn {: sh4_stats[I_ROTR]++; :}5.347 +RTE {: sh4_stats[I_RTE]++; :}5.348 +RTS {: sh4_stats[I_RTS]++; :}5.349 +SETS {: sh4_stats[I_SETS]++; :}5.350 +SETT {: sh4_stats[I_SETT]++; :}5.351 +SHAD Rm, Rn {: sh4_stats[I_SHAD]++; :}5.352 +SHAL Rn {: sh4_stats[I_SHAL]++; :}5.353 +SHAR Rn {: sh4_stats[I_SHAR]++; :}5.354 +SHLD Rm, Rn {: sh4_stats[I_SHLD]++; :}5.355 +SHLL Rn {: sh4_stats[I_SHLL]++; :}5.356 +SHLL2 Rn {: sh4_stats[I_SHLL]++; :}5.357 +SHLL8 Rn {: sh4_stats[I_SHLL]++; :}5.358 +SHLL16 Rn {: sh4_stats[I_SHLL]++; :}5.359 +SHLR Rn {: sh4_stats[I_SHLR]++; :}5.360 +SHLR2 Rn {: sh4_stats[I_SHLR]++; :}5.361 +SHLR8 Rn {: sh4_stats[I_SHLR]++; :}5.362 +SHLR16 Rn {: sh4_stats[I_SHLR]++; :}5.363 +SLEEP {: sh4_stats[I_SLEEP]++; :}5.364 +STC SR, Rn {: sh4_stats[I_STCSR]++; :}5.365 +STC GBR, Rn {: sh4_stats[I_STC]++; :}5.366 +STC VBR, Rn {: sh4_stats[I_STC]++; :}5.367 +STC SSR, Rn {: sh4_stats[I_STC]++; :}5.368 +STC SPC, Rn {: sh4_stats[I_STC]++; :}5.369 +STC SGR, Rn {: sh4_stats[I_STC]++; :}5.370 +STC DBR, Rn {: sh4_stats[I_STC]++; :}5.371 +STC Rm_BANK, Rn {: sh4_stats[I_STC]++; :}5.372 +STC.L SR, @-Rn {: sh4_stats[I_STCSRM]++; :}5.373 +STC.L VBR, @-Rn {: sh4_stats[I_STCM]++; :}5.374 +STC.L SSR, @-Rn {: sh4_stats[I_STCM]++; :}5.375 +STC.L SPC, @-Rn {: sh4_stats[I_STCM]++; :}5.376 +STC.L SGR, @-Rn {: sh4_stats[I_STCM]++; :}5.377 +STC.L DBR, @-Rn {: sh4_stats[I_STCM]++; :}5.378 +STC.L Rm_BANK, @-Rn {: sh4_stats[I_STCM]++; :}5.379 +STC.L GBR, @-Rn {: sh4_stats[I_STCM]++; :}5.380 +STS FPSCR, Rn {: sh4_stats[I_STS]++; :}5.381 +STS.L FPSCR, @-Rn {: sh4_stats[I_STSM]++; :}5.382 +STS FPUL, Rn {: sh4_stats[I_STS]++; :}5.383 +STS.L FPUL, @-Rn {: sh4_stats[I_STSM]++; :}5.384 +STS MACH, Rn {: sh4_stats[I_STS]++; :}5.385 +STS.L MACH, @-Rn {: sh4_stats[I_STSM]++; :}5.386 +STS MACL, Rn {: sh4_stats[I_STS]++; :}5.387 +STS.L MACL, @-Rn {: sh4_stats[I_STSM]++; :}5.388 +STS PR, Rn {: sh4_stats[I_STS]++; :}5.389 +STS.L PR, @-Rn {: sh4_stats[I_STSM]++; :}5.390 +SUB Rm, Rn {: sh4_stats[I_SUB]++; :}5.391 +SUBC Rm, Rn {: sh4_stats[I_SUBC]++; :}5.392 +SUBV Rm, Rn {: sh4_stats[I_SUBV]++; :}5.393 +SWAP.B Rm, Rn {: sh4_stats[I_SWAPB]++; :}5.394 +SWAP.W Rm, Rn {: sh4_stats[I_SWAPW]++; :}5.395 +TAS.B @Rn {: sh4_stats[I_TASB]++; :}5.396 +TRAPA #imm {: sh4_stats[I_TRAPA]++; :}5.397 +TST Rm, Rn {: sh4_stats[I_TST]++; :}5.398 +TST #imm, R0 {: sh4_stats[I_TSTI]++; :}5.399 +TST.B #imm, @(R0, GBR) {: sh4_stats[I_TSTB]++; :}5.400 +XOR Rm, Rn {: sh4_stats[I_XOR]++; :}5.401 +XOR #imm, R0 {: sh4_stats[I_XORI]++; :}5.402 +XOR.B #imm, @(R0, GBR) {: sh4_stats[I_XORB]++; :}5.403 +XTRCT Rm, Rn {: sh4_stats[I_XTRCT]++; :}5.404 +UNDEF {: sh4_stats[I_UNDEF]++; :}5.405 +%%5.406 +5.407 +sh4_stats_total++;5.408 +}
.