1.1 --- a/src/aica/aica.c	Wed Dec 24 06:06:23 2008 +0000
     1.2 +++ b/src/aica/aica.c	Fri Dec 26 14:25:23 2008 +0000
     1.3 @@ -70,7 +70,6 @@
     1.4      register_io_regions( mmio_list_spu );
     1.5      MMIO_NOTRACE(AICA0);
     1.6      MMIO_NOTRACE(AICA1);
     1.7 -    arm_mem_init();
     1.8      aica_reset();
     1.9  }
    1.10  

     2.1 --- a/src/aica/aica.h	Wed Dec 24 06:06:23 2008 +0000
     2.2 +++ b/src/aica/aica.h	Fri Dec 26 14:25:23 2008 +0000
     2.3 @@ -71,6 +71,10 @@
     2.4  void aica_event( int event );
     2.5  void aica_write_channel( int channel, uint32_t addr, uint32_t val );
     2.6  
     2.7 +extern unsigned char aica_main_ram[];
     2.8 +extern unsigned char aica_scratch_ram[];
     2.9 +
    2.10 +
    2.11  /**
    2.12   * The AICA core runs at 44100 samples/second, regardless of what we're
    2.13   * actually outputing.

     3.1 --- a/src/aica/armcore.h	Wed Dec 24 06:06:23 2008 +0000
     3.2 +++ b/src/aica/armcore.h	Fri Dec 26 14:25:23 2008 +0000
     3.3 @@ -109,7 +109,6 @@
     3.4  void arm_write_byte_user( uint32_t addr, uint32_t val );
     3.5  int32_t arm_read_phys_word( uint32_t addr );
     3.6  int arm_has_page( uint32_t addr );
     3.7 -void arm_mem_init(void);
     3.8  
     3.9  #ifdef __cplusplus
    3.10  }

     4.1 --- a/src/aica/armmem.c	Wed Dec 24 06:06:23 2008 +0000
     4.2 +++ b/src/aica/armmem.c	Fri Dec 26 14:25:23 2008 +0000
     4.3 @@ -1,4 +1,4 @@
     4.4 -/**
     4.5 +/*`*
     4.6   * $Id$
     4.7   *
     4.8   * Implements the ARM's memory map.
     4.9 @@ -22,50 +22,45 @@
    4.10  #include "aica.h"
    4.11  #include "armcore.h"
    4.12  
    4.13 -unsigned char *arm_mem = NULL;
    4.14 -unsigned char *arm_mem_scratch = NULL;
    4.15 -
    4.16 -void arm_mem_init() {
    4.17 -    arm_mem = mem_get_region_by_name( MEM_REGION_AUDIO );
    4.18 -    arm_mem_scratch = mem_get_region_by_name( MEM_REGION_AUDIO_SCRATCH );
    4.19 -}
    4.20 +unsigned char aica_main_ram[2 MB];
    4.21 +unsigned char aica_scratch_ram[8 KB];
    4.22  
    4.23  /*************** ARM memory access function blocks **************/
    4.24  
    4.25  static int32_t FASTCALL ext_audioram_read_long( sh4addr_t addr )
    4.26  {
    4.27 -    return *((int32_t *)(arm_mem + (addr&0x001FFFFF)));
    4.28 +    return *((int32_t *)(aica_main_ram + (addr&0x001FFFFF)));
    4.29  }
    4.30  static int32_t FASTCALL ext_audioram_read_word( sh4addr_t addr )
    4.31  {
    4.32 -    return SIGNEXT16(*((int16_t *)(arm_mem + (addr&0x001FFFFF))));
    4.33 +    return SIGNEXT16(*((int16_t *)(aica_main_ram + (addr&0x001FFFFF))));
    4.34  }
    4.35  static int32_t FASTCALL ext_audioram_read_byte( sh4addr_t addr )
    4.36  {
    4.37 -    return SIGNEXT8(*((int16_t *)(arm_mem + (addr&0x001FFFFF))));
    4.38 +    return SIGNEXT8(*((int16_t *)(aica_main_ram + (addr&0x001FFFFF))));
    4.39  }
    4.40  static void FASTCALL ext_audioram_write_long( sh4addr_t addr, uint32_t val )
    4.41  {
    4.42 -    *(uint32_t *)(arm_mem + (addr&0x001FFFFF)) = val;
    4.43 +    *(uint32_t *)(aica_main_ram + (addr&0x001FFFFF)) = val;
    4.44      asic_g2_write_word();
    4.45  }
    4.46  static void FASTCALL ext_audioram_write_word( sh4addr_t addr, uint32_t val )
    4.47  {
    4.48 -    *(uint16_t *)(arm_mem + (addr&0x001FFFFF)) = (uint16_t)val;
    4.49 +    *(uint16_t *)(aica_main_ram + (addr&0x001FFFFF)) = (uint16_t)val;
    4.50      asic_g2_write_word();
    4.51  }
    4.52  static void FASTCALL ext_audioram_write_byte( sh4addr_t addr, uint32_t val )
    4.53  {
    4.54 -    *(uint8_t *)(arm_mem + (addr&0x001FFFFF)) = (uint8_t)val;
    4.55 +    *(uint8_t *)(aica_main_ram + (addr&0x001FFFFF)) = (uint8_t)val;
    4.56      asic_g2_write_word();
    4.57  }
    4.58  static void FASTCALL ext_audioram_read_burst( unsigned char *dest, sh4addr_t addr )
    4.59  {
    4.60 -    memcpy( dest, arm_mem+(addr&0x001FFFFF), 32 );
    4.61 +    memcpy( dest, aica_main_ram+(addr&0x001FFFFF), 32 );
    4.62  }
    4.63  static void FASTCALL ext_audioram_write_burst( sh4addr_t addr, unsigned char *src )
    4.64  {
    4.65 -    memcpy( arm_mem+(addr&0x001FFFFF), src, 32 );
    4.66 +    memcpy( aica_main_ram+(addr&0x001FFFFF), src, 32 );
    4.67  }
    4.68  
    4.69  struct mem_region_fn mem_region_audioram = { ext_audioram_read_long, ext_audioram_write_long, 
    4.70 @@ -76,38 +71,38 @@
    4.71  
    4.72  static int32_t FASTCALL ext_audioscratch_read_long( sh4addr_t addr )
    4.73  {
    4.74 -    return *((int32_t *)(arm_mem_scratch + (addr&0x00001FFF)));
    4.75 +    return *((int32_t *)(aica_scratch_ram + (addr&0x00001FFF)));
    4.76  }
    4.77  static int32_t FASTCALL ext_audioscratch_read_word( sh4addr_t addr )
    4.78  {
    4.79 -    return SIGNEXT16(*((int16_t *)(arm_mem_scratch + (addr&0x00001FFF))));
    4.80 +    return SIGNEXT16(*((int16_t *)(aica_scratch_ram + (addr&0x00001FFF))));
    4.81  }
    4.82  static int32_t FASTCALL ext_audioscratch_read_byte( sh4addr_t addr )
    4.83  {
    4.84 -    return SIGNEXT8(*((int16_t *)(arm_mem_scratch + (addr&0x00001FFF))));
    4.85 +    return SIGNEXT8(*((int16_t *)(aica_scratch_ram + (addr&0x00001FFF))));
    4.86  }
    4.87  static void FASTCALL ext_audioscratch_write_long( sh4addr_t addr, uint32_t val )
    4.88  {
    4.89 -    *(uint32_t *)(arm_mem_scratch + (addr&0x00001FFF)) = val;
    4.90 +    *(uint32_t *)(aica_scratch_ram + (addr&0x00001FFF)) = val;
    4.91      asic_g2_write_word();
    4.92  }
    4.93  static void FASTCALL ext_audioscratch_write_word( sh4addr_t addr, uint32_t val )
    4.94  {
    4.95 -    *(uint16_t *)(arm_mem_scratch + (addr&0x00001FFF)) = (uint16_t)val;
    4.96 +    *(uint16_t *)(aica_scratch_ram + (addr&0x00001FFF)) = (uint16_t)val;
    4.97      asic_g2_write_word();
    4.98  }
    4.99  static void FASTCALL ext_audioscratch_write_byte( sh4addr_t addr, uint32_t val )
   4.100  {
   4.101 -    *(uint8_t *)(arm_mem_scratch + (addr&0x00001FFF)) = (uint8_t)val;
   4.102 +    *(uint8_t *)(aica_scratch_ram + (addr&0x00001FFF)) = (uint8_t)val;
   4.103      asic_g2_write_word();
   4.104  }
   4.105  static void FASTCALL ext_audioscratch_read_burst( unsigned char *dest, sh4addr_t addr )
   4.106  {
   4.107 -    memcpy( dest, arm_mem_scratch+(addr&0x00001FFF), 32 );
   4.108 +    memcpy( dest, aica_scratch_ram+(addr&0x00001FFF), 32 );
   4.109  }
   4.110  static void FASTCALL ext_audioscratch_write_burst( sh4addr_t addr, unsigned char *src )
   4.111  {
   4.112 -    memcpy( arm_mem_scratch+(addr&0x00001FFF), src, 32 );
   4.113 +    memcpy( aica_scratch_ram+(addr&0x00001FFF), src, 32 );
   4.114  }
   4.115  
   4.116  struct mem_region_fn mem_region_audioscratch = { ext_audioscratch_read_long, ext_audioscratch_write_long, 
   4.117 @@ -123,7 +118,7 @@
   4.118  
   4.119  uint32_t arm_read_long( uint32_t addr ) {
   4.120      if( addr < 0x00200000 ) {
   4.121 -        return *(int32_t *)(arm_mem + addr);
   4.122 +        return *(int32_t *)(aica_main_ram + addr);
   4.123          /* Main sound ram */
   4.124      } else {
   4.125          uint32_t val;
   4.126 @@ -142,7 +137,7 @@
   4.127              return val;
   4.128          case 0x00803000:
   4.129          case 0x00804000:
   4.130 -            return *(int32_t *)(arm_mem_scratch + addr - 0x00803000);
   4.131 +            return *(int32_t *)(aica_scratch_ram + addr - 0x00803000);
   4.132          }
   4.133      }
   4.134      ERROR( "Attempted long read to undefined page: %08X at %08X",
   4.135 @@ -163,7 +158,7 @@
   4.136  {
   4.137      if( addr < 0x00200000 ) {
   4.138          /* Main sound ram */
   4.139 -        *(uint32_t *)(arm_mem + addr) = value;
   4.140 +        *(uint32_t *)(aica_main_ram + addr) = value;
   4.141      } else {
   4.142          switch( addr & 0xFFFFF000 ) {
   4.143          case 0x00800000:
   4.144 @@ -180,7 +175,7 @@
   4.145              break;
   4.146          case 0x00803000:
   4.147          case 0x00804000:
   4.148 -            *(uint32_t *)(arm_mem_scratch + addr - 0x00803000) = value;
   4.149 +            *(uint32_t *)(aica_scratch_ram + addr - 0x00803000) = value;
   4.150              break;
   4.151          default:
   4.152              ERROR( "Attempted long write to undefined address: %08X",
   4.153 @@ -209,7 +204,7 @@
   4.154  void arm_write_word( uint32_t addr, uint32_t value )
   4.155  {
   4.156  	if( addr < 0x00200000 ) {
   4.157 -        *(uint16_t *)(arm_mem + addr) = (uint16_t)value;
   4.158 +        *(uint16_t *)(aica_main_ram + addr) = (uint16_t)value;
   4.159  	} else {
   4.160  		
   4.161  	}
   4.162 @@ -218,7 +213,7 @@
   4.163  {
   4.164      if( addr < 0x00200000 ) {
   4.165          /* Main sound ram */
   4.166 -        *(uint8_t *)(arm_mem + addr) = (uint8_t)value;
   4.167 +        *(uint8_t *)(aica_main_ram + addr) = (uint8_t)value;
   4.168      } else {
   4.169          uint32_t tmp;
   4.170          switch( addr & 0xFFFFF000 ) {
   4.171 @@ -239,7 +234,7 @@
   4.172              break;
   4.173          case 0x00803000:
   4.174          case 0x00804000:
   4.175 -            *(uint8_t *)(arm_mem_scratch + addr - 0x00803000) = (uint8_t)value;
   4.176 +            *(uint8_t *)(aica_scratch_ram + addr - 0x00803000) = (uint8_t)value;
   4.177              break;
   4.178          default:
   4.179              ERROR( "Attempted byte write to undefined address: %08X",

     5.1 --- a/src/aica/audio.c	Wed Dec 24 06:06:23 2008 +0000
     5.2 +++ b/src/aica/audio.c	Fri Dec 26 14:25:23 2008 +0000
     5.3 @@ -68,8 +68,6 @@
     5.4  
     5.5  #define NEXT_BUFFER() ((audio.write_buffer == NUM_BUFFERS-1) ? 0 : audio.write_buffer+1)
     5.6  
     5.7 -extern char *arm_mem;
     5.8 -
     5.9  /**
    5.10   * Preserve audio channel state only - don't bother saving the buffers
    5.11   */
    5.12 @@ -299,7 +297,7 @@
    5.13              switch( channel->sample_format ) {
    5.14              case AUDIO_FMT_16BIT:
    5.15                  for( j=0; j<num_samples; j++ ) {
    5.16 -                    sample = ((int16_t *)(arm_mem + channel->start))[channel->posn];
    5.17 +                    sample = ((int16_t *)(aica_main_ram + channel->start))[channel->posn];
    5.18                      result_buf[j][0] += sample * vol_left;
    5.19                      result_buf[j][1] += sample * vol_right;
    5.20  
    5.21 @@ -323,7 +321,7 @@
    5.22                  break;
    5.23              case AUDIO_FMT_8BIT:
    5.24                  for( j=0; j<num_samples; j++ ) {
    5.25 -                    sample = ((int8_t *)(arm_mem + channel->start))[channel->posn] << 8;
    5.26 +                    sample = ((int8_t *)(aica_main_ram + channel->start))[channel->posn] << 8;
    5.27                      result_buf[j][0] += sample * vol_left;
    5.28                      result_buf[j][1] += sample * vol_right;
    5.29  
    5.30 @@ -366,7 +364,7 @@
    5.31                                  break;
    5.32                              }
    5.33                          }
    5.34 -                        uint8_t data = ((uint8_t *)(arm_mem + channel->start))[channel->posn>>1];
    5.35 +                        uint8_t data = ((uint8_t *)(aica_main_ram + channel->start))[channel->posn>>1];
    5.36                          if( channel->posn&1 ) {
    5.37                              adpcm_yamaha_decode_nibble( channel, (data >> 4) & 0x0F );
    5.38                          } else {
    5.39 @@ -478,7 +476,7 @@
    5.40      if( audio.channels[channel].sample_format == AUDIO_FMT_ADPCM ) {
    5.41          audio.channels[channel].adpcm_step = 0;
    5.42          audio.channels[channel].adpcm_predict = 0;
    5.43 -        uint8_t data = ((uint8_t *)(arm_mem + audio.channels[channel].start))[0];
    5.44 +        uint8_t data = ((uint8_t *)(aica_main_ram + audio.channels[channel].start))[0];
    5.45          adpcm_yamaha_decode_nibble( &audio.channels[channel], data & 0x0F );
    5.46      }
    5.47  }

     6.1 --- a/src/dreamcast.c	Wed Dec 24 06:06:23 2008 +0000
     6.2 +++ b/src/dreamcast.c	Fri Dec 26 14:25:23 2008 +0000
     6.3 @@ -29,6 +29,7 @@
     6.4  #include "aica/aica.h"
     6.5  #include "gdrom/ide.h"
     6.6  #include "maple/maple.h"
     6.7 +#include "pvr2/pvr2.h"
     6.8  #include "sh4/sh4.h"
     6.9  #include "sh4/sh4core.h"
    6.10  
    6.11 @@ -70,6 +71,10 @@
    6.12  extern struct mem_region_fn mem_region_pvr2vdma1;
    6.13  extern struct mem_region_fn mem_region_pvr2vdma2;
    6.14  
    6.15 +unsigned char dc_main_ram[16 MB];
    6.16 +unsigned char dc_boot_rom[2 MB];
    6.17 +unsigned char dc_flash_ram[128 KB];
    6.18 +
    6.19  /**
    6.20   * This function is responsible for defining how all the pieces of the
    6.21   * dreamcast actually fit together. 
    6.22 @@ -87,20 +92,19 @@
    6.23      dreamcast_register_module( &mem_module );
    6.24  
    6.25      /* Setup standard memory map */
    6.26 -    dreamcast_has_bios = 
    6.27 -        mem_load_rom( bios_path, 0x00000000, 2 MB, 0x89f2b1a1, MEM_REGION_BIOS, &mem_region_bootrom );
    6.28 -    mem_create_ram_region( 0x00200000, 0x00020000, MEM_REGION_FLASH, &mem_region_flashram );
    6.29 -    mem_create_ram_region( 0x00800000, 2 MB, MEM_REGION_AUDIO, &mem_region_audioram );
    6.30 -    mem_create_ram_region( 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH, &mem_region_audioscratch );
    6.31 -    register_misc_region(  0x04000000, 8 MB, MEM_REGION_VIDEO64, &mem_region_vram64 );
    6.32 -    mem_create_ram_region( 0x05000000, 8 MB, MEM_REGION_VIDEO, &mem_region_vram32 );
    6.33 -    mem_create_repeating_ram_region( 0x0C000000, 16 MB, MEM_REGION_MAIN, &mem_region_sdram, 0x01000000, 0x0F000000 );
    6.34 -    register_misc_region(  0x10000000, 8 MB, "PVR2 TA Command 1", &mem_region_pvr2ta );
    6.35 -    register_misc_region(  0x10800000, 8 MB, "PVR2 YUV Decode 1", &mem_region_pvr2yuv );
    6.36 -    register_misc_region(  0x11000000, 16 MB,"PVR2 VRAM DMA 1", &mem_region_pvr2vdma1 );
    6.37 -    register_misc_region(  0x12000000, 8 MB, "PVR2 TA Command 2", &mem_region_pvr2ta );
    6.38 -    register_misc_region(  0x12800000, 8 MB, "PVR2 YUV Decode 2", &mem_region_pvr2yuv );
    6.39 -    register_misc_region(  0x13000000, 16 MB,"PVR2 VRAM DMA 2", &mem_region_pvr2vdma2 );
    6.40 +    mem_map_region( dc_boot_rom,     0x00000000, 2 MB,   MEM_REGION_BIOS,         &mem_region_bootrom, MEM_FLAG_ROM, 2 MB, 0 );
    6.41 +    mem_map_region( dc_flash_ram,    0x00200000, 128 KB, MEM_REGION_FLASH,        &mem_region_flashram, MEM_FLAG_RAM, 128 KB, 0 );
    6.42 +    mem_map_region( aica_main_ram,   0x00800000, 2 MB,   MEM_REGION_AUDIO,        &mem_region_audioram, MEM_FLAG_RAM, 2 MB, 0 );
    6.43 +    mem_map_region( aica_scratch_ram,0x00703000, 8 KB,   MEM_REGION_AUDIO_SCRATCH,&mem_region_audioscratch, MEM_FLAG_RAM, 8 KB, 0 );
    6.44 +    mem_map_region( NULL,            0x04000000, 8 MB,   MEM_REGION_VIDEO64,      &mem_region_vram64, 0, 8 MB, 0 );
    6.45 +    mem_map_region( pvr2_main_ram,   0x05000000, 8 MB,   MEM_REGION_VIDEO,        &mem_region_vram32, MEM_FLAG_RAM, 8 MB, 0 ); 
    6.46 +    mem_map_region( dc_main_ram,     0x0C000000, 16 MB,  MEM_REGION_MAIN,         &mem_region_sdram, MEM_FLAG_RAM, 0x01000000, 0x0F000000 );
    6.47 +    mem_map_region( NULL,            0x10000000, 8 MB,   MEM_REGION_PVR2TA,       &mem_region_pvr2ta, 0, 0x02000000, 0x12000000 );
    6.48 +    mem_map_region( NULL,            0x10800000, 8 MB,   MEM_REGION_PVR2YUV,      &mem_region_pvr2yuv, 0, 0x02000000, 0x12800000 );
    6.49 +    mem_map_region( NULL,            0x11000000, 16 MB,  MEM_REGION_PVR2VDMA1,    &mem_region_pvr2vdma1, 0, 16 MB, 0 );
    6.50 +    mem_map_region( NULL,            0x13000000, 16 MB,  MEM_REGION_PVR2VDMA2,    &mem_region_pvr2vdma2, 0, 16 MB, 0 );
    6.51 +    
    6.52 +    dreamcast_has_bios = mem_load_rom( dc_boot_rom, bios_path, 2 MB, 0x89f2b1a1 );
    6.53      if( flash_path != NULL && flash_path[0] != '\0' ) {
    6.54          mem_load_block( flash_path, 0x00200000, 0x00020000 );
    6.55      }
    6.56 @@ -119,7 +123,7 @@
    6.57  {
    6.58      const char *bios_path = lxdream_get_config_value(CONFIG_BIOS_PATH);
    6.59      const char *flash_path = lxdream_get_config_value(CONFIG_FLASH_PATH);
    6.60 -    dreamcast_has_bios = mem_load_rom( bios_path, 0x00000000, 0x00200000, 0x89f2b1a1, MEM_REGION_BIOS, &mem_region_bootrom );
    6.61 +    dreamcast_has_bios = mem_load_rom( dc_boot_rom, bios_path, 2 MB, 0x89f2b1a1 );
    6.62      if( flash_path != NULL && flash_path[0] != '\0' ) {
    6.63          mem_load_block( flash_path, 0x00200000, 0x00020000 );
    6.64      }
    6.65 @@ -140,8 +144,8 @@
    6.66  void dreamcast_configure_aica_only( )
    6.67  {
    6.68      dreamcast_register_module( &mem_module );
    6.69 -    mem_create_ram_region( 0x00800000, 2 MB, MEM_REGION_AUDIO, &mem_region_audioram );
    6.70 -    mem_create_ram_region( 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH, &mem_region_audioscratch );
    6.71 +    mem_map_region( aica_main_ram, 0x00800000, 2 MB, MEM_REGION_AUDIO, &mem_region_audioram, MEM_FLAG_RAM, 2 MB, 0 );
    6.72 +    mem_map_region( aica_scratch_ram, 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH, &mem_region_audioscratch, MEM_FLAG_RAM, 8 KB, 0 );
    6.73      dreamcast_register_module( &aica_module );
    6.74      aica_enable();
    6.75      dreamcast_state = STATE_STOPPED;
    6.76 @@ -487,3 +491,69 @@
    6.77      return 0;
    6.78  }
    6.79  
    6.80 +/********************* The Boot ROM address space **********************/
    6.81 +static int32_t FASTCALL ext_bootrom_read_long( sh4addr_t addr )
    6.82 +{
    6.83 +    return *((int32_t *)(dc_boot_rom + (addr&0x001FFFFF)));
    6.84 +}
    6.85 +static int32_t FASTCALL ext_bootrom_read_word( sh4addr_t addr )
    6.86 +{
    6.87 +    return SIGNEXT16(*((int16_t *)(dc_boot_rom + (addr&0x001FFFFF))));
    6.88 +}
    6.89 +static int32_t FASTCALL ext_bootrom_read_byte( sh4addr_t addr )
    6.90 +{
    6.91 +    return SIGNEXT8(*((int16_t *)(dc_boot_rom + (addr&0x001FFFFF))));
    6.92 +}
    6.93 +static void FASTCALL ext_bootrom_read_burst( unsigned char *dest, sh4addr_t addr )
    6.94 +{
    6.95 +    memcpy( dest, dc_boot_rom +(addr&0x001FFFFF), 32 );
    6.96 +}
    6.97 +
    6.98 +struct mem_region_fn mem_region_bootrom = { 
    6.99 +        ext_bootrom_read_long, unmapped_write_long, 
   6.100 +        ext_bootrom_read_word, unmapped_write_long, 
   6.101 +        ext_bootrom_read_byte, unmapped_write_long, 
   6.102 +        ext_bootrom_read_burst, unmapped_write_burst }; 
   6.103 +
   6.104 +/********************* The Flash RAM address space **********************/
   6.105 +static int32_t FASTCALL ext_flashram_read_long( sh4addr_t addr )
   6.106 +{
   6.107 +    return *((int32_t *)(dc_flash_ram + (addr&0x0001FFFF)));
   6.108 +}
   6.109 +static int32_t FASTCALL ext_flashram_read_word( sh4addr_t addr )
   6.110 +{
   6.111 +    return SIGNEXT16(*((int16_t *)(dc_flash_ram + (addr&0x0001FFFF))));
   6.112 +}
   6.113 +static int32_t FASTCALL ext_flashram_read_byte( sh4addr_t addr )
   6.114 +{
   6.115 +    return SIGNEXT8(*((int16_t *)(dc_flash_ram + (addr&0x0001FFFF))));
   6.116 +}
   6.117 +static void FASTCALL ext_flashram_write_long( sh4addr_t addr, uint32_t val )
   6.118 +{
   6.119 +    *(uint32_t *)(dc_flash_ram + (addr&0x0001FFFF)) = val;
   6.120 +    asic_g2_write_word();
   6.121 +}
   6.122 +static void FASTCALL ext_flashram_write_word( sh4addr_t addr, uint32_t val )
   6.123 +{
   6.124 +    *(uint16_t *)(dc_flash_ram + (addr&0x0001FFFF)) = (uint16_t)val;
   6.125 +    asic_g2_write_word();
   6.126 +}
   6.127 +static void FASTCALL ext_flashram_write_byte( sh4addr_t addr, uint32_t val )
   6.128 +{
   6.129 +    *(uint8_t *)(dc_flash_ram + (addr&0x0001FFFF)) = (uint8_t)val;
   6.130 +    asic_g2_write_word();
   6.131 +}
   6.132 +static void FASTCALL ext_flashram_read_burst( unsigned char *dest, sh4addr_t addr )
   6.133 +{
   6.134 +    memcpy( dest, dc_flash_ram+(addr&0x0001FFFF), 32 );
   6.135 +}
   6.136 +static void FASTCALL ext_flashram_write_burst( sh4addr_t addr, unsigned char *src )
   6.137 +{
   6.138 +    memcpy( dc_flash_ram+(addr&0x0001FFFF), src, 32 );
   6.139 +}
   6.140 +
   6.141 +struct mem_region_fn mem_region_flashram = { ext_flashram_read_long, ext_flashram_write_long, 
   6.142 +        ext_flashram_read_word, ext_flashram_write_word, 
   6.143 +        ext_flashram_read_byte, ext_flashram_write_byte, 
   6.144 +        ext_flashram_read_burst, ext_flashram_write_burst }; 
   6.145 +

     7.1 --- a/src/dreamcast.h	Wed Dec 24 06:06:23 2008 +0000
     7.2 +++ b/src/dreamcast.h	Fri Dec 26 14:25:23 2008 +0000
     7.3 @@ -78,6 +78,10 @@
     7.4  #define SCENE_SAVE_MAGIC "%!-lxDream!Scene"
     7.5  #define SCENE_SAVE_VERSION 0x00010000
     7.6  
     7.7 +extern unsigned char dc_main_ram[];
     7.8 +extern unsigned char dc_boot_rom[];
     7.9 +extern unsigned char dc_flash_ram[];
    7.10 +
    7.11  #ifdef __cplusplus
    7.12  }
    7.13  #endif

     8.1 --- a/src/mem.c	Wed Dec 24 06:06:23 2008 +0000
     8.2 +++ b/src/mem.c	Fri Dec 26 14:25:23 2008 +0000
     8.3 @@ -131,19 +131,25 @@
     8.4  
     8.5  void mem_save( FILE *f ) 
     8.6  {
     8.7 -    int i;
     8.8 +    int i, num_ram_regions = 0;
     8.9      uint32_t len;
    8.10  
    8.11 -    /* All memory regions */
    8.12 -    fwrite( &num_mem_rgns, sizeof(num_mem_rgns), 1, f );
    8.13 +    /* All RAM regions (ROM and non-memory regions don't need to be saved)
    8.14 +     * Flash is questionable - for now we save it too */
    8.15      for( i=0; i<num_mem_rgns; i++ ) {
    8.16 -        if( mem_rgn[i].mem != NULL ) {
    8.17 +        if( mem_rgn[i].flags == MEM_FLAG_RAM ) {
    8.18 +            num_ram_regions++;
    8.19 +        }
    8.20 +    }
    8.21 +    fwrite( &num_ram_regions, sizeof(num_ram_regions), 1, f );
    8.22 +    
    8.23 +    for( i=0; i<num_mem_rgns; i++ ) {
    8.24 +        if( mem_rgn[i].flags == MEM_FLAG_RAM ) {
    8.25              fwrite_string( mem_rgn[i].name, f );
    8.26              fwrite( &mem_rgn[i].base, sizeof(uint32_t), 1, f );
    8.27              fwrite( &mem_rgn[i].flags, sizeof(uint32_t), 1, f );
    8.28              fwrite( &mem_rgn[i].size, sizeof(uint32_t), 1, f );
    8.29 -            if( mem_rgn[i].flags != MEM_FLAG_ROM )
    8.30 -                fwrite_gzip( mem_rgn[i].mem, mem_rgn[i].size, 1, f );
    8.31 +            fwrite_gzip( mem_rgn[i].mem, mem_rgn[i].size, 1, f );
    8.32          }
    8.33      }
    8.34  
    8.35 @@ -164,34 +170,51 @@
    8.36      uint32_t len;
    8.37      uint32_t base, size;
    8.38      uint32_t flags;
    8.39 -    int i;
    8.40 +    int i, j;
    8.41 +    int mem_region_loaded[MAX_MEM_REGIONS];
    8.42  
    8.43 -    /* All memory regions */
    8.44 +    /* All RAM regions */
    8.45 +    memset( mem_region_loaded, 0, sizeof(mem_region_loaded) );
    8.46      fread( &len, sizeof(len), 1, f );
    8.47 -    if( len != num_mem_rgns )
    8.48 -        return -1;
    8.49      for( i=0; i<len; i++ ) {
    8.50 -        if( mem_rgn[i].mem != NULL ) {
    8.51 -            fread_string( tmp, sizeof(tmp), f );
    8.52 -            fread( &base, sizeof(base), 1, f );
    8.53 -            fread( &flags, sizeof(flags), 1, f );
    8.54 -            fread( &size, sizeof(size), 1, f );
    8.55 -            if( strcmp( mem_rgn[i].name, tmp ) != 0 ||
    8.56 -                    base != mem_rgn[i].base ||
    8.57 -                    flags != mem_rgn[i].flags ||
    8.58 -                    size != mem_rgn[i].size ) {
    8.59 -                ERROR( "Bad memory region %d %s", i, tmp );
    8.60 -                return -1;
    8.61 +        fread_string( tmp, sizeof(tmp), f );
    8.62 +
    8.63 +        for( j=0; j<num_mem_rgns; j++ ) {
    8.64 +            if( strcasecmp( mem_rgn[j].name, tmp ) == 0 ) {
    8.65 +                fread( &base, sizeof(base), 1, f );
    8.66 +                fread( &flags, sizeof(flags), 1, f );
    8.67 +                fread( &size, sizeof(size), 1, f );
    8.68 +                if( base != mem_rgn[j].base ||
    8.69 +                    flags != mem_rgn[j].flags ||
    8.70 +                    size != mem_rgn[j].size ) {
    8.71 +                    ERROR( "Bad memory block %d %s (not mapped to expected region)", i, tmp );
    8.72 +                    return -1;
    8.73 +                }
    8.74 +                if( flags != MEM_FLAG_RAM ) {
    8.75 +                    ERROR( "Unexpected memory block %d %s (Not a RAM region)", i, tmp );
    8.76 +                    return -1;
    8.77 +                }
    8.78 +                fread_gzip( mem_rgn[j].mem, size, 1, f );
    8.79 +                mem_region_loaded[j] = 1;
    8.80              }
    8.81 -            if( flags != MEM_FLAG_ROM )
    8.82 -                fread_gzip( mem_rgn[i].mem, size, 1, f );
    8.83 +        }
    8.84 +    }
    8.85 +    /* Make sure we got all the memory regions we expected */
    8.86 +    for( i=0; i<num_mem_rgns; i++ ) {
    8.87 +        if( mem_rgn[i].flags == MEM_FLAG_RAM &&
    8.88 +            mem_region_loaded[i] == 0 ) {
    8.89 +            ERROR( "Missing memory block %s (not found in save state)", mem_rgn[i].name );
    8.90 +            return -1;
    8.91          }
    8.92      }
    8.93  
    8.94      /* All MMIO regions */
    8.95      fread( &len, sizeof(len), 1, f );
    8.96 -    if( len != num_io_rgns ) 
    8.97 +    if( len != num_io_rgns ) {
    8.98 +        ERROR( "Unexpected IO region count %d (expected %d)", len, num_io_rgns );
    8.99          return -1;
   8.100 +    }
   8.101 +    
   8.102      for( i=0; i<len; i++ ) {
   8.103          fread_string( tmp, sizeof(tmp), f );
   8.104          fread( &base, sizeof(base), 1, f );
   8.105 @@ -270,8 +293,8 @@
   8.106  }
   8.107  
   8.108  struct mem_region *mem_map_region( void *mem, uint32_t base, uint32_t size,
   8.109 -                                   const char *name, mem_region_fn_t fn, int flags, uint32_t repeat_offset,
   8.110 -                                   uint32_t repeat_until )
   8.111 +                                   const char *name, mem_region_fn_t fn, int flags, 
   8.112 +                                   uint32_t repeat_offset, uint32_t repeat_until )
   8.113  {
   8.114      int i;
   8.115      mem_rgn[num_mem_rgns].base = base;
   8.116 @@ -284,7 +307,9 @@
   8.117  
   8.118      do {
   8.119          for( i=0; i<size>>LXDREAM_PAGE_BITS; i++ ) {
   8.120 -            page_map[(base>>LXDREAM_PAGE_BITS)+i] = mem + (i<<LXDREAM_PAGE_BITS);
   8.121 +            if( mem != NULL ) {
   8.122 +                page_map[(base>>LXDREAM_PAGE_BITS)+i] = mem + (i<<LXDREAM_PAGE_BITS);
   8.123 +            }
   8.124              ext_address_space[(base>>LXDREAM_PAGE_BITS)+i] = fn;
   8.125              mem_page_remapped( base + (i<<LXDREAM_PAGE_BITS), fn );
   8.126          }
   8.127 @@ -294,78 +319,39 @@
   8.128      return &mem_rgn[num_mem_rgns-1];
   8.129  }
   8.130  
   8.131 -void register_misc_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn )
   8.132 +gboolean mem_load_rom( void *output, const gchar *file, uint32_t size, uint32_t crc )
   8.133  {
   8.134 -    mem_rgn[num_mem_rgns].base = base;
   8.135 -    mem_rgn[num_mem_rgns].size = size;
   8.136 -    mem_rgn[num_mem_rgns].flags = 0;
   8.137 -    mem_rgn[num_mem_rgns].name = name;
   8.138 -    mem_rgn[num_mem_rgns].mem = NULL;
   8.139 -    mem_rgn[num_mem_rgns].fn = fn;
   8.140 -    num_mem_rgns++;
   8.141 +    if( file != NULL && file[0] != '\0' ) {
   8.142 +        FILE *f = fopen(file,"r");
   8.143 +        struct stat st;
   8.144 +        uint32_t calc_crc;
   8.145  
   8.146 -    int count = size >> 12;
   8.147 -    mem_region_fn_t *ptr = &ext_address_space[base>>12];
   8.148 -    while( count-- > 0 ) {
   8.149 -        *ptr++ = fn;
   8.150 -    }
   8.151 -}
   8.152 -
   8.153 -void *mem_create_ram_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn )
   8.154 -{
   8.155 -    return mem_create_repeating_ram_region( base, size, name, fn, size, base );
   8.156 -}
   8.157 -
   8.158 -void *mem_create_repeating_ram_region( uint32_t base, uint32_t size, const char *name,
   8.159 -                                       mem_region_fn_t fn,
   8.160 -                                       uint32_t repeat_offset, uint32_t repeat_until )
   8.161 -{
   8.162 -    char *mem;
   8.163 -
   8.164 -    assert( (base&0xFFFFF000) == base ); /* must be page aligned */
   8.165 -    assert( (size&0x00000FFF) == 0 );
   8.166 -    assert( num_mem_rgns < MAX_MEM_REGIONS );
   8.167 -    assert( page_map != NULL );
   8.168 -
   8.169 -    mem = mem_alloc_pages( size>>LXDREAM_PAGE_BITS );
   8.170 -
   8.171 -    mem_map_region( mem, base, size, name, fn, MEM_FLAG_RAM, repeat_offset, repeat_until );
   8.172 -
   8.173 -    return mem;
   8.174 -}
   8.175 -
   8.176 -gboolean mem_load_rom( const gchar *file, uint32_t base, uint32_t size, uint32_t crc,
   8.177 -                       const gchar *region_name, mem_region_fn_t fn )
   8.178 -{
   8.179 -    sh4ptr_t mem;
   8.180 -    uint32_t calc_crc;
   8.181 -    int status;
   8.182 -
   8.183 -    mem = mem_get_region(base);
   8.184 -    if( mem == NULL ) {
   8.185 -        mem = mmap( NULL, size, PROT_WRITE|PROT_READ, MAP_ANON|MAP_PRIVATE, -1, 0 );
   8.186 -        if( mem == MAP_FAILED ) {
   8.187 -            ERROR( "Unable to allocate ROM memory: %s (%s)", file, strerror(errno) );
   8.188 +        if( f == NULL ) {
   8.189 +            ERROR( "Unable to load file '%s': %s", file, strerror(errno) );
   8.190              return FALSE;
   8.191          }
   8.192 -        mem_map_region( mem, base, size, region_name, fn, MEM_FLAG_ROM, size, base );
   8.193 -    } else {
   8.194 -        mprotect( mem, size, PROT_READ|PROT_WRITE );
   8.195 -    }
   8.196  
   8.197 -    if( file != NULL && file[0] != '\0' ) {
   8.198 -        status = mem_load_block( file, base, size );
   8.199 -        mprotect( mem, size, PROT_READ );
   8.200 +        fstat( fileno(f), &st );
   8.201 +        if( st.st_size != size ) {
   8.202 +            ERROR( "File '%s' is invalid, expected %d bytes but was %d bytes long.", file, size, st.st_size );
   8.203 +            fclose(f);
   8.204 +            return FALSE;
   8.205 +        }
   8.206 +        
   8.207 +        if( fread( output, 1, size, f ) != size ) { 
   8.208 +            ERROR( "Failed to load file '%s': %s", file, strerror(errno) );
   8.209 +            fclose(f);
   8.210 +            return FALSE;
   8.211 +        }
   8.212  
   8.213 -        if( status == 0 ) {
   8.214 -            /* CRC check only if we loaded something */
   8.215 -            calc_crc = crc32(0L, (sh4ptr_t)mem, size);
   8.216 -            if( calc_crc != crc ) {
   8.217 -                WARN( "Bios CRC Mismatch in %s: %08X (expected %08X)",
   8.218 -                        file, calc_crc, crc);
   8.219 -            }
   8.220 -            return TRUE;
   8.221 +        /* CRC check only if we loaded something */
   8.222 +        calc_crc = crc32(0L, output, size);
   8.223 +        if( calc_crc != crc ) {
   8.224 +            WARN( "Bios CRC Mismatch in %s: %08X (expected %08X)",
   8.225 +                   file, calc_crc, crc);
   8.226          }
   8.227 +        /* Even if the CRC fails, continue normally */
   8.228 +        return TRUE;
   8.229      }
   8.230      return FALSE;
   8.231  }
   8.232 @@ -413,16 +399,9 @@
   8.233      while( *io ) register_io_region( *io++ );
   8.234  }
   8.235  
   8.236 -int mem_has_page( uint32_t addr )
   8.237 +gboolean mem_has_page( uint32_t addr )
   8.238  {
   8.239 -    sh4ptr_t page = page_map[ (addr & 0x1FFFFFFF) >> 12 ];
   8.240 -    return page != NULL;
   8.241 -}
   8.242 -
   8.243 -sh4ptr_t mem_get_page( uint32_t addr )
   8.244 -{
   8.245 -    sh4ptr_t page = page_map[ (addr & 0x1FFFFFFF) >> 12 ];
   8.246 -    return page;
   8.247 +    return ext_address_space[ (addr&0x1FFFFFFF)>>12 ] != &mem_region_unmapped;
   8.248  }
   8.249  
   8.250  sh4ptr_t mem_get_region( uint32_t addr )
   8.251 @@ -437,22 +416,7 @@
   8.252  
   8.253  void mem_write_long( sh4addr_t addr, uint32_t value )
   8.254  {
   8.255 -    sh4ptr_t ptr = mem_get_region(addr);
   8.256 -    assert(ptr != NULL);
   8.257 -    *((uint32_t *)ptr) = value;
   8.258 -}
   8.259 -
   8.260 -struct mmio_region *mem_get_io_region( uint32_t addr )
   8.261 -{
   8.262 -    if( addr > 0xFF000000 ) {
   8.263 -        return P4_io[(addr&0x00FFFFFF)>>12];
   8.264 -    }
   8.265 -    sh4ptr_t page = page_map[(addr&0x1FFFFFFF)>>12];
   8.266 -    if( ((uintptr_t)page) < MAX_IO_REGIONS ) {
   8.267 -        return io_rgn[(uintptr_t)page];
   8.268 -    } else {
   8.269 -        return NULL;
   8.270 -    }
   8.271 +    ext_address_space[(addr&0x1FFFFFFF)>>12]->write_long(addr, value);
   8.272  }
   8.273  
   8.274  struct mmio_region *mem_get_io_region_by_name( const gchar *name )

     9.1 --- a/src/mem.h	Wed Dec 24 06:06:23 2008 +0000
     9.2 +++ b/src/mem.h	Fri Dec 26 14:25:23 2008 +0000
     9.3 @@ -68,14 +68,17 @@
     9.4  #define MEM_REGION_AUDIO "Audio RAM"
     9.5  #define MEM_REGION_AUDIO_SCRATCH "Audio Scratch RAM"
     9.6  #define MEM_REGION_FLASH "System Flash"
     9.7 +#define MEM_REGION_PVR2TA "PVR2 TA Command"
     9.8 +#define MEM_REGION_PVR2YUV "PVR2 YUV Decode"
     9.9 +#define MEM_REGION_PVR2VDMA1 "PVR2 VRAM DMA 1"
    9.10 +#define MEM_REGION_PVR2VDMA2 "PVR2 VRAM DMA 2"
    9.11  
    9.12  typedef gboolean (*mem_page_remapped_hook_t)(sh4addr_t page, mem_region_fn_t newfn, void *user_data);
    9.13  DECLARE_HOOK( mem_page_remapped_hook, mem_page_remapped_hook_t );
    9.14  
    9.15 -void *mem_create_ram_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn );
    9.16 -void *mem_create_repeating_ram_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn,
    9.17 -				       uint32_t repeat_offset, uint32_t last_repeat );
    9.18 -void register_misc_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn );
    9.19 +struct mem_region *mem_map_region( void *mem, uint32_t base, uint32_t size,
    9.20 +                                   const char *name, mem_region_fn_t fn, int flags, uint32_t repeat_offset,
    9.21 +                                   uint32_t repeat_until );
    9.22  
    9.23  /**
    9.24   * Load a ROM image from the specified filename. If the memory region has not
    9.25 @@ -83,13 +86,11 @@
    9.26   * If the CRC check fails, a warning will be printed.
    9.27   * @return TRUE if the image was loaded successfully (irrespective of CRC failure).
    9.28   */
    9.29 -gboolean mem_load_rom( const gchar *filename, uint32_t base, uint32_t size, 
    9.30 -		       uint32_t crc, const gchar *region_name, mem_region_fn_t fn );
    9.31 +gboolean mem_load_rom( void *output, const gchar *filename, uint32_t size, uint32_t crc ); 
    9.32  void *mem_alloc_pages( int n );
    9.33  sh4ptr_t mem_get_region( uint32_t addr );
    9.34  sh4ptr_t mem_get_region_by_name( const char *name );
    9.35 -int mem_has_page( uint32_t addr );
    9.36 -sh4ptr_t mem_get_page( uint32_t addr );
    9.37 +gboolean mem_has_page( uint32_t addr );
    9.38  int mem_load_block( const gchar *filename, uint32_t base, uint32_t size );
    9.39  int mem_save_block( const gchar *filename, uint32_t base, uint32_t size );
    9.40  void mem_set_trace( const gchar *tracelist, int flag );
    9.41 @@ -130,7 +131,6 @@
    9.42  void mem_delete_watch( watch_point_t watch );
    9.43  watch_point_t mem_is_watched( uint32_t addr, int size, int op );
    9.44  
    9.45 -extern sh4ptr_t *page_map;
    9.46  extern mem_region_fn_t *ext_address_space;
    9.47  
    9.48  #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)

    10.1 --- a/src/pvr2/glrender.c	Wed Dec 24 06:06:23 2008 +0000
    10.2 +++ b/src/pvr2/glrender.c	Fri Dec 26 14:25:23 2008 +0000
    10.3 @@ -24,7 +24,7 @@
    10.4  #include "pvr2/scene.h"
    10.5  #include "pvr2/glutil.h"
    10.6  
    10.7 -#define IS_EMPTY_TILE_LIST(p) ((*((uint32_t *)(video_base+(p))) >> 28) == 0x0F)
    10.8 +#define IS_EMPTY_TILE_LIST(p) ((*((uint32_t *)(pvr2_main_ram+(p))) >> 28) == 0x0F)
    10.9  
   10.10  int pvr2_poly_depthmode[8] = { GL_NEVER, GL_LESS, GL_EQUAL, GL_LEQUAL,
   10.11          GL_GREATER, GL_NOTEQUAL, GL_GEQUAL, 
   10.12 @@ -274,7 +274,7 @@
   10.13  
   10.14  void gl_render_tilelist( pvraddr_t tile_entry, GLint depth_mode )
   10.15  {
   10.16 -    uint32_t *tile_list = (uint32_t *)(video_base+tile_entry);
   10.17 +    uint32_t *tile_list = (uint32_t *)(pvr2_main_ram+tile_entry);
   10.18      int strip_count;
   10.19      struct polygon_struct *poly;
   10.20  
   10.21 @@ -287,7 +287,7 @@
   10.22          case 0x0F:
   10.23              return; // End-of-list
   10.24          case 0x0E:
   10.25 -            tile_list = (uint32_t *)(video_base + (entry&0x007FFFFF));
   10.26 +            tile_list = (uint32_t *)(pvr2_main_ram + (entry&0x007FFFFF));
   10.27              break;
   10.28          case 0x08: case 0x09: case 0x0A: case 0x0B:
   10.29              strip_count = ((entry >> 25) & 0x0F)+1;
   10.30 @@ -313,7 +313,7 @@
   10.31   */
   10.32  void gl_render_tilelist_depthonly( pvraddr_t tile_entry )
   10.33  {
   10.34 -    uint32_t *tile_list = (uint32_t *)(video_base+tile_entry);
   10.35 +    uint32_t *tile_list = (uint32_t *)(pvr2_main_ram+tile_entry);
   10.36      int strip_count;
   10.37      struct polygon_struct *poly;
   10.38      
   10.39 @@ -330,7 +330,7 @@
   10.40          case 0x0F:
   10.41              return; // End-of-list
   10.42          case 0x0E:
   10.43 -            tile_list = (uint32_t *)(video_base + (entry&0x007FFFFF));
   10.44 +            tile_list = (uint32_t *)(pvr2_main_ram + (entry&0x007FFFFF));
   10.45              break;
   10.46          case 0x08: case 0x09: case 0x0A: case 0x0B:
   10.47              strip_count = ((entry >> 25) & 0x0F)+1;
   10.48 @@ -428,7 +428,7 @@
   10.49  
   10.50  void gl_render_modifier_tilelist( pvraddr_t tile_entry, uint32_t tile_bounds[] )
   10.51  {
   10.52 -    uint32_t *tile_list = (uint32_t *)(video_base+tile_entry);
   10.53 +    uint32_t *tile_list = (uint32_t *)(pvr2_main_ram+tile_entry);
   10.54      int strip_count;
   10.55      struct polygon_struct *poly;
   10.56  
   10.57 @@ -456,7 +456,7 @@
   10.58              glStencilOp( GL_KEEP, GL_KEEP, GL_KEEP );
   10.59              return; // End-of-list
   10.60          case 0x0E:
   10.61 -            tile_list = (uint32_t *)(video_base + (entry&0x007FFFFF));
   10.62 +            tile_list = (uint32_t *)(pvr2_main_ram + (entry&0x007FFFFF));
   10.63              break;
   10.64          case 0x08: case 0x09: case 0x0A: case 0x0B:
   10.65              strip_count = ((entry >> 25) & 0x0F)+1;

    11.1 --- a/src/pvr2/pvr2.c	Wed Dec 24 06:06:23 2008 +0000
    11.2 +++ b/src/pvr2/pvr2.c	Fri Dec 26 14:25:23 2008 +0000
    11.3 @@ -31,8 +31,6 @@
    11.4  #define MMIO_IMPL
    11.5  #include "pvr2/pvr2mmio.h"
    11.6  
    11.7 -unsigned char *video_base;
    11.8 -
    11.9  #define MAX_RENDER_BUFFERS 4
   11.10  
   11.11  #define HPOS_PER_FRAME 0
   11.12 @@ -146,7 +144,6 @@
   11.13      register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
   11.14      register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
   11.15      register_event_callback( EVENT_GUNPOS, pvr2_gunpos_callback );
   11.16 -    video_base = mem_get_region_by_name( MEM_REGION_VIDEO );
   11.17      texcache_init();
   11.18      pvr2_reset();
   11.19      pvr2_ta_reset();
   11.20 @@ -444,7 +441,7 @@
   11.21          }
   11.22          fbuf.address = (fbuf.address & 0x00FFFFFF) + PVR2_RAM_BASE;
   11.23          fbuf.inverted = FALSE;
   11.24 -        fbuf.data = video_base + (fbuf.address&0x00FFFFFF);
   11.25 +        fbuf.data = pvr2_main_ram + (fbuf.address&0x00FFFFFF);
   11.26  
   11.27          render_buffer_t rbuf = pvr2_get_render_buffer( &fbuf );
   11.28          if( rbuf == NULL ) {

    12.1 --- a/src/pvr2/pvr2.h	Wed Dec 24 06:06:23 2008 +0000
    12.2 +++ b/src/pvr2/pvr2.h	Fri Dec 26 14:25:23 2008 +0000
    12.3 @@ -134,6 +134,8 @@
    12.4  
    12.5  /****************************** Frame Buffer *****************************/
    12.6  
    12.7 +extern unsigned char pvr2_main_ram[];
    12.8 +
    12.9  /**
   12.10   * Write a block of data to an address in the DMA range (0x10000000 -
   12.11   * 0x13FFFFFF), ie TA, YUV, or texture ram.

    13.1 --- a/src/pvr2/pvr2mem.c	Wed Dec 24 06:06:23 2008 +0000
    13.2 +++ b/src/pvr2/pvr2mem.c	Fri Dec 26 14:25:23 2008 +0000
    13.3 @@ -23,51 +23,51 @@
    13.4  #include "asic.h"
    13.5  #include "dream.h"
    13.6  
    13.7 -extern unsigned char *video_base;
    13.8 +unsigned char pvr2_main_ram[8 MB];
    13.9  
   13.10  /************************* VRAM32 address space ***************************/
   13.11  
   13.12  static int32_t FASTCALL pvr2_vram32_read_long( sh4addr_t addr )
   13.13  {
   13.14      pvr2_render_buffer_invalidate(addr, FALSE);
   13.15 -    return *((int32_t *)(video_base+(addr&0x007FFFFF)));
   13.16 +    return *((int32_t *)(pvr2_main_ram+(addr&0x007FFFFF)));
   13.17  }
   13.18  static int32_t FASTCALL pvr2_vram32_read_word( sh4addr_t addr )
   13.19  {
   13.20      pvr2_render_buffer_invalidate(addr, FALSE);
   13.21 -    return SIGNEXT16(*((int16_t *)(video_base+(addr&0x007FFFFF))));
   13.22 +    return SIGNEXT16(*((int16_t *)(pvr2_main_ram+(addr&0x007FFFFF))));
   13.23  }
   13.24  static int32_t FASTCALL pvr2_vram32_read_byte( sh4addr_t addr )
   13.25  {
   13.26      pvr2_render_buffer_invalidate(addr, FALSE);
   13.27 -    return SIGNEXT8(*((int8_t *)(video_base+(addr&0x007FFFFF))));
   13.28 +    return SIGNEXT8(*((int8_t *)(pvr2_main_ram+(addr&0x007FFFFF))));
   13.29  }
   13.30  static void FASTCALL pvr2_vram32_write_long( sh4addr_t addr, uint32_t val )
   13.31  {
   13.32      pvr2_render_buffer_invalidate(addr, TRUE);
   13.33 -    *(uint32_t *)(video_base + (addr&0x007FFFFF)) = val;
   13.34 +    *(uint32_t *)(pvr2_main_ram + (addr&0x007FFFFF)) = val;
   13.35  }
   13.36  static void FASTCALL pvr2_vram32_write_word( sh4addr_t addr, uint32_t val )
   13.37  {
   13.38      pvr2_render_buffer_invalidate(addr, TRUE);
   13.39 -    *(uint16_t *)(video_base + (addr&0x007FFFFF)) = (uint16_t)val;
   13.40 +    *(uint16_t *)(pvr2_main_ram + (addr&0x007FFFFF)) = (uint16_t)val;
   13.41  }
   13.42  static void FASTCALL pvr2_vram32_write_byte( sh4addr_t addr, uint32_t val )
   13.43  {
   13.44      pvr2_render_buffer_invalidate(addr, TRUE);
   13.45 -    *(uint8_t *)(video_base + (addr&0x007FFFFF)) = (uint8_t)val;
   13.46 +    *(uint8_t *)(pvr2_main_ram + (addr&0x007FFFFF)) = (uint8_t)val;
   13.47  }
   13.48  static void FASTCALL pvr2_vram32_read_burst( unsigned char *dest, sh4addr_t addr )
   13.49  {
   13.50      // Render buffers pretty much have to be (at least) 32-byte aligned
   13.51      pvr2_render_buffer_invalidate(addr, FALSE);
   13.52 -    memcpy( dest, (video_base + (addr&0x007FFFFF)), 32 );
   13.53 +    memcpy( dest, (pvr2_main_ram + (addr&0x007FFFFF)), 32 );
   13.54  }
   13.55  static void FASTCALL pvr2_vram32_write_burst( sh4addr_t addr, unsigned char *src )
   13.56  {
   13.57      // Render buffers pretty much have to be (at least) 32-byte aligned
   13.58      pvr2_render_buffer_invalidate(addr, TRUE);
   13.59 -    memcpy( (video_base + (addr&0x007FFFFF)), src, 32 );    
   13.60 +    memcpy( (pvr2_main_ram + (addr&0x007FFFFF)), src, 32 );    
   13.61  }
   13.62  
   13.63  struct mem_region_fn mem_region_vram32 = { pvr2_vram32_read_long, pvr2_vram32_write_long, 
   13.64 @@ -83,40 +83,40 @@
   13.65  {
   13.66      addr = TRANSLATE_VIDEO_64BIT_ADDRESS(addr);
   13.67      pvr2_render_buffer_invalidate(addr, FALSE);
   13.68 -    return *((int32_t *)(video_base+(addr&0x007FFFFF)));
   13.69 +    return *((int32_t *)(pvr2_main_ram+(addr&0x007FFFFF)));
   13.70  }
   13.71  static int32_t FASTCALL pvr2_vram64_read_word( sh4addr_t addr )
   13.72  {
   13.73      addr = TRANSLATE_VIDEO_64BIT_ADDRESS(addr);
   13.74      pvr2_render_buffer_invalidate(addr, FALSE);
   13.75 -    return SIGNEXT16(*((int16_t *)(video_base+(addr&0x007FFFFF))));
   13.76 +    return SIGNEXT16(*((int16_t *)(pvr2_main_ram+(addr&0x007FFFFF))));
   13.77  }
   13.78  static int32_t FASTCALL pvr2_vram64_read_byte( sh4addr_t addr )
   13.79  {
   13.80      addr = TRANSLATE_VIDEO_64BIT_ADDRESS(addr);
   13.81      pvr2_render_buffer_invalidate(addr, FALSE);
   13.82 -    return SIGNEXT8(*((int8_t *)(video_base+(addr&0x007FFFFF))));
   13.83 +    return SIGNEXT8(*((int8_t *)(pvr2_main_ram+(addr&0x007FFFFF))));
   13.84  }
   13.85  static void FASTCALL pvr2_vram64_write_long( sh4addr_t addr, uint32_t val )
   13.86  {
   13.87      texcache_invalidate_page(addr& 0x007FFFFF);
   13.88      addr = TRANSLATE_VIDEO_64BIT_ADDRESS(addr);
   13.89      pvr2_render_buffer_invalidate(addr, TRUE);
   13.90 -    *(uint32_t *)(video_base + (addr&0x007FFFFF)) = val;
   13.91 +    *(uint32_t *)(pvr2_main_ram + (addr&0x007FFFFF)) = val;
   13.92  }
   13.93  static void FASTCALL pvr2_vram64_write_word( sh4addr_t addr, uint32_t val )
   13.94  {
   13.95      texcache_invalidate_page(addr& 0x007FFFFF);
   13.96      addr = TRANSLATE_VIDEO_64BIT_ADDRESS(addr);
   13.97      pvr2_render_buffer_invalidate(addr, TRUE);
   13.98 -    *(uint16_t *)(video_base + (addr&0x007FFFFF)) = (uint16_t)val;
   13.99 +    *(uint16_t *)(pvr2_main_ram + (addr&0x007FFFFF)) = (uint16_t)val;
  13.100  }
  13.101  static void FASTCALL pvr2_vram64_write_byte( sh4addr_t addr, uint32_t val )
  13.102  {
  13.103      texcache_invalidate_page(addr& 0x007FFFFF);
  13.104      addr = TRANSLATE_VIDEO_64BIT_ADDRESS(addr);
  13.105      pvr2_render_buffer_invalidate(addr, TRUE);
  13.106 -    *(uint8_t *)(video_base + (addr&0x007FFFFF)) = (uint8_t)val;
  13.107 +    *(uint8_t *)(pvr2_main_ram + (addr&0x007FFFFF)) = (uint8_t)val;
  13.108  }
  13.109  static void FASTCALL pvr2_vram64_read_burst( unsigned char *dest, sh4addr_t addr )
  13.110  {
  13.111 @@ -141,7 +141,7 @@
  13.112          pvr2_vram64_write( destaddr, src, 32 );
  13.113      } else {
  13.114          destaddr &= PVR2_RAM_MASK;
  13.115 -        unsigned char *dest = video_base + destaddr;
  13.116 +        unsigned char *dest = pvr2_main_ram + destaddr;
  13.117          memcpy( dest, src, 32 );
  13.118      }   
  13.119  }
  13.120 @@ -153,7 +153,7 @@
  13.121          pvr2_vram64_write( destaddr, src, 32 );
  13.122      } else {
  13.123          destaddr &= PVR2_RAM_MASK;
  13.124 -        unsigned char *dest = video_base + destaddr;
  13.125 +        unsigned char *dest = pvr2_main_ram + destaddr;
  13.126          memcpy( dest, src, 32 );
  13.127      }
  13.128  }
  13.129 @@ -204,7 +204,7 @@
  13.130              pvr2_vram64_write( destaddr, src, count );
  13.131          } else {
  13.132              destaddr &= PVR2_RAM_MASK;
  13.133 -            unsigned char *dest = video_base + destaddr;
  13.134 +            unsigned char *dest = pvr2_main_ram + destaddr;
  13.135              if( PVR2_RAM_SIZE - destaddr < count ) {
  13.136                  count = PVR2_RAM_SIZE - destaddr;
  13.137              }
  13.138 @@ -222,7 +222,7 @@
  13.139              pvr2_vram64_write( destaddr, src, count );
  13.140          } else {
  13.141              destaddr &= PVR2_RAM_MASK;
  13.142 -            unsigned char *dest = video_base + destaddr;
  13.143 +            unsigned char *dest = pvr2_main_ram + destaddr;
  13.144              if( PVR2_RAM_SIZE - destaddr < count ) {
  13.145                  count = PVR2_RAM_SIZE - destaddr;
  13.146              }
  13.147 @@ -247,7 +247,7 @@
  13.148          texcache_invalidate_page( i );
  13.149      }
  13.150  
  13.151 -    banks[0] = ((uint32_t *)(video_base + ((destaddr & 0x007FFFF8) >>1)));
  13.152 +    banks[0] = ((uint32_t *)(pvr2_main_ram + ((destaddr & 0x007FFFF8) >>1)));
  13.153      banks[1] = banks[0] + 0x100000;
  13.154      if( bank_flag )
  13.155          banks[0]++;
  13.156 @@ -298,7 +298,7 @@
  13.157          texcache_invalidate_page( i );
  13.158      }
  13.159  
  13.160 -    banks[0] = (uint32_t *)(video_base + (destaddr >>1));
  13.161 +    banks[0] = (uint32_t *)(pvr2_main_ram + (destaddr >>1));
  13.162      banks[1] = banks[0] + 0x100000;
  13.163  
  13.164      for( i=0; i<line_count; i++ ) {
  13.165 @@ -342,7 +342,7 @@
  13.166          line_bytes = dest_line_bytes >> 2;
  13.167      }
  13.168  
  13.169 -    banks[0] = (uint32_t *)(video_base + (srcaddr>>1));
  13.170 +    banks[0] = (uint32_t *)(pvr2_main_ram + (srcaddr>>1));
  13.171      banks[1] = banks[0] + 0x100000;
  13.172      if( bank_flag )
  13.173          banks[0]++;
  13.174 @@ -473,7 +473,7 @@
  13.175  
  13.176      srcaddr = srcaddr & 0x7FFFF8;
  13.177  
  13.178 -    banks[0] = (uint8_t *)(video_base + (srcaddr>>1));
  13.179 +    banks[0] = (uint8_t *)(pvr2_main_ram + (srcaddr>>1));
  13.180      banks[1] = banks[0] + 0x400000;
  13.181      if( offset_flag & 0x04 ) { // If source is not 64-bit aligned, swap the banks
  13.182          uint8_t *tmp = banks[0];
  13.183 @@ -515,7 +515,7 @@
  13.184  
  13.185      srcaddr = srcaddr & 0x7FFFF8;
  13.186  
  13.187 -    banks[0] = (uint8_t *)(video_base + (srcaddr>>1));
  13.188 +    banks[0] = (uint8_t *)(pvr2_main_ram + (srcaddr>>1));
  13.189      banks[1] = banks[0] + 0x400000;
  13.190      if( offset_flag & 0x04 ) { // If source is not 64-bit aligned, swap the banks
  13.191          uint8_t *tmp = banks[0];
  13.192 @@ -556,7 +556,7 @@
  13.193  
  13.194      srcaddr = srcaddr & 0x7FFFF8;
  13.195  
  13.196 -    banks[0] = (uint16_t *)(video_base + (srcaddr>>1));
  13.197 +    banks[0] = (uint16_t *)(pvr2_main_ram + (srcaddr>>1));
  13.198      banks[1] = banks[0] + 0x200000;
  13.199      if( offset_flag & 0x02 ) { // If source is not 64-bit aligned, swap the banks
  13.200          uint16_t *tmp = banks[0];
  13.201 @@ -586,7 +586,7 @@
  13.202                               uint32_t line_size, uint32_t dest_stride,
  13.203                               uint32_t src_stride )
  13.204  {
  13.205 -    unsigned char *dest = video_base + (destaddr & 0x007FFFFF);
  13.206 +    unsigned char *dest = pvr2_main_ram + (destaddr & 0x007FFFFF);
  13.207      unsigned char *p = src + src_size - src_stride;
  13.208      while( p >= src ) {
  13.209          memcpy( dest, p, line_size );
  13.210 @@ -611,7 +611,7 @@
  13.211          texcache_invalidate_page( i );
  13.212      }
  13.213  
  13.214 -    banks[0] = (uint32_t *)(video_base + (destaddr >>1));
  13.215 +    banks[0] = (uint32_t *)(pvr2_main_ram + (destaddr >>1));
  13.216      banks[1] = banks[0] + 0x100000;
  13.217  
  13.218      while( dwsrc >= (uint32_t *)src ) { 
  13.219 @@ -633,7 +633,7 @@
  13.220                               uint32_t line_size, uint32_t dest_stride,
  13.221                               uint32_t src_stride, int bpp )
  13.222  {
  13.223 -    unsigned char *dest = video_base + (destaddr & 0x007FFFFF);
  13.224 +    unsigned char *dest = pvr2_main_ram + (destaddr & 0x007FFFFF);
  13.225      unsigned char *p = src + src_size - src_stride;
  13.226      while( p >= src ) {
  13.227          unsigned char *s = p, *d = dest;
  13.228 @@ -660,7 +660,7 @@
  13.229      if( srcaddr + length > 0x800000 )
  13.230          length = 0x800000 - srcaddr;
  13.231  
  13.232 -    banks[0] = ((uint32_t *)(video_base + ((srcaddr&0x007FFFF8)>>1)));
  13.233 +    banks[0] = ((uint32_t *)(pvr2_main_ram + ((srcaddr&0x007FFFF8)>>1)));
  13.234      banks[1] = banks[0] + 0x100000;
  13.235      if( bank_flag )
  13.236          banks[0]++;

    14.1 --- a/src/pvr2/rendsave.c	Wed Dec 24 06:06:23 2008 +0000
    14.2 +++ b/src/pvr2/rendsave.c	Fri Dec 26 14:25:23 2008 +0000
    14.3 @@ -31,8 +31,6 @@
    14.4  #define SAVE_PAGE_SIZE 1024
    14.5  #define SAVE_PAGE_COUNT 8192
    14.6  
    14.7 -extern char *video_base;
    14.8 -
    14.9  /* Determine pages of memory to save. Start walking from the render tilemap
   14.10   * data and build up a page list
   14.11   */
   14.12 @@ -88,7 +86,7 @@
   14.13              uint32_t length = (j-i) * SAVE_PAGE_SIZE;
   14.14              fwrite( &start, sizeof(uint32_t), 1, f );
   14.15              fwrite( &length, sizeof(uint32_t), 1, f );
   14.16 -            fwrite( video_base + start, 1, length, f );
   14.17 +            fwrite( pvr2_main_ram + start, 1, length, f );
   14.18              i = j-1;
   14.19          }
   14.20      }

    15.1 --- a/src/pvr2/rendsort.c	Wed Dec 24 06:06:23 2008 +0000
    15.2 +++ b/src/pvr2/rendsort.c	Fri Dec 26 14:25:23 2008 +0000
    15.3 @@ -41,14 +41,14 @@
    15.4   * pvr memory address.
    15.5   */
    15.6  static int sort_count_triangles( pvraddr_t tile_entry ) {
    15.7 -    uint32_t *tile_list = (uint32_t *)(video_base+tile_entry);
    15.8 +    uint32_t *tile_list = (uint32_t *)(pvr2_main_ram+tile_entry);
    15.9      int count = 0;
   15.10      while(1) {
   15.11          uint32_t entry = *tile_list++;
   15.12          if( entry >> 28 == 0x0F ) {
   15.13              break;
   15.14          } else if( entry >> 28 == 0x0E ) {
   15.15 -            tile_list = (uint32_t *)(video_base+(entry&0x007FFFFF));
   15.16 +            tile_list = (uint32_t *)(pvr2_main_ram+(entry&0x007FFFFF));
   15.17          } else if( entry >> 29 == 0x04 ) { /* Triangle array */
   15.18              count += ((entry >> 25) & 0x0F)+1;
   15.19          } else if( entry >> 29 == 0x05 ) { /* Quad array */
   15.20 @@ -100,7 +100,7 @@
   15.21   */
   15.22  int sort_extract_triangles( pvraddr_t tile_entry, struct sort_triangle *triangles )
   15.23  {
   15.24 -    uint32_t *tile_list = (uint32_t *)(video_base+tile_entry);
   15.25 +    uint32_t *tile_list = (uint32_t *)(pvr2_main_ram+tile_entry);
   15.26      int strip_count;
   15.27      struct polygon_struct *poly;
   15.28      int count = 0, i;
   15.29 @@ -111,7 +111,7 @@
   15.30          case 0x0F:
   15.31              return count; // End-of-list
   15.32          case 0x0E:
   15.33 -            tile_list = (uint32_t *)(video_base + (entry&0x007FFFFF));
   15.34 +            tile_list = (uint32_t *)(pvr2_main_ram + (entry&0x007FFFFF));
   15.35              break;
   15.36          case 0x08: case 0x09: case 0x0A: case 0x0B:
   15.37              strip_count = ((entry >> 25) & 0x0F)+1;

    16.1 --- a/src/pvr2/scene.c	Wed Dec 24 06:06:23 2008 +0000
    16.2 +++ b/src/pvr2/scene.c	Fri Dec 26 14:25:23 2008 +0000
    16.3 @@ -506,13 +506,13 @@
    16.4  
    16.5  static void scene_extract_polygons( pvraddr_t tile_entry )
    16.6  {
    16.7 -    uint32_t *tile_list = (uint32_t *)(video_base+tile_entry);
    16.8 +    uint32_t *tile_list = (uint32_t *)(pvr2_main_ram+tile_entry);
    16.9      do {
   16.10          uint32_t entry = *tile_list++;
   16.11          if( entry >> 28 == 0x0F ) {
   16.12              break;
   16.13          } else if( entry >> 28 == 0x0E ) {
   16.14 -            tile_list = (uint32_t *)(video_base + (entry&0x007FFFFF));
   16.15 +            tile_list = (uint32_t *)(pvr2_main_ram + (entry&0x007FFFFF));
   16.16          } else {
   16.17              pvraddr_t polyaddr = entry&0x000FFFFF;
   16.18              shadow_mode_t is_modified = (entry & 0x01000000) ? pvr2_scene.shadow_mode : SHADOW_NONE;
   16.19 @@ -571,13 +571,13 @@
   16.20  
   16.21  static void scene_extract_vertexes( pvraddr_t tile_entry )
   16.22  {
   16.23 -    uint32_t *tile_list = (uint32_t *)(video_base+tile_entry);
   16.24 +    uint32_t *tile_list = (uint32_t *)(pvr2_main_ram+tile_entry);
   16.25      do {
   16.26          uint32_t entry = *tile_list++;
   16.27          if( entry >> 28 == 0x0F ) {
   16.28              break;
   16.29          } else if( entry >> 28 == 0x0E ) {
   16.30 -            tile_list = (uint32_t *)(video_base + (entry&0x007FFFFF));
   16.31 +            tile_list = (uint32_t *)(pvr2_main_ram + (entry&0x007FFFFF));
   16.32          } else {
   16.33              pvraddr_t polyaddr = entry&0x000FFFFF;
   16.34              shadow_mode_t is_modified = (entry & 0x01000000) ? pvr2_scene.shadow_mode : SHADOW_NONE;
   16.35 @@ -737,11 +737,11 @@
   16.36      fog_col = MMIO_READ( PVR2, RENDER_FOGVRTCOL );
   16.37      unpack_bgra( fog_col, pvr2_scene.fog_vert_colour );
   16.38      
   16.39 -    uint32_t *tilebuffer = (uint32_t *)(video_base + MMIO_READ( PVR2, RENDER_TILEBASE ));
   16.40 +    uint32_t *tilebuffer = (uint32_t *)(pvr2_main_ram + MMIO_READ( PVR2, RENDER_TILEBASE ));
   16.41      uint32_t *segment = tilebuffer;
   16.42      uint32_t shadow = MMIO_READ(PVR2,RENDER_SHADOW);
   16.43      pvr2_scene.segment_list = (struct tile_segment *)tilebuffer;
   16.44 -    pvr2_scene.pvr2_pbuf = (uint32_t *)(video_base + MMIO_READ(PVR2,RENDER_POLYBASE));
   16.45 +    pvr2_scene.pvr2_pbuf = (uint32_t *)(pvr2_main_ram + MMIO_READ(PVR2,RENDER_POLYBASE));
   16.46      pvr2_scene.shadow_mode = shadow & 0x100 ? SHADOW_CHEAP : SHADOW_FULL;
   16.47      scene_shadow_intensity = U8TOFLOAT(shadow&0xFF);
   16.48  
   16.49 @@ -814,7 +814,7 @@
   16.50      fprintf( f, "Polygons: %d\n", pvr2_scene.poly_count );
   16.51      for( i=0; i<pvr2_scene.poly_count; i++ ) {
   16.52          struct polygon_struct *poly = &pvr2_scene.poly_array[i];
   16.53 -        fprintf( f, "  %08X ", ((unsigned char *)poly->context) - video_base );
   16.54 +        fprintf( f, "  %08X ", ((unsigned char *)poly->context) - pvr2_main_ram );
   16.55          switch( poly->vertex_count ) {
   16.56          case 3: fprintf( f, "Tri     " ); break;
   16.57          case 4: fprintf( f, "Quad    " ); break;

    17.1 --- a/src/pvr2/tacore.c	Wed Dec 24 06:06:23 2008 +0000
    17.2 +++ b/src/pvr2/tacore.c	Fri Dec 26 14:25:23 2008 +0000
    17.3 @@ -119,8 +119,7 @@
    17.4  
    17.5  #define TILESLOT( x, y ) (ta_status.current_tile_matrix + (ta_status.current_tile_size * (y * ta_status.width+ x) << 2))
    17.6  
    17.7 -extern char *video_base;
    17.8 -#define PVRRAM(addr) (*(uint32_t *)(video_base + ((addr)&PVR2_RAM_MASK)))
    17.9 +#define PVRRAM(addr) (*(uint32_t *)(pvr2_main_ram + ((addr)&PVR2_RAM_MASK)))
   17.10  
   17.11  struct pvr2_ta_vertex {
   17.12      float x,y,z;
   17.13 @@ -296,7 +295,7 @@
   17.14  
   17.15          /* Initialize each tile to 0xF0000000 */
   17.16          if( ta_status.current_tile_size != 0 ) {
   17.17 -            p = (uint32_t *)(video_base + ta_status.current_tile_matrix);
   17.18 +            p = (uint32_t *)(pvr2_main_ram + ta_status.current_tile_matrix);
   17.19              for( i=0; i< ta_status.width * ta_status.height; i++ ) {
   17.20                  *p = 0xF0000000;
   17.21                  p += ta_status.current_tile_size;
   17.22 @@ -346,7 +345,7 @@
   17.23      int rv;
   17.24      int posn = MMIO_READ( PVR2, TA_POLYPOS );
   17.25      int end = MMIO_READ( PVR2, TA_POLYEND );
   17.26 -    uint32_t *target = (uint32_t *)(video_base + posn);
   17.27 +    uint32_t *target = (uint32_t *)(pvr2_main_ram + posn);
   17.28      for( rv=0; rv < length; rv++ ) {
   17.29          if( posn == end ) {
   17.30              asic_event( EVENT_PVR_PRIM_ALLOC_FAIL );

    18.1 --- a/src/sh4/mmu.c	Wed Dec 24 06:06:23 2008 +0000
    18.2 +++ b/src/sh4/mmu.c	Fri Dec 26 14:25:23 2008 +0000
    18.3 @@ -22,6 +22,7 @@
    18.4  #include "sh4/sh4mmio.h"
    18.5  #include "sh4/sh4core.h"
    18.6  #include "sh4/sh4trans.h"
    18.7 +#include "dreamcast.h"
    18.8  #include "mem.h"
    18.9  #include "mmu.h"
   18.10  
   18.11 @@ -850,13 +851,13 @@
   18.12          sh4_icache.page_vma = addr & 0xFF000000;
   18.13          sh4_icache.page_ppa = 0x0C000000;
   18.14          sh4_icache.mask = 0xFF000000;
   18.15 -        sh4_icache.page = sh4_main_ram;
   18.16 +        sh4_icache.page = dc_main_ram;
   18.17      } else if( (addr & 0x1FE00000) == 0 ) {
   18.18          /* BIOS ROM */
   18.19          sh4_icache.page_vma = addr & 0xFFE00000;
   18.20          sh4_icache.page_ppa = 0;
   18.21          sh4_icache.mask = 0xFFE00000;
   18.22 -        sh4_icache.page = mem_get_region(0);
   18.23 +        sh4_icache.page = dc_boot_rom;
   18.24      } else {
   18.25          /* not supported */
   18.26          sh4_icache.page_vma = -1;

    19.1 --- a/src/sh4/sh4.c	Wed Dec 24 06:06:23 2008 +0000
    19.2 +++ b/src/sh4/sh4.c	Fri Dec 26 14:25:23 2008 +0000
    19.3 @@ -52,10 +52,6 @@
    19.4  struct sh4_registers sh4r __attribute__((aligned(16)));
    19.5  struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    19.6  int sh4_breakpoint_count = 0;
    19.7 -sh4ptr_t sh4_main_ram;
    19.8 -sh4ptr_t dc_boot_rom;
    19.9 -sh4ptr_t dc_flash_ram;
   19.10 -sh4ptr_t dc_audio_ram;
   19.11  
   19.12  gboolean sh4_starting = FALSE;
   19.13  static gboolean sh4_use_translator = FALSE;
   19.14 @@ -83,10 +79,6 @@
   19.15  void sh4_init(void)
   19.16  {
   19.17      register_io_regions( mmio_list_sh4mmio );
   19.18 -    sh4_main_ram = mem_get_region_by_name(MEM_REGION_MAIN);
   19.19 -    dc_boot_rom = mem_get_region_by_name(MEM_REGION_BIOS);
   19.20 -    dc_flash_ram = mem_get_region_by_name(MEM_REGION_FLASH);
   19.21 -    dc_audio_ram = mem_get_region_by_name(MEM_REGION_AUDIO);
   19.22      TMU_init();
   19.23      sh4_mem_init();
   19.24      sh4_reset();

    20.1 --- a/src/sh4/sh4core.h	Wed Dec 24 06:06:23 2008 +0000
    20.2 +++ b/src/sh4/sh4core.h	Fri Dec 26 14:25:23 2008 +0000
    20.3 @@ -33,7 +33,6 @@
    20.4  /* Breakpoint data structure */
    20.5  extern struct breakpoint_struct sh4_breakpoints[MAX_BREAKPOINTS];
    20.6  extern int sh4_breakpoint_count;
    20.7 -extern sh4ptr_t sh4_main_ram;
    20.8  extern gboolean sh4_starting;
    20.9  
   20.10  /**

    21.1 --- a/src/sh4/sh4mem.c	Wed Dec 24 06:06:23 2008 +0000
    21.2 +++ b/src/sh4/sh4mem.c	Fri Dec 26 14:25:23 2008 +0000
    21.3 @@ -51,38 +51,38 @@
    21.4  /********************* The main ram address space **********************/
    21.5  static int32_t FASTCALL ext_sdram_read_long( sh4addr_t addr )
    21.6  {
    21.7 -    return *((int32_t *)(sh4_main_ram + (addr&0x00FFFFFF)));
    21.8 +    return *((int32_t *)(dc_main_ram + (addr&0x00FFFFFF)));
    21.9  }
   21.10  static int32_t FASTCALL ext_sdram_read_word( sh4addr_t addr )
   21.11  {
   21.12 -    return SIGNEXT16(*((int16_t *)(sh4_main_ram + (addr&0x00FFFFFF))));
   21.13 +    return SIGNEXT16(*((int16_t *)(dc_main_ram + (addr&0x00FFFFFF))));
   21.14  }
   21.15  static int32_t FASTCALL ext_sdram_read_byte( sh4addr_t addr )
   21.16  {
   21.17 -    return SIGNEXT8(*((int16_t *)(sh4_main_ram + (addr&0x00FFFFFF))));
   21.18 +    return SIGNEXT8(*((int16_t *)(dc_main_ram + (addr&0x00FFFFFF))));
   21.19  }
   21.20  static void FASTCALL ext_sdram_write_long( sh4addr_t addr, uint32_t val )
   21.21  {
   21.22 -    *(uint32_t *)(sh4_main_ram + (addr&0x00FFFFFF)) = val;
   21.23 +    *(uint32_t *)(dc_main_ram + (addr&0x00FFFFFF)) = val;
   21.24      xlat_invalidate_long(addr);
   21.25  }
   21.26  static void FASTCALL ext_sdram_write_word( sh4addr_t addr, uint32_t val )
   21.27  {
   21.28 -    *(uint16_t *)(sh4_main_ram + (addr&0x00FFFFFF)) = (uint16_t)val;
   21.29 +    *(uint16_t *)(dc_main_ram + (addr&0x00FFFFFF)) = (uint16_t)val;
   21.30      xlat_invalidate_word(addr);
   21.31  }
   21.32  static void FASTCALL ext_sdram_write_byte( sh4addr_t addr, uint32_t val )
   21.33  {
   21.34 -    *(uint8_t *)(sh4_main_ram + (addr&0x00FFFFFF)) = (uint8_t)val;
   21.35 +    *(uint8_t *)(dc_main_ram + (addr&0x00FFFFFF)) = (uint8_t)val;
   21.36      xlat_invalidate_word(addr);
   21.37  }
   21.38  static void FASTCALL ext_sdram_read_burst( unsigned char *dest, sh4addr_t addr )
   21.39  {
   21.40 -    memcpy( dest, sh4_main_ram+(addr&0x00FFFFFF), 32 );
   21.41 +    memcpy( dest, dc_main_ram+(addr&0x00FFFFFF), 32 );
   21.42  }
   21.43  static void FASTCALL ext_sdram_write_burst( sh4addr_t addr, unsigned char *src )
   21.44  {
   21.45 -    memcpy( sh4_main_ram+(addr&0x00FFFFFF), src, 32 );
   21.46 +    memcpy( dc_main_ram+(addr&0x00FFFFFF), src, 32 );
   21.47  }
   21.48  
   21.49  struct mem_region_fn mem_region_sdram = { ext_sdram_read_long, ext_sdram_write_long, 
   21.50 @@ -91,75 +91,6 @@
   21.51          ext_sdram_read_burst, ext_sdram_write_burst }; 
   21.52  
   21.53  
   21.54 -/********************* The Boot ROM address space **********************/
   21.55 -extern sh4ptr_t dc_boot_rom;
   21.56 -extern sh4ptr_t dc_flash_ram;
   21.57 -extern sh4ptr_t dc_audio_ram;
   21.58 -static int32_t FASTCALL ext_bootrom_read_long( sh4addr_t addr )
   21.59 -{
   21.60 -    return *((int32_t *)(dc_boot_rom + (addr&0x001FFFFF)));
   21.61 -}
   21.62 -static int32_t FASTCALL ext_bootrom_read_word( sh4addr_t addr )
   21.63 -{
   21.64 -    return SIGNEXT16(*((int16_t *)(dc_boot_rom + (addr&0x001FFFFF))));
   21.65 -}
   21.66 -static int32_t FASTCALL ext_bootrom_read_byte( sh4addr_t addr )
   21.67 -{
   21.68 -    return SIGNEXT8(*((int16_t *)(dc_boot_rom + (addr&0x001FFFFF))));
   21.69 -}
   21.70 -static void FASTCALL ext_bootrom_read_burst( unsigned char *dest, sh4addr_t addr )
   21.71 -{
   21.72 -    memcpy( dest, sh4_main_ram+(addr&0x001FFFFF), 32 );
   21.73 -}
   21.74 -
   21.75 -struct mem_region_fn mem_region_bootrom = { 
   21.76 -        ext_bootrom_read_long, unmapped_write_long, 
   21.77 -        ext_bootrom_read_word, unmapped_write_long, 
   21.78 -        ext_bootrom_read_byte, unmapped_write_long, 
   21.79 -        ext_bootrom_read_burst, unmapped_write_burst }; 
   21.80 -
   21.81 -/********************* The Flash RAM address space **********************/
   21.82 -static int32_t FASTCALL ext_flashram_read_long( sh4addr_t addr )
   21.83 -{
   21.84 -    return *((int32_t *)(dc_flash_ram + (addr&0x0001FFFF)));
   21.85 -}
   21.86 -static int32_t FASTCALL ext_flashram_read_word( sh4addr_t addr )
   21.87 -{
   21.88 -    return SIGNEXT16(*((int16_t *)(dc_flash_ram + (addr&0x0001FFFF))));
   21.89 -}
   21.90 -static int32_t FASTCALL ext_flashram_read_byte( sh4addr_t addr )
   21.91 -{
   21.92 -    return SIGNEXT8(*((int16_t *)(dc_flash_ram + (addr&0x0001FFFF))));
   21.93 -}
   21.94 -static void FASTCALL ext_flashram_write_long( sh4addr_t addr, uint32_t val )
   21.95 -{
   21.96 -    *(uint32_t *)(dc_flash_ram + (addr&0x0001FFFF)) = val;
   21.97 -    asic_g2_write_word();
   21.98 -}
   21.99 -static void FASTCALL ext_flashram_write_word( sh4addr_t addr, uint32_t val )
  21.100 -{
  21.101 -    *(uint16_t *)(dc_flash_ram + (addr&0x0001FFFF)) = (uint16_t)val;
  21.102 -    asic_g2_write_word();
  21.103 -}
  21.104 -static void FASTCALL ext_flashram_write_byte( sh4addr_t addr, uint32_t val )
  21.105 -{
  21.106 -    *(uint8_t *)(dc_flash_ram + (addr&0x0001FFFF)) = (uint8_t)val;
  21.107 -    asic_g2_write_word();
  21.108 -}
  21.109 -static void FASTCALL ext_flashram_read_burst( unsigned char *dest, sh4addr_t addr )
  21.110 -{
  21.111 -    memcpy( dest, dc_flash_ram+(addr&0x0001FFFF), 32 );
  21.112 -}
  21.113 -static void FASTCALL ext_flashram_write_burst( sh4addr_t addr, unsigned char *src )
  21.114 -{
  21.115 -    memcpy( dc_flash_ram+(addr&0x0001FFFF), src, 32 );
  21.116 -}
  21.117 -
  21.118 -struct mem_region_fn mem_region_flashram = { ext_flashram_read_long, ext_flashram_write_long, 
  21.119 -        ext_flashram_read_word, ext_flashram_write_word, 
  21.120 -        ext_flashram_read_byte, ext_flashram_write_byte, 
  21.121 -        ext_flashram_read_burst, ext_flashram_write_burst }; 
  21.122 -
  21.123  /***************************** P4 Regions ************************************/
  21.124  
  21.125  /* Store-queue (long-write only?) */

    22.1 --- a/src/test/testsh4x86.c	Wed Dec 24 06:06:23 2008 +0000
    22.2 +++ b/src/test/testsh4x86.c	Fri Dec 26 14:25:23 2008 +0000
    22.3 @@ -46,7 +46,8 @@
    22.4  gboolean sh4_starting;
    22.5  uint32_t start_addr = 0x8C010000;
    22.6  uint32_t sh4_cpu_period = 5;
    22.7 -sh4ptr_t sh4_main_ram;
    22.8 +unsigned char dc_main_ram[4096];
    22.9 +unsigned char dc_boot_rom[4096];
   22.10  FILE *in;
   22.11  
   22.12  char *inbuf;
   22.13 @@ -200,7 +201,7 @@
   22.14      uintptr_t pc;
   22.15      uint8_t *buf = sh4_translate_basic_block( start_addr );
   22.16      uint32_t buflen = xlat_get_code_size(buf);
   22.17 -    x86_disasm_init( buf, buf, buflen );
   22.18 +    x86_disasm_init( (uintptr_t)buf, (uintptr_t)buf, buflen );
   22.19      x86_set_symtab( local_symbols, sizeof(local_symbols)/sizeof(struct x86_symbol) );
   22.20      for( pc = buf; pc < buf + buflen;  ) {
   22.21  	char buf[256];