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lxdream.org :: lxdream :: r931:430048ea8b71
lxdream 0.9.1
released Jun 29
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changeset931:430048ea8b71 lxdream-mem
parent930:07e5b11419db
child932:2602c5603ce2
authornkeynes
dateTue Dec 23 05:48:05 2008 +0000 (10 years ago)
branchlxdream-mem
More refactoring and general cleanup. Most things should be working again now.
Split off cache and start real implementation, breaking save states in the process
Makefile.in
src/Makefile.am
src/Makefile.in
src/aica/armmem.c
src/dreamcast.c
src/dreamcast.h
src/mem.c
src/mem.h
src/pvr2/pvr2.c
src/pvr2/pvr2.h
src/pvr2/pvr2mem.c
src/pvr2/pvr2mmio.h
src/pvr2/tacore.c
src/sh4/cache.c
src/sh4/mmu.c
src/sh4/mmu.h
src/sh4/sh4.c
src/sh4/sh4core.h
src/sh4/sh4mem.c
src/test/testsh4x86.c
1.1 --- a/Makefile.in Mon Dec 22 09:51:11 2008 +0000
1.2 +++ b/Makefile.in Tue Dec 23 05:48:05 2008 +0000
1.3 @@ -44,7 +44,8 @@
1.4 config.sub depcomp install-sh missing mkinstalldirs
1.5 subdir = .
1.6 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
1.7 -am__aclocal_m4_deps = $(top_srcdir)/configure.in
1.8 +am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \
1.9 + $(top_srcdir)/configure.in
1.10 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
1.11 $(ACLOCAL_M4)
1.12 am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \
2.1 --- a/src/Makefile.am Mon Dec 22 09:51:11 2008 +0000
2.2 +++ b/src/Makefile.am Tue Dec 23 05:48:05 2008 +0000
2.3 @@ -46,6 +46,7 @@
2.4 sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
2.5 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
2.6 sh4/xltcache.c sh4/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \
2.7 + sh4/cache.c sh4/mmu.h \
2.8 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armdasm.h aica/armmem.c \
2.9 aica/aica.c aica/aica.h aica/audio.c aica/audio.h \
2.10 pvr2/pvr2.c pvr2/pvr2.h pvr2/pvr2mem.c pvr2/pvr2mmio.h \
3.1 --- a/src/Makefile.in Mon Dec 22 09:51:11 2008 +0000
3.2 +++ b/src/Makefile.in Tue Dec 23 05:48:05 2008 +0000
3.3 @@ -73,7 +73,8 @@
3.4 subdir = src
3.5 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in
3.6 ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
3.7 -am__aclocal_m4_deps = $(top_srcdir)/configure.in
3.8 +am__aclocal_m4_deps = $(top_srcdir)/acinclude.m4 \
3.9 + $(top_srcdir)/configure.in
3.10 am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
3.11 $(ACLOCAL_M4)
3.12 mkinstalldirs = $(SHELL) $(top_srcdir)/mkinstalldirs
3.13 @@ -104,38 +105,38 @@
3.14 sh4/dmac.c sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c \
3.15 sh4/sh4dasm.h sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c \
3.16 sh4/sh4stat.c sh4/sh4stat.h sh4/xltcache.c sh4/xltcache.h \
3.17 - sh4/sh4.h sh4/dmac.h sh4/pmm.c aica/armcore.c aica/armcore.h \
3.18 - aica/armdasm.c aica/armdasm.h aica/armmem.c aica/aica.c \
3.19 - aica/aica.h aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \
3.20 - pvr2/pvr2mem.c pvr2/pvr2mmio.h pvr2/tacore.c pvr2/rendsort.c \
3.21 - pvr2/texcache.c pvr2/yuv.c pvr2/rendsave.c pvr2/scene.c \
3.22 - pvr2/scene.h pvr2/gl_sl.c pvr2/gl_slsrc.c pvr2/glutil.c \
3.23 - pvr2/glutil.h pvr2/glrender.c pvr2/vertex.glsl \
3.24 - pvr2/fragment.glsl maple/maple.c maple/maple.h \
3.25 - maple/controller.c maple/kbd.c maple/mouse.c maple/lightgun.c \
3.26 - loader.c loader.h elf.h bootstrap.c bootstrap.h util.c \
3.27 - gdlist.c gdlist.h display.c display.h dckeysyms.h \
3.28 - drivers/audio_null.c drivers/video_null.c drivers/video_gl.c \
3.29 - drivers/video_gl.h drivers/gl_fbo.c sh4/sh4.def sh4/sh4core.in \
3.30 - sh4/sh4x86.in sh4/sh4dasm.in sh4/sh4stat.in sh4/sh4x86.c \
3.31 - sh4/x86op.h sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h \
3.32 - sh4/sh4trans.c sh4/sh4trans.h x86dasm/x86dasm.c \
3.33 - x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
3.34 - x86dasm/dis-buf.c x86dasm/ansidecl.h x86dasm/bfd.h \
3.35 - x86dasm/dis-asm.h x86dasm/symcat.h x86dasm/sysdep.h \
3.36 - gtkui/gtkui.c gtkui/gtkui.h gtkui/gtk_win.c gtkui/gtkcb.c \
3.37 - gtkui/gtk_mmio.c gtkui/gtk_debug.c gtkui/gtk_dump.c \
3.38 - gtkui/gtk_ctrl.c gtkui/gtk_path.c gtkui/gtk_gd.c \
3.39 - drivers/video_gtk.c cocoaui/cocoaui.c cocoaui/cocoaui.h \
3.40 - cocoaui/cocoa_win.c cocoaui/cocoa_gd.c cocoaui/cocoa_prefs.c \
3.41 - cocoaui/cocoa_path.c cocoaui/cocoa_ctrl.c drivers/video_osx.c \
3.42 - drivers/mac_keymap.h drivers/mac_keymap.txt \
3.43 - drivers/video_gdk.c drivers/video_glx.c drivers/video_glx.h \
3.44 - drivers/video_nsgl.c drivers/video_nsgl.h drivers/audio_osx.c \
3.45 - drivers/audio_pulse.c drivers/audio_esd.c drivers/audio_alsa.c \
3.46 - drivers/cd_linux.c drivers/cd_osx.c drivers/osx_iokit.c \
3.47 - drivers/osx_iokit.h drivers/cd_none.c drivers/joy_linux.c \
3.48 - drivers/joy_linux.h
3.49 + sh4/sh4.h sh4/dmac.h sh4/pmm.c sh4/cache.c sh4/mmu.h \
3.50 + aica/armcore.c aica/armcore.h aica/armdasm.c aica/armdasm.h \
3.51 + aica/armmem.c aica/aica.c aica/aica.h aica/audio.c \
3.52 + aica/audio.h pvr2/pvr2.c pvr2/pvr2.h pvr2/pvr2mem.c \
3.53 + pvr2/pvr2mmio.h pvr2/tacore.c pvr2/rendsort.c pvr2/texcache.c \
3.54 + pvr2/yuv.c pvr2/rendsave.c pvr2/scene.c pvr2/scene.h \
3.55 + pvr2/gl_sl.c pvr2/gl_slsrc.c pvr2/glutil.c pvr2/glutil.h \
3.56 + pvr2/glrender.c pvr2/vertex.glsl pvr2/fragment.glsl \
3.57 + maple/maple.c maple/maple.h maple/controller.c maple/kbd.c \
3.58 + maple/mouse.c maple/lightgun.c loader.c loader.h elf.h \
3.59 + bootstrap.c bootstrap.h util.c gdlist.c gdlist.h display.c \
3.60 + display.h dckeysyms.h drivers/audio_null.c \
3.61 + drivers/video_null.c drivers/video_gl.c drivers/video_gl.h \
3.62 + drivers/gl_fbo.c sh4/sh4.def sh4/sh4core.in sh4/sh4x86.in \
3.63 + sh4/sh4dasm.in sh4/sh4stat.in sh4/sh4x86.c sh4/x86op.h \
3.64 + sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h sh4/sh4trans.c \
3.65 + sh4/sh4trans.h x86dasm/x86dasm.c x86dasm/x86dasm.h \
3.66 + x86dasm/i386-dis.c x86dasm/dis-init.c x86dasm/dis-buf.c \
3.67 + x86dasm/ansidecl.h x86dasm/bfd.h x86dasm/dis-asm.h \
3.68 + x86dasm/symcat.h x86dasm/sysdep.h gtkui/gtkui.c gtkui/gtkui.h \
3.69 + gtkui/gtk_win.c gtkui/gtkcb.c gtkui/gtk_mmio.c \
3.70 + gtkui/gtk_debug.c gtkui/gtk_dump.c gtkui/gtk_ctrl.c \
3.71 + gtkui/gtk_path.c gtkui/gtk_gd.c drivers/video_gtk.c \
3.72 + cocoaui/cocoaui.c cocoaui/cocoaui.h cocoaui/cocoa_win.c \
3.73 + cocoaui/cocoa_gd.c cocoaui/cocoa_prefs.c cocoaui/cocoa_path.c \
3.74 + cocoaui/cocoa_ctrl.c drivers/video_osx.c drivers/mac_keymap.h \
3.75 + drivers/mac_keymap.txt drivers/video_gdk.c drivers/video_glx.c \
3.76 + drivers/video_glx.h drivers/video_nsgl.c drivers/video_nsgl.h \
3.77 + drivers/audio_osx.c drivers/audio_pulse.c drivers/audio_esd.c \
3.78 + drivers/audio_alsa.c drivers/cd_linux.c drivers/cd_osx.c \
3.79 + drivers/osx_iokit.c drivers/osx_iokit.h drivers/cd_none.c \
3.80 + drivers/joy_linux.c drivers/joy_linux.h
3.81 @BUILD_SH4X86_TRUE@am__objects_1 = sh4x86.$(OBJEXT) sh4trans.$(OBJEXT) \
3.82 @BUILD_SH4X86_TRUE@ x86dasm.$(OBJEXT) i386-dis.$(OBJEXT) \
3.83 @BUILD_SH4X86_TRUE@ dis-init.$(OBJEXT) dis-buf.$(OBJEXT)
3.84 @@ -168,22 +169,22 @@
3.85 intc.$(OBJEXT) sh4mem.$(OBJEXT) timer.$(OBJEXT) dmac.$(OBJEXT) \
3.86 mmu.$(OBJEXT) sh4core.$(OBJEXT) sh4dasm.$(OBJEXT) \
3.87 sh4mmio.$(OBJEXT) scif.$(OBJEXT) sh4stat.$(OBJEXT) \
3.88 - xltcache.$(OBJEXT) pmm.$(OBJEXT) armcore.$(OBJEXT) \
3.89 - armdasm.$(OBJEXT) armmem.$(OBJEXT) aica.$(OBJEXT) \
3.90 - audio.$(OBJEXT) pvr2.$(OBJEXT) pvr2mem.$(OBJEXT) \
3.91 - tacore.$(OBJEXT) rendsort.$(OBJEXT) texcache.$(OBJEXT) \
3.92 - yuv.$(OBJEXT) rendsave.$(OBJEXT) scene.$(OBJEXT) \
3.93 - gl_sl.$(OBJEXT) gl_slsrc.$(OBJEXT) glutil.$(OBJEXT) \
3.94 - glrender.$(OBJEXT) maple.$(OBJEXT) controller.$(OBJEXT) \
3.95 - kbd.$(OBJEXT) mouse.$(OBJEXT) lightgun.$(OBJEXT) \
3.96 - loader.$(OBJEXT) bootstrap.$(OBJEXT) util.$(OBJEXT) \
3.97 - gdlist.$(OBJEXT) display.$(OBJEXT) audio_null.$(OBJEXT) \
3.98 - video_null.$(OBJEXT) video_gl.$(OBJEXT) gl_fbo.$(OBJEXT) \
3.99 - $(am__objects_1) $(am__objects_2) $(am__objects_3) \
3.100 - $(am__objects_4) $(am__objects_5) $(am__objects_6) \
3.101 - $(am__objects_7) $(am__objects_8) $(am__objects_9) \
3.102 - $(am__objects_10) $(am__objects_11) $(am__objects_12) \
3.103 - $(am__objects_13) $(am__objects_14)
3.104 + xltcache.$(OBJEXT) pmm.$(OBJEXT) cache.$(OBJEXT) \
3.105 + armcore.$(OBJEXT) armdasm.$(OBJEXT) armmem.$(OBJEXT) \
3.106 + aica.$(OBJEXT) audio.$(OBJEXT) pvr2.$(OBJEXT) \
3.107 + pvr2mem.$(OBJEXT) tacore.$(OBJEXT) rendsort.$(OBJEXT) \
3.108 + texcache.$(OBJEXT) yuv.$(OBJEXT) rendsave.$(OBJEXT) \
3.109 + scene.$(OBJEXT) gl_sl.$(OBJEXT) gl_slsrc.$(OBJEXT) \
3.110 + glutil.$(OBJEXT) glrender.$(OBJEXT) maple.$(OBJEXT) \
3.111 + controller.$(OBJEXT) kbd.$(OBJEXT) mouse.$(OBJEXT) \
3.112 + lightgun.$(OBJEXT) loader.$(OBJEXT) bootstrap.$(OBJEXT) \
3.113 + util.$(OBJEXT) gdlist.$(OBJEXT) display.$(OBJEXT) \
3.114 + audio_null.$(OBJEXT) video_null.$(OBJEXT) video_gl.$(OBJEXT) \
3.115 + gl_fbo.$(OBJEXT) $(am__objects_1) $(am__objects_2) \
3.116 + $(am__objects_3) $(am__objects_4) $(am__objects_5) \
3.117 + $(am__objects_6) $(am__objects_7) $(am__objects_8) \
3.118 + $(am__objects_9) $(am__objects_10) $(am__objects_11) \
3.119 + $(am__objects_12) $(am__objects_13) $(am__objects_14)
3.120 lxdream_OBJECTS = $(am_lxdream_OBJECTS)
3.121 lxdream_DEPENDENCIES = $(am__DEPENDENCIES_1)
3.122 am__test_testsh4x86_SOURCES_DIST = test/testsh4x86.c x86dasm/x86dasm.c \
3.123 @@ -412,24 +413,25 @@
3.124 sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h sh4/sh4mmio.c \
3.125 sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
3.126 sh4/xltcache.c sh4/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \
3.127 - aica/armcore.c aica/armcore.h aica/armdasm.c aica/armdasm.h \
3.128 - aica/armmem.c aica/aica.c aica/aica.h aica/audio.c \
3.129 - aica/audio.h pvr2/pvr2.c pvr2/pvr2.h pvr2/pvr2mem.c \
3.130 - pvr2/pvr2mmio.h pvr2/tacore.c pvr2/rendsort.c pvr2/texcache.c \
3.131 - pvr2/yuv.c pvr2/rendsave.c pvr2/scene.c pvr2/scene.h \
3.132 - pvr2/gl_sl.c pvr2/gl_slsrc.c pvr2/glutil.c pvr2/glutil.h \
3.133 - pvr2/glrender.c pvr2/vertex.glsl pvr2/fragment.glsl \
3.134 - maple/maple.c maple/maple.h maple/controller.c maple/kbd.c \
3.135 - maple/mouse.c maple/lightgun.c loader.c loader.h elf.h \
3.136 - bootstrap.c bootstrap.h util.c gdlist.c gdlist.h display.c \
3.137 - display.h dckeysyms.h drivers/audio_null.c \
3.138 - drivers/video_null.c drivers/video_gl.c drivers/video_gl.h \
3.139 - drivers/gl_fbo.c sh4/sh4.def sh4/sh4core.in sh4/sh4x86.in \
3.140 - sh4/sh4dasm.in sh4/sh4stat.in $(am__append_1) $(am__append_3) \
3.141 - $(am__append_4) $(am__append_5) $(am__append_6) \
3.142 - $(am__append_7) $(am__append_8) $(am__append_9) \
3.143 - $(am__append_10) $(am__append_11) $(am__append_12) \
3.144 - $(am__append_13) $(am__append_14) $(am__append_15)
3.145 + sh4/cache.c sh4/mmu.h aica/armcore.c aica/armcore.h \
3.146 + aica/armdasm.c aica/armdasm.h aica/armmem.c aica/aica.c \
3.147 + aica/aica.h aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \
3.148 + pvr2/pvr2mem.c pvr2/pvr2mmio.h pvr2/tacore.c pvr2/rendsort.c \
3.149 + pvr2/texcache.c pvr2/yuv.c pvr2/rendsave.c pvr2/scene.c \
3.150 + pvr2/scene.h pvr2/gl_sl.c pvr2/gl_slsrc.c pvr2/glutil.c \
3.151 + pvr2/glutil.h pvr2/glrender.c pvr2/vertex.glsl \
3.152 + pvr2/fragment.glsl maple/maple.c maple/maple.h \
3.153 + maple/controller.c maple/kbd.c maple/mouse.c maple/lightgun.c \
3.154 + loader.c loader.h elf.h bootstrap.c bootstrap.h util.c \
3.155 + gdlist.c gdlist.h display.c display.h dckeysyms.h \
3.156 + drivers/audio_null.c drivers/video_null.c drivers/video_gl.c \
3.157 + drivers/video_gl.h drivers/gl_fbo.c sh4/sh4.def sh4/sh4core.in \
3.158 + sh4/sh4x86.in sh4/sh4dasm.in sh4/sh4stat.in $(am__append_1) \
3.159 + $(am__append_3) $(am__append_4) $(am__append_5) \
3.160 + $(am__append_6) $(am__append_7) $(am__append_8) \
3.161 + $(am__append_9) $(am__append_10) $(am__append_11) \
3.162 + $(am__append_12) $(am__append_13) $(am__append_14) \
3.163 + $(am__append_15)
3.164 @BUILD_SH4X86_TRUE@test_testsh4x86_LDADD = @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@
3.165 @BUILD_SH4X86_TRUE@test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \
3.166 @BUILD_SH4X86_TRUE@ x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
3.167 @@ -543,6 +545,7 @@
3.168 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/audio_pulse.Po@am__quote@
3.169 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bios.Po@am__quote@
3.170 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/bootstrap.Po@am__quote@
3.171 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cache.Po@am__quote@
3.172 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cd_linux.Po@am__quote@
3.173 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cd_none.Po@am__quote@
3.174 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cd_osx.Po@am__quote@
3.175 @@ -999,6 +1002,20 @@
3.176 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
3.177 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o pmm.obj `if test -f 'sh4/pmm.c'; then $(CYGPATH_W) 'sh4/pmm.c'; else $(CYGPATH_W) '$(srcdir)/sh4/pmm.c'; fi`
3.178
3.179 +cache.o: sh4/cache.c
3.180 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT cache.o -MD -MP -MF "$(DEPDIR)/cache.Tpo" -c -o cache.o `test -f 'sh4/cache.c' || echo '$(srcdir)/'`sh4/cache.c; \
3.181 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/cache.Tpo" "$(DEPDIR)/cache.Po"; else rm -f "$(DEPDIR)/cache.Tpo"; exit 1; fi
3.182 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/cache.c' object='cache.o' libtool=no @AMDEPBACKSLASH@
3.183 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
3.184 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o cache.o `test -f 'sh4/cache.c' || echo '$(srcdir)/'`sh4/cache.c
3.185 +
3.186 +cache.obj: sh4/cache.c
3.187 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT cache.obj -MD -MP -MF "$(DEPDIR)/cache.Tpo" -c -o cache.obj `if test -f 'sh4/cache.c'; then $(CYGPATH_W) 'sh4/cache.c'; else $(CYGPATH_W) '$(srcdir)/sh4/cache.c'; fi`; \
3.188 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/cache.Tpo" "$(DEPDIR)/cache.Po"; else rm -f "$(DEPDIR)/cache.Tpo"; exit 1; fi
3.189 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/cache.c' object='cache.obj' libtool=no @AMDEPBACKSLASH@
3.190 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
3.191 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o cache.obj `if test -f 'sh4/cache.c'; then $(CYGPATH_W) 'sh4/cache.c'; else $(CYGPATH_W) '$(srcdir)/sh4/cache.c'; fi`
3.192 +
3.193 armcore.o: aica/armcore.c
3.194 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT armcore.o -MD -MP -MF "$(DEPDIR)/armcore.Tpo" -c -o armcore.o `test -f 'aica/armcore.c' || echo '$(srcdir)/'`aica/armcore.c; \
3.195 @am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/armcore.Tpo" "$(DEPDIR)/armcore.Po"; else rm -f "$(DEPDIR)/armcore.Tpo"; exit 1; fi
4.1 --- a/src/aica/armmem.c Mon Dec 22 09:51:11 2008 +0000
4.2 +++ b/src/aica/armmem.c Tue Dec 23 05:48:05 2008 +0000
4.3 @@ -30,6 +30,92 @@
4.4 arm_mem_scratch = mem_get_region_by_name( MEM_REGION_AUDIO_SCRATCH );
4.5 }
4.6
4.7 +/*************** ARM memory access function blocks **************/
4.8 +
4.9 +static int32_t FASTCALL ext_audioram_read_long( sh4addr_t addr )
4.10 +{
4.11 + return *((int32_t *)(arm_mem + (addr&0x001FFFFF)));
4.12 +}
4.13 +static int32_t FASTCALL ext_audioram_read_word( sh4addr_t addr )
4.14 +{
4.15 + return SIGNEXT16(*((int16_t *)(arm_mem + (addr&0x001FFFFF))));
4.16 +}
4.17 +static int32_t FASTCALL ext_audioram_read_byte( sh4addr_t addr )
4.18 +{
4.19 + return SIGNEXT8(*((int16_t *)(arm_mem + (addr&0x001FFFFF))));
4.20 +}
4.21 +static void FASTCALL ext_audioram_write_long( sh4addr_t addr, uint32_t val )
4.22 +{
4.23 + *(uint32_t *)(arm_mem + (addr&0x001FFFFF)) = val;
4.24 + asic_g2_write_word();
4.25 +}
4.26 +static void FASTCALL ext_audioram_write_word( sh4addr_t addr, uint32_t val )
4.27 +{
4.28 + *(uint16_t *)(arm_mem + (addr&0x001FFFFF)) = (uint16_t)val;
4.29 + asic_g2_write_word();
4.30 +}
4.31 +static void FASTCALL ext_audioram_write_byte( sh4addr_t addr, uint32_t val )
4.32 +{
4.33 + *(uint8_t *)(arm_mem + (addr&0x001FFFFF)) = (uint8_t)val;
4.34 + asic_g2_write_word();
4.35 +}
4.36 +static void FASTCALL ext_audioram_read_burst( unsigned char *dest, sh4addr_t addr )
4.37 +{
4.38 + memcpy( dest, arm_mem+(addr&0x001FFFFF), 32 );
4.39 +}
4.40 +static void FASTCALL ext_audioram_write_burst( sh4addr_t addr, unsigned char *src )
4.41 +{
4.42 + memcpy( arm_mem+(addr&0x001FFFFF), src, 32 );
4.43 +}
4.44 +
4.45 +struct mem_region_fn mem_region_audioram = { ext_audioram_read_long, ext_audioram_write_long,
4.46 + ext_audioram_read_word, ext_audioram_write_word,
4.47 + ext_audioram_read_byte, ext_audioram_write_byte,
4.48 + ext_audioram_read_burst, ext_audioram_write_burst };
4.49 +
4.50 +
4.51 +static int32_t FASTCALL ext_audioscratch_read_long( sh4addr_t addr )
4.52 +{
4.53 + return *((int32_t *)(arm_mem_scratch + (addr&0x00001FFF)));
4.54 +}
4.55 +static int32_t FASTCALL ext_audioscratch_read_word( sh4addr_t addr )
4.56 +{
4.57 + return SIGNEXT16(*((int16_t *)(arm_mem_scratch + (addr&0x00001FFF))));
4.58 +}
4.59 +static int32_t FASTCALL ext_audioscratch_read_byte( sh4addr_t addr )
4.60 +{
4.61 + return SIGNEXT8(*((int16_t *)(arm_mem_scratch + (addr&0x00001FFF))));
4.62 +}
4.63 +static void FASTCALL ext_audioscratch_write_long( sh4addr_t addr, uint32_t val )
4.64 +{
4.65 + *(uint32_t *)(arm_mem_scratch + (addr&0x00001FFF)) = val;
4.66 + asic_g2_write_word();
4.67 +}
4.68 +static void FASTCALL ext_audioscratch_write_word( sh4addr_t addr, uint32_t val )
4.69 +{
4.70 + *(uint16_t *)(arm_mem_scratch + (addr&0x00001FFF)) = (uint16_t)val;
4.71 + asic_g2_write_word();
4.72 +}
4.73 +static void FASTCALL ext_audioscratch_write_byte( sh4addr_t addr, uint32_t val )
4.74 +{
4.75 + *(uint8_t *)(arm_mem_scratch + (addr&0x00001FFF)) = (uint8_t)val;
4.76 + asic_g2_write_word();
4.77 +}
4.78 +static void FASTCALL ext_audioscratch_read_burst( unsigned char *dest, sh4addr_t addr )
4.79 +{
4.80 + memcpy( dest, arm_mem_scratch+(addr&0x00001FFF), 32 );
4.81 +}
4.82 +static void FASTCALL ext_audioscratch_write_burst( sh4addr_t addr, unsigned char *src )
4.83 +{
4.84 + memcpy( arm_mem_scratch+(addr&0x00001FFF), src, 32 );
4.85 +}
4.86 +
4.87 +struct mem_region_fn mem_region_audioscratch = { ext_audioscratch_read_long, ext_audioscratch_write_long,
4.88 + ext_audioscratch_read_word, ext_audioscratch_write_word,
4.89 + ext_audioscratch_read_byte, ext_audioscratch_write_byte,
4.90 + ext_audioscratch_read_burst, ext_audioscratch_write_burst };
4.91 +
4.92 +/************************** Local ARM support **************************/
4.93 int arm_has_page( uint32_t addr ) {
4.94 return ( addr < 0x00200000 ||
4.95 (addr >= 0x00800000 && addr <= 0x00805000 ) );
5.1 --- a/src/dreamcast.c Mon Dec 22 09:51:11 2008 +0000
5.2 +++ b/src/dreamcast.c Tue Dec 23 05:48:05 2008 +0000
5.3 @@ -62,8 +62,13 @@
5.4 extern struct mem_region_fn mem_region_vram32;
5.5 extern struct mem_region_fn mem_region_vram64;
5.6 extern struct mem_region_fn mem_region_audioram;
5.7 +extern struct mem_region_fn mem_region_audioscratch;
5.8 extern struct mem_region_fn mem_region_flashram;
5.9 extern struct mem_region_fn mem_region_bootrom;
5.10 +extern struct mem_region_fn mem_region_pvr2ta;
5.11 +extern struct mem_region_fn mem_region_pvr2yuv;
5.12 +extern struct mem_region_fn mem_region_pvr2vdma1;
5.13 +extern struct mem_region_fn mem_region_pvr2vdma2;
5.14
5.15 /**
5.16 * This function is responsible for defining how all the pieces of the
5.17 @@ -82,12 +87,20 @@
5.18 dreamcast_register_module( &mem_module );
5.19
5.20 /* Setup standard memory map */
5.21 + dreamcast_has_bios =
5.22 + mem_load_rom( bios_path, 0x00000000, 2 MB, 0x89f2b1a1, MEM_REGION_BIOS, &mem_region_bootrom );
5.23 + mem_create_ram_region( 0x00200000, 0x00020000, MEM_REGION_FLASH, &mem_region_flashram );
5.24 + mem_create_ram_region( 0x00800000, 2 MB, MEM_REGION_AUDIO, &mem_region_audioram );
5.25 + mem_create_ram_region( 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH, &mem_region_audioscratch );
5.26 + register_misc_region( 0x04000000, 8 MB, MEM_REGION_VIDEO64, &mem_region_vram64 );
5.27 + mem_create_ram_region( 0x05000000, 8 MB, MEM_REGION_VIDEO, &mem_region_vram32 );
5.28 mem_create_repeating_ram_region( 0x0C000000, 16 MB, MEM_REGION_MAIN, &mem_region_sdram, 0x01000000, 0x0F000000 );
5.29 - mem_create_ram_region( 0x00800000, 2 MB, MEM_REGION_AUDIO, &mem_region_audioram );
5.30 - mem_create_ram_region( 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH, NULL );
5.31 - mem_create_ram_region( 0x05000000, 8 MB, MEM_REGION_VIDEO, &mem_region_vram32 );
5.32 - dreamcast_has_bios = mem_load_rom( bios_path, 0x00000000, 0x00200000, 0x89f2b1a1, MEM_REGION_BIOS, &mem_region_bootrom );
5.33 - mem_create_ram_region( 0x00200000, 0x00020000, MEM_REGION_FLASH, &mem_region_flashram );
5.34 + register_misc_region( 0x10000000, 8 MB, "PVR2 TA Command 1", &mem_region_pvr2ta );
5.35 + register_misc_region( 0x10800000, 8 MB, "PVR2 YUV Decode 1", &mem_region_pvr2yuv );
5.36 + register_misc_region( 0x11000000, 16 MB,"PVR2 VRAM DMA 1", &mem_region_pvr2vdma1 );
5.37 + register_misc_region( 0x12000000, 8 MB, "PVR2 TA Command 2", &mem_region_pvr2ta );
5.38 + register_misc_region( 0x12800000, 8 MB, "PVR2 YUV Decode 2", &mem_region_pvr2yuv );
5.39 + register_misc_region( 0x13000000, 16 MB,"PVR2 VRAM DMA 2", &mem_region_pvr2vdma2 );
5.40 if( flash_path != NULL && flash_path[0] != '\0' ) {
5.41 mem_load_block( flash_path, 0x00200000, 0x00020000 );
5.42 }
5.43 @@ -100,7 +113,6 @@
5.44 dreamcast_register_module( &aica_module );
5.45 dreamcast_register_module( &maple_module );
5.46 dreamcast_register_module( &ide_module );
5.47 - sh4_mem_init();
5.48 }
5.49
5.50 void dreamcast_config_changed(void)
5.51 @@ -129,7 +141,7 @@
5.52 {
5.53 dreamcast_register_module( &mem_module );
5.54 mem_create_ram_region( 0x00800000, 2 MB, MEM_REGION_AUDIO, &mem_region_audioram );
5.55 - mem_create_ram_region( 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH, NULL );
5.56 + mem_create_ram_region( 0x00703000, 8 KB, MEM_REGION_AUDIO_SCRATCH, &mem_region_audioscratch );
5.57 dreamcast_register_module( &aica_module );
5.58 aica_enable();
5.59 dreamcast_state = STATE_STOPPED;
5.60 @@ -251,7 +263,6 @@
5.61 #ifdef ENABLE_SH4STATS
5.62 sh4_stats_print(stdout);
5.63 #endif
5.64 - print_sh4mem_stats();
5.65 }
5.66
5.67 void dreamcast_program_loaded( const gchar *name, sh4addr_t entry_point )
6.1 --- a/src/dreamcast.h Mon Dec 22 09:51:11 2008 +0000
6.2 +++ b/src/dreamcast.h Tue Dec 23 05:48:05 2008 +0000
6.3 @@ -61,7 +61,7 @@
6.4 void dreamcast_program_loaded( const gchar *name, sh4addr_t entry_point );
6.5
6.6 #define DREAMCAST_SAVE_MAGIC "%!-lxDream!Save\0"
6.7 -#define DREAMCAST_SAVE_VERSION 0x00010005
6.8 +#define DREAMCAST_SAVE_VERSION 0x00010006
6.9
6.10 int dreamcast_save_state( const gchar *filename );
6.11 int dreamcast_load_state( const gchar *filename );
7.1 --- a/src/mem.c Mon Dec 22 09:51:11 2008 +0000
7.2 +++ b/src/mem.c Tue Dec 23 05:48:05 2008 +0000
7.3 @@ -51,6 +51,35 @@
7.4
7.5 uint32_t num_io_rgns = 0, num_mem_rgns = 0;
7.6
7.7 +DEFINE_HOOK( mem_page_remapped_hook, mem_page_remapped_hook_t );
7.8 +static void mem_page_remapped( sh4addr_t addr, mem_region_fn_t fn )
7.9 +{
7.10 + CALL_HOOKS( mem_page_remapped_hook, addr, fn );
7.11 +}
7.12 +
7.13 +/********************* The "unmapped" address space ********************/
7.14 +/* Always reads as 0, writes have no effect */
7.15 +int32_t FASTCALL unmapped_read_long( sh4addr_t addr )
7.16 +{
7.17 + return 0;
7.18 +}
7.19 +void FASTCALL unmapped_write_long( sh4addr_t addr, uint32_t val )
7.20 +{
7.21 +}
7.22 +void FASTCALL unmapped_read_burst( unsigned char *dest, sh4addr_t addr )
7.23 +{
7.24 + memset( dest, 0, 32 );
7.25 +}
7.26 +void FASTCALL unmapped_write_burst( sh4addr_t addr, unsigned char *src )
7.27 +{
7.28 +}
7.29 +
7.30 +struct mem_region_fn mem_region_unmapped = {
7.31 + unmapped_read_long, unmapped_write_long,
7.32 + unmapped_read_long, unmapped_write_long,
7.33 + unmapped_read_long, unmapped_write_long,
7.34 + unmapped_read_burst, unmapped_write_burst };
7.35 +
7.36 void *mem_alloc_pages( int n )
7.37 {
7.38 void *mem = mmap( NULL, n * 4096,
7.39 @@ -253,6 +282,7 @@
7.40 for( i=0; i<size>>LXDREAM_PAGE_BITS; i++ ) {
7.41 page_map[(base>>LXDREAM_PAGE_BITS)+i] = mem + (i<<LXDREAM_PAGE_BITS);
7.42 ext_address_space[(base>>LXDREAM_PAGE_BITS)+i] = fn;
7.43 + mem_page_remapped( base + (i<<LXDREAM_PAGE_BITS), fn );
7.44 }
7.45 base += repeat_offset;
7.46 } while( base <= repeat_until );
7.47 @@ -260,6 +290,23 @@
7.48 return &mem_rgn[num_mem_rgns-1];
7.49 }
7.50
7.51 +void register_misc_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn )
7.52 +{
7.53 + mem_rgn[num_mem_rgns].base = base;
7.54 + mem_rgn[num_mem_rgns].size = size;
7.55 + mem_rgn[num_mem_rgns].flags = 0;
7.56 + mem_rgn[num_mem_rgns].name = name;
7.57 + mem_rgn[num_mem_rgns].mem = NULL;
7.58 + mem_rgn[num_mem_rgns].fn = fn;
7.59 + num_mem_rgns++;
7.60 +
7.61 + int count = size >> 12;
7.62 + mem_region_fn_t *ptr = &ext_address_space[base>>12];
7.63 + while( count-- > 0 ) {
7.64 + *ptr++ = fn;
7.65 + }
7.66 +}
7.67 +
7.68 void *mem_create_ram_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn )
7.69 {
7.70 return mem_create_repeating_ram_region( base, size, name, fn, size, base );
7.71 @@ -351,6 +398,7 @@
7.72 } else {
7.73 page_map[io->base>>12] = (sh4ptr_t)(uintptr_t)num_io_rgns;
7.74 ext_address_space[io->base>>12] = &io->fn;
7.75 + mem_page_remapped( io->base, &io->fn );
7.76 }
7.77 io_rgn[num_io_rgns] = io;
7.78 num_io_rgns++;
8.1 --- a/src/mem.h Mon Dec 22 09:51:11 2008 +0000
8.2 +++ b/src/mem.h Tue Dec 23 05:48:05 2008 +0000
8.3 @@ -22,11 +22,16 @@
8.4
8.5 #include <stdint.h>
8.6 #include "lxdream.h"
8.7 +#include "hook.h"
8.8
8.9 #ifdef __cplusplus
8.10 extern "C" {
8.11 #endif
8.12
8.13 +/**
8.14 + * Basic memory region vtable - read/write at byte, word, long, and burst
8.15 + * (32-byte) sizes.
8.16 + */
8.17 typedef struct mem_region_fn {
8.18 FASTCALL int32_t (*read_long)(sh4addr_t addr);
8.19 FASTCALL void (*write_long)(sh4addr_t addr, uint32_t val);
8.20 @@ -37,7 +42,13 @@
8.21 FASTCALL void (*read_burst)(unsigned char *dest, sh4addr_t addr);
8.22 FASTCALL void (*write_burst)(sh4addr_t addr, unsigned char *src);
8.23 } *mem_region_fn_t;
8.24 -
8.25 +
8.26 +int32_t FASTCALL unmapped_read_long( sh4addr_t addr );
8.27 +void FASTCALL unmapped_write_long( sh4addr_t addr, uint32_t val );
8.28 +void FASTCALL unmapped_read_burst( unsigned char *dest, sh4addr_t addr );
8.29 +void FASTCALL unmapped_write_burst( sh4addr_t addr, unsigned char *src );
8.30 +extern struct mem_region_fn mem_region_unmapped;
8.31 +
8.32 typedef struct mem_region {
8.33 uint32_t base;
8.34 uint32_t size;
8.35 @@ -48,18 +59,24 @@
8.36 } *mem_region_t;
8.37
8.38 #define MAX_IO_REGIONS 24
8.39 -#define MAX_MEM_REGIONS 8
8.40 +#define MAX_MEM_REGIONS 16
8.41
8.42 #define MEM_REGION_BIOS "Bios ROM"
8.43 #define MEM_REGION_MAIN "System RAM"
8.44 #define MEM_REGION_VIDEO "Video RAM"
8.45 +#define MEM_REGION_VIDEO64 "Video RAM 64-bit"
8.46 #define MEM_REGION_AUDIO "Audio RAM"
8.47 #define MEM_REGION_AUDIO_SCRATCH "Audio Scratch RAM"
8.48 #define MEM_REGION_FLASH "System Flash"
8.49
8.50 +typedef gboolean (*mem_page_remapped_hook_t)(sh4addr_t page, mem_region_fn_t newfn, void *user_data);
8.51 +DECLARE_HOOK( mem_page_remapped_hook, mem_page_remapped_hook_t );
8.52 +
8.53 void *mem_create_ram_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn );
8.54 void *mem_create_repeating_ram_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn,
8.55 uint32_t repeat_offset, uint32_t last_repeat );
8.56 +void register_misc_region( uint32_t base, uint32_t size, const char *name, mem_region_fn_t fn );
8.57 +
8.58 /**
8.59 * Load a ROM image from the specified filename. If the memory region has not
8.60 * been allocated, it is created now, otherwise the existing region is reused.
8.61 @@ -114,6 +131,15 @@
8.62 watch_point_t mem_is_watched( uint32_t addr, int size, int op );
8.63
8.64 extern sh4ptr_t *page_map;
8.65 +extern mem_region_fn_t *ext_address_space;
8.66 +
8.67 +#define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
8.68 +#define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
8.69 +#define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
8.70 +#define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
8.71 +#define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
8.72 +#define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
8.73 +#define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n))))
8.74
8.75 #ifdef __cplusplus
8.76 }
9.1 --- a/src/pvr2/pvr2.c Mon Dec 22 09:51:11 2008 +0000
9.2 +++ b/src/pvr2/pvr2.c Tue Dec 23 05:48:05 2008 +0000
9.3 @@ -142,7 +142,6 @@
9.4 int i;
9.5 register_io_region( &mmio_region_PVR2 );
9.6 register_io_region( &mmio_region_PVR2PAL );
9.7 - register_io_region( &mmio_region_PVR2TA );
9.8 register_event_callback( EVENT_HPOS, pvr2_hpos_callback );
9.9 register_event_callback( EVENT_SCANLINE1, pvr2_scanline_callback );
9.10 register_event_callback( EVENT_SCANLINE2, pvr2_scanline_callback );
9.11 @@ -858,19 +857,6 @@
9.12 mmio_region_PVR2_write( DISP_ADDR1, base );
9.13 }
9.14
9.15 -
9.16 -
9.17 -
9.18 -MMIO_REGION_READ_FN( PVR2TA, reg )
9.19 -{
9.20 - return 0xFFFFFFFF;
9.21 -}
9.22 -
9.23 -MMIO_REGION_WRITE_FN( PVR2TA, reg, val )
9.24 -{
9.25 - pvr2_ta_write( (unsigned char *)&val, sizeof(uint32_t) );
9.26 -}
9.27 -
9.28 render_buffer_t pvr2_create_render_buffer( sh4addr_t addr, int width, int height, GLuint tex_id )
9.29 {
9.30 if( display_driver != NULL && display_driver->create_render_buffer != NULL ) {
10.1 --- a/src/pvr2/pvr2.h Mon Dec 22 09:51:11 2008 +0000
10.2 +++ b/src/pvr2/pvr2.h Tue Dec 23 05:48:05 2008 +0000
10.3 @@ -219,6 +219,8 @@
10.4 */
10.5 void pvr2_ta_write( unsigned char *buf, uint32_t length );
10.6
10.7 +void FASTCALL pvr2_ta_write_burst( sh4addr_t addr, unsigned char *buf );
10.8 +
10.9 /**
10.10 * Find the first polygon or sprite context in the supplied buffer of TA
10.11 * data.
11.1 --- a/src/pvr2/pvr2mem.c Mon Dec 22 09:51:11 2008 +0000
11.2 +++ b/src/pvr2/pvr2mem.c Tue Dec 23 05:48:05 2008 +0000
11.3 @@ -132,6 +132,60 @@
11.4 pvr2_vram64_read_byte, pvr2_vram64_write_byte,
11.5 pvr2_vram64_read_burst, pvr2_vram64_write_burst };
11.6
11.7 +/******************************* Burst areas ******************************/
11.8 +
11.9 +static void FASTCALL pvr2_vramdma1_write_burst( sh4addr_t destaddr, unsigned char *src )
11.10 +{
11.11 + int region = MMIO_READ( ASIC, PVRDMARGN1 );
11.12 + if( region == 0 ) {
11.13 + pvr2_vram64_write( destaddr, src, 32 );
11.14 + } else {
11.15 + destaddr &= PVR2_RAM_MASK;
11.16 + unsigned char *dest = video_base + destaddr;
11.17 + memcpy( dest, src, 32 );
11.18 + }
11.19 +}
11.20 +
11.21 +static void FASTCALL pvr2_vramdma2_write_burst( sh4addr_t destaddr, unsigned char *src )
11.22 +{
11.23 + int region = MMIO_READ( ASIC, PVRDMARGN2 );
11.24 + if( region == 0 ) {
11.25 + pvr2_vram64_write( destaddr, src, 32 );
11.26 + } else {
11.27 + destaddr &= PVR2_RAM_MASK;
11.28 + unsigned char *dest = video_base + destaddr;
11.29 + memcpy( dest, src, 32 );
11.30 + }
11.31 +}
11.32 +
11.33 +static void FASTCALL pvr2_yuv_write_burst( sh4addr_t destaddr, unsigned char *src )
11.34 +{
11.35 + pvr2_yuv_write( src, 32 );
11.36 +}
11.37 +
11.38 +struct mem_region_fn mem_region_pvr2ta = {
11.39 + unmapped_read_long, unmapped_write_long,
11.40 + unmapped_read_long, unmapped_write_long,
11.41 + unmapped_read_long, unmapped_write_long,
11.42 + unmapped_read_burst, pvr2_ta_write_burst };
11.43 +
11.44 +struct mem_region_fn mem_region_pvr2yuv = {
11.45 + unmapped_read_long, unmapped_write_long,
11.46 + unmapped_read_long, unmapped_write_long,
11.47 + unmapped_read_long, unmapped_write_long,
11.48 + unmapped_read_burst, pvr2_yuv_write_burst };
11.49 +
11.50 +struct mem_region_fn mem_region_pvr2vdma1 = {
11.51 + unmapped_read_long, unmapped_write_long,
11.52 + unmapped_read_long, unmapped_write_long,
11.53 + unmapped_read_long, unmapped_write_long,
11.54 + unmapped_read_burst, pvr2_vramdma1_write_burst };
11.55 +
11.56 +struct mem_region_fn mem_region_pvr2vdma2 = {
11.57 + unmapped_read_long, unmapped_write_long,
11.58 + unmapped_read_long, unmapped_write_long,
11.59 + unmapped_read_long, unmapped_write_long,
11.60 + unmapped_read_burst, pvr2_vramdma2_write_burst };
11.61
11.62
11.63 void pvr2_dma_write( sh4addr_t destaddr, unsigned char *src, uint32_t count )
12.1 --- a/src/pvr2/pvr2mmio.h Mon Dec 22 09:51:11 2008 +0000
12.2 +++ b/src/pvr2/pvr2mmio.h Tue Dec 23 05:48:05 2008 +0000
12.3 @@ -95,7 +95,3 @@
12.4 MMIO_REGION_BEGIN( 0x005F9000, PVR2PAL, "Power VR/2 CLUT Palettes" )
12.5 LONG_PORT( 0x000, PAL0_0, PORT_MRW, 0, "Pal0 colour 0" )
12.6 MMIO_REGION_END
12.7 -
12.8 -MMIO_REGION_BEGIN( 0x10000000, PVR2TA, "Power VR/2 TA Command port" )
12.9 - LONG_PORT( 0x000, TACMD, PORT_MRW, 0, "TA Command port" )
12.10 -MMIO_REGION_END
13.1 --- a/src/pvr2/tacore.c Mon Dec 22 09:51:11 2008 +0000
13.2 +++ b/src/pvr2/tacore.c Tue Dec 23 05:48:05 2008 +0000
13.3 @@ -1200,3 +1200,11 @@
13.4 buf += 32;
13.5 }
13.6 }
13.7 +
13.8 +void FASTCALL pvr2_ta_write_burst( sh4addr_t addr, unsigned char *data )
13.9 +{
13.10 + if( ta_status.debug_output ) {
13.11 + fwrite_dump32( (uint32_t *)data, 32, stderr );
13.12 + }
13.13 + pvr2_ta_process_block( data );
13.14 +}
14.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
14.2 +++ b/src/sh4/cache.c Tue Dec 23 05:48:05 2008 +0000
14.3 @@ -0,0 +1,191 @@
14.4 +/**
14.5 + * $Id$
14.6 + * Implements the on-chip operand cache and instruction caches
14.7 + *
14.8 + * Copyright (c) 2008 Nathan Keynes.
14.9 + *
14.10 + * This program is free software; you can redistribute it and/or modify
14.11 + * it under the terms of the GNU General Public License as published by
14.12 + * the Free Software Foundation; either version 2 of the License, or
14.13 + * (at your option) any later version.
14.14 + *
14.15 + * This program is distributed in the hope that it will be useful,
14.16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
14.17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14.18 + * GNU General Public License for more details.
14.19 + */
14.20 +
14.21 +#define MODULE sh4_module
14.22 +
14.23 +#include <string.h>
14.24 +#include "dream.h"
14.25 +#include "mem.h"
14.26 +#include "mmio.h"
14.27 +#include "sh4/sh4core.h"
14.28 +#include "sh4/sh4mmio.h"
14.29 +#include "sh4/xltcache.h"
14.30 +
14.31 +#define OCRAM_START (0x7C000000>>LXDREAM_PAGE_BITS)
14.32 +#define OCRAM_MID (0x7E000000>>LXDREAM_PAGE_BITS)
14.33 +#define OCRAM_END (0x80000000>>LXDREAM_PAGE_BITS)
14.34 +
14.35 +#define CACHE_VALID 1
14.36 +#define CACHE_DIRTY 2
14.37 +
14.38 +#define ICACHE_ENTRY_COUNT 256
14.39 +#define OCACHE_ENTRY_COUNT 512
14.40 +
14.41 +struct cache_line {
14.42 + uint32_t key; // Fast address match - bits 5..28 for valid entry, -1 for invalid entry
14.43 + uint32_t tag; // tag + flags value from the address field
14.44 +};
14.45 +
14.46 +
14.47 +static struct cache_line ccn_icache[ICACHE_ENTRY_COUNT];
14.48 +static struct cache_line ccn_ocache[OCACHE_ENTRY_COUNT];
14.49 +static unsigned char ccn_icache_data[ICACHE_ENTRY_COUNT*32];
14.50 +static unsigned char ccn_ocache_data[OCACHE_ENTRY_COUNT*32];
14.51 +
14.52 +
14.53 +/*********************** General module requirements ********************/
14.54 +
14.55 +void CCN_save_state( FILE *f )
14.56 +{
14.57 + fwrite( &ccn_icache, sizeof(ccn_icache), 1, f );
14.58 + fwrite( &ccn_icache_data, sizeof(ccn_icache_data), 1, f );
14.59 + fwrite( &ccn_ocache, sizeof(ccn_ocache), 1, f);
14.60 + fwrite( &ccn_ocache_data, sizeof(ccn_ocache_data), 1, f);
14.61 +}
14.62 +
14.63 +int CCN_load_state( FILE *f )
14.64 +{
14.65 + /* Setup the cache mode according to the saved register value
14.66 + * (mem_load runs before this point to load all MMIO data)
14.67 + */
14.68 + mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
14.69 +
14.70 + if( fread( &ccn_icache, sizeof(ccn_icache), 1, f ) != 1 ) {
14.71 + return 1;
14.72 + }
14.73 + if( fread( &ccn_icache_data, sizeof(ccn_icache_data), 1, f ) != 1 ) {
14.74 + return 1;
14.75 + }
14.76 + if( fread( &ccn_ocache, sizeof(ccn_ocache), 1, f ) != 1 ) {
14.77 + return 1;
14.78 + }
14.79 + if( fread( &ccn_ocache_data, sizeof(ccn_ocache_data), 1, f ) != 1 ) {
14.80 + return 1;
14.81 + }
14.82 + return 0;
14.83 +}
14.84 +
14.85 +
14.86 +/************************* OCRAM memory address space ************************/
14.87 +
14.88 +#define OCRAMPAGE0 (&ccn_ocache_data[4096]) /* Lines 128-255 */
14.89 +#define OCRAMPAGE1 (&ccn_ocache_data[12288]) /* Lines 384-511 */
14.90 +
14.91 +static int32_t FASTCALL ocram_page0_read_long( sh4addr_t addr )
14.92 +{
14.93 + return *((int32_t *)(OCRAMPAGE0 + (addr&0x00000FFF)));
14.94 +}
14.95 +static int32_t FASTCALL ocram_page0_read_word( sh4addr_t addr )
14.96 +{
14.97 + return SIGNEXT16(*((int16_t *)(OCRAMPAGE0 + (addr&0x00000FFF))));
14.98 +}
14.99 +static int32_t FASTCALL ocram_page0_read_byte( sh4addr_t addr )
14.100 +{
14.101 + return SIGNEXT8(*((int16_t *)(OCRAMPAGE0 + (addr&0x00000FFF))));
14.102 +}
14.103 +static void FASTCALL ocram_page0_write_long( sh4addr_t addr, uint32_t val )
14.104 +{
14.105 + *(uint32_t *)(OCRAMPAGE0 + (addr&0x00000FFF)) = val;
14.106 +}
14.107 +static void FASTCALL ocram_page0_write_word( sh4addr_t addr, uint32_t val )
14.108 +{
14.109 + *(uint16_t *)(OCRAMPAGE0 + (addr&0x00000FFF)) = (uint16_t)val;
14.110 +}
14.111 +static void FASTCALL ocram_page0_write_byte( sh4addr_t addr, uint32_t val )
14.112 +{
14.113 + *(uint8_t *)(OCRAMPAGE0 + (addr&0x00000FFF)) = (uint8_t)val;
14.114 +}
14.115 +static void FASTCALL ocram_page0_read_burst( unsigned char *dest, sh4addr_t addr )
14.116 +{
14.117 + memcpy( dest, OCRAMPAGE0+(addr&0x00000FFF), 32 );
14.118 +}
14.119 +static void FASTCALL ocram_page0_write_burst( sh4addr_t addr, unsigned char *src )
14.120 +{
14.121 + memcpy( OCRAMPAGE0+(addr&0x00000FFF), src, 32 );
14.122 +}
14.123 +
14.124 +struct mem_region_fn mem_region_ocram_page0 = {
14.125 + ocram_page0_read_long, ocram_page0_write_long,
14.126 + ocram_page0_read_word, ocram_page0_write_word,
14.127 + ocram_page0_read_byte, ocram_page0_write_byte,
14.128 + ocram_page0_read_burst, ocram_page0_write_burst };
14.129 +
14.130 +static int32_t FASTCALL ocram_page1_read_long( sh4addr_t addr )
14.131 +{
14.132 + return *((int32_t *)(OCRAMPAGE1 + (addr&0x00000FFF)));
14.133 +}
14.134 +static int32_t FASTCALL ocram_page1_read_word( sh4addr_t addr )
14.135 +{
14.136 + return SIGNEXT16(*((int16_t *)(OCRAMPAGE1 + (addr&0x00000FFF))));
14.137 +}
14.138 +static int32_t FASTCALL ocram_page1_read_byte( sh4addr_t addr )
14.139 +{
14.140 + return SIGNEXT8(*((int16_t *)(OCRAMPAGE1 + (addr&0x00000FFF))));
14.141 +}
14.142 +static void FASTCALL ocram_page1_write_long( sh4addr_t addr, uint32_t val )
14.143 +{
14.144 + *(uint32_t *)(OCRAMPAGE1 + (addr&0x00000FFF)) = val;
14.145 +}
14.146 +static void FASTCALL ocram_page1_write_word( sh4addr_t addr, uint32_t val )
14.147 +{
14.148 + *(uint16_t *)(OCRAMPAGE1 + (addr&0x00000FFF)) = (uint16_t)val;
14.149 +}
14.150 +static void FASTCALL ocram_page1_write_byte( sh4addr_t addr, uint32_t val )
14.151 +{
14.152 + *(uint8_t *)(OCRAMPAGE1 + (addr&0x00000FFF)) = (uint8_t)val;
14.153 +}
14.154 +static void FASTCALL ocram_page1_read_burst( unsigned char *dest, sh4addr_t addr )
14.155 +{
14.156 + memcpy( dest, OCRAMPAGE1+(addr&0x00000FFF), 32 );
14.157 +}
14.158 +static void FASTCALL ocram_page1_write_burst( sh4addr_t addr, unsigned char *src )
14.159 +{
14.160 + memcpy( OCRAMPAGE1+(addr&0x00000FFF), src, 32 );
14.161 +}
14.162 +
14.163 +struct mem_region_fn mem_region_ocram_page1 = {
14.164 + ocram_page1_read_long, ocram_page1_write_long,
14.165 + ocram_page1_read_word, ocram_page1_write_word,
14.166 + ocram_page1_read_byte, ocram_page1_write_byte,
14.167 + ocram_page1_read_burst, ocram_page1_write_burst };
14.168 +
14.169 +/****************** Cache control *********************/
14.170 +
14.171 +void CCN_set_cache_control( int reg )
14.172 +{
14.173 + uint32_t i;
14.174 + switch( reg & (CCR_OIX|CCR_ORA|CCR_OCE) ) {
14.175 + case MEM_OC_INDEX0: /* OIX=0 */
14.176 + for( i=OCRAM_START; i<OCRAM_END; i+=4 ) {
14.177 + sh4_address_space[i] = &mem_region_ocram_page0;
14.178 + sh4_address_space[i+1] = &mem_region_ocram_page0;
14.179 + sh4_address_space[i+2] = &mem_region_ocram_page1;
14.180 + sh4_address_space[i+3] = &mem_region_ocram_page1;
14.181 + }
14.182 + break;
14.183 + case MEM_OC_INDEX1: /* OIX=1 */
14.184 + for( i=OCRAM_START; i<OCRAM_MID; i++ )
14.185 + sh4_address_space[i] = &mem_region_ocram_page0;
14.186 + for( i=OCRAM_MID; i<OCRAM_END; i++ )
14.187 + sh4_address_space[i] = &mem_region_ocram_page1;
14.188 + break;
14.189 + default: /* disabled */
14.190 + for( i=OCRAM_START; i<OCRAM_END; i++ )
14.191 + sh4_address_space[i] = &mem_region_unmapped;
14.192 + break;
14.193 + }
14.194 +}
14.195 \ No newline at end of file
15.1 --- a/src/sh4/mmu.c Mon Dec 22 09:51:11 2008 +0000
15.2 +++ b/src/sh4/mmu.c Tue Dec 23 05:48:05 2008 +0000
15.3 @@ -23,6 +23,7 @@
15.4 #include "sh4/sh4core.h"
15.5 #include "sh4/sh4trans.h"
15.6 #include "mem.h"
15.7 +#include "mmu.h"
15.8
15.9 #ifdef HAVE_FRAME_ADDRESS
15.10 #define RETURN_VIA(exc) do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
15.11 @@ -30,8 +31,6 @@
15.12 #define RETURN_VIA(exc) return MMU_VMA_ERROR
15.13 #endif
15.14
15.15 -#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
15.16 -
15.17 /* The MMU (practically unique in the system) is allowed to raise exceptions
15.18 * directly, with a return code indicating that one was raised and the caller
15.19 * had better behave appropriately.
15.20 @@ -68,52 +67,6 @@
15.21 #define OCRAM_START (0x1C000000>>LXDREAM_PAGE_BITS)
15.22 #define OCRAM_END (0x20000000>>LXDREAM_PAGE_BITS)
15.23
15.24 -#define ITLB_ENTRY_COUNT 4
15.25 -#define UTLB_ENTRY_COUNT 64
15.26 -
15.27 -/* Entry address */
15.28 -#define TLB_VALID 0x00000100
15.29 -#define TLB_USERMODE 0x00000040
15.30 -#define TLB_WRITABLE 0x00000020
15.31 -#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
15.32 -#define TLB_SIZE_MASK 0x00000090
15.33 -#define TLB_SIZE_1K 0x00000000
15.34 -#define TLB_SIZE_4K 0x00000010
15.35 -#define TLB_SIZE_64K 0x00000080
15.36 -#define TLB_SIZE_1M 0x00000090
15.37 -#define TLB_CACHEABLE 0x00000008
15.38 -#define TLB_DIRTY 0x00000004
15.39 -#define TLB_SHARE 0x00000002
15.40 -#define TLB_WRITETHRU 0x00000001
15.41 -
15.42 -#define MASK_1K 0xFFFFFC00
15.43 -#define MASK_4K 0xFFFFF000
15.44 -#define MASK_64K 0xFFFF0000
15.45 -#define MASK_1M 0xFFF00000
15.46 -
15.47 -struct itlb_entry {
15.48 - sh4addr_t vpn; // Virtual Page Number
15.49 - uint32_t asid; // Process ID
15.50 - uint32_t mask;
15.51 - sh4addr_t ppn; // Physical Page Number
15.52 - uint32_t flags;
15.53 -};
15.54 -
15.55 -struct utlb_entry {
15.56 - sh4addr_t vpn; // Virtual Page Number
15.57 - uint32_t mask; // Page size mask
15.58 - uint32_t asid; // Process ID
15.59 - sh4addr_t ppn; // Physical Page Number
15.60 - uint32_t flags;
15.61 - uint32_t pcmcia; // extra pcmcia data - not used
15.62 -};
15.63 -
15.64 -struct utlb_sort_entry {
15.65 - sh4addr_t key; // Masked VPN + ASID
15.66 - uint32_t mask; // Mask + 0x00FF
15.67 - int entryNo;
15.68 -};
15.69 -
15.70
15.71 static struct itlb_entry mmu_itlb[ITLB_ENTRY_COUNT];
15.72 static struct utlb_entry mmu_utlb[UTLB_ENTRY_COUNT];
15.73 @@ -129,8 +82,7 @@
15.74
15.75 static void mmu_invalidate_tlb();
15.76 static void mmu_utlb_sorted_reset();
15.77 -static void mmu_utlb_sorted_reload();
15.78 -
15.79 +static void mmu_utlb_sorted_reload();
15.80
15.81 static uint32_t get_mask_for_flags( uint32_t flags )
15.82 {
15.83 @@ -199,7 +151,7 @@
15.84 }
15.85 break;
15.86 case CCR:
15.87 - mmu_set_cache_mode( val & (CCR_OIX|CCR_ORA|CCR_OCE) );
15.88 + CCN_set_cache_control( val );
15.89 val &= 0x81A7;
15.90 break;
15.91 case MMUUNK1:
15.92 @@ -229,7 +181,6 @@
15.93
15.94 void MMU_init()
15.95 {
15.96 - cache = mem_alloc_pages(2);
15.97 }
15.98
15.99 void MMU_reset()
15.100 @@ -241,7 +192,6 @@
15.101
15.102 void MMU_save_state( FILE *f )
15.103 {
15.104 - fwrite( cache, 4096, 2, f );
15.105 fwrite( &mmu_itlb, sizeof(mmu_itlb), 1, f );
15.106 fwrite( &mmu_utlb, sizeof(mmu_utlb), 1, f );
15.107 fwrite( &mmu_urc, sizeof(mmu_urc), 1, f );
15.108 @@ -252,13 +202,6 @@
15.109
15.110 int MMU_load_state( FILE *f )
15.111 {
15.112 - /* Setup the cache mode according to the saved register value
15.113 - * (mem_load runs before this point to load all MMIO data)
15.114 - */
15.115 - mmio_region_MMU_write( CCR, MMIO_READ(MMU, CCR) );
15.116 - if( fread( cache, 4096, 2, f ) != 2 ) {
15.117 - return 1;
15.118 - }
15.119 if( fread( &mmu_itlb, sizeof(mmu_itlb), 1, f ) != 1 ) {
15.120 return 1;
15.121 }
15.122 @@ -281,24 +224,6 @@
15.123 return 0;
15.124 }
15.125
15.126 -void mmu_set_cache_mode( int mode )
15.127 -{
15.128 - uint32_t i;
15.129 - switch( mode ) {
15.130 - case MEM_OC_INDEX0: /* OIX=0 */
15.131 - for( i=OCRAM_START; i<OCRAM_END; i++ )
15.132 - page_map[i] = cache + ((i&0x02)<<(LXDREAM_PAGE_BITS-1));
15.133 - break;
15.134 - case MEM_OC_INDEX1: /* OIX=1 */
15.135 - for( i=OCRAM_START; i<OCRAM_END; i++ )
15.136 - page_map[i] = cache + ((i&0x02000000)>>(25-LXDREAM_PAGE_BITS));
15.137 - break;
15.138 - default: /* disabled */
15.139 - for( i=OCRAM_START; i<OCRAM_END; i++ )
15.140 - page_map[i] = NULL;
15.141 - break;
15.142 - }
15.143 -}
15.144
15.145 /******************* Sorted TLB data structure ****************/
15.146 /*
15.147 @@ -1091,7 +1016,8 @@
15.148 uint32_t hi = MMIO_READ( MMU, QACR0 + (queue>>1)) << 24;
15.149 sh4ptr_t src = (sh4ptr_t)&sh4r.store_queue[queue];
15.150 sh4addr_t target = (addr&0x03FFFFE0) | hi;
15.151 - mem_copy_to_sh4( target, src, 32 );
15.152 + ext_address_space[target>>12]->write_burst( target, src );
15.153 +// mem_copy_to_sh4( target, src, 32 );
15.154 }
15.155
15.156 gboolean FASTCALL sh4_flush_store_queue_mmu( sh4addr_t addr )
15.157 @@ -1133,7 +1059,8 @@
15.158 (addr & (~mmu_utlb[entryNo].mask))) & 0xFFFFFFE0;
15.159 }
15.160
15.161 - mem_copy_to_sh4( target, src, 32 );
15.162 + ext_address_space[target>>12]->write_burst( target, src );
15.163 + // mem_copy_to_sh4( target, src, 32 );
15.164 return TRUE;
15.165 }
15.166
16.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
16.2 +++ b/src/sh4/mmu.h Tue Dec 23 05:48:05 2008 +0000
16.3 @@ -0,0 +1,81 @@
16.4 +/**
16.5 + * $Id$
16.6 + *
16.7 + * MMU/TLB definitions.
16.8 + *
16.9 + * Copyright (c) 2005 Nathan Keynes.
16.10 + *
16.11 + * This program is free software; you can redistribute it and/or modify
16.12 + * it under the terms of the GNU General Public License as published by
16.13 + * the Free Software Foundation; either version 2 of the License, or
16.14 + * (at your option) any later version.
16.15 + *
16.16 + * This program is distributed in the hope that it will be useful,
16.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
16.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16.19 + * GNU General Public License for more details.
16.20 + */
16.21 +
16.22 +
16.23 +#ifndef lxdream_sh4_mmu_H
16.24 +#define lxdream_sh4_mmu_H 1
16.25 +
16.26 +#include "lxdream.h"
16.27 +
16.28 +#ifdef __cplusplus
16.29 +extern "C" {
16.30 +#endif
16.31 +
16.32 +#define VMA_TO_EXT_ADDR(vma) ((vma)&0x1FFFFFFF)
16.33 +
16.34 +/************************** UTLB/ITLB Definitions ***************************/
16.35 +#define ITLB_ENTRY_COUNT 4
16.36 +#define UTLB_ENTRY_COUNT 64
16.37 +
16.38 +/* Entry address */
16.39 +#define TLB_VALID 0x00000100
16.40 +#define TLB_USERMODE 0x00000040
16.41 +#define TLB_WRITABLE 0x00000020
16.42 +#define TLB_USERWRITABLE (TLB_WRITABLE|TLB_USERMODE)
16.43 +#define TLB_SIZE_MASK 0x00000090
16.44 +#define TLB_SIZE_1K 0x00000000
16.45 +#define TLB_SIZE_4K 0x00000010
16.46 +#define TLB_SIZE_64K 0x00000080
16.47 +#define TLB_SIZE_1M 0x00000090
16.48 +#define TLB_CACHEABLE 0x00000008
16.49 +#define TLB_DIRTY 0x00000004
16.50 +#define TLB_SHARE 0x00000002
16.51 +#define TLB_WRITETHRU 0x00000001
16.52 +
16.53 +#define MASK_1K 0xFFFFFC00
16.54 +#define MASK_4K 0xFFFFF000
16.55 +#define MASK_64K 0xFFFF0000
16.56 +#define MASK_1M 0xFFF00000
16.57 +
16.58 +struct itlb_entry {
16.59 + sh4addr_t vpn; // Virtual Page Number
16.60 + uint32_t asid; // Process ID
16.61 + uint32_t mask;
16.62 + sh4addr_t ppn; // Physical Page Number
16.63 + uint32_t flags;
16.64 +};
16.65 +
16.66 +struct utlb_entry {
16.67 + sh4addr_t vpn; // Virtual Page Number
16.68 + uint32_t mask; // Page size mask
16.69 + uint32_t asid; // Process ID
16.70 + sh4addr_t ppn; // Physical Page Number
16.71 + uint32_t flags;
16.72 + uint32_t pcmcia; // extra pcmcia data - not used
16.73 +};
16.74 +
16.75 +struct utlb_sort_entry {
16.76 + sh4addr_t key; // Masked VPN + ASID
16.77 + uint32_t mask; // Mask + 0x00FF
16.78 + int entryNo;
16.79 +};
16.80 +
16.81 +#ifdef __cplusplus
16.82 +}
16.83 +#endif
16.84 +#endif /* !lxdream_sh4_mmu_H */
17.1 --- a/src/sh4/sh4.c Mon Dec 22 09:51:11 2008 +0000
17.2 +++ b/src/sh4/sh4.c Tue Dec 23 05:48:05 2008 +0000
17.3 @@ -87,8 +87,8 @@
17.4 dc_boot_rom = mem_get_region_by_name(MEM_REGION_BIOS);
17.5 dc_flash_ram = mem_get_region_by_name(MEM_REGION_FLASH);
17.6 dc_audio_ram = mem_get_region_by_name(MEM_REGION_AUDIO);
17.7 - MMU_init();
17.8 TMU_init();
17.9 + sh4_mem_init();
17.10 sh4_reset();
17.11 #ifdef ENABLE_SH4STATS
17.12 sh4_stats_reset();
17.13 @@ -243,6 +243,7 @@
17.14
17.15 fwrite( &sh4r, sizeof(sh4r), 1, f );
17.16 MMU_save_state( f );
17.17 + CCN_save_state( f );
17.18 PMM_save_state( f );
17.19 INTC_save_state( f );
17.20 TMU_save_state( f );
17.21 @@ -256,6 +257,7 @@
17.22 }
17.23 fread( &sh4r, sizeof(sh4r), 1, f );
17.24 MMU_load_state( f );
17.25 + CCN_load_state( f );
17.26 PMM_load_state( f );
17.27 INTC_load_state( f );
17.28 TMU_load_state( f );
18.1 --- a/src/sh4/sh4core.h Mon Dec 22 09:51:11 2008 +0000
18.2 +++ b/src/sh4/sh4core.h Tue Dec 23 05:48:05 2008 +0000
18.3 @@ -147,11 +147,12 @@
18.4 void INTC_reset( void );
18.5 void INTC_save_state( FILE *f );
18.6 int INTC_load_state( FILE *f );
18.7 -void MMU_init( void );
18.8 void MMU_reset( void );
18.9 void MMU_save_state( FILE *f );
18.10 int MMU_load_state( FILE *f );
18.11 void MMU_ldtlb();
18.12 +void CCN_save_state( FILE *f );
18.13 +int CCN_load_state( FILE *f );
18.14 void SCIF_reset( void );
18.15 void SCIF_run_slice( uint32_t );
18.16 void SCIF_save_state( FILE *f );
18.17 @@ -252,14 +253,6 @@
18.18 gboolean FASTCALL sh4_raise_tlb_exception( int );
18.19 void FASTCALL sh4_accept_interrupt( void );
18.20
18.21 -#define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
18.22 -#define SIGNEXT8(n) ((int32_t)((int8_t)(n)))
18.23 -#define SIGNEXT12(n) ((((int32_t)(n))<<20)>>20)
18.24 -#define SIGNEXT16(n) ((int32_t)((int16_t)(n)))
18.25 -#define SIGNEXT32(n) ((int64_t)((int32_t)(n)))
18.26 -#define SIGNEXT48(n) ((((int64_t)(n))<<16)>>16)
18.27 -#define ZEROEXT32(n) ((int64_t)((uint64_t)((uint32_t)(n))))
18.28 -
18.29 /* Status Register (SR) bits */
18.30 #define SR_MD 0x40000000 /* Processor mode ( User=0, Privileged=1 ) */
18.31 #define SR_RB 0x20000000 /* Register bank (priviledged mode only) */
19.1 --- a/src/sh4/sh4mem.c Mon Dec 22 09:51:11 2008 +0000
19.2 +++ b/src/sh4/sh4mem.c Tue Dec 23 05:48:05 2008 +0000
19.3 @@ -48,48 +48,6 @@
19.4 extern struct mem_region_fn mem_region_utlb_addr;
19.5 extern struct mem_region_fn mem_region_utlb_data;
19.6
19.7 -extern struct mmio_region *P4_io[];
19.8 -
19.9 -mem_region_fn_t *sh4_address_space;
19.10 -
19.11 -/********************* The "unmapped" address space ********************/
19.12 -/* Always reads as 0, writes have no effect */
19.13 -static int32_t FASTCALL unmapped_read_long( sh4addr_t addr )
19.14 -{
19.15 - return 0;
19.16 -}
19.17 -static void FASTCALL unmapped_write_long( sh4addr_t addr, uint32_t val )
19.18 -{
19.19 -}
19.20 -static void FASTCALL unmapped_read_burst( unsigned char *dest, sh4addr_t addr )
19.21 -{
19.22 - memset( dest, 0, 32 );
19.23 -}
19.24 -static void FASTCALL unmapped_write_burst( sh4addr_t addr, unsigned char *src )
19.25 -{
19.26 -}
19.27 -
19.28 -struct mem_region_fn mem_region_unmapped = {
19.29 - unmapped_read_long, unmapped_write_long,
19.30 - unmapped_read_long, unmapped_write_long,
19.31 - unmapped_read_long, unmapped_write_long,
19.32 - unmapped_read_burst, unmapped_write_burst };
19.33 -
19.34 -/********************* Store-queue (long-write only?) ******************/
19.35 -static void FASTCALL p4_storequeue_write_long( sh4addr_t addr, uint32_t val )
19.36 -{
19.37 - sh4r.store_queue[(addr>>2)&0xF] = val;
19.38 -}
19.39 -static int32_t FASTCALL p4_storequeue_read_long( sh4addr_t addr )
19.40 -{
19.41 - return sh4r.store_queue[(addr>>2)&0xF];
19.42 -}
19.43 -struct mem_region_fn p4_region_storequeue = {
19.44 - p4_storequeue_read_long, p4_storequeue_write_long,
19.45 - p4_storequeue_read_long, p4_storequeue_write_long,
19.46 - p4_storequeue_read_long, p4_storequeue_write_long,
19.47 - unmapped_read_burst, unmapped_write_burst }; // No burst access.
19.48 -
19.49 /********************* The main ram address space **********************/
19.50 static int32_t FASTCALL ext_sdram_read_long( sh4addr_t addr )
19.51 {
19.52 @@ -160,48 +118,6 @@
19.53 ext_bootrom_read_byte, unmapped_write_long,
19.54 ext_bootrom_read_burst, unmapped_write_burst };
19.55
19.56 -/********************* The Audio RAM address space **********************/
19.57 -static int32_t FASTCALL ext_audioram_read_long( sh4addr_t addr )
19.58 -{
19.59 - return *((int32_t *)(dc_audio_ram + (addr&0x001FFFFF)));
19.60 -}
19.61 -static int32_t FASTCALL ext_audioram_read_word( sh4addr_t addr )
19.62 -{
19.63 - return SIGNEXT16(*((int16_t *)(dc_audio_ram + (addr&0x001FFFFF))));
19.64 -}
19.65 -static int32_t FASTCALL ext_audioram_read_byte( sh4addr_t addr )
19.66 -{
19.67 - return SIGNEXT8(*((int16_t *)(dc_audio_ram + (addr&0x001FFFFF))));
19.68 -}
19.69 -static void FASTCALL ext_audioram_write_long( sh4addr_t addr, uint32_t val )
19.70 -{
19.71 - *(uint32_t *)(dc_audio_ram + (addr&0x001FFFFF)) = val;
19.72 - asic_g2_write_word();
19.73 -}
19.74 -static void FASTCALL ext_audioram_write_word( sh4addr_t addr, uint32_t val )
19.75 -{
19.76 - *(uint16_t *)(dc_audio_ram + (addr&0x001FFFFF)) = (uint16_t)val;
19.77 - asic_g2_write_word();
19.78 -}
19.79 -static void FASTCALL ext_audioram_write_byte( sh4addr_t addr, uint32_t val )
19.80 -{
19.81 - *(uint8_t *)(dc_audio_ram + (addr&0x001FFFFF)) = (uint8_t)val;
19.82 - asic_g2_write_word();
19.83 -}
19.84 -static void FASTCALL ext_audioram_read_burst( unsigned char *dest, sh4addr_t addr )
19.85 -{
19.86 - memcpy( dest, dc_audio_ram+(addr&0x001FFFFF), 32 );
19.87 -}
19.88 -static void FASTCALL ext_audioram_write_burst( sh4addr_t addr, unsigned char *src )
19.89 -{
19.90 - memcpy( dc_audio_ram+(addr&0x001FFFFF), src, 32 );
19.91 -}
19.92 -
19.93 -struct mem_region_fn mem_region_audioram = { ext_audioram_read_long, ext_audioram_write_long,
19.94 - ext_audioram_read_word, ext_audioram_write_word,
19.95 - ext_audioram_read_byte, ext_audioram_write_byte,
19.96 - ext_audioram_read_burst, ext_audioram_write_burst };
19.97 -
19.98 /********************* The Flash RAM address space **********************/
19.99 static int32_t FASTCALL ext_flashram_read_long( sh4addr_t addr )
19.100 {
19.101 @@ -244,8 +160,25 @@
19.102 ext_flashram_read_byte, ext_flashram_write_byte,
19.103 ext_flashram_read_burst, ext_flashram_write_burst };
19.104
19.105 -/**************************************************************************/
19.106 +/***************************** P4 Regions ************************************/
19.107
19.108 +/* Store-queue (long-write only?) */
19.109 +static void FASTCALL p4_storequeue_write_long( sh4addr_t addr, uint32_t val )
19.110 +{
19.111 + sh4r.store_queue[(addr>>2)&0xF] = val;
19.112 +}
19.113 +static int32_t FASTCALL p4_storequeue_read_long( sh4addr_t addr )
19.114 +{
19.115 + return sh4r.store_queue[(addr>>2)&0xF];
19.116 +}
19.117 +
19.118 +struct mem_region_fn p4_region_storequeue = {
19.119 + p4_storequeue_read_long, p4_storequeue_write_long,
19.120 + p4_storequeue_read_long, p4_storequeue_write_long,
19.121 + p4_storequeue_read_long, p4_storequeue_write_long,
19.122 + unmapped_read_burst, unmapped_write_burst }; // No burst access.
19.123 +
19.124 +/* Cache access */
19.125 struct mem_region_fn p4_region_icache_addr = {
19.126 mmu_icache_addr_read, mmu_icache_addr_write,
19.127 mmu_icache_addr_read, mmu_icache_addr_write,
19.128 @@ -266,6 +199,8 @@
19.129 mmu_ocache_data_read, mmu_ocache_data_write,
19.130 mmu_ocache_data_read, mmu_ocache_data_write,
19.131 unmapped_read_burst, unmapped_write_burst };
19.132 +
19.133 +/* TLB access */
19.134 struct mem_region_fn p4_region_itlb_addr = {
19.135 mmu_itlb_addr_read, mmu_itlb_addr_write,
19.136 mmu_itlb_addr_read, mmu_itlb_addr_write,
19.137 @@ -287,94 +222,104 @@
19.138 mmu_utlb_data_read, mmu_utlb_data_write,
19.139 unmapped_read_burst, unmapped_write_burst };
19.140
19.141 +/********************** Initialization *************************/
19.142 +
19.143 +mem_region_fn_t *sh4_address_space;
19.144 +
19.145 +static void sh4_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
19.146 +{
19.147 + int count = (end - start) >> 12;
19.148 + mem_region_fn_t *ptr = &sh4_address_space[start>>12];
19.149 + while( count-- > 0 ) {
19.150 + *ptr++ = fn;
19.151 + }
19.152 +}
19.153 +
19.154 +static gboolean sh4_ext_page_remapped( sh4addr_t page, mem_region_fn_t fn, void *user_data )
19.155 +{
19.156 + int i;
19.157 + for( i=0; i<= 0xC0000000; i+= 0x20000000 ) {
19.158 + sh4_address_space[(page|i)>>12] = fn;
19.159 + }
19.160 +}
19.161 +
19.162 +
19.163 +void sh4_mem_init()
19.164 +{
19.165 + int i;
19.166 + mem_region_fn_t *ptr;
19.167 + sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
19.168 + for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
19.169 + memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
19.170 + }
19.171 +
19.172 + /* Setup main P4 regions */
19.173 + sh4_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
19.174 + sh4_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
19.175 + sh4_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
19.176 + sh4_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
19.177 + sh4_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
19.178 + sh4_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
19.179 + sh4_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
19.180 + sh4_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
19.181 + sh4_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
19.182 + sh4_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
19.183 + sh4_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
19.184 +
19.185 + /* Setup P4 control region */
19.186 + sh4_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
19.187 + sh4_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
19.188 + sh4_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
19.189 + sh4_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
19.190 + sh4_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
19.191 + sh4_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
19.192 + sh4_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
19.193 + sh4_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
19.194 + sh4_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
19.195 + sh4_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
19.196 + sh4_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
19.197 + sh4_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
19.198 + sh4_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
19.199 +
19.200 + register_mem_page_remapped_hook( sh4_ext_page_remapped, NULL );
19.201 +}
19.202 +
19.203 +/************** Access methods ***************/
19.204 #ifdef HAVE_FRAME_ADDRESS
19.205 #define RETURN_VIA(exc) do{ *(((void **)__builtin_frame_address(0))+1) = exc; return; } while(0)
19.206 #else
19.207 #define RETURN_VIA(exc) return NULL
19.208 #endif
19.209
19.210 -int decode_sdram = 0;
19.211 -mem_region_fn_t FASTCALL mem_decode_address( sh4addr_t addr )
19.212 +
19.213 +int32_t FASTCALL sh4_read_long( sh4addr_t addr )
19.214 {
19.215 - sh4ptr_t page;
19.216 - switch( addr >> 26 ) { /* Area */
19.217 - case 0: /* Holly multiplexed */
19.218 - page = page_map[(addr&0x1FFFFFFF)>>12];
19.219 - if( ((uintptr_t)page) < MAX_IO_REGIONS ) {
19.220 - return &io_rgn[(uintptr_t)page]->fn;
19.221 - } else if( addr < 0x00200000 ) {
19.222 - return &mem_region_bootrom;
19.223 - } else if( addr < 0x00400000 ) {
19.224 - return &mem_region_flashram;
19.225 - } else if( addr >= 0x00800000 && addr < 0x00A00000 ) {
19.226 - return &mem_region_audioram;
19.227 - }
19.228 - break;
19.229 - case 1: /* VRAM */
19.230 - switch( addr >> 24 ) {
19.231 - case 4: return &mem_region_vram64; /* 0x04xxxxxx */
19.232 - case 5: return &mem_region_vram32; /* 0x05xxxxxx */
19.233 - }
19.234 - break;
19.235 - case 2: /* Unmapped */
19.236 - break;
19.237 - case 3: /* Main sdram */
19.238 - decode_sdram++;
19.239 - return &mem_region_sdram;
19.240 - case 4: /* Holly burst-access only? */
19.241 - break;
19.242 - }
19.243 - return &mem_region_unmapped;
19.244 + return sh4_address_space[addr>>12]->read_long(addr);
19.245 }
19.246
19.247 -int decode_count = 0;
19.248 -int p4_count = 0;
19.249 -int sq_count = 0;
19.250 -
19.251 -mem_region_fn_t FASTCALL sh7750_decode_address( sh4addr_t addr )
19.252 +int32_t FASTCALL sh4_read_word( sh4addr_t addr )
19.253 {
19.254 - decode_count++;
19.255 - sh4addr_t region = addr >> 29;
19.256 - switch( region ) {
19.257 - case 7: /* P4 E0000000-FFFFFFFF - On-chip I/O */
19.258 - if( addr < 0xE4000000 ) {
19.259 - sq_count++;
19.260 - return &p4_region_storequeue;
19.261 - } else if( addr < 0xFC000000 ) { /* Control register region */
19.262 - p4_count++;
19.263 - switch( addr & 0x1F000000 ) {
19.264 - case 0x10000000: return &p4_region_icache_addr;
19.265 - case 0x11000000: return &p4_region_icache_data;
19.266 - case 0x12000000: return &p4_region_itlb_addr;
19.267 - case 0x13000000: return &p4_region_itlb_data;
19.268 - case 0x14000000: return &p4_region_ocache_addr;
19.269 - case 0x15000000: return &p4_region_ocache_data;
19.270 - case 0x16000000: return &p4_region_utlb_addr;
19.271 - case 0x17000000: return &p4_region_utlb_data;
19.272 - default: return &mem_region_unmapped;
19.273 - }
19.274 - } else {
19.275 - p4_count++;
19.276 - struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19];
19.277 - if( io != NULL ) {
19.278 - return &io->fn;
19.279 - }
19.280 - return &mem_region_unmapped;
19.281 - }
19.282 - break;
19.283 - case 6: /* P3 C0000000-DFFFFFFF - TLB on, Cache on */
19.284 - case 5: /* P2 A0000000-BFFFFFFF - TLB off, Cache off*/
19.285 - case 4: /* P1 80000000-9FFFFFFF - TLB off, Cache on */
19.286 - default: /* P0/U0 00000000-7FFFFFFF - TLB on, Cache on */
19.287 - return mem_decode_address( addr & 0x1FFFFFFF );
19.288 - /* TODO: Integrate TLB, Operand Cache lookups */
19.289 - }
19.290 + return sh4_address_space[addr>>12]->read_word(addr);
19.291 }
19.292
19.293 -void FASTCALL sh7750_decode_address_copy( sh4addr_t addr, mem_region_fn_t result )
19.294 +int32_t FASTCALL sh4_read_byte( sh4addr_t addr )
19.295 {
19.296 - mem_region_fn_t region = sh7750_decode_address( addr );
19.297 - memcpy( result, region, sizeof(struct mem_region_fn) -8 );
19.298 + return sh4_address_space[addr>>12]->read_byte(addr);
19.299 +}
19.300 +
19.301 +void FASTCALL sh4_write_long( sh4addr_t addr, uint32_t val )
19.302 +{
19.303 + sh4_address_space[addr>>12]->write_long(addr, val);
19.304 +}
19.305 +
19.306 +void FASTCALL sh4_write_word( sh4addr_t addr, uint32_t val )
19.307 +{
19.308 + sh4_address_space[addr>>12]->write_word(addr,val);
19.309 +}
19.310 +
19.311 +void FASTCALL sh4_write_byte( sh4addr_t addr, uint32_t val )
19.312 +{
19.313 + sh4_address_space[addr>>12]->write_byte(addr, val);
19.314 }
19.315
19.316 /* FIXME: Handle all the many special cases when the range doesn't fall cleanly
19.317 @@ -411,106 +356,3 @@
19.318 memcpy( dest, src, count );
19.319 }
19.320 }
19.321 -
19.322 -static uint32_t last_page = -1;
19.323 -static mem_region_fn_t last_region = NULL;
19.324 -static uint32_t hit_count = 0;
19.325 -static uint32_t miss_count = 0;
19.326 -static uint32_t rl_count = 0, rw_count = 0, rb_count = 0;
19.327 -static uint32_t wl_count = 0, ww_count = 0, wb_count = 0;
19.328 -
19.329 -/************** Compatibility methods ***************/
19.330 -
19.331 -int32_t FASTCALL sh4_read_long( sh4addr_t addr )
19.332 -{
19.333 - rl_count++;
19.334 - return sh4_address_space[addr>>12]->read_long(addr);
19.335 -}
19.336 -
19.337 -int32_t FASTCALL sh4_read_word( sh4addr_t addr )
19.338 -{
19.339 - rw_count++;
19.340 - return sh4_address_space[addr>>12]->read_word(addr);
19.341 -}
19.342 -
19.343 -int32_t FASTCALL sh4_read_byte( sh4addr_t addr )
19.344 -{
19.345 - rb_count++;
19.346 - return sh4_address_space[addr>>12]->read_byte(addr);
19.347 -}
19.348 -
19.349 -void FASTCALL sh4_write_long( sh4addr_t addr, uint32_t val )
19.350 -{
19.351 - wl_count++;
19.352 - sh4_address_space[addr>>12]->write_long(addr, val);
19.353 -}
19.354 -
19.355 -void FASTCALL sh4_write_word( sh4addr_t addr, uint32_t val )
19.356 -{
19.357 - ww_count++;
19.358 - sh4_address_space[addr>>12]->write_word(addr,val);
19.359 -}
19.360 -
19.361 -void FASTCALL sh4_write_byte( sh4addr_t addr, uint32_t val )
19.362 -{
19.363 - wb_count++;
19.364 - sh4_address_space[addr>>12]->write_byte(addr, val);
19.365 -}
19.366 -
19.367 -extern mem_region_fn_t *ext_address_space;
19.368 -
19.369 -static void sh4_register_mem_region( uint32_t start, uint32_t end, mem_region_fn_t fn )
19.370 -{
19.371 - int count = (end - start) >> 12;
19.372 - mem_region_fn_t *ptr = &sh4_address_space[start>>12];
19.373 - while( count-- > 0 ) {
19.374 - *ptr++ = fn;
19.375 - }
19.376 -}
19.377 -
19.378 -
19.379 -void sh4_mem_init()
19.380 -{
19.381 - int i;
19.382 - mem_region_fn_t *ptr;
19.383 - sh4_address_space = mem_alloc_pages( sizeof(mem_region_fn_t) * 256 );
19.384 - for( i=0, ptr = sh4_address_space; i<7; i++, ptr += LXDREAM_PAGE_TABLE_ENTRIES ) {
19.385 - memcpy( ptr, ext_address_space, sizeof(mem_region_fn_t) * LXDREAM_PAGE_TABLE_ENTRIES );
19.386 - }
19.387 -
19.388 - /* Setup main P4 regions */
19.389 - sh4_register_mem_region( 0xE0000000, 0xE4000000, &p4_region_storequeue );
19.390 - sh4_register_mem_region( 0xE4000000, 0xF0000000, &mem_region_unmapped );
19.391 - sh4_register_mem_region( 0xF0000000, 0xF1000000, &p4_region_icache_addr );
19.392 - sh4_register_mem_region( 0xF1000000, 0xF2000000, &p4_region_icache_data );
19.393 - sh4_register_mem_region( 0xF2000000, 0xF3000000, &p4_region_itlb_addr );
19.394 - sh4_register_mem_region( 0xF3000000, 0xF4000000, &p4_region_itlb_data );
19.395 - sh4_register_mem_region( 0xF4000000, 0xF5000000, &p4_region_ocache_addr );
19.396 - sh4_register_mem_region( 0xF5000000, 0xF6000000, &p4_region_ocache_data );
19.397 - sh4_register_mem_region( 0xF6000000, 0xF7000000, &p4_region_utlb_addr );
19.398 - sh4_register_mem_region( 0xF7000000, 0xF8000000, &p4_region_utlb_data );
19.399 - sh4_register_mem_region( 0xF8000000, 0x00000000, &mem_region_unmapped );
19.400 -
19.401 - /* Setup P4 control region */
19.402 - sh4_register_mem_region( 0xFF000000, 0xFF001000, &mmio_region_MMU.fn );
19.403 - sh4_register_mem_region( 0xFF100000, 0xFF101000, &mmio_region_PMM.fn );
19.404 - sh4_register_mem_region( 0xFF200000, 0xFF201000, &mmio_region_UBC.fn );
19.405 - sh4_register_mem_region( 0xFF800000, 0xFF801000, &mmio_region_BSC.fn );
19.406 - sh4_register_mem_region( 0xFF900000, 0xFFA00000, &mem_region_unmapped ); // SDMR2 + SDMR3
19.407 - sh4_register_mem_region( 0xFFA00000, 0xFFA01000, &mmio_region_DMAC.fn );
19.408 - sh4_register_mem_region( 0xFFC00000, 0xFFC01000, &mmio_region_CPG.fn );
19.409 - sh4_register_mem_region( 0xFFC80000, 0xFFC81000, &mmio_region_RTC.fn );
19.410 - sh4_register_mem_region( 0xFFD00000, 0xFFD01000, &mmio_region_INTC.fn );
19.411 - sh4_register_mem_region( 0xFFD80000, 0xFFD81000, &mmio_region_TMU.fn );
19.412 - sh4_register_mem_region( 0xFFE00000, 0xFFE01000, &mmio_region_SCI.fn );
19.413 - sh4_register_mem_region( 0xFFE80000, 0xFFE81000, &mmio_region_SCIF.fn );
19.414 - sh4_register_mem_region( 0xFFF00000, 0xFFF01000, &mem_region_unmapped ); // H-UDI
19.415 -}
19.416 -
19.417 -void print_sh4mem_stats() {
19.418 - printf( "Decodes to p4: %d sq: %d\n", p4_count+sq_count, sq_count );
19.419 - printf( "Decodes to sdram: %d\n", decode_sdram );
19.420 - printf( "Decodes: %d Hits: %d Miss: %d\n", decode_count, hit_count, miss_count );
19.421 - printf( "Read long: %d word: %d byte: %d\n", rl_count, rw_count, rb_count );
19.422 - printf( "Write long: %d word: %d byte: %d\n", wl_count, ww_count, wb_count );
19.423 -}
19.424 \ No newline at end of file
20.1 --- a/src/test/testsh4x86.c Mon Dec 22 09:51:11 2008 +0000
20.2 +++ b/src/test/testsh4x86.c Tue Dec 23 05:48:05 2008 +0000
20.3 @@ -88,13 +88,6 @@
20.4 {
20.5 return *(uint32_t *)(inbuf+(addr-start_addr));
20.6 }
20.7 -mem_region_fn_t FASTCALL sh7750_decode_address( sh4addr_t address )
20.8 -{
20.9 - return NULL;
20.10 -}
20.11 -void FASTCALL sh7750_decode_address_copy( sh4addr_t address, mem_region_fn_t out )
20.12 -{
20.13 -}
20.14
20.15 // Stubs
20.16 gboolean sh4_execute_instruction( ) { return TRUE; }
20.17 @@ -107,6 +100,7 @@
20.18 void sh4_flush_icache(){}
20.19 void event_execute() {}
20.20 void TMU_run_slice( uint32_t nanos ) {}
20.21 +void CCN_set_cache_control( uint32_t val ) { }
20.22 void PMM_write_control( int ctr, uint32_t val ) { }
20.23 void SCIF_run_slice( uint32_t nanos ) {}
20.24 void FASTCALL sh4_write_byte( uint32_t addr, uint32_t val ) {}
.