lxdream 0.9.1revision 673:44c579439d73
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raw | bz2 | zip | gz | changeset | 673:44c579439d73 |
| parent | 672:cc2c2b0ab272 |
| child | 674:377d987db8f2 |
| author | nkeynes |
| date | Sun May 25 21:01:55 2008 +0000 (15 years ago) |
Count fpscr ops separately from other LDS/STS instructions
 | src/sh4/sh4stat.c | view | annotate | diff | log | |
| src/sh4/sh4stat.h | view | annotate | diff | log | |
| src/sh4/sh4stat.in | view | annotate | diff | log | |
| src/sh4/sh4x86.c | view | annotate | diff | log | |
| src/sh4/sh4x86.in | view | annotate | diff | log |
1.1 --- a/src/sh4/sh4stat.c Sun May 25 20:59:29 2008 +00001.2 +++ b/src/sh4/sh4stat.c Sun May 25 21:01:55 2008 +00001.3 @@ -98,7 +98,9 @@1.4 "LDC Rm, *",1.5 "LDC.L @Rm+, SR",1.6 "LDC.L @Rm+, *",1.7 +"LDS Rm, FPSCR",1.8 "LDS Rm, *",1.9 +"LDS.L @Rm+, FPSCR",1.10 "LDS.L @Rm+, *",1.11 "LDTLB",1.12 "MAC.L @Rm+, @Rn+",1.13 @@ -145,7 +147,9 @@1.14 "STC *, Rn",1.15 "STC.L SR, @-Rn",1.16 "STC.L *, @-Rn",1.17 +"STS FPSCR, Rn",1.18 "STS *, Rn",1.19 +"STS.L FPSCR, @-Rn",1.20 "STS.L *, @-Rn",1.21 "SUB Rm, Rn",1.22 "SUBC Rm, Rn",1.23 @@ -410,7 +414,7 @@1.24 case 0x6:1.25 { /* STS FPSCR, Rn */1.26 uint32_t Rn = ((ir>>8)&0xF);1.27 - sh4_stats[I_STS]++;1.28 + sh4_stats[I_STSFPSCR]++;1.29 }1.30 break;1.31 case 0xF:1.32 @@ -756,7 +760,7 @@1.33 case 0x6:1.34 { /* STS.L FPSCR, @-Rn */1.35 uint32_t Rn = ((ir>>8)&0xF);1.36 - sh4_stats[I_STSM]++;1.37 + sh4_stats[I_STSFPSCRM]++;1.38 }1.39 break;1.40 case 0xF:1.41 @@ -896,7 +900,7 @@1.42 case 0x6:1.43 { /* LDS.L @Rm+, FPSCR */1.44 uint32_t Rm = ((ir>>8)&0xF);1.45 - sh4_stats[I_LDSM]++;1.46 + sh4_stats[I_LDSFPSCRM]++;1.47 }1.48 break;1.49 case 0xF:1.50 @@ -1042,7 +1046,7 @@1.51 case 0x6:1.52 { /* LDS Rm, FPSCR */1.53 uint32_t Rm = ((ir>>8)&0xF);1.54 - sh4_stats[I_LDS]++;1.55 + sh4_stats[I_LDSFPSCR]++;1.56 }1.57 break;1.58 case 0xF:
2.1 --- a/src/sh4/sh4stat.h Sun May 25 20:59:29 2008 +00002.2 +++ b/src/sh4/sh4stat.h Sun May 25 21:01:55 2008 +00002.3 @@ -37,7 +37,7 @@2.4 I_FMOV5, I_FMOV6, I_FMOV7, I_FMUL, I_FNEG, I_FRCHG, I_FSCA, I_FSCHG,2.5 I_FSQRT, I_FSRRA, I_FSTS, I_FSUB, I_FTRC, I_FTRV,2.6 I_JMP, I_JSR,2.7 - I_LDCSR, I_LDC, I_LDCSRM, I_LDCM, I_LDS, I_LDSM, I_LDTLB,2.8 + I_LDCSR, I_LDC, I_LDCSRM, I_LDCM, I_LDSFPSCR, I_LDS, I_LDSFPSCRM, I_LDSM, I_LDTLB,2.9 I_MACL, I_MACW,2.10 I_MOV, I_MOVI, I_MOVB, I_MOVL, I_MOVLPC, I_MOVW, I_MOVA, I_MOVCA, I_MOVT,2.11 I_MULL, I_MULSW, I_MULUW,2.12 @@ -50,7 +50,7 @@2.13 I_SETS, I_SETT,2.14 I_SHAD, I_SHAL, I_SHAR, I_SHLD, I_SHLL, I_SHLR,2.15 I_SLEEP,2.16 - I_STCSR, I_STC, I_STCSRM, I_STCM, I_STS, I_STSM,2.17 + I_STCSR, I_STC, I_STCSRM, I_STCM, I_STSFPSCR, I_STS, I_STSFPSCRM, I_STSM,2.18 I_SUB, I_SUBC, I_SUBV,2.19 I_SWAPB, I_SWAPW, I_TASB,2.20 I_TRAPA,
3.1 --- a/src/sh4/sh4stat.in Sun May 25 20:59:29 2008 +00003.2 +++ b/src/sh4/sh4stat.in Sun May 25 21:01:55 2008 +00003.3 @@ -98,7 +98,9 @@3.4 "LDC Rm, *",3.5 "LDC.L @Rm+, SR",3.6 "LDC.L @Rm+, *",3.7 +"LDS Rm, FPSCR",3.8 "LDS Rm, *",3.9 +"LDS.L @Rm+, FPSCR",3.10 "LDS.L @Rm+, *",3.11 "LDTLB",3.12 "MAC.L @Rm+, @Rn+",3.13 @@ -145,7 +147,9 @@3.14 "STC *, Rn",3.15 "STC.L SR, @-Rn",3.16 "STC.L *, @-Rn",3.17 +"STS FPSCR, Rn",3.18 "STS *, Rn",3.19 +"STS.L FPSCR, @-Rn",3.20 "STS.L *, @-Rn",3.21 "SUB Rm, Rn",3.22 "SUBC Rm, Rn",3.23 @@ -279,8 +283,8 @@3.24 LDC.L @Rm+, SPC {: sh4_stats[I_LDCM]++; :}3.25 LDC.L @Rm+, DBR {: sh4_stats[I_LDCM]++; :}3.26 LDC.L @Rm+, Rn_BANK {: sh4_stats[I_LDCM]++; :}3.27 -LDS Rm, FPSCR {: sh4_stats[I_LDS]++; :}3.28 -LDS.L @Rm+, FPSCR {: sh4_stats[I_LDSM]++; :}3.29 +LDS Rm, FPSCR {: sh4_stats[I_LDSFPSCR]++; :}3.30 +LDS.L @Rm+, FPSCR {: sh4_stats[I_LDSFPSCRM]++; :}3.31 LDS Rm, FPUL {: sh4_stats[I_LDS]++; :}3.32 LDS.L @Rm+, FPUL {: sh4_stats[I_LDSM]++; :}3.33 LDS Rm, MACH {: sh4_stats[I_LDS]++; :}3.34 @@ -380,8 +384,8 @@3.35 STC.L DBR, @-Rn {: sh4_stats[I_STCM]++; :}3.36 STC.L Rm_BANK, @-Rn {: sh4_stats[I_STCM]++; :}3.37 STC.L GBR, @-Rn {: sh4_stats[I_STCM]++; :}3.38 -STS FPSCR, Rn {: sh4_stats[I_STS]++; :}3.39 -STS.L FPSCR, @-Rn {: sh4_stats[I_STSM]++; :}3.40 +STS FPSCR, Rn {: sh4_stats[I_STSFPSCR]++; :}3.41 +STS.L FPSCR, @-Rn {: sh4_stats[I_STSFPSCRM]++; :}3.42 STS FPUL, Rn {: sh4_stats[I_STS]++; :}3.43 STS.L FPUL, @-Rn {: sh4_stats[I_STSM]++; :}3.44 STS MACH, Rn {: sh4_stats[I_STS]++; :}
4.1 --- a/src/sh4/sh4x86.c Sun May 25 20:59:29 2008 +00004.2 +++ b/src/sh4/sh4x86.c Sun May 25 21:01:55 2008 +00004.3 @@ -750,7 +750,7 @@4.4 case 0x6:4.5 { /* STS FPSCR, Rn */4.6 uint32_t Rn = ((ir>>8)&0xF);4.7 - COUNT_INST(I_STS);4.8 + COUNT_INST(I_STSFPSCR);4.9 check_fpuen();4.10 load_spreg( R_EAX, R_FPSCR );4.11 store_reg( R_EAX, Rn );4.12 @@ -1488,7 +1488,7 @@4.13 case 0x6:4.14 { /* STS.L FPSCR, @-Rn */4.15 uint32_t Rn = ((ir>>8)&0xF);4.16 - COUNT_INST(I_STSM);4.17 + COUNT_INST(I_STSFPSCRM);4.18 check_fpuen();4.19 load_reg( R_EAX, Rn );4.20 check_walign32( R_EAX );4.21 @@ -1768,7 +1768,7 @@4.22 case 0x6:4.23 { /* LDS.L @Rm+, FPSCR */4.24 uint32_t Rm = ((ir>>8)&0xF);4.25 - COUNT_INST(I_LDS);4.26 + COUNT_INST(I_LDSFPSCRM);4.27 check_fpuen();4.28 load_reg( R_EAX, Rm );4.29 check_ralign32( R_EAX );4.30 @@ -2020,7 +2020,7 @@4.31 case 0x6:4.32 { /* LDS Rm, FPSCR */4.33 uint32_t Rm = ((ir>>8)&0xF);4.34 - COUNT_INST(I_LDS);4.35 + COUNT_INST(I_LDSFPSCR);4.36 check_fpuen();4.37 load_reg( R_EAX, Rm );4.38 call_func1( sh4_write_fpscr, R_EAX );4.39 @@ -3296,18 +3296,11 @@4.40 { /* FMOV FRm, FRn */4.41 uint32_t FRn = ((ir>>8)&0xF); uint32_t FRm = ((ir>>4)&0xF);4.42 COUNT_INST(I_FMOV1);4.43 - /* As horrible as this looks, it's actually covering 5 separate cases:4.44 - * 1. 32-bit fr-to-fr (PR=0)4.45 - * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )4.46 - * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )4.47 - * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )4.48 - * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )4.49 - */4.50 check_fpuen();4.51 load_spreg( R_ECX, R_FPSCR );4.52 TEST_imm32_r32( FPSCR_SZ, R_ECX );4.53 JNE_rel8(doublesize);4.54 - load_fr( R_EAX, FRm ); // PR=0 branch4.55 + load_fr( R_EAX, FRm ); // SZ=0 branch4.56 store_fr( R_EAX, FRn );4.57 JMP_rel8(end);4.58 JMP_TARGET(doublesize);
5.1 --- a/src/sh4/sh4x86.in Sun May 25 20:59:29 2008 +00005.2 +++ b/src/sh4/sh4x86.in Sun May 25 21:01:55 2008 +00005.3 @@ -1798,18 +1798,11 @@5.4 /* Floating point moves */5.5 FMOV FRm, FRn {:5.6 COUNT_INST(I_FMOV1);5.7 - /* As horrible as this looks, it's actually covering 5 separate cases:5.8 - * 1. 32-bit fr-to-fr (PR=0)5.9 - * 2. 64-bit dr-to-dr (PR=1, FRm&1 == 0, FRn&1 == 0 )5.10 - * 3. 64-bit dr-to-xd (PR=1, FRm&1 == 0, FRn&1 == 1 )5.11 - * 4. 64-bit xd-to-dr (PR=1, FRm&1 == 1, FRn&1 == 0 )5.12 - * 5. 64-bit xd-to-xd (PR=1, FRm&1 == 1, FRn&1 == 1 )5.13 - */5.14 check_fpuen();5.15 load_spreg( R_ECX, R_FPSCR );5.16 TEST_imm32_r32( FPSCR_SZ, R_ECX );5.17 JNE_rel8(doublesize);5.18 - load_fr( R_EAX, FRm ); // PR=0 branch5.19 + load_fr( R_EAX, FRm ); // SZ=0 branch5.20 store_fr( R_EAX, FRn );5.21 JMP_rel8(end);5.22 JMP_TARGET(doublesize);5.23 @@ -2495,14 +2488,14 @@5.24 sh4_x86.tstate = TSTATE_NONE;5.25 :}5.26 LDS Rm, FPSCR {:5.27 - COUNT_INST(I_LDS);5.28 + COUNT_INST(I_LDSFPSCR);5.29 check_fpuen();5.30 load_reg( R_EAX, Rm );5.31 call_func1( sh4_write_fpscr, R_EAX );5.32 sh4_x86.tstate = TSTATE_NONE;5.33 :}5.34 LDS.L @Rm+, FPSCR {:5.35 - COUNT_INST(I_LDS);5.36 + COUNT_INST(I_LDSFPSCRM);5.37 check_fpuen();5.38 load_reg( R_EAX, Rm );5.39 check_ralign32( R_EAX );5.40 @@ -2760,13 +2753,13 @@5.41 sh4_x86.tstate = TSTATE_NONE;5.42 :}5.43 STS FPSCR, Rn {:5.44 - COUNT_INST(I_STS);5.45 + COUNT_INST(I_STSFPSCR);5.46 check_fpuen();5.47 load_spreg( R_EAX, R_FPSCR );5.48 store_reg( R_EAX, Rn );5.49 :}5.50 STS.L FPSCR, @-Rn {:5.51 - COUNT_INST(I_STSM);5.52 + COUNT_INST(I_STSFPSCRM);5.53 check_fpuen();5.54 load_reg( R_EAX, Rn );5.55 check_walign32( R_EAX );
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