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lxdream.org :: lxdream :: r125:49bf45f8210a
lxdream 0.9.1
released Jun 29
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changeset125:49bf45f8210a
parent124:ceb38f08619a
child126:988003554ab5
authornkeynes
dateWed Mar 22 14:29:02 2006 +0000 (14 years ago)
Rename IDE DMA registers appropriately
Remove forced irq hack
Add correct irq handling for IDE
Miscellaneous WIP for the GD-rom drive
src/asic.c
src/asic.h
src/gdrom/gdrom.h
src/gdrom/ide.c
src/gdrom/ide.h
1.1 --- a/src/asic.c Wed Mar 22 14:27:40 2006 +0000
1.2 +++ b/src/asic.c Wed Mar 22 14:29:02 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.c,v 1.12 2006-02-15 13:11:42 nkeynes Exp $
1.6 + * $Id: asic.c,v 1.13 2006-03-22 14:29:00 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA).
1.10 @@ -50,14 +50,15 @@
1.11 register_io_region( &mmio_region_ASIC );
1.12 register_io_region( &mmio_region_EXTDMA );
1.13 mmio_region_ASIC.trace_flag = 0; /* Because this is called so often */
1.14 - asic_event( EVENT_GDROM_CMD );
1.15 }
1.16
1.17 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
1.18 {
1.19 switch( reg ) {
1.20 + case PIRQ1:
1.21 + val = val & 0xFFFFFFFE; /* Prevent the IDE event from clearing */
1.22 + /* fallthrough */
1.23 case PIRQ0:
1.24 - case PIRQ1:
1.25 case PIRQ2:
1.26 /* Clear any interrupts */
1.27 MMIO_WRITE( ASIC, reg, MMIO_READ(ASIC, reg)&~val );
1.28 @@ -143,6 +144,14 @@
1.29 intc_raise_interrupt( INT_IRQ9 );
1.30 }
1.31
1.32 +void asic_clear_event( int event ) {
1.33 + int offset = ((event&0x60)>>3);
1.34 + uint32_t result = MMIO_READ(ASIC, PIRQ0 + offset) & (~(1<<(event&0x1F)));
1.35 + MMIO_WRITE( ASIC, PIRQ0 + offset, result );
1.36 +
1.37 + asic_check_cleared_events();
1.38 +}
1.39 +
1.40 void asic_check_cleared_events( )
1.41 {
1.42 int i, setA = 0, setB = 0, setC = 0;
1.43 @@ -164,46 +173,55 @@
1.44
1.45 MMIO_REGION_WRITE_FN( EXTDMA, reg, val )
1.46 {
1.47 + WARN( "EXTDMA write %08X <= %08X", reg, val );
1.48 +
1.49 switch( reg ) {
1.50 - case IDEALTSTATUS: /* Device control */
1.51 - ide_write_control( val );
1.52 - break;
1.53 - case IDEDATA:
1.54 - ide_write_data_pio( val );
1.55 - break;
1.56 - case IDEFEAT:
1.57 - if( ide_can_write_regs() )
1.58 - idereg.feature = (uint8_t)val;
1.59 - break;
1.60 - case IDECOUNT:
1.61 - if( ide_can_write_regs() )
1.62 - idereg.count = (uint8_t)val;
1.63 - break;
1.64 - case IDELBA0:
1.65 - if( ide_can_write_regs() )
1.66 - idereg.lba0 = (uint8_t)val;
1.67 - break;
1.68 - case IDELBA1:
1.69 - if( ide_can_write_regs() )
1.70 - idereg.lba1 = (uint8_t)val;
1.71 - break;
1.72 - case IDELBA2:
1.73 - if( ide_can_write_regs() )
1.74 - idereg.lba2 = (uint8_t)val;
1.75 - break;
1.76 - case IDEDEV:
1.77 - if( ide_can_write_regs() )
1.78 - idereg.device = (uint8_t)val;
1.79 - break;
1.80 - case IDECMD:
1.81 - if( ide_can_write_regs() ) {
1.82 - ide_clear_interrupt();
1.83 - ide_write_command( (uint8_t)val );
1.84 - }
1.85 - break;
1.86 - default:
1.87 - WARN( "EXTDMA write %08X <= %08X", reg, val );
1.88 -
1.89 + case IDEALTSTATUS: /* Device control */
1.90 + ide_write_control( val );
1.91 + break;
1.92 + case IDEDATA:
1.93 + ide_write_data_pio( val );
1.94 + break;
1.95 + case IDEFEAT:
1.96 + if( ide_can_write_regs() )
1.97 + idereg.feature = (uint8_t)val;
1.98 + break;
1.99 + case IDECOUNT:
1.100 + if( ide_can_write_regs() )
1.101 + idereg.count = (uint8_t)val;
1.102 + break;
1.103 + case IDELBA0:
1.104 + if( ide_can_write_regs() )
1.105 + idereg.lba0 = (uint8_t)val;
1.106 + break;
1.107 + case IDELBA1:
1.108 + if( ide_can_write_regs() )
1.109 + idereg.lba1 = (uint8_t)val;
1.110 + break;
1.111 + case IDELBA2:
1.112 + if( ide_can_write_regs() )
1.113 + idereg.lba2 = (uint8_t)val;
1.114 + break;
1.115 + case IDEDEV:
1.116 + if( ide_can_write_regs() )
1.117 + idereg.device = (uint8_t)val;
1.118 + break;
1.119 + case IDECMD:
1.120 + if( ide_can_write_regs() ) {
1.121 + ide_write_command( (uint8_t)val );
1.122 + }
1.123 + break;
1.124 + case IDEDMACTL1:
1.125 + case IDEDMACTL2:
1.126 + MMIO_WRITE( EXTDMA, reg, val );
1.127 + if( MMIO_READ( EXTDMA, IDEDMACTL1 ) == 1 &&
1.128 + MMIO_READ( EXTDMA, IDEDMACTL2 ) == 1 ) {
1.129 + uint32_t target_addr = MMIO_READ( EXTDMA, IDEDMASH4 );
1.130 + uint32_t length = MMIO_READ( EXTDMA, IDEDMASIZ );
1.131 + int dir = MMIO_READ( EXTDMA, IDEDMADIR );
1.132 + }
1.133 + break;
1.134 + default:
1.135 MMIO_WRITE( EXTDMA, reg, val );
1.136 }
1.137 }
1.138 @@ -221,8 +239,7 @@
1.139 case IDELBA2: return idereg.lba2;
1.140 case IDEDEV: return idereg.device;
1.141 case IDECMD:
1.142 - ide_clear_interrupt();
1.143 - return idereg.status;
1.144 + return ide_read_status();
1.145 default:
1.146 val = MMIO_READ( EXTDMA, reg );
1.147 //DEBUG( "EXTDMA read %08X => %08X", reg, val );
2.1 --- a/src/asic.h Wed Mar 22 14:27:40 2006 +0000
2.2 +++ b/src/asic.h Wed Mar 22 14:29:02 2006 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: asic.h,v 1.5 2006-01-03 12:21:45 nkeynes Exp $
2.6 + * $Id: asic.h,v 1.6 2006-03-22 14:29:00 nkeynes Exp $
2.7 *
2.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
2.9 * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions,
2.10 @@ -94,11 +94,11 @@
2.11 BYTE_PORT( 0x094, IDELBA2, PORT_RW, 0, "IDE LBA hi" ) /* AKA Cyl hi */
2.12 BYTE_PORT( 0x098, IDEDEV, PORT_RW, 0, "IDE Device" )
2.13 BYTE_PORT( 0x09C, IDECMD, PORT_RW, 0, "IDE Command/Status" )
2.14 - LONG_PORT( 0x404, EXTDMASH4, PORT_MRW, 0, "Ext DMA SH4 address" )
2.15 - LONG_PORT( 0x408, EXTDMASIZ, PORT_MRW, 0, "Ext DMA Size" )
2.16 - LONG_PORT( 0x40C, EXTDMADIR, PORT_MRW, 0, "Ext DMA Direction" )
2.17 - LONG_PORT( 0x414, EXTDMACTL1, PORT_MRW, 0, "Ext DMA Control 1" )
2.18 - LONG_PORT( 0x418, EXTDMACTL2, PORT_MRW, 0, "Ext DMA Control 2" )
2.19 + LONG_PORT( 0x404, IDEDMASH4, PORT_MRW, 0, "IDE DMA SH4 address" )
2.20 + LONG_PORT( 0x408, IDEDMASIZ, PORT_MRW, 0, "IDE DMA Size" )
2.21 + LONG_PORT( 0x40C, IDEDMADIR, PORT_MRW, 0, "IDE DMA Direction" )
2.22 + LONG_PORT( 0x414, IDEDMACTL1, PORT_MRW, 0, "IDE DMA Control 1" )
2.23 + LONG_PORT( 0x418, IDEDMACTL2, PORT_MRW, 0, "IDE DMA Control 2" )
2.24 WORD_PORT( 0x480, EXTDMAUNK0, PORT_MRW, 0, "Ext DMA <unknown0>" )
2.25 LONG_PORT( 0x484, EXTDMAUNK1, PORT_MRW, 0, "Ext DMA <unknown1>" )
2.26 LONG_PORT( 0x488, EXTDMAUNK2, PORT_MRW, 0, "Ext DMA <unknown2>" )
2.27 @@ -176,7 +176,7 @@
2.28 #define EVENT_PVR_TRANSMOD_DONE 10
2.29 #define EVENT_MAPLE_DMA 12
2.30 #define EVENT_MAPLE_ERR 13 /* ??? */
2.31 -#define EVENT_GDROM_DMA 14
2.32 +#define EVENT_IDE_DMA 14
2.33 #define EVENT_SPU_DMA0 15
2.34 #define EVENT_SPU_DMA1 16
2.35 #define EVENT_SPU_DMA2 17
2.36 @@ -184,8 +184,18 @@
2.37 #define EVENT_PVR_DMA 19
2.38 #define EVENT_PVR_PUNCHOUT_DONE 21
2.39
2.40 -#define EVENT_GDROM_CMD 32
2.41 +#define EVENT_IDE 32
2.42 #define EVENT_AICA 33
2.43
2.44 +/**
2.45 + * Raise an ASIC event
2.46 + */
2.47 void asic_event( int event );
2.48 +
2.49 +/**
2.50 + * Clear an ASIC event. Currently only the IDE controller is known to use
2.51 + * this functionality.
2.52 + */
2.53 +void asic_clear_event( int event );
2.54 +
2.55 void asic_init( void );
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
3.2 +++ b/src/gdrom/gdrom.h Wed Mar 22 14:29:02 2006 +0000
3.3 @@ -0,0 +1,44 @@
3.4 +/**
3.5 + * $Id: gdrom.h,v 1.1 2006-03-22 14:29:02 nkeynes Exp $
3.6 + *
3.7 + * This file defines the structures and functions used by the GD-Rom
3.8 + * disc driver. (ie, the modules that supply a CD image to be used by the
3.9 + * system).
3.10 + *
3.11 + * Copyright (c) 2005 Nathan Keynes.
3.12 + *
3.13 + * This program is free software; you can redistribute it and/or modify
3.14 + * it under the terms of the GNU General Public License as published by
3.15 + * the Free Software Foundation; either version 2 of the License, or
3.16 + * (at your option) any later version.
3.17 + *
3.18 + * This program is distributed in the hope that it will be useful,
3.19 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3.20 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3.21 + * GNU General Public License for more details.
3.22 + */
3.23 +
3.24 +#ifndef dream_gdrom_H
3.25 +#define dream_gdrom_H 1
3.26 +
3.27 +#include "dream.h"
3.28 +
3.29 +typedef struct gdrom_toc {
3.30 + uint32_t tracks[99];
3.31 + uint32_t first, last, leadout;
3.32 +} *gdrom_toc_t;
3.33 +
3.34 +
3.35 +typedef struct gdrom_disc {
3.36 +
3.37 + gboolean (*read_toc)( gdrom_toc_t toc );
3.38 +
3.39 + gboolean (*read_data_sectors)( uint32_t lba, uint32_t sector_count,
3.40 + char *buf );
3.41 +} *gdrom_disc_t;
3.42 +
3.43 +void gdrom_mount( gdrom_disc_t disc );
3.44 +
3.45 +void gdrom_unmount( void );
3.46 +
3.47 +#endif
4.1 --- a/src/gdrom/ide.c Wed Mar 22 14:27:40 2006 +0000
4.2 +++ b/src/gdrom/ide.c Wed Mar 22 14:29:02 2006 +0000
4.3 @@ -1,5 +1,5 @@
4.4 /**
4.5 - * $Id: ide.c,v 1.7 2005-12-27 12:41:33 nkeynes Exp $
4.6 + * $Id: ide.c,v 1.8 2006-03-22 14:29:02 nkeynes Exp $
4.7 *
4.8 * IDE interface implementation
4.9 *
4.10 @@ -20,7 +20,9 @@
4.11
4.12 #include <stdlib.h>
4.13 #include "dream.h"
4.14 +#include "asic.h"
4.15 #include "gdrom/ide.h"
4.16 +#include "gdrom/gdrom.h"
4.17
4.18 #define MAX_WRITE_BUF 4096;
4.19
4.20 @@ -32,16 +34,18 @@
4.21
4.22 struct ide_registers idereg;
4.23
4.24 -static char command_buffer[12];
4.25 +static unsigned char command_buffer[12];
4.26
4.27 /* "\0\0\0\0\xb4\x19\0\0\x08SE REV 6.42990316" */
4.28 -char gdrom_ident[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x19, 0x00,
4.29 +unsigned char gdrom_ident[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x19, 0x00,
4.30 0x00, 0x08, 0x53, 0x45, 0x20, 0x20, 0x20, 0x20,
4.31 0x20, 0x20, 0x52, 0x65, 0x76, 0x20, 0x36, 0x2e,
4.32 0x34, 0x32, 0x39, 0x39, 0x30, 0x33, 0x31, 0x36 };
4.33
4.34
4.35 -void set_write_buffer( char *buf, int len )
4.36 +gdrom_disc_t gdrom_disc = NULL;
4.37 +
4.38 +static void ide_set_write_buffer( unsigned char *buf, int len )
4.39 {
4.40 idereg.status |= IDE_ST_DATA;
4.41 idereg.data = buf;
4.42 @@ -50,7 +54,7 @@
4.43 idereg.readptr = NULL;
4.44 }
4.45
4.46 -void set_read_buffer( char *buf, int len )
4.47 +static void ide_set_read_buffer( unsigned char *buf, int len, int blocksize )
4.48 {
4.49 idereg.status |= IDE_ST_DATA;
4.50 idereg.data = buf;
4.51 @@ -59,11 +63,31 @@
4.52 idereg.writeptr = NULL;
4.53 idereg.lba1 = len&0xFF;
4.54 idereg.lba2 = len>>8;
4.55 + idereg.blocksize = idereg.blockleft = blocksize;
4.56 }
4.57
4.58 -void ide_clear_interrupt( void )
4.59 +static void ide_raise_interrupt( void )
4.60 {
4.61 - /* TODO */
4.62 + if( idereg.intrq_pending == 0 ) {
4.63 + idereg.intrq_pending = 1;
4.64 + if( IS_IDE_IRQ_ENABLED() )
4.65 + asic_event( EVENT_IDE );
4.66 + }
4.67 +}
4.68 +
4.69 +static void ide_clear_interrupt( void )
4.70 +{
4.71 + if( idereg.intrq_pending != 0 ) {
4.72 + idereg.intrq_pending = 0;
4.73 + if( IS_IDE_IRQ_ENABLED() )
4.74 + asic_clear_event( EVENT_IDE );
4.75 + }
4.76 +}
4.77 +
4.78 +static void ide_set_error( int error_code )
4.79 +{
4.80 + idereg.status = 0x51;
4.81 + idereg.error = error_code;
4.82 }
4.83
4.84 void ide_init( void )
4.85 @@ -76,13 +100,20 @@
4.86 ide_clear_interrupt();
4.87 idereg.error = 0x01;
4.88 idereg.count = 0x01;
4.89 - idereg.lba0 = 0x21;
4.90 + idereg.lba0 = /* 0x21; */ 0x81;
4.91 idereg.lba1 = 0x14;
4.92 idereg.lba2 = 0xeb;
4.93 idereg.feature = 0; /* Indeterminate really */
4.94 idereg.status = 0x00;
4.95 idereg.device = 0x00;
4.96 - idereg.disc = IDE_DISC_GDROM | IDE_DISC_READY;
4.97 + idereg.disc = (gdrom_disc == NULL ? IDE_DISC_NONE : (IDE_DISC_CDROM|IDE_DISC_READY));
4.98 +}
4.99 +
4.100 +uint8_t ide_read_status( void )
4.101 +{
4.102 + if( (idereg.status & IDE_ST_BUSY) == 0 )
4.103 + ide_clear_interrupt();
4.104 + return idereg.status;
4.105 }
4.106
4.107 uint16_t ide_read_data_pio( void ) {
4.108 @@ -90,9 +121,13 @@
4.109 return 0xFFFF;
4.110 uint16_t rv = *idereg.readptr++;
4.111 idereg.datalen-=2;
4.112 + idereg.blockleft-=2;
4.113 if( idereg.datalen <=0 ) {
4.114 idereg.readptr = NULL;
4.115 idereg.status &= ~IDE_ST_DATA;
4.116 + } else if( idereg.blockleft <= 0 ) {
4.117 + ide_raise_interrupt();
4.118 + idereg.blockleft = idereg.blocksize;
4.119 }
4.120 return rv;
4.121 }
4.122 @@ -103,26 +138,33 @@
4.123 *idereg.writeptr++ = val;
4.124 idereg.datalen-=2;
4.125 if( idereg.datalen <= 0 ) {
4.126 + int len = ((unsigned char *)idereg.writeptr) - idereg.data;
4.127 idereg.writeptr = NULL;
4.128 idereg.status &= ~IDE_ST_DATA;
4.129 - ide_write_buffer( idereg.data );
4.130 + ide_write_buffer( idereg.data, len );
4.131 }
4.132 }
4.133
4.134 void ide_write_control( uint8_t val ) {
4.135 - /* TODO: In theory we can cause a soft-reset here, but the DC doesn't
4.136 - * appear to support it.
4.137 - */
4.138 + if( IS_IDE_IRQ_ENABLED() ) {
4.139 + if( (val & 0x02) != 0 && idereg.intrq_pending != 0 )
4.140 + asic_clear_event( EVENT_IDE );
4.141 + } else {
4.142 + if( (val & 0x02) == 0 && idereg.intrq_pending != 0 )
4.143 + asic_event( EVENT_IDE );
4.144 + }
4.145 + idereg.control = val;
4.146 }
4.147
4.148 void ide_write_command( uint8_t val ) {
4.149 + ide_clear_interrupt();
4.150 idereg.command = val;
4.151 switch( val ) {
4.152 case IDE_CMD_RESET_DEVICE:
4.153 ide_reset();
4.154 break;
4.155 case IDE_CMD_PACKET:
4.156 - set_write_buffer(command_buffer,12);
4.157 + ide_set_write_buffer(command_buffer,12);
4.158 break;
4.159 case IDE_CMD_SET_FEATURE:
4.160 switch( idereg.feature ) {
4.161 @@ -148,6 +190,7 @@
4.162 default:
4.163 WARN( "IDE: unimplemented feature: %02X", idereg.feature );
4.164 }
4.165 + ide_raise_interrupt( );
4.166 break;
4.167 default:
4.168 WARN( "IDE: Unimplemented command: %02X", val );
4.169 @@ -155,24 +198,65 @@
4.170 idereg.status |= IDE_ST_READY | IDE_ST_SERV;
4.171 }
4.172
4.173 -void ide_write_buffer( char *data ) {
4.174 - uint16_t length;
4.175 +void ide_packet_command( unsigned char *cmd )
4.176 +{
4.177 + uint32_t length;
4.178 + uint32_t lba;
4.179 + int blocksize = idereg.lba1 + (idereg.lba2<<8);
4.180 +
4.181 + ide_raise_interrupt( );
4.182 + /* Okay we have the packet in the command buffer */
4.183 + WARN( "ATAPI: Received Packet command: %02X", cmd[0] );
4.184 + fwrite_dump( (unsigned char *)cmd, 12, stderr );
4.185 + switch( cmd[0] ) {
4.186 + case PKT_CMD_IDENTIFY:
4.187 + /* NB: Bios sets cmd[4] = 0x08, no idea what this is for;
4.188 + * different values here appear to have no effect.
4.189 + */
4.190 + length = *((uint16_t*)(cmd+2));
4.191 + if( length > sizeof(gdrom_ident) )
4.192 + length = sizeof(gdrom_ident);
4.193 + ide_set_read_buffer(gdrom_ident, length, blocksize);
4.194 + break;
4.195 + case PKT_CMD_READ_TOC:
4.196 +
4.197 + break;
4.198 + case PKT_CMD_READ_SECTOR:
4.199 + lba = cmd[2] << 16 | cmd[3] << 8 | cmd[4];
4.200 + length = cmd[8] << 16 | cmd[9] << 8 | cmd[10]; /* blocks */
4.201 + if( gdrom_disc == NULL ) {
4.202 + ide_set_error( 0x50 );
4.203 + return;
4.204 + }
4.205 + /*
4.206 + if( gdrom_disc->read_data_sectors( lba, length ) == FALSE ) {
4.207 + ide_set_error( 0x50 );
4.208 + return;
4.209 + }
4.210 +
4.211 + */
4.212 + break;
4.213 + }
4.214 +}
4.215 +
4.216 +void ide_write_buffer( unsigned char *data, int datalen ) {
4.217 switch( idereg.command ) {
4.218 case IDE_CMD_PACKET:
4.219 - /* Okay we have the packet in the command buffer */
4.220 - WARN( "ATAPI: Received Packet command: %02X", data[0] );
4.221 -
4.222 - switch( command_buffer[0] ) {
4.223 - case PKT_CMD_IDENTIFY:
4.224 - /* NB: Bios sets data[4] = 0x08, no idea what this is for;
4.225 - * different values here appear to have no effect.
4.226 - */
4.227 - length = *((uint16_t*)(data+2));
4.228 - if( length > sizeof(gdrom_ident) )
4.229 - length = sizeof(gdrom_ident);
4.230 - set_read_buffer(gdrom_ident, length);
4.231 - break;
4.232 - }
4.233 + ide_packet_command( data );
4.234 break;
4.235 }
4.236 }
4.237 +
4.238 +/**
4.239 + * DMA read request
4.240 + *
4.241 + * This method is called from the ASIC side when a DMA read request is
4.242 + * initiated. If there is a pending DMA transfer already, we copy the
4.243 + * data immediately, otherwise we record the DMA buffer for use when we
4.244 + * get to actually doing the transfer.
4.245 + */
4.246 +void ide_dma_read_req( uint32_t addr, uint32_t length )
4.247 +{
4.248 +
4.249 +
4.250 +}
5.1 --- a/src/gdrom/ide.h Wed Mar 22 14:27:40 2006 +0000
5.2 +++ b/src/gdrom/ide.h Wed Mar 22 14:29:02 2006 +0000
5.3 @@ -1,5 +1,5 @@
5.4 /**
5.5 - * $Id: ide.h,v 1.3 2005-12-27 12:41:33 nkeynes Exp $
5.6 + * $Id: ide.h,v 1.4 2006-03-22 14:29:02 nkeynes Exp $
5.7 *
5.8 * This file defines the interface and structures of the dreamcast's IDE
5.9 * port. Note that the register definitions are in asic.h, as the registers
5.10 @@ -37,15 +37,18 @@
5.11 uint8_t lba2; /* A05F7094 Read/Write 10101 */
5.12 uint8_t device; /* A05F7098 Read/Write 10110 */
5.13 uint8_t command; /* A05F709C Write-only 10111 */
5.14 -
5.15 +
5.16 /* We don't keep the data register per se, rather the currently pending
5.17 * data is kept here and read out a byte at a time (in PIO mode) or all at
5.18 * once (in DMA mode). The IDE routines are responsible for managing this
5.19 * memory. If dataptr == NULL, there is no data available.
5.20 */
5.21 - char *data;
5.22 + unsigned char *data;
5.23 uint16_t *readptr, *writeptr;
5.24 int datalen;
5.25 + int blocksize; /* Used to determine the transfer unit size */
5.26 + int blockleft; /* Bytes remaining in the current block */
5.27 + uint8_t intrq_pending; /* Flag to indicate if the INTRQ line is active */
5.28 };
5.29
5.30 #define IDE_ST_BUSY 0x80
5.31 @@ -82,6 +85,9 @@
5.32
5.33 #define PKT_CMD_RESET 0x00 /* Wild-ass guess */
5.34 #define PKT_CMD_IDENTIFY 0x11
5.35 +#define PKT_CMD_SENSE 0x13
5.36 +#define PKT_CMD_READ_TOC 0x14
5.37 +#define PKT_CMD_READ_SECTOR 0x30
5.38
5.39 extern struct ide_registers idereg;
5.40
5.41 @@ -89,19 +95,14 @@
5.42 * only when ide_can_write_regs() is true
5.43 */
5.44 #define ide_can_write_regs() ((idereg.status&0x88)==0)
5.45 -
5.46 -/* Called upon:
5.47 - * a) Writing the command register
5.48 - * b) Reading the status (but not altstatus) register
5.49 - * (whether this actually has any effect an the ASIC event is TBD)
5.50 - */
5.51 -void ide_clear_interrupt(void);
5.52 +#define IS_IDE_IRQ_ENABLED() ((idereg.control&0x02)==0)
5.53
5.54 void ide_reset(void);
5.55
5.56 uint16_t ide_read_data_pio(void);
5.57 +uint8_t ide_read_status(void);
5.58 void ide_write_data_pio( uint16_t value );
5.59 -void ide_write_buffer( char * );
5.60 +void ide_write_buffer( unsigned char *data, int length );
5.61
5.62 void ide_write_command( uint8_t command );
5.63 void ide_write_control( uint8_t value );
.