Search
lxdream.org :: lxdream :: r369:4b4223e7d720
lxdream 0.9.1
released Jun 29
Download Now
changeset369:4b4223e7d720
parent368:36fac4c42322
child370:3131ba1440fc
authornkeynes
dateSat Sep 08 03:12:21 2007 +0000 (12 years ago)
Move the store queue operation to a function in sh4mem.c
src/sh4/sh4core.c
src/sh4/sh4core.h
src/sh4/sh4core.in
src/sh4/sh4mem.c
src/test/testsh4x86.c
1.1 --- a/src/sh4/sh4core.c Tue Sep 04 08:40:23 2007 +0000
1.2 +++ b/src/sh4/sh4core.c Sat Sep 08 03:12:21 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4core.c,v 1.42 2007-09-04 08:38:33 nkeynes Exp $
1.6 + * $Id: sh4core.c,v 1.43 2007-09-08 03:11:53 nkeynes Exp $
1.7 *
1.8 * SH4 emulation core, and parent module for all the SH4 peripheral
1.9 * modules.
1.10 @@ -540,12 +540,7 @@
1.11 uint32_t Rn = ((ir>>8)&0xF);
1.12 tmp = sh4r.r[Rn];
1.13 if( (tmp & 0xFC000000) == 0xE0000000 ) {
1.14 - /* Store queue operation */
1.15 - int queue = (tmp&0x20)>>2;
1.16 - int32_t *src = &sh4r.store_queue[queue];
1.17 - uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
1.18 - uint32_t target = tmp&0x03FFFFE0 | hi;
1.19 - mem_copy_to_sh4( target, src, 32 );
1.20 + sh4_flush_store_queue(tmp);
1.21 }
1.22 }
1.23 break;
2.1 --- a/src/sh4/sh4core.h Tue Sep 04 08:40:23 2007 +0000
2.2 +++ b/src/sh4/sh4core.h Sat Sep 08 03:12:21 2007 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: sh4core.h,v 1.20 2007-09-04 08:38:33 nkeynes Exp $
2.6 + * $Id: sh4core.h,v 1.21 2007-09-08 03:12:21 nkeynes Exp $
2.7 *
2.8 * This file defines the internal functions exported/used by the SH4 core,
2.9 * except for disassembly functions defined in sh4dasm.h
2.10 @@ -109,6 +109,7 @@
2.11 void sh4_write_word( uint32_t addr, uint32_t val );
2.12 void sh4_write_byte( uint32_t addr, uint32_t val );
2.13 int32_t sh4_read_phys_word( uint32_t addr );
2.14 +void sh4_flush_store_queue( uint32_t addr );
2.15
2.16 /* Peripheral functions */
2.17 void CPG_reset( void );
3.1 --- a/src/sh4/sh4core.in Tue Sep 04 08:40:23 2007 +0000
3.2 +++ b/src/sh4/sh4core.in Sat Sep 08 03:12:21 2007 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: sh4core.in,v 1.2 2007-09-04 08:38:33 nkeynes Exp $
3.6 + * $Id: sh4core.in,v 1.3 2007-09-08 03:12:21 nkeynes Exp $
3.7 *
3.8 * SH4 emulation core, and parent module for all the SH4 peripheral
3.9 * modules.
3.10 @@ -546,12 +546,7 @@
3.11 PREF @Rn {:
3.12 tmp = sh4r.r[Rn];
3.13 if( (tmp & 0xFC000000) == 0xE0000000 ) {
3.14 - /* Store queue operation */
3.15 - int queue = (tmp&0x20)>>2;
3.16 - int32_t *src = &sh4r.store_queue[queue];
3.17 - uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
3.18 - uint32_t target = tmp&0x03FFFFE0 | hi;
3.19 - mem_copy_to_sh4( target, src, 32 );
3.20 + sh4_flush_store_queue(tmp);
3.21 }
3.22 :}
3.23 OCBI @Rn {: :}
4.1 --- a/src/sh4/sh4mem.c Tue Sep 04 08:40:23 2007 +0000
4.2 +++ b/src/sh4/sh4mem.c Sat Sep 08 03:12:21 2007 +0000
4.3 @@ -1,5 +1,5 @@
4.4 /**
4.5 - * $Id: sh4mem.c,v 1.20 2007-02-11 10:17:03 nkeynes Exp $
4.6 + * $Id: sh4mem.c,v 1.21 2007-09-08 03:11:53 nkeynes Exp $
4.7 * sh4mem.c is responsible for the SH4's access to memory (including memory
4.8 * mapped I/O), using the page maps created in mem.c
4.9 *
4.10 @@ -389,3 +389,13 @@
4.11 memcpy( dest, src, count );
4.12 }
4.13 }
4.14 +
4.15 +void sh4_flush_store_queue( uint32_t addr )
4.16 +{
4.17 + /* Store queue operation */
4.18 + int queue = (addr&0x20)>>2;
4.19 + int32_t *src = &sh4r.store_queue[queue];
4.20 + uint32_t hi = (MMIO_READ( MMU, (queue == 0 ? QACR0 : QACR1) ) & 0x1C) << 24;
4.21 + uint32_t target = addr&0x03FFFFE0 | hi;
4.22 + mem_copy_to_sh4( target, src, 32 );
4.23 +}
5.1 --- a/src/test/testsh4x86.c Tue Sep 04 08:40:23 2007 +0000
5.2 +++ b/src/test/testsh4x86.c Sat Sep 08 03:12:21 2007 +0000
5.3 @@ -1,5 +1,5 @@
5.4 /**
5.5 - * $Id: testsh4x86.c,v 1.2 2007-09-04 08:32:10 nkeynes Exp $
5.6 + * $Id: testsh4x86.c,v 1.3 2007-09-08 03:11:53 nkeynes Exp $
5.7 *
5.8 * Test cases for the SH4 => x86 translator core. Takes as
5.9 * input a binary SH4 object (and VMA), generates the
5.10 @@ -73,6 +73,7 @@
5.11 void sh4_write_byte( uint32_t addr, uint32_t val ) {}
5.12 void sh4_write_word( uint32_t addr, uint32_t val ) {}
5.13 void sh4_write_long( uint32_t addr, uint32_t val ) {}
5.14 +void sh4_flush_store_queue( uint32_t addr ) {}
5.15 gboolean sh4_raise_exception( int exc ) {}
5.16
5.17 void usage()
.