1.1 --- a/src/lxdream.h	Wed Oct 29 23:36:31 2008 +0000
     1.2 +++ b/src/lxdream.h	Wed Oct 29 23:51:58 2008 +0000
     1.3 @@ -91,6 +91,17 @@
     1.4  const char *get_sysconf_path();
     1.5  const char *get_locale_path();
     1.6  
     1.7 +/* Use fast (regparam) calling conventions for core code - for now just turn it
     1.8 + * on always, but define the macro in case we need to remove it for some platforms
     1.9 + */
    1.10 +#define HAVE_FASTCALL 1
    1.11 +
    1.12 +#ifdef HAVE_FASTCALL
    1.13 +#define FASTCALL __attribute__((regparm(3)))
    1.14 +#else
    1.15 +#define FASTCALL
    1.16 +#endif
    1.17 +
    1.18  #ifdef __cplusplus
    1.19  }
    1.20  #endif

     2.1 --- a/src/sh4/ia32abi.h	Wed Oct 29 23:36:31 2008 +0000
     2.2 +++ b/src/sh4/ia32abi.h	Wed Oct 29 23:51:58 2008 +0000
     2.3 @@ -26,14 +26,68 @@
     2.4   * Note: clobbers EAX to make the indirect call - this isn't usually
     2.5   * a problem since the callee will usually clobber it anyway.
     2.6   */
     2.7 -#define CALL_FUNC0_SIZE 7
     2.8  static inline void call_func0( void *ptr )
     2.9  {
    2.10      load_imm32(R_EAX, (uint32_t)ptr);
    2.11      CALL_r32(R_EAX);
    2.12  }
    2.13  
    2.14 -#define CALL_FUNC1_SIZE 11
    2.15 +#ifdef HAVE_FASTCALL
    2.16 +static inline void call_func1( void *ptr, int arg1 )
    2.17 +{
    2.18 +    if( arg1 != R_EAX ) {
    2.19 +        MOV_r32_r32( arg1, R_EAX );
    2.20 +    }
    2.21 +    load_imm32(R_ECX, (uint32_t)ptr);
    2.22 +    CALL_r32(R_ECX);
    2.23 +}
    2.24 +
    2.25 +static inline void call_func2( void *ptr, int arg1, int arg2 )
    2.26 +{
    2.27 +    if( arg2 != R_EDX ) {
    2.28 +        MOV_r32_r32( arg2, R_EDX );
    2.29 +    }
    2.30 +    if( arg1 != R_EAX ) {
    2.31 +        MOV_r32_r32( arg1, R_EAX );
    2.32 +    }
    2.33 +    load_imm32(R_ECX, (uint32_t)ptr);
    2.34 +    CALL_r32(R_ECX);
    2.35 +}
    2.36 +
    2.37 +/**
    2.38 + * Write a double (64-bit) value into memory, with the first word in arg2a, and
    2.39 + * the second in arg2b
    2.40 + */
    2.41 +static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
    2.42 +{
    2.43 +    PUSH_r32(arg2b);
    2.44 +    PUSH_r32(addr);
    2.45 +    call_func2(sh4_write_long, addr, arg2a);
    2.46 +    POP_r32(R_EAX);
    2.47 +    POP_r32(R_EDX);
    2.48 +    ADD_imm8s_r32(4, R_EAX);
    2.49 +    call_func0(sh4_write_long);
    2.50 +}
    2.51 +
    2.52 +/**
    2.53 + * Read a double (64-bit) value from memory, writing the first word into arg2a
    2.54 + * and the second into arg2b. The addr must not be in EAX
    2.55 + */
    2.56 +static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
    2.57 +{
    2.58 +    PUSH_r32(addr);
    2.59 +    call_func1(sh4_read_long, addr);
    2.60 +    POP_r32(R_ECX);
    2.61 +    PUSH_r32(R_EAX);
    2.62 +    MOV_r32_r32(R_ECX, R_EAX);
    2.63 +    ADD_imm8s_r32(4, R_EAX);
    2.64 +    call_func0(sh4_read_long);
    2.65 +    if( arg2b != R_EAX ) {
    2.66 +        MOV_r32_r32(R_EAX, arg2b);
    2.67 +    }
    2.68 +    POP_r32(arg2a);
    2.69 +}
    2.70 +#else
    2.71  static inline void call_func1( void *ptr, int arg1 )
    2.72  {
    2.73      PUSH_r32(arg1);
    2.74 @@ -41,7 +95,6 @@
    2.75      ADD_imm8s_r32( 4, R_ESP );
    2.76  }
    2.77  
    2.78 -#define CALL_FUNC2_SIZE 12
    2.79  static inline void call_func2( void *ptr, int arg1, int arg2 )
    2.80  {
    2.81      PUSH_r32(arg2);
    2.82 @@ -53,9 +106,7 @@
    2.83  /**
    2.84   * Write a double (64-bit) value into memory, with the first word in arg2a, and
    2.85   * the second in arg2b
    2.86 - * NB: 30 bytes
    2.87   */
    2.88 -#define MEM_WRITE_DOUBLE_SIZE 30
    2.89  static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
    2.90  {
    2.91      ADD_imm8s_r32( 4, addr );
    2.92 @@ -73,9 +124,7 @@
    2.93  /**
    2.94   * Read a double (64-bit) value from memory, writing the first word into arg2a
    2.95   * and the second into arg2b. The addr must not be in EAX
    2.96 - * NB: 27 bytes
    2.97   */
    2.98 -#define MEM_READ_DOUBLE_SIZE 27
    2.99  static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
   2.100  {
   2.101      PUSH_r32(addr);
   2.102 @@ -89,6 +138,7 @@
   2.103      MOV_r32_r32( R_EAX, arg2b );
   2.104      POP_r32(arg2a);
   2.105  }
   2.106 +#endif
   2.107  
   2.108  /**
   2.109   * Emit the 'start of block' assembly. Sets up the stack frame and save

     3.1 --- a/src/sh4/ia32mac.h	Wed Oct 29 23:36:31 2008 +0000
     3.2 +++ b/src/sh4/ia32mac.h	Wed Oct 29 23:51:58 2008 +0000
     3.3 @@ -32,12 +32,73 @@
     3.4  {
     3.5      int adj = (-sh4_x86.stack_posn)&0x0F;
     3.6      SUB_imm8s_r32( adj, R_ESP );
     3.7 -    load_imm32(R_EAX, (uint32_t)ptr);
     3.8 -    CALL_r32(R_EAX);
     3.9 +    load_imm32(R_ECX, (uint32_t)ptr);
    3.10 +    CALL_r32(R_ECX);
    3.11      ADD_imm8s_r32( adj, R_ESP );
    3.12  }
    3.13  
    3.14 -#define CALL_FUNC1_SIZE 14
    3.15 +#ifdef HAVE_FASTCALL
    3.16 +static inline void call_func1( void *ptr, int arg1 )
    3.17 +{
    3.18 +    int adj = (-sh4_x86.stack_posn)&0x0F;
    3.19 +    SUB_imm8s_r32( adj, R_ESP );
    3.20 +    if( arg1 != R_EAX ) {
    3.21 +        MOV_r32_r32( arg1, R_EAX );
    3.22 +    }
    3.23 +    load_imm32(R_ECX, (uint32_t)ptr);
    3.24 +    CALL_r32(R_ECX);
    3.25 +    ADD_imm8s_r32( adj, R_ESP );
    3.26 +}
    3.27 +
    3.28 +static inline void call_func2( void *ptr, int arg1, int arg2 )
    3.29 +{
    3.30 +    int adj = (-sh4_x86.stack_posn)&0x0F;
    3.31 +    SUB_imm8s_r32( adj, R_ESP );
    3.32 +    if( arg2 != R_EDX ) {
    3.33 +        MOV_r32_r32( arg2, R_EDX );
    3.34 +    }
    3.35 +    if( arg1 != R_EAX ) {
    3.36 +        MOV_r32_r32( arg1, R_EAX );
    3.37 +    }
    3.38 +    load_imm32(R_ECX, (uint32_t)ptr);
    3.39 +    CALL_r32(R_ECX);
    3.40 +    ADD_imm8s_r32( adj, R_ESP );
    3.41 +}
    3.42 +
    3.43 +/**
    3.44 + * Write a double (64-bit) value into memory, with the first word in arg2a, and
    3.45 + * the second in arg2b
    3.46 + */
    3.47 +static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
    3.48 +{
    3.49 +    PUSH_r32(arg2b);
    3.50 +    PUSH_r32(addr);
    3.51 +    call_func2(sh4_write_long, addr, arg2a);
    3.52 +    POP_r32(R_EAX);
    3.53 +    POP_r32(R_EDX);
    3.54 +    ADD_imm8s_r32(4, R_EAX);
    3.55 +    call_func0(sh4_write_long);
    3.56 +}
    3.57 +
    3.58 +/**
    3.59 + * Read a double (64-bit) value from memory, writing the first word into arg2a
    3.60 + * and the second into arg2b. The addr must not be in EAX
    3.61 + */
    3.62 +static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
    3.63 +{
    3.64 +    PUSH_r32(addr);
    3.65 +    call_func1(sh4_read_long, addr);
    3.66 +    POP_r32(R_ECX);
    3.67 +    PUSH_r32(R_EAX);
    3.68 +    MOV_r32_r32(R_ECX, R_EAX);
    3.69 +    ADD_imm8s_r32(4, R_EAX);
    3.70 +    call_func0(sh4_read_long);
    3.71 +    if( arg2b != R_EAX ) {
    3.72 +        MOV_r32_r32(R_EAX, arg2b);
    3.73 +    }
    3.74 +    POP_r32(arg2a);
    3.75 +}
    3.76 +#else
    3.77  static inline void call_func1( void *ptr, int arg1 )
    3.78  {
    3.79      int adj = (-4-sh4_x86.stack_posn)&0x0F;
    3.80 @@ -65,9 +126,7 @@
    3.81  /**
    3.82   * Write a double (64-bit) value into memory, with the first word in arg2a, and
    3.83   * the second in arg2b
    3.84 - * NB: 30 bytes
    3.85   */
    3.86 -#define MEM_WRITE_DOUBLE_SIZE 36
    3.87  static inline void MEM_WRITE_DOUBLE( int addr, int arg2a, int arg2b )
    3.88  {
    3.89      int adj = (-8-sh4_x86.stack_posn)&0x0F;
    3.90 @@ -91,9 +150,7 @@
    3.91  /**
    3.92   * Read a double (64-bit) value from memory, writing the first word into arg2a
    3.93   * and the second into arg2b. The addr must not be in EAX
    3.94 - * NB: 27 bytes
    3.95   */
    3.96 -#define MEM_READ_DOUBLE_SIZE 36
    3.97  static inline void MEM_READ_DOUBLE( int addr, int arg2a, int arg2b )
    3.98  {
    3.99      int adj = (-4-sh4_x86.stack_posn)&0x0F;
   3.100 @@ -116,6 +173,8 @@
   3.101      sh4_x86.stack_posn -= 4;
   3.102  }
   3.103  
   3.104 +#endif
   3.105 +
   3.106  /**
   3.107   * Emit the 'start of block' assembly. Sets up the stack frame and save
   3.108   * SI/DI as required
   3.109 @@ -164,9 +223,6 @@
   3.110  }
   3.111  
   3.112  
   3.113 -#define EXIT_BLOCK_SIZE(pc)  (24 + (IS_IN_ICACHE(pc)?5:CALL_FUNC1_SIZE))
   3.114 -
   3.115 -
   3.116  /**
   3.117   * Exit the block to an absolute PC
   3.118   */
   3.119 @@ -188,8 +244,6 @@
   3.120      RET();
   3.121  }
   3.122  
   3.123 -#define EXIT_BLOCK_REL_SIZE(pc)  (27 + (IS_IN_ICACHE(pc)?5:CALL_FUNC1_SIZE))
   3.124 -
   3.125  /**
   3.126   * Exit the block to a relative PC
   3.127   */
   3.128 @@ -280,6 +334,47 @@
   3.129      }
   3.130  }
   3.131  
   3.132 +
   3.133 +/**
   3.134 + * The unwind methods only work if we compiled with DWARF2 frame information
   3.135 + * (ie -fexceptions), otherwise we have to use the direct frame scan.
   3.136 + */
   3.137 +#ifdef HAVE_EXCEPTIONS
   3.138 +#include <unwind.h>
   3.139 +
   3.140 +struct UnwindInfo {
   3.141 +    int have_result;
   3.142 +    void *pc;
   3.143 +};
   3.144 +
   3.145 +_Unwind_Reason_Code xlat_check_frame( struct _Unwind_Context *context, void *arg )
   3.146 +{
   3.147 +    void *ebp = (void *)_Unwind_GetGR(context, 5);
   3.148 +    void *expect = (((uint8_t *)&sh4r) + 128 );
   3.149 +    struct UnwindInfo *info = arg;
   3.150 +    if( ebp == expect ) { 
   3.151 +        info->have_result = 1;
   3.152 +        info->pc = (void *)_Unwind_GetIP(context);
   3.153 +    } else if( info->have_result ) {
   3.154 +        return _URC_NORMAL_STOP;
   3.155 +    }
   3.156 +
   3.157 +    return _URC_NO_REASON;
   3.158 +}
   3.159 +
   3.160 +void *xlat_get_native_pc()
   3.161 +{
   3.162 +    struct _Unwind_Exception exc;
   3.163 +    struct UnwindInfo info;
   3.164 +
   3.165 +    info.have_result = 0;
   3.166 +    void *result = NULL;
   3.167 +    _Unwind_Backtrace( xlat_check_frame, &info );
   3.168 +    if( info.have_result )
   3.169 +        return info.pc;
   3.170 +    return NULL;
   3.171 +}
   3.172 +#else 
   3.173  void *xlat_get_native_pc()
   3.174  {
   3.175      void *result = NULL;
   3.176 @@ -302,7 +397,7 @@
   3.177          : "eax", "ecx", "edx" );
   3.178      return result;
   3.179  }
   3.180 -
   3.181 +#endif
   3.182  
   3.183  #endif /* !lxdream_ia32mac.h */
   3.184  

     4.1 --- a/src/sh4/mmu.c	Wed Oct 29 23:36:31 2008 +0000
     4.2 +++ b/src/sh4/mmu.c	Wed Oct 29 23:51:58 2008 +0000
     4.3 @@ -664,7 +664,7 @@
     4.4      return result;
     4.5  }
     4.6  
     4.7 -sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr )
     4.8 +sh4addr_t FASTCALL mmu_vma_to_phys_read( sh4vma_t addr )
     4.9  {
    4.10      uint32_t mmucr = MMIO_READ(MMU,MMUCR);
    4.11      if( addr & 0x80000000 ) {
    4.12 @@ -722,7 +722,7 @@
    4.13      }
    4.14  }
    4.15  
    4.16 -sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr )
    4.17 +sh4addr_t FASTCALL mmu_vma_to_phys_write( sh4vma_t addr )
    4.18  {
    4.19      uint32_t mmucr = MMIO_READ(MMU,MMUCR);
    4.20      if( addr & 0x80000000 ) {
    4.21 @@ -788,7 +788,7 @@
    4.22  /**
    4.23   * Update the icache for an untranslated address
    4.24   */
    4.25 -void mmu_update_icache_phys( sh4addr_t addr )
    4.26 +static inline void mmu_update_icache_phys( sh4addr_t addr )
    4.27  {
    4.28      if( (addr & 0x1C000000) == 0x0C000000 ) {
    4.29          /* Main ram */
    4.30 @@ -820,7 +820,7 @@
    4.31   * @return TRUE if the update completed (successfully or otherwise), FALSE
    4.32   * if an exception was raised.
    4.33   */
    4.34 -gboolean mmu_update_icache( sh4vma_t addr )
    4.35 +gboolean FASTCALL mmu_update_icache( sh4vma_t addr )
    4.36  {
    4.37      int entryNo;
    4.38      if( IS_SH4_PRIVMODE()  ) {
    4.39 @@ -891,7 +891,7 @@
    4.40   * protection bits. Returns the translated address, or MMU_VMA_ERROR
    4.41   * on translation failure.
    4.42   */
    4.43 -sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t vma )
    4.44 +sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t vma )
    4.45  {
    4.46      if( vma & 0x80000000 ) {
    4.47          if( vma < 0xC0000000 ) {
    4.48 @@ -920,7 +920,7 @@
    4.49      }
    4.50  }
    4.51  
    4.52 -gboolean sh4_flush_store_queue( sh4addr_t addr )
    4.53 +gboolean FASTCALL sh4_flush_store_queue( sh4addr_t addr )
    4.54  {
    4.55      uint32_t mmucr = MMIO_READ(MMU,MMUCR);
    4.56      int queue = (addr&0x20)>>2;

     5.1 --- a/src/sh4/sh4.c	Wed Oct 29 23:36:31 2008 +0000
     5.2 +++ b/src/sh4/sh4.c	Wed Oct 29 23:51:58 2008 +0000
     5.3 @@ -315,7 +315,7 @@
     5.4      memcpy( sh4r.r_bank, tmp, sizeof(uint32_t)*8 );
     5.5  }
     5.6  
     5.7 -void sh4_switch_fr_banks()
     5.8 +void FASTCALL sh4_switch_fr_banks()
     5.9  {
    5.10      int i;
    5.11      for( i=0; i<16; i++ ) {
    5.12 @@ -325,7 +325,7 @@
    5.13      }
    5.14  }
    5.15  
    5.16 -void sh4_write_sr( uint32_t newval )
    5.17 +void FASTCALL sh4_write_sr( uint32_t newval )
    5.18  {
    5.19      int oldbank = (sh4r.sr&SR_MDRB) == SR_MDRB;
    5.20      int newbank = (newval&SR_MDRB) == SR_MDRB;
    5.21 @@ -339,7 +339,7 @@
    5.22      intc_mask_changed();
    5.23  }
    5.24  
    5.25 -void sh4_write_fpscr( uint32_t newval )
    5.26 +void FASTCALL sh4_write_fpscr( uint32_t newval )
    5.27  {
    5.28      if( (sh4r.fpscr ^ newval) & FPSCR_FR ) {
    5.29          sh4_switch_fr_banks();
    5.30 @@ -347,7 +347,7 @@
    5.31      sh4r.fpscr = newval & FPSCR_MASK;
    5.32  }
    5.33  
    5.34 -uint32_t sh4_read_sr( void )
    5.35 +uint32_t FASTCALL sh4_read_sr( void )
    5.36  {
    5.37      /* synchronize sh4r.sr with the various bitflags */
    5.38      sh4r.sr &= SR_MQSTMASK;
    5.39 @@ -383,7 +383,7 @@
    5.40   * Raise a general CPU exception for the specified exception code.
    5.41   * (NOT for TRAPA or TLB exceptions)
    5.42   */
    5.43 -gboolean sh4_raise_exception( int code )
    5.44 +gboolean FASTCALL sh4_raise_exception( int code )
    5.45  {
    5.46      RAISE( code, EXV_EXCEPTION );
    5.47  }
    5.48 @@ -391,7 +391,7 @@
    5.49  /**
    5.50   * Raise a CPU reset exception with the specified exception code.
    5.51   */
    5.52 -gboolean sh4_raise_reset( int code )
    5.53 +gboolean FASTCALL sh4_raise_reset( int code )
    5.54  {
    5.55      // FIXME: reset modules as per "manual reset"
    5.56      sh4_reset();
    5.57 @@ -404,13 +404,13 @@
    5.58      return TRUE;
    5.59  }
    5.60  
    5.61 -gboolean sh4_raise_trap( int trap )
    5.62 +gboolean FASTCALL sh4_raise_trap( int trap )
    5.63  {
    5.64      MMIO_WRITE( MMU, TRA, trap<<2 );
    5.65      RAISE( EXC_TRAP, EXV_EXCEPTION );
    5.66  }
    5.67  
    5.68 -gboolean sh4_raise_slot_exception( int normal_code, int slot_code ) {
    5.69 +gboolean FASTCALL sh4_raise_slot_exception( int normal_code, int slot_code ) {
    5.70      if( sh4r.in_delay_slot ) {
    5.71          return sh4_raise_exception(slot_code);
    5.72      } else {
    5.73 @@ -418,12 +418,12 @@
    5.74      }
    5.75  }
    5.76  
    5.77 -gboolean sh4_raise_tlb_exception( int code )
    5.78 +gboolean FASTCALL sh4_raise_tlb_exception( int code )
    5.79  {
    5.80      RAISE( code, EXV_TLBMISS );
    5.81  }
    5.82  
    5.83 -void sh4_accept_interrupt( void )
    5.84 +void FASTCALL sh4_accept_interrupt( void )
    5.85  {
    5.86      uint32_t code = intc_accept_interrupt();
    5.87      sh4r.ssr = sh4_read_sr();
    5.88 @@ -436,7 +436,7 @@
    5.89      //    WARN( "Accepting interrupt %03X, from %08X => %08X", code, sh4r.spc, sh4r.pc );
    5.90  }
    5.91  
    5.92 -void signsat48( void )
    5.93 +void FASTCALL signsat48( void )
    5.94  {
    5.95      if( ((int64_t)sh4r.mac) < (int64_t)0xFFFF800000000000LL )
    5.96          sh4r.mac = 0xFFFF800000000000LL;
    5.97 @@ -444,7 +444,7 @@
    5.98          sh4r.mac = 0x00007FFFFFFFFFFFLL;
    5.99  }
   5.100  
   5.101 -void sh4_fsca( uint32_t anglei, float *fr )
   5.102 +void FASTCALL sh4_fsca( uint32_t anglei, float *fr )
   5.103  {
   5.104      float angle = (((float)(anglei&0xFFFF))/65536.0) * 2 * M_PI;
   5.105      *fr++ = cosf(angle);
   5.106 @@ -456,7 +456,7 @@
   5.107   * Sets sh4_state appropriately and ensures any stopping peripheral modules
   5.108   * are up to date.
   5.109   */
   5.110 -void sh4_sleep(void)
   5.111 +void FASTCALL sh4_sleep(void)
   5.112  {
   5.113      if( MMIO_READ( CPG, STBCR ) & 0x80 ) {
   5.114          sh4r.sh4_state = SH4_STATE_STANDBY;
   5.115 @@ -523,7 +523,7 @@
   5.116   * Compute the matrix tranform of fv given the matrix xf.
   5.117   * Both fv and xf are word-swapped as per the sh4r.fr banks
   5.118   */
   5.119 -void sh4_ftrv( float *target )
   5.120 +void FASTCALL sh4_ftrv( float *target )
   5.121  {
   5.122      float fv[4] = { target[1], target[0], target[3], target[2] };
   5.123      target[1] = sh4r.fr[1][1] * fv[0] + sh4r.fr[1][5]*fv[1] +

     6.1 --- a/src/sh4/sh4core.h	Wed Oct 29 23:36:31 2008 +0000
     6.2 +++ b/src/sh4/sh4core.h	Wed Oct 29 23:51:58 2008 +0000
     6.3 @@ -170,14 +170,14 @@
     6.4  uint32_t sh4_emulate_run_slice(uint32_t);
     6.5  
     6.6  /* SH4 instruction support methods */
     6.7 -void sh4_sleep( void );
     6.8 -void sh4_fsca( uint32_t angle, float *fr );
     6.9 -void sh4_ftrv( float *fv );
    6.10 -uint32_t sh4_read_sr(void);
    6.11 -void sh4_write_sr(uint32_t val);
    6.12 -void sh4_write_fpscr(uint32_t val);
    6.13 -void sh4_switch_fr_banks(void);
    6.14 -void signsat48(void);
    6.15 +void FASTCALL sh4_sleep( void );
    6.16 +void FASTCALL sh4_fsca( uint32_t angle, float *fr );
    6.17 +void FASTCALL sh4_ftrv( float *fv );
    6.18 +uint32_t FASTCALL sh4_read_sr(void);
    6.19 +void FASTCALL sh4_write_sr(uint32_t val);
    6.20 +void FASTCALL sh4_write_fpscr(uint32_t val);
    6.21 +void FASTCALL sh4_switch_fr_banks(void);
    6.22 +void FASTCALL signsat48(void);
    6.23  gboolean sh4_has_page( sh4vma_t vma );
    6.24  
    6.25  /* SH4 Memory */
    6.26 @@ -190,7 +190,7 @@
    6.27   * invalidated, but the function will still return TRUE.
    6.28   * @return FALSE if an MMU exception was raised, otherwise TRUE.
    6.29   */
    6.30 -gboolean mmu_update_icache( sh4vma_t addr );
    6.31 +gboolean FASTCALL mmu_update_icache( sh4vma_t addr );
    6.32  
    6.33  /**
    6.34   * Resolve a virtual address through the TLB for a read operation, returning 
    6.35 @@ -199,20 +199,20 @@
    6.36   * @return An external address (0x00000000-0x1FFFFFFF), a P4 address
    6.37   * (0xE0000000 - 0xFFFFFFFF), or MMU_VMA_ERROR.
    6.38   */
    6.39 -sh4addr_t mmu_vma_to_phys_read( sh4vma_t addr );
    6.40 -sh4addr_t mmu_vma_to_phys_write( sh4vma_t addr );
    6.41 -sh4addr_t mmu_vma_to_phys_disasm( sh4vma_t addr );
    6.42 +sh4addr_t FASTCALL mmu_vma_to_phys_read( sh4vma_t addr );
    6.43 +sh4addr_t FASTCALL mmu_vma_to_phys_write( sh4vma_t addr );
    6.44 +sh4addr_t FASTCALL mmu_vma_to_phys_disasm( sh4vma_t addr );
    6.45  
    6.46 -int64_t sh4_read_quad( sh4addr_t addr );
    6.47 -int32_t sh4_read_long( sh4addr_t addr );
    6.48 -int32_t sh4_read_word( sh4addr_t addr );
    6.49 -int32_t sh4_read_byte( sh4addr_t addr );
    6.50 -void sh4_write_quad( sh4addr_t addr, uint64_t val );
    6.51 -void sh4_write_long( sh4addr_t addr, uint32_t val );
    6.52 -void sh4_write_word( sh4addr_t addr, uint32_t val );
    6.53 -void sh4_write_byte( sh4addr_t addr, uint32_t val );
    6.54 +int64_t FASTCALL sh4_read_quad( sh4addr_t addr );
    6.55 +int32_t FASTCALL sh4_read_long( sh4addr_t addr );
    6.56 +int32_t FASTCALL sh4_read_word( sh4addr_t addr );
    6.57 +int32_t FASTCALL sh4_read_byte( sh4addr_t addr );
    6.58 +void FASTCALL sh4_write_quad( sh4addr_t addr, uint64_t val );
    6.59 +void FASTCALL sh4_write_long( sh4addr_t addr, uint32_t val );
    6.60 +void FASTCALL sh4_write_word( sh4addr_t addr, uint32_t val );
    6.61 +void FASTCALL sh4_write_byte( sh4addr_t addr, uint32_t val );
    6.62  int32_t sh4_read_phys_word( sh4addr_t addr );
    6.63 -gboolean sh4_flush_store_queue( sh4addr_t addr );
    6.64 +gboolean FASTCALL sh4_flush_store_queue( sh4addr_t addr );
    6.65  
    6.66  /* SH4 Exceptions */
    6.67  #define EXC_POWER_RESET     0x000 /* reset vector */
    6.68 @@ -235,12 +235,12 @@
    6.69  #define EXV_TLBMISS      0x400  /* TLB-miss exception vector */
    6.70  #define EXV_INTERRUPT    0x600  /* External interrupt vector */
    6.71  
    6.72 -gboolean sh4_raise_exception( int );
    6.73 -gboolean sh4_raise_reset( int );
    6.74 -gboolean sh4_raise_trap( int );
    6.75 -gboolean sh4_raise_slot_exception( int, int );
    6.76 -gboolean sh4_raise_tlb_exception( int );
    6.77 -void sh4_accept_interrupt( void );
    6.78 +gboolean FASTCALL sh4_raise_exception( int );
    6.79 +gboolean FASTCALL sh4_raise_reset( int );
    6.80 +gboolean FASTCALL sh4_raise_trap( int );
    6.81 +gboolean FASTCALL sh4_raise_slot_exception( int, int );
    6.82 +gboolean FASTCALL sh4_raise_tlb_exception( int );
    6.83 +void FASTCALL sh4_accept_interrupt( void );
    6.84  
    6.85  #define SIGNEXT4(n) ((((int32_t)(n))<<28)>>28)
    6.86  #define SIGNEXT8(n) ((int32_t)((int8_t)(n)))

     7.1 --- a/src/sh4/sh4mem.c	Wed Oct 29 23:36:31 2008 +0000
     7.2 +++ b/src/sh4/sh4mem.c	Wed Oct 29 23:51:58 2008 +0000
     7.3 @@ -68,7 +68,7 @@
     7.4  extern struct mem_region mem_rgn[];
     7.5  extern struct mmio_region *P4_io[];
     7.6  
     7.7 -int32_t sh4_read_p4( sh4addr_t addr )
     7.8 +int32_t FASTCALL sh4_read_p4( sh4addr_t addr )
     7.9  {
    7.10      struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19];
    7.11      if( !io ) {
    7.12 @@ -96,7 +96,7 @@
    7.13      }    
    7.14  }
    7.15  
    7.16 -void sh4_write_p4( sh4addr_t addr, int32_t val )
    7.17 +void FASTCALL sh4_write_p4( sh4addr_t addr, int32_t val )
    7.18  {
    7.19      struct mmio_region *io = P4_io[(addr&0x1FFFFFFF)>>19];
    7.20      if( !io ) {
    7.21 @@ -153,13 +153,13 @@
    7.22  /**
    7.23   * Convenience function to read a quad-word (implemented as two long reads).
    7.24   */
    7.25 -int64_t sh4_read_quad( sh4addr_t addr )
    7.26 +int64_t FASTCALL sh4_read_quad( sh4addr_t addr )
    7.27  {
    7.28      return ((int64_t)((uint32_t)sh4_read_long(addr))) |
    7.29      (((int64_t)((uint32_t)sh4_read_long(addr+4))) << 32);
    7.30  }
    7.31  
    7.32 -int32_t sh4_read_long( sh4addr_t addr )
    7.33 +int32_t FASTCALL sh4_read_long( sh4addr_t addr )
    7.34  {
    7.35      sh4ptr_t page;
    7.36  
    7.37 @@ -191,7 +191,7 @@
    7.38      }
    7.39  }
    7.40  
    7.41 -int32_t sh4_read_word( sh4addr_t addr )
    7.42 +int32_t FASTCALL sh4_read_word( sh4addr_t addr )
    7.43  {
    7.44      sh4ptr_t page;
    7.45  
    7.46 @@ -223,7 +223,7 @@
    7.47      }
    7.48  }
    7.49  
    7.50 -int32_t sh4_read_byte( sh4addr_t addr )
    7.51 +int32_t FASTCALL sh4_read_byte( sh4addr_t addr )
    7.52  {
    7.53      sh4ptr_t page;
    7.54  
    7.55 @@ -259,13 +259,13 @@
    7.56  /**
    7.57   * Convenience function to write a quad-word (implemented as two long writes).
    7.58   */
    7.59 -void sh4_write_quad( sh4addr_t addr, uint64_t val )
    7.60 +void FASTCALL sh4_write_quad( sh4addr_t addr, uint64_t val )
    7.61  {
    7.62      sh4_write_long( addr, (uint32_t)val );
    7.63      sh4_write_long( addr+4, (uint32_t)(val>>32) );
    7.64  }
    7.65  
    7.66 -void sh4_write_long( sh4addr_t addr, uint32_t val )
    7.67 +void FASTCALL sh4_write_long( sh4addr_t addr, uint32_t val )
    7.68  {
    7.69      sh4ptr_t page;
    7.70  
    7.71 @@ -311,7 +311,7 @@
    7.72      }
    7.73  }
    7.74  
    7.75 -void sh4_write_word( sh4addr_t addr, uint32_t val )
    7.76 +void FASTCALL sh4_write_word( sh4addr_t addr, uint32_t val )
    7.77  {
    7.78      sh4ptr_t page;
    7.79  
    7.80 @@ -351,7 +351,7 @@
    7.81      }
    7.82  }
    7.83  
    7.84 -void sh4_write_byte( sh4addr_t addr, uint32_t val )
    7.85 +void FASTCALL sh4_write_byte( sh4addr_t addr, uint32_t val )
    7.86  {
    7.87      sh4ptr_t page;
    7.88  

     8.1 --- a/src/sh4/sh4stat.h	Wed Oct 29 23:36:31 2008 +0000
     8.2 +++ b/src/sh4/sh4stat.h	Wed Oct 29 23:51:58 2008 +0000
     8.3 @@ -21,6 +21,7 @@
     8.4  
     8.5  #include <stdio.h>
     8.6  #include <stdint.h>
     8.7 +#include "lxdream.h"
     8.8  
     8.9  #ifdef __cplusplus
    8.10  extern "C" {
    8.11 @@ -67,7 +68,7 @@
    8.12  
    8.13      void sh4_stats_reset( void );
    8.14      void sh4_stats_print( FILE *out );
    8.15 -    void sh4_stats_add( sh4_inst_id id );
    8.16 +    void FASTCALL sh4_stats_add( sh4_inst_id id );
    8.17      void sh4_stats_add_by_pc( uint32_t pc );
    8.18  
    8.19  #ifdef __cplusplus

     9.1 --- a/src/sh4/sh4stat.in	Wed Oct 29 23:36:31 2008 +0000
     9.2 +++ b/src/sh4/sh4stat.in	Wed Oct 29 23:51:58 2008 +0000
     9.3 @@ -186,7 +186,7 @@
     9.4      fprintf( out, "Total: %lld\n", sh4_stats_total );
     9.5  }
     9.6  
     9.7 -void sh4_stats_add( sh4_inst_id item )
     9.8 +void FASTCALL sh4_stats_add( sh4_inst_id item )
     9.9  {
    9.10      sh4_stats[item]++;
    9.11      sh4_stats_total++;

    10.1 --- a/src/sh4/sh4trans.c	Wed Oct 29 23:36:31 2008 +0000
    10.2 +++ b/src/sh4/sh4trans.c	Wed Oct 29 23:51:58 2008 +0000
    10.3 @@ -170,7 +170,7 @@
    10.4      }
    10.5  }
    10.6  
    10.7 -void sh4_translate_breakpoint_hit(uint32_t pc)
    10.8 +void FASTCALL sh4_translate_breakpoint_hit(uint32_t pc)
    10.9  {
   10.10      if( sh4_starting && sh4r.slice_cycle == 0 && pc == sh4r.pc ) {
   10.11          return;
   10.12 @@ -207,7 +207,7 @@
   10.13      }
   10.14  }
   10.15  
   10.16 -void *xlat_get_code_by_vma( sh4vma_t vma )
   10.17 +void * FASTCALL xlat_get_code_by_vma( sh4vma_t vma )
   10.18  {
   10.19      void *result = NULL;
   10.20  

    11.1 --- a/src/sh4/sh4trans.h	Wed Oct 29 23:36:31 2008 +0000
    11.2 +++ b/src/sh4/sh4trans.h	Wed Oct 29 23:51:58 2008 +0000
    11.3 @@ -124,7 +124,7 @@
    11.4   * Either returns immediately (to skip the breakpoint), or aborts the current
    11.5   * cycle and never returns.
    11.6   */
    11.7 -void sh4_translate_breakpoint_hit( sh4vma_t pc );
    11.8 +void FASTCALL sh4_translate_breakpoint_hit( sh4vma_t pc );
    11.9  
   11.10  #ifdef __cplusplus
   11.11  }

    12.1 --- a/src/sh4/sh4x86.in	Wed Oct 29 23:36:31 2008 +0000
    12.2 +++ b/src/sh4/sh4x86.in	Wed Oct 29 23:51:58 2008 +0000
    12.3 @@ -25,6 +25,7 @@
    12.4  #define DEBUG_JUMPS 1
    12.5  #endif
    12.6  
    12.7 +#include "lxdream.h"
    12.8  #include "sh4/xltcache.h"
    12.9  #include "sh4/sh4core.h"
   12.10  #include "sh4/sh4trans.h"
   12.11 @@ -312,10 +313,6 @@
   12.12   */
   12.13  #define MMU_TRANSLATE_WRITE( addr_reg ) if( sh4_x86.tlb_on ) { call_func1(mmu_vma_to_phys_write, addr_reg); CMP_imm32_r32(MMU_VMA_ERROR, R_EAX); JE_exc(-1); MEM_RESULT(addr_reg); }
   12.14  
   12.15 -#define MEM_READ_SIZE (CALL_FUNC1_SIZE)
   12.16 -#define MEM_WRITE_SIZE (CALL_FUNC2_SIZE)
   12.17 -#define MMU_TRANSLATE_SIZE (sh4_x86.tlb_on ? (CALL_FUNC1_SIZE + 12) : 0 )
   12.18 -
   12.19  #define SLOTILLEGAL() JMP_exc(EXC_SLOT_ILLEGAL); sh4_x86.in_delay_slot = DELAY_NONE; return 1;
   12.20  
   12.21  /****** Import appropriate calling conventions ******/
   12.22 @@ -491,10 +488,10 @@
   12.23      ADD_r32_r32( R_ECX, R_EAX );
   12.24      MMU_TRANSLATE_WRITE( R_EAX );
   12.25      PUSH_realigned_r32(R_EAX);
   12.26 -    MEM_READ_BYTE( R_EAX, R_EAX );
   12.27 -    POP_realigned_r32(R_ECX);
   12.28 -    AND_imm32_r32(imm, R_EAX );
   12.29 -    MEM_WRITE_BYTE( R_ECX, R_EAX );
   12.30 +    MEM_READ_BYTE( R_EAX, R_EDX );
   12.31 +    POP_realigned_r32(R_EAX);
   12.32 +    AND_imm32_r32(imm, R_EDX );
   12.33 +    MEM_WRITE_BYTE( R_EAX, R_EDX );
   12.34      sh4_x86.tstate = TSTATE_NONE;
   12.35  :}
   12.36  CMP/EQ Rm, Rn {:  
   12.37 @@ -848,10 +845,10 @@
   12.38      ADD_r32_r32( R_ECX, R_EAX );
   12.39      MMU_TRANSLATE_WRITE( R_EAX );
   12.40      PUSH_realigned_r32(R_EAX);
   12.41 -    MEM_READ_BYTE( R_EAX, R_EAX );
   12.42 -    POP_realigned_r32(R_ECX);
   12.43 -    OR_imm32_r32(imm, R_EAX );
   12.44 -    MEM_WRITE_BYTE( R_ECX, R_EAX );
   12.45 +    MEM_READ_BYTE( R_EAX, R_EDX );
   12.46 +    POP_realigned_r32(R_EAX);
   12.47 +    OR_imm32_r32(imm, R_EDX );
   12.48 +    MEM_WRITE_BYTE( R_EAX, R_EDX );
   12.49      sh4_x86.tstate = TSTATE_NONE;
   12.50  :}
   12.51  ROTCL Rn {:
   12.52 @@ -1067,12 +1064,12 @@
   12.53      load_reg( R_EAX, Rn );
   12.54      MMU_TRANSLATE_WRITE( R_EAX );
   12.55      PUSH_realigned_r32( R_EAX );
   12.56 -    MEM_READ_BYTE( R_EAX, R_EAX );
   12.57 -    TEST_r8_r8( R_AL, R_AL );
   12.58 +    MEM_READ_BYTE( R_EAX, R_EDX );
   12.59 +    TEST_r8_r8( R_DL, R_DL );
   12.60      SETE_t();
   12.61 -    OR_imm8_r8( 0x80, R_AL );
   12.62 -    POP_realigned_r32( R_ECX );
   12.63 -    MEM_WRITE_BYTE( R_ECX, R_EAX );
   12.64 +    OR_imm8_r8( 0x80, R_DL );
   12.65 +    POP_realigned_r32( R_EAX );
   12.66 +    MEM_WRITE_BYTE( R_EAX, R_EDX );
   12.67      sh4_x86.tstate = TSTATE_NONE;
   12.68  :}
   12.69  TST Rm, Rn {:  
   12.70 @@ -1123,10 +1120,10 @@
   12.71      ADD_r32_r32( R_ECX, R_EAX );
   12.72      MMU_TRANSLATE_WRITE( R_EAX );
   12.73      PUSH_realigned_r32(R_EAX);
   12.74 -    MEM_READ_BYTE(R_EAX, R_EAX);
   12.75 -    POP_realigned_r32(R_ECX);
   12.76 -    XOR_imm32_r32( imm, R_EAX );
   12.77 -    MEM_WRITE_BYTE( R_ECX, R_EAX );
   12.78 +    MEM_READ_BYTE(R_EAX, R_EDX);
   12.79 +    POP_realigned_r32(R_EAX);
   12.80 +    XOR_imm32_r32( imm, R_EDX );
   12.81 +    MEM_WRITE_BYTE( R_EAX, R_EDX );
   12.82      sh4_x86.tstate = TSTATE_NONE;
   12.83  :}
   12.84  XTRCT Rm, Rn {:
   12.85 @@ -1863,14 +1860,14 @@
   12.86      if( sh4_x86.double_size ) {
   12.87          check_walign64( R_EAX );
   12.88          MMU_TRANSLATE_WRITE( R_EAX );
   12.89 -        load_dr0( R_ECX, FRm );
   12.90 -        load_dr1( R_EDX, FRm );
   12.91 -        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
   12.92 +        load_dr0( R_EDX, FRm );
   12.93 +        load_dr1( R_ECX, FRm );
   12.94 +        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
   12.95      } else {
   12.96          check_walign32( R_EAX );
   12.97          MMU_TRANSLATE_WRITE( R_EAX );
   12.98 -        load_fr( R_ECX, FRm );
   12.99 -        MEM_WRITE_LONG( R_EAX, R_ECX );
  12.100 +        load_fr( R_EDX, FRm );
  12.101 +        MEM_WRITE_LONG( R_EAX, R_EDX );
  12.102      }
  12.103      sh4_x86.tstate = TSTATE_NONE;
  12.104  :}
  12.105 @@ -1881,8 +1878,8 @@
  12.106      if( sh4_x86.double_size ) {
  12.107          check_ralign64( R_EAX );
  12.108          MMU_TRANSLATE_READ( R_EAX );
  12.109 -        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  12.110 -        store_dr0( R_ECX, FRn );
  12.111 +        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
  12.112 +        store_dr0( R_EDX, FRn );
  12.113          store_dr1( R_EAX, FRn );    
  12.114      } else {
  12.115          check_ralign32( R_EAX );
  12.116 @@ -1900,17 +1897,17 @@
  12.117          check_walign64( R_EAX );
  12.118          ADD_imm8s_r32(-8,R_EAX);
  12.119          MMU_TRANSLATE_WRITE( R_EAX );
  12.120 -        load_dr0( R_ECX, FRm );
  12.121 -        load_dr1( R_EDX, FRm );
  12.122 +        load_dr0( R_EDX, FRm );
  12.123 +        load_dr1( R_ECX, FRm );
  12.124          ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
  12.125 -        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  12.126 +        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
  12.127      } else {
  12.128          check_walign32( R_EAX );
  12.129          ADD_imm8s_r32( -4, R_EAX );
  12.130          MMU_TRANSLATE_WRITE( R_EAX );
  12.131 -        load_fr( R_ECX, FRm );
  12.132 +        load_fr( R_EDX, FRm );
  12.133          ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
  12.134 -        MEM_WRITE_LONG( R_EAX, R_ECX );
  12.135 +        MEM_WRITE_LONG( R_EAX, R_EDX );
  12.136      }
  12.137      sh4_x86.tstate = TSTATE_NONE;
  12.138  :}
  12.139 @@ -1922,8 +1919,8 @@
  12.140          check_ralign64( R_EAX );
  12.141          MMU_TRANSLATE_READ( R_EAX );
  12.142          ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
  12.143 -        MEM_READ_DOUBLE( R_EAX, R_ECX, R_EAX );
  12.144 -        store_dr0( R_ECX, FRn );
  12.145 +        MEM_READ_DOUBLE( R_EAX, R_EDX, R_EAX );
  12.146 +        store_dr0( R_EDX, FRn );
  12.147          store_dr1( R_EAX, FRn );
  12.148      } else {
  12.149          check_ralign32( R_EAX );
  12.150 @@ -1942,14 +1939,14 @@
  12.151      if( sh4_x86.double_size ) {
  12.152          check_walign64( R_EAX );
  12.153          MMU_TRANSLATE_WRITE( R_EAX );
  12.154 -        load_dr0( R_ECX, FRm );
  12.155 -        load_dr1( R_EDX, FRm );
  12.156 -        MEM_WRITE_DOUBLE( R_EAX, R_ECX, R_EDX );
  12.157 +        load_dr0( R_EDX, FRm );
  12.158 +        load_dr1( R_ECX, FRm );
  12.159 +        MEM_WRITE_DOUBLE( R_EAX, R_EDX, R_ECX );
  12.160      } else {
  12.161          check_walign32( R_EAX );
  12.162          MMU_TRANSLATE_WRITE( R_EAX );
  12.163 -        load_fr( R_ECX, FRm );
  12.164 -        MEM_WRITE_LONG( R_EAX, R_ECX ); // 12
  12.165 +        load_fr( R_EDX, FRm );
  12.166 +        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
  12.167      }
  12.168      sh4_x86.tstate = TSTATE_NONE;
  12.169  :}
  12.170 @@ -2228,9 +2225,9 @@
  12.171      COUNT_INST(I_FSCA);
  12.172      check_fpuen();
  12.173      if( sh4_x86.double_prec == 0 ) {
  12.174 -        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_ECX );
  12.175 -        load_spreg( R_EDX, R_FPUL );
  12.176 -        call_func2( sh4_fsca, R_EDX, R_ECX );
  12.177 +        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
  12.178 +        load_spreg( R_EAX, R_FPUL );
  12.179 +        call_func2( sh4_fsca, R_EAX, R_EDX );
  12.180      }
  12.181      sh4_x86.tstate = TSTATE_NONE;
  12.182  :}
  12.183 @@ -2571,10 +2568,10 @@
  12.184      COUNT_INST(I_PREF);
  12.185      load_reg( R_EAX, Rn );
  12.186      MOV_r32_r32( R_EAX, R_ECX );
  12.187 -    AND_imm32_r32( 0xFC000000, R_EAX );
  12.188 -    CMP_imm32_r32( 0xE0000000, R_EAX );
  12.189 +    AND_imm32_r32( 0xFC000000, R_ECX );
  12.190 +    CMP_imm32_r32( 0xE0000000, R_ECX );
  12.191      JNE_rel8(end);
  12.192 -    call_func1( sh4_flush_store_queue, R_ECX );
  12.193 +    call_func1( sh4_flush_store_queue, R_EAX );
  12.194      TEST_r32_r32( R_EAX, R_EAX );
  12.195      JE_exc(-1);
  12.196      JMP_TARGET(end);

    13.1 --- a/src/sh4/xltcache.c	Wed Oct 29 23:36:31 2008 +0000
    13.2 +++ b/src/sh4/xltcache.c	Wed Oct 29 23:51:58 2008 +0000
    13.3 @@ -129,7 +129,7 @@
    13.4      }
    13.5  }
    13.6  
    13.7 -void xlat_invalidate_word( sh4addr_t addr )
    13.8 +void FASTCALL xlat_invalidate_word( sh4addr_t addr )
    13.9  {
   13.10      if( xlat_lut ) {
   13.11          void **page = xlat_lut[XLAT_LUT_PAGE(addr)];
   13.12 @@ -142,7 +142,7 @@
   13.13      }
   13.14  }
   13.15  
   13.16 -void xlat_invalidate_long( sh4addr_t addr )
   13.17 +void FASTCALL xlat_invalidate_long( sh4addr_t addr )
   13.18  {
   13.19      if( xlat_lut ) {
   13.20          void **page = xlat_lut[XLAT_LUT_PAGE(addr)];
   13.21 @@ -155,7 +155,7 @@
   13.22      }
   13.23  }
   13.24  
   13.25 -void xlat_invalidate_block( sh4addr_t address, size_t size )
   13.26 +void FASTCALL xlat_invalidate_block( sh4addr_t address, size_t size )
   13.27  {
   13.28      int i;
   13.29      int entry_count = size >> 1; // words;
   13.30 @@ -189,7 +189,7 @@
   13.31      }
   13.32  }
   13.33  
   13.34 -void xlat_flush_page( sh4addr_t address )
   13.35 +void FASTCALL xlat_flush_page( sh4addr_t address )
   13.36  {
   13.37      void **page = xlat_lut[XLAT_LUT_PAGE(address)];
   13.38      if( page != NULL ) {
   13.39 @@ -197,7 +197,7 @@
   13.40      }
   13.41  }
   13.42  
   13.43 -void *xlat_get_code( sh4addr_t address )
   13.44 +void * FASTCALL xlat_get_code( sh4addr_t address )
   13.45  {
   13.46      void *result = NULL;
   13.47      void **page = xlat_lut[XLAT_LUT_PAGE(address)];
   13.48 @@ -248,7 +248,7 @@
   13.49      return NULL;	
   13.50  }
   13.51  
   13.52 -void **xlat_get_lut_entry( sh4addr_t address )
   13.53 +void ** FASTCALL xlat_get_lut_entry( sh4addr_t address )
   13.54  {
   13.55      void **page = xlat_lut[XLAT_LUT_PAGE(address)];
   13.56  
   13.57 @@ -265,13 +265,13 @@
   13.58  
   13.59  
   13.60  
   13.61 -uint32_t xlat_get_block_size( void *block )
   13.62 +uint32_t FASTCALL xlat_get_block_size( void *block )
   13.63  {
   13.64      xlat_cache_block_t xlt = (xlat_cache_block_t)(((char *)block)-sizeof(struct xlat_cache_block));
   13.65      return xlt->size;
   13.66  }
   13.67  
   13.68 -uint32_t xlat_get_code_size( void *block )
   13.69 +uint32_t FASTCALL xlat_get_code_size( void *block )
   13.70  {
   13.71      xlat_cache_block_t xlt = (xlat_cache_block_t)(((char *)block)-sizeof(struct xlat_cache_block));
   13.72      if( xlt->recover_table_offset == 0 ) {

    14.1 --- a/src/sh4/xltcache.h	Wed Oct 29 23:36:31 2008 +0000
    14.2 +++ b/src/sh4/xltcache.h	Wed Oct 29 23:51:58 2008 +0000
    14.3 @@ -99,7 +99,7 @@
    14.4   * Retrieve the entry point for the translated code corresponding to the given
    14.5   * SH4 address, or NULL if there is no code for that address.
    14.6   */
    14.7 -void *xlat_get_code( sh4addr_t address );
    14.8 +void * FASTCALL xlat_get_code( sh4addr_t address );
    14.9  
   14.10  /**
   14.11   * Retrieve the post-instruction recovery record corresponding to the given
   14.12 @@ -130,13 +130,13 @@
   14.13   * If the virtual address cannot be resolved, this method will raise a TLB miss 
   14.14   * exception, and return NULL.
   14.15   */
   14.16 -void *xlat_get_code_by_vma( sh4vma_t address );
   14.17 +void * FASTCALL xlat_get_code_by_vma( sh4vma_t address );
   14.18  
   14.19  /**
   14.20   * Retrieve the address of the lookup table entry corresponding to the
   14.21   * given SH4 address.
   14.22   */
   14.23 -void **xlat_get_lut_entry( sh4addr_t address );
   14.24 +void ** FASTCALL xlat_get_lut_entry( sh4addr_t address );
   14.25  
   14.26  /**
   14.27   * Retrieve the current host address of the running translated code block.
   14.28 @@ -150,7 +150,7 @@
   14.29   * Retrieve the size of the block starting at the specified pointer. If the
   14.30   * pointer is not a valid code block, the return value is undefined.
   14.31   */
   14.32 -uint32_t xlat_get_block_size( void *ptr );
   14.33 +uint32_t FASTCALL xlat_get_block_size( void *ptr );
   14.34  
   14.35  /**
   14.36   * Retrieve the size of the code in the block starting at the specified 
   14.37 @@ -158,21 +158,21 @@
   14.38   * the recovery table. If the pointer is not a valid code block, the 
   14.39   * return value is undefined.
   14.40   */
   14.41 -uint32_t xlat_get_code_size( void *ptr );
   14.42 +uint32_t FASTCALL xlat_get_code_size( void *ptr );
   14.43  
   14.44  /**
   14.45   * Flush the code cache for the page containing the given address
   14.46   */
   14.47 -void xlat_flush_page( sh4addr_t address );
   14.48 +void FASTCALL xlat_flush_page( sh4addr_t address );
   14.49  
   14.50 -void xlat_invalidate_word( sh4addr_t address );
   14.51 -void xlat_invalidate_long( sh4addr_t address );
   14.52 +void FASTCALL xlat_invalidate_word( sh4addr_t address );
   14.53 +void FASTCALL xlat_invalidate_long( sh4addr_t address );
   14.54  
   14.55  
   14.56  /**
   14.57   * Invalidate the code cache for a memory region
   14.58   */
   14.59 -void xlat_invalidate_block( sh4addr_t address, size_t bytes );
   14.60 +void FASTCALL xlat_invalidate_block( sh4addr_t address, size_t bytes );
   14.61  
   14.62  /**
   14.63   * Flush the entire code cache. This isn't as cheap as one might like

    15.1 --- a/src/test/testsh4x86.c	Wed Oct 29 23:36:31 2008 +0000
    15.2 +++ b/src/test/testsh4x86.c	Wed Oct 29 23:51:58 2008 +0000
    15.3 @@ -58,15 +58,15 @@
    15.4      { "_sh4_write_long", sh4_write_long }
    15.5  };
    15.6  
    15.7 -int32_t sh4_read_byte( uint32_t addr ) 
    15.8 +int32_t FASTCALL sh4_read_byte( uint32_t addr ) 
    15.9  {
   15.10      return *(uint8_t *)(inbuf+(addr-start_addr));
   15.11  }
   15.12 -int32_t sh4_read_word( uint32_t addr ) 
   15.13 +int32_t FASTCALL sh4_read_word( uint32_t addr ) 
   15.14  {
   15.15      return *(uint16_t *)(inbuf+(addr-start_addr));
   15.16  }
   15.17 -int32_t sh4_read_long( uint32_t addr ) 
   15.18 +int32_t FASTCALL sh4_read_long( uint32_t addr ) 
   15.19  {
   15.20      return *(uint32_t *)(inbuf+(addr-start_addr));
   15.21  }
   15.22 @@ -83,27 +83,27 @@
   15.23  void TMU_run_slice( uint32_t nanos ) {}
   15.24  void PMM_write_control( int ctr, uint32_t val ) { }
   15.25  void SCIF_run_slice( uint32_t nanos ) {}
   15.26 -void sh4_write_byte( uint32_t addr, uint32_t val ) {}
   15.27 -void sh4_write_word( uint32_t addr, uint32_t val ) {}
   15.28 -void sh4_write_long( uint32_t addr, uint32_t val ) {}
   15.29 -void sh4_write_fpscr( uint32_t val ) { }
   15.30 +void FASTCALL sh4_write_byte( uint32_t addr, uint32_t val ) {}
   15.31 +void FASTCALL sh4_write_word( uint32_t addr, uint32_t val ) {}
   15.32 +void FASTCALL sh4_write_long( uint32_t addr, uint32_t val ) {}
   15.33 +void FASTCALL sh4_write_fpscr( uint32_t val ) { }
   15.34 +void FASTCALL sh4_write_sr( uint32_t val ) { }
   15.35 +uint32_t FASTCALL sh4_read_sr( void ) { return 0; }
   15.36 +void FASTCALL sh4_sleep() { }
   15.37 +void FASTCALL sh4_fsca( uint32_t angle, float *fr ) { }
   15.38 +void FASTCALL sh4_ftrv( float *fv ) { }
   15.39 +void FASTCALL signsat48(void) { }
   15.40  void sh4_switch_fr_banks() { }
   15.41  void mem_copy_to_sh4( sh4addr_t addr, sh4ptr_t src, size_t size ) { }
   15.42 -void sh4_write_sr( uint32_t val ) { }
   15.43  gboolean sh4_has_page( sh4vma_t vma ) { return TRUE; }
   15.44  void syscall_invoke( uint32_t val ) { }
   15.45  void dreamcast_stop() {} 
   15.46  void dreamcast_reset() {}
   15.47 -uint32_t sh4_read_sr( void ) { return 0; }
   15.48 -gboolean sh4_raise_reset( int exc ) { return TRUE; }
   15.49 -gboolean sh4_raise_exception( int exc ) { return TRUE; }
   15.50 -gboolean sh4_raise_tlb_exception( int exc ) { return TRUE; }
   15.51 -gboolean sh4_raise_trap( int exc ) { return TRUE; }
   15.52 -void sh4_sleep() { }
   15.53 +gboolean FASTCALL sh4_raise_reset( int exc ) { return TRUE; }
   15.54 +gboolean FASTCALL sh4_raise_exception( int exc ) { return TRUE; }
   15.55 +gboolean FASTCALL sh4_raise_tlb_exception( int exc ) { return TRUE; }
   15.56 +gboolean FASTCALL sh4_raise_trap( int exc ) { return TRUE; }
   15.57  uint32_t sh4_sleep_run_slice(uint32_t nanosecs) { return nanosecs; }
   15.58 -void sh4_fsca( uint32_t angle, float *fr ) { }
   15.59 -void sh4_ftrv( float *fv ) { }
   15.60 -void signsat48(void) { }
   15.61  gboolean gui_error_dialog( const char *fmt, ... ) { return TRUE; }
   15.62  struct sh4_icache_struct sh4_icache;
   15.63