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lxdream.org :: lxdream :: r728:4dfc293b9d96
lxdream 0.9.1
released Jun 29
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changeset728:4dfc293b9d96
parent727:f934967b77a3
child729:4cc913eabd3d
authornkeynes
dateSun Jul 06 05:30:32 2008 +0000 (11 years ago)
Add register defns for sort DMA
Add register defn for 005F81AC to match the test
src/asic.c
src/asic.h
src/pvr2/pvr2.c
src/pvr2/pvr2mmio.h
test/testregs.c
1.1 --- a/src/asic.c Sun Jul 06 04:52:37 2008 +0000
1.2 +++ b/src/asic.c Sun Jul 06 05:30:32 2008 +0000
1.3 @@ -350,6 +350,16 @@
1.4 asic_event( EVENT_PVR_DMA );
1.5 }
1.6
1.7 +void sort_dma_transfer( )
1.8 +{
1.9 + sh4addr_t table_addr = MMIO_READ( ASIC, SORTDMATBL );
1.10 + sh4addr_t data_addr = MMIO_READ( ASIC, SORTDMADATA );
1.11 + int table_size = MMIO_READ( ASIC, SORTDMATSIZ );
1.12 + int data_size = MMIO_READ( ASIC, SORTDMADSIZ );
1.13 +
1.14 + WARN( "Sort DMA not implemented" );
1.15 +}
1.16 +
1.17 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )
1.18 {
1.19 switch( reg ) {
1.20 @@ -409,7 +419,19 @@
1.21 pvr_dma_transfer();
1.22 }
1.23 break;
1.24 -
1.25 + case SORTDMATBL: case SORTDMADATA:
1.26 + MMIO_WRITE( ASIC, reg, (val & 0x0FFFFFE0) | 0x08000000 );
1.27 + break;
1.28 + case SORTDMATSIZ: case SORTDMADSIZ:
1.29 + MMIO_WRITE( ASIC, reg, (val & 1) );
1.30 + break;
1.31 + case SORTDMACTL:
1.32 + val = val & 1;
1.33 + MMIO_WRITE( ASIC, reg, val );
1.34 + if( val == 1 ) {
1.35 + sort_dma_transfer();
1.36 + }
1.37 + break;
1.38 case MAPLE_DMA:
1.39 MMIO_WRITE( ASIC, reg, val );
1.40 break;
2.1 --- a/src/asic.h Sun Jul 06 04:52:37 2008 +0000
2.2 +++ b/src/asic.h Sun Jul 06 05:30:32 2008 +0000
2.3 @@ -29,11 +29,11 @@
2.4 LONG_PORT( 0x800, PVRDMADEST, PORT_MRW, 0, "PVR DMA Dest Address" )
2.5 LONG_PORT( 0x804, PVRDMACNT, PORT_MRW, 0, "PVR DMA Byte Count" )
2.6 LONG_PORT( 0x808, PVRDMACTL, PORT_MRW, 0, "PVR DMA Control" )
2.7 - LONG_PORT( 0x810, ASICUNK1, PORT_MRW, 0, "ASIC <unknown1 - host address?>" )
2.8 - LONG_PORT( 0x814, ASICUNK2, PORT_MRW, 0, "ASIC <unknown2 - host address?>" )
2.9 - LONG_PORT( 0x818, ASICUNK3, PORT_MRW, 0, "ASIC <unknown3>" )
2.10 - LONG_PORT( 0x81C, ASICUNK4, PORT_MRW, 0, "ASIC <unknown4>" )
2.11 - LONG_PORT( 0x820, ASICUNKF, PORT_MRW, 0, "ASIC <unknownF>" )
2.12 + LONG_PORT( 0x810, SORTDMATBL, PORT_MRW, 0, "Sort DMA Table address" )
2.13 + LONG_PORT( 0x814, SORTDMADATA, PORT_MRW, 0, "Sort DMA Data base address" )
2.14 + LONG_PORT( 0x818, SORTDMATSIZ, PORT_MRW, 0, "Sort DMA Table entry size" )
2.15 + LONG_PORT( 0x81C, SORTDMADSIZ, PORT_MRW, 0, "Sort DMA Data size" )
2.16 + LONG_PORT( 0x820, SORTDMACTL, PORT_MRW, 0, "Sort DMA Control" )
2.17 LONG_PORT( 0x840, ASICUNK5, PORT_MRW, 0, "ASIC <unknown5>" )
2.18 LONG_PORT( 0x844, ASICUNK6, PORT_MRW, 0, "ASIC <unknown6>" )
2.19 LONG_PORT( 0x848, ASICUNK7, PORT_MRW, 0, "ASIC <unknown7>" )
3.1 --- a/src/pvr2/pvr2.c Sun Jul 06 04:52:37 2008 +0000
3.2 +++ b/src/pvr2/pvr2.c Sun Jul 06 05:30:32 2008 +0000
3.3 @@ -694,6 +694,9 @@
3.4 case PVRUNK7:
3.5 MMIO_WRITE( PVR2, reg, val&0x00000001 );
3.6 break;
3.7 + case PVRUNK8:
3.8 + MMIO_WRITE( PVR2, reg, val&0x0300FFFF );
3.9 + break;
3.10 }
3.11 }
3.12
4.1 --- a/src/pvr2/pvr2mmio.h Sun Jul 06 04:52:37 2008 +0000
4.2 +++ b/src/pvr2/pvr2mmio.h Sun Jul 06 05:30:32 2008 +0000
4.3 @@ -88,6 +88,7 @@
4.4 LONG_PORT( 0x160, TA_REINIT, PORT_W, 0, "TA re-initialize" )
4.5 LONG_PORT( 0x164, TA_LISTBASE, PORT_MRW, 0, "TA Tile list start" )
4.6 LONG_PORT( 0x1A8, PVRUNK7, PORT_MRW, 0, "PVR2 unknown register 7" )
4.7 + LONG_PORT( 0x1AC, PVRUNK8, PORT_MRW, 0, "PVR2 unknown register 8" )
4.8 MMIO_REGION_END
4.9
4.10 MMIO_REGION_BEGIN( 0x005F9000, PVR2PAL, "Power VR/2 CLUT Palettes" )
5.1 --- a/test/testregs.c Sun Jul 06 04:52:37 2008 +0000
5.2 +++ b/test/testregs.c Sun Jul 06 05:30:32 2008 +0000
5.3 @@ -40,6 +40,12 @@
5.4 // { 0xA05F6808, 0xFFFFFFFF, 0x00000001 },
5.5 // { 0xA05F6808, 0x00000000, 0x00000000 }, // DMA start
5.6 // { 0xA05F680C, 0xFFFFFFFF, 0x00000000 }, // Not a register afaik
5.7 + { 0xA05F6810, 0x00000000, 0x08000000 },
5.8 + { 0xA05F6810, 0xFFFFFFFF, 0x0FFFFFE0 },
5.9 + { 0xA05F6814, 0x00000000, 0x08000000 },
5.10 + { 0xA05F6814, 0xFFFFFFFF, 0x0FFFFFE0 },
5.11 + { 0xA05F6818, 0xFFFFFFFF, 0x00000001 },
5.12 + { 0xA05F681C, 0xFFFFFFFF, 0x00000001 },
5.13 // { 0xA05F7400, 0xFFFFFFFF, 0x00000000 }, // Not a register
5.14 { 0xA05F7404, 0xFFFFFFFF, 0x1FFFFFE0 },
5.15 { 0xA05F7404, 0x00000000, 0x00000000 },
5.16 @@ -165,7 +171,7 @@
5.17 { 0xA05F81A4, 0xFFFFFFFF, 0 },
5.18 { 0xA05F81A8, 0xFFFFFFFF, 0x00000001 },
5.19 { 0xA05F81A8, 0x00000000, 0x00000000 },
5.20 - { 0xA05F81AC, 0xFFFFFFFF, 0 },
5.21 + { 0xA05F81AC, 0xFFFFFFFF, 0x0300FFFF },
5.22 { 0xA05F81B0, 0xFFFFFFFF, 0 },
5.23 { 0xA05F81B4, 0xFFFFFFFF, 0 },
5.24 { 0xA05F81B8, 0xFFFFFFFF, 0 },
.