lxdream 0.9.1revision 325:5717ae5d4746
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raw | bz2 | zip | gz | changeset | 325:5717ae5d4746 |
| parent | 324:340f0b0b7af3 |
| child | 326:0c107e0d0fe0 |
| author | nkeynes |
| date | Thu Jan 25 10:16:32 2007 +0000 (14 years ago) |
Move PVR2 dma handling (0x10000000-0x13FFFFFF) into pvr2mem.c, minor
register cleanups in asic.c
register cleanups in asic.c
 | src/asic.c | view | annotate | diff | log | |
| src/asic.h | view | annotate | diff | log | |
| src/pvr2/pvr2.h | view | annotate | diff | log | |
| src/pvr2/pvr2mem.c | view | annotate | diff | log | |
| src/sh4/sh4mem.c | view | annotate | diff | log |
1.1 --- a/src/asic.c Thu Jan 25 10:12:54 2007 +00001.2 +++ b/src/asic.c Thu Jan 25 10:16:32 2007 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: asic.c,v 1.25 2007-01-18 11:14:01 nkeynes Exp $1.6 + * $Id: asic.c,v 1.26 2007-01-25 10:16:32 nkeynes Exp $1.7 *1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,1.9 * and DMA).1.10 @@ -303,9 +303,26 @@1.11 MMIO_WRITE( EXTDMA, IDEDMACTL2, 0 );1.12 }1.13 }1.14 -1.15 }1.17 +void pvr_dma_transfer( )1.18 +{1.19 + sh4addr_t destaddr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;1.20 + uint32_t count = MMIO_READ( ASIC, PVRDMACNT );1.21 + char *data = alloca( count );1.22 + uint32_t rcount = DMAC_get_buffer( 2, data, count );1.23 + if( rcount != count )1.24 + WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );1.25 +1.26 + pvr2_dma_write( destaddr, data, rcount );1.27 +1.28 + MMIO_WRITE( ASIC, PVRDMACTL, 0 );1.29 + MMIO_WRITE( ASIC, PVRDMACNT, 0 );1.30 + if( destaddr & 0x01000000 ) { /* Write to texture RAM */1.31 + MMIO_WRITE( ASIC, PVRDMADEST, destaddr + rcount );1.32 + }1.33 + asic_event( EVENT_PVR_DMA );1.34 +}1.36 void mmio_region_ASIC_write( uint32_t reg, uint32_t val )1.37 {1.38 @@ -342,22 +359,20 @@1.39 MMIO_WRITE( ASIC, reg, 0 );1.40 }1.41 break;1.42 + case PVRDMADEST:1.43 + MMIO_WRITE( ASIC, reg, (val & 0x03FFFFE0) | 0x10000000 );1.44 + break;1.45 + case PVRDMACNT:1.46 + MMIO_WRITE( ASIC, reg, val & 0x00FFFFE0 );1.47 + break;1.48 case PVRDMACTL: /* Initiate PVR DMA transfer */1.49 + val = val & 0x01;1.50 MMIO_WRITE( ASIC, reg, val );1.51 - if( val & 1 ) {1.52 - uint32_t dest_addr = MMIO_READ( ASIC, PVRDMADEST) &0x1FFFFFE0;1.53 - uint32_t count = MMIO_READ( ASIC, PVRDMACNT );1.54 - char *data = alloca( count );1.55 - uint32_t rcount = DMAC_get_buffer( 2, data, count );1.56 - if( rcount != count )1.57 - WARN( "PVR received %08X bytes from DMA, expected %08X", rcount, count );1.58 - mem_copy_to_sh4( dest_addr, data, rcount );1.59 - asic_event( EVENT_PVR_DMA );1.60 - MMIO_WRITE( ASIC, PVRDMACTL, 0 );1.61 - MMIO_WRITE( ASIC, PVRDMACNT, 0 );1.62 + if( val == 1 ) {1.63 + pvr_dma_transfer();1.64 }1.65 break;1.66 - case PVRDMADEST: case PVRDMACNT: case MAPLE_DMA:1.67 + case MAPLE_DMA:1.68 MMIO_WRITE( ASIC, reg, val );1.69 break;1.70 default:
2.1 --- a/src/asic.h Thu Jan 25 10:12:54 2007 +00002.2 +++ b/src/asic.h Thu Jan 25 10:16:32 2007 +00002.3 @@ -1,5 +1,5 @@2.4 /**2.5 - * $Id: asic.h,v 1.18 2007-01-18 11:14:01 nkeynes Exp $2.6 + * $Id: asic.h,v 1.19 2007-01-25 10:16:32 nkeynes Exp $2.7 *2.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,2.9 * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions,2.10 @@ -38,8 +38,8 @@2.11 LONG_PORT( 0x844, ASICUNK6, PORT_MRW, 0, "ASIC <unknown6>" )2.12 LONG_PORT( 0x848, ASICUNK7, PORT_MRW, 0, "ASIC <unknown7>" )2.13 LONG_PORT( 0x84C, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )2.14 - LONG_PORT( 0x884, PVRDMARGN, PORT_MRW, 0, "PVR DMA Dest region" )2.15 - LONG_PORT( 0x888, ASICUNKA, PORT_MRW, 0, "ASIC <unknownA>" )2.16 + LONG_PORT( 0x884, PVRDMARGN1, PORT_MRW, 0, "PVR DMA Dest region 1" )2.17 + LONG_PORT( 0x888, PVRDMARGN2, PORT_MRW, 0, "PVR DMA Dest region 2" )2.18 LONG_PORT( 0x88C, G2STATUS, PORT_MR|PORT_NOTRACE, 0x0E, "G2 Fifo status" )2.19 LONG_PORT( 0x890, SYSRESET, PORT_W, 0, "System reset port" )2.20 LONG_PORT( 0x89C, ASICUNKB, PORT_MRW, 0xB, "Unknown, always 0xB?" )
3.1 --- a/src/pvr2/pvr2.h Thu Jan 25 10:12:54 2007 +00003.2 +++ b/src/pvr2/pvr2.h Thu Jan 25 10:16:32 2007 +00003.3 @@ -1,5 +1,5 @@3.4 /**3.5 - * $Id: pvr2.h,v 1.27 2007-01-25 08:18:03 nkeynes Exp $3.6 + * $Id: pvr2.h,v 1.28 2007-01-25 10:16:32 nkeynes Exp $3.7 *3.8 * PVR2 (video chip) functions and macros.3.9 *3.10 @@ -112,6 +112,12 @@3.11 /****************************** Frame Buffer *****************************/3.13 /**3.14 + * Write a block of data to an address in the DMA range (0x10000000 -3.15 + * 0x13FFFFFF), ie TA, YUV, or texture ram.3.16 + */3.17 +void pvr2_dma_write( sh4addr_t dest, char *src, uint32_t length );3.18 +3.19 +/**3.20 * Write to the interleaved memory address space (aka 64-bit address space).3.21 */3.22 void pvr2_vram64_write( sh4addr_t dest, char *src, uint32_t length );
4.1 --- a/src/pvr2/pvr2mem.c Thu Jan 25 10:12:54 2007 +00004.2 +++ b/src/pvr2/pvr2mem.c Thu Jan 25 10:16:32 2007 +00004.3 @@ -1,5 +1,5 @@4.4 /**4.5 - * $Id: pvr2mem.c,v 1.5 2007-01-23 11:19:32 nkeynes Exp $4.6 + * $Id: pvr2mem.c,v 1.6 2007-01-25 10:16:32 nkeynes Exp $4.7 *4.8 * PVR2 (Video) VRAM handling routines (mainly for the 64-bit region)4.9 *4.10 @@ -16,11 +16,47 @@4.11 * GNU General Public License for more details.4.12 */4.13 #include "pvr2.h"4.14 +#include "asic.h"4.15 #include <stdio.h>4.16 #include <errno.h>4.18 extern char *video_base;4.20 +void pvr2_dma_write( sh4addr_t destaddr, char *src, uint32_t count )4.21 +{4.22 + int region;4.23 +4.24 + switch( destaddr & 0x13800000 ) {4.25 + case 0x10000000:4.26 + case 0x12000000:4.27 + pvr2_ta_write( src, count );4.28 + break;4.29 + case 0x11000000:4.30 + case 0x11800000:4.31 + region = MMIO_READ( ASIC, PVRDMARGN1 );4.32 + if( region == 0 ) {4.33 + pvr2_vram64_write( destaddr, src, count );4.34 + } else {4.35 + char *dest = mem_get_region(destaddr);4.36 + memcpy( dest, src, count );4.37 + }4.38 + break;4.39 + case 0x10800000:4.40 + case 0x12800000:4.41 + pvr2_yuv_write( src, count );4.42 + break;4.43 + case 0x13000000:4.44 + case 0x13800000:4.45 + region = MMIO_READ( ASIC, PVRDMARGN2 );4.46 + if( region == 0 ) {4.47 + pvr2_vram64_write( destaddr, src, count );4.48 + } else {4.49 + char *dest = mem_get_region(destaddr);4.50 + memcpy( dest, src, count );4.51 + }4.52 + }4.53 +}4.54 +4.55 void pvr2_vram64_write( sh4addr_t destaddr, char *src, uint32_t length )4.56 {4.57 int bank_flag = (destaddr & 0x04) >> 2;
5.1 --- a/src/sh4/sh4mem.c Thu Jan 25 10:12:54 2007 +00005.2 +++ b/src/sh4/sh4mem.c Thu Jan 25 10:16:32 2007 +00005.3 @@ -1,5 +1,5 @@5.4 /**5.5 - * $Id: sh4mem.c,v 1.18 2007-01-23 11:20:26 nkeynes Exp $5.6 + * $Id: sh4mem.c,v 1.19 2007-01-25 10:16:32 nkeynes Exp $5.7 * sh4mem.c is responsible for the SH4's access to memory (including memory5.8 * mapped I/O), using the page maps created in mem.c5.9 *5.10 @@ -371,22 +371,21 @@5.11 }5.13 void mem_copy_to_sh4( uint32_t destaddr, char *src, size_t count ) {5.14 - if( destaddr >= 0x10000000 && destaddr < 0x10800000 ) {5.15 - pvr2_ta_write( src, count );5.16 - } else if( destaddr >= 0x10800000 && destaddr < 0x11000000 ) {5.17 - /* YUV data */5.18 - pvr2_yuv_write( src, count );5.19 - } else if( destaddr >= 0x04000000 && destaddr < 0x05000000 ||5.20 - destaddr >= 0x11000000 && destaddr < 0x12000000 ) {5.21 + int region;5.22 +5.23 + if( destaddr >= 0x10000000 && destaddr < 0x14000000 ) {5.24 + pvr2_dma_write( destaddr, src, count );5.25 + return;5.26 + } else if( (destaddr & 0x1F800000) == 0x05000000 ) {5.27 + pvr2_render_buffer_invalidate( destaddr );5.28 + } else if( (destaddr & 0x1F800000) == 0x04000000 ) {5.29 pvr2_vram64_write( destaddr, src, count );5.30 - } else {5.31 - if( (destaddr & 0x1F800000) == 0x05000000 )5.32 - pvr2_render_buffer_invalidate( destaddr );5.33 - char *dest = mem_get_region(destaddr);5.34 - if( dest == NULL )5.35 - ERROR( "Attempted block write to unknown address %08X", destaddr );5.36 - else {5.37 - memcpy( dest, src, count );5.38 - }5.39 + return;5.40 + }5.41 + char *dest = mem_get_region(destaddr);5.42 + if( dest == NULL )5.43 + ERROR( "Attempted block write to unknown address %08X", destaddr );5.44 + else {5.45 + memcpy( dest, src, count );5.46 }5.47 }
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