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lxdream.org :: lxdream :: r172:59cf18b4cfb2
lxdream 0.9.1
released Jun 29
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changeset172:59cf18b4cfb2
parent171:3542185a8cf9
child173:b006aaba9dff
authornkeynes
dateTue Jun 27 11:02:48 2006 +0000 (13 years ago)
Add register-by-register NOTRACE option (useful for tracing eg 0xA05F6000
without the ridiculous traffic certain status ports get...)
src/asic.h
src/mmio.h
src/sh4/sh4mem.c
1.1 --- a/src/asic.h Tue Jun 27 09:34:27 2006 +0000
1.2 +++ b/src/asic.h Tue Jun 27 11:02:48 2006 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: asic.h,v 1.10 2006-06-15 10:32:38 nkeynes Exp $
1.6 + * $Id: asic.h,v 1.11 2006-06-27 11:02:46 nkeynes Exp $
1.7 *
1.8 * Support for the miscellaneous ASIC functions (Primarily event multiplexing,
1.9 * and DMA). Includes MMIO definitions for the 5f6000 and 5f7000 regions,
1.10 @@ -40,12 +40,12 @@
1.11 LONG_PORT( 0x84C, ASICUNK8, PORT_MRW, 0, "ASIC <unknown8>" )
1.12 LONG_PORT( 0x884, ASICUNK9, PORT_MRW, 0, "ASIC <unknown9>" )
1.13 LONG_PORT( 0x888, ASICUNKA, PORT_MRW, 0, "ASIC <unknownA>" )
1.14 - LONG_PORT( 0x88C, G2STATUS, PORT_MR, 0, "G2 Bus status" )
1.15 + LONG_PORT( 0x88C, G2STATUS, PORT_MR|PORT_NOTRACE, 0, "G2 Bus status" )
1.16 LONG_PORT( 0x89C, ASICUNKB, PORT_MRW, 0xB, "Unknown, always 0xB?" )
1.17 LONG_PORT( 0x8A0, ASICUNKC, PORT_MRW, 0, "ASIC <unknownC>" )
1.18 LONG_PORT( 0x8A4, ASICUNKD, PORT_MRW, 0, "ASIC <unknownD>" )
1.19 LONG_PORT( 0x8AC, ASICUNKE, PORT_MRW, 0, "ASIC <unknownE>" )
1.20 - LONG_PORT( 0x900, PIRQ0, PORT_MRW, 0, "Pending interrupts 0" )
1.21 + LONG_PORT( 0x900, PIRQ0, PORT_MRW|PORT_NOTRACE, 0, "Pending interrupts 0" )
1.22 LONG_PORT( 0x904, PIRQ1, PORT_MRW, 0, "Pending interrupts 1" )
1.23 LONG_PORT( 0x908, PIRQ2, PORT_MRW, 0, "Pending interrupts 2" )
1.24 LONG_PORT( 0x910, IRQA0, PORT_MRW, 0, "IRQ A event map 0" )
1.25 @@ -113,7 +113,7 @@
1.26 LONG_PORT( 0x4A0, EXTDMAUNK6, PORT_MRW, 0, "Ext DMA <unknown6>" )
1.27 LONG_PORT( 0x4A4, EXTDMAUNK7, PORT_MRW, 0, "Ext DMA <unknown7>" )
1.28 LONG_PORT( 0x4B4, EXTDMAUNK8, PORT_MRW, 0, "Ext DMA <unknown8>" )
1.29 - LONG_PORT( 0x4B8, IDEDMACFG, PORT_MRW, 0, "IDE DMA Config" )
1.30 + LONG_PORT( 0x4B8, IDEDMACFG, PORT_MRW, 0, "IDE DMA Config" ) /* 88437F00 */
1.31 LONG_PORT( 0x4E4, IDEACTIVATE, PORT_MRW, 0, "IDE activate" )
1.32 LONG_PORT( 0x4F8, IDEDMATXSIZ, PORT_MRW, 0, "IDE DMA transfered size" )
1.33 LONG_PORT( 0x800, SPUDMA0EXT, PORT_MRW, 0, "SPU DMA0 External address" )
1.34 @@ -159,7 +159,7 @@
1.35 LONG_PORT( 0x8B0, SPUDMAUN8, PORT_MRW, 0, "SPU DMA <unknown8>" )
1.36 LONG_PORT( 0x8B4, SPUDMAUN9, PORT_MRW, 0, "SPU DMA <unknown9>" )
1.37 LONG_PORT( 0x8B8, SPUDMAUN10, PORT_MRW, 0, "SPU DMA <unknown10>" )
1.38 - LONG_PORT( 0x8BC, SPUDMAUN11, PORT_MRW, 0, "SPU DMA <unknown11>" )
1.39 + LONG_PORT( 0x8BC, SPUDMACFG, PORT_MRW, 0, "SPU DMA Config" ) /* 46597F00 */
1.40 LONG_PORT( 0xC00, PVRDMA2EXT, PORT_MRW, 0, "PVR DMA External address" )
1.41 LONG_PORT( 0xC04, PVRDMA2SH4, PORT_MRW, 0, "PVR DMA SH4 address" )
1.42 LONG_PORT( 0xC08, PVRDMA2SIZ, PORT_MRW, 0, "PVR DMA Size" )
1.43 @@ -167,7 +167,7 @@
1.44 LONG_PORT( 0xC10, PVRDMA2MOD, PORT_MRW, 0, "PVR DMA Mode" )
1.45 LONG_PORT( 0xC14, PVRDMA2CTL1, PORT_MRW, 0, "PVR DMA Control 1" )
1.46 LONG_PORT( 0xC18, PVRDMA2CTL2, PORT_MRW, 0, "PVR DMA Control 2" )
1.47 - LONG_PORT( 0xC80, PVRDMA2CFG, PORT_MRW, 0, "PVR DMA Config" )
1.48 + LONG_PORT( 0xC80, PVRDMA2CFG, PORT_MRW, 0, "PVR DMA Config" ) /* 67027F00 */
1.49
1.50 MMIO_REGION_END
1.51
2.1 --- a/src/mmio.h Tue Jun 27 09:34:27 2006 +0000
2.2 +++ b/src/mmio.h Tue Jun 27 11:02:48 2006 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: mmio.h,v 1.5 2006-06-15 10:25:42 nkeynes Exp $
2.6 + * $Id: mmio.h,v 1.6 2006-06-27 11:02:46 nkeynes Exp $
2.7 *
2.8 * mmio.h defines a complicated batch of macros used to build up the
2.9 * memory-mapped I/O regions in a reasonably readable fashion.
2.10 @@ -39,6 +39,7 @@
2.11 #define PORT_RW 3
2.12 #define PORT_MR 5
2.13 #define PORT_MRW 7
2.14 +#define PORT_NOTRACE 16
2.15 #define UNDEFINED 0xDEADBEEF /* This has to be a value that nothing inits to */
2.16
2.17 struct mmio_region {
2.18 @@ -81,12 +82,16 @@
2.19 io_rgn[mid]->index[(r)>>2]->id : "<UNDEF>" )
2.20 #define MMIO_REGDESC_BYNUM( mid, r ) (io_rgn[mid]->index[(r)>>2] != NULL ? \
2.21 io_rgn[mid]->index[(r)>>2]->desc : "Undefined register" )
2.22 +#define MMIO_NOTRACE_BYNUM( mid, r ) (io_rgn[mid]->index[(r)>>2] != NULL ? \
2.23 + (io_rgn[mid]->index[(r)>>2]->flags & PORT_NOTRACE) : 0 )
2.24 #define MMIO_NAME_BYNUM( mid ) (io_rgn[mid]->id)
2.25
2.26 #define MMIO_REGID_IOBYNUM( io, r ) (io->index[(r)>>2] != NULL ? \
2.27 io->index[(r)>>2]->id : "<UNDEF>" )
2.28 #define MMIO_REGDESC_IOBYNUM( io, r ) (io->index[(r)>>2] != NULL ? \
2.29 io->index[(r)>>2]->desc : "Undefined register" )
2.30 +#define MMIO_NOTRACE_IOBYNUM( io, r ) (io->index[(r)>>2] != NULL ? \
2.31 + (io->index[(r)>>2]->flags & PORT_NOTRACE) : 0 )
2.32
2.33 #ifdef __cplusplus
2.34 }
3.1 --- a/src/sh4/sh4mem.c Tue Jun 27 09:34:27 2006 +0000
3.2 +++ b/src/sh4/sh4mem.c Tue Jun 27 11:02:48 2006 +0000
3.3 @@ -1,5 +1,5 @@
3.4 /**
3.5 - * $Id: sh4mem.c,v 1.13 2006-06-18 12:01:06 nkeynes Exp $
3.6 + * $Id: sh4mem.c,v 1.14 2006-06-27 11:02:48 nkeynes Exp $
3.7 * sh4mem.c is responsible for the SH4's access to memory (including memory
3.8 * mapped I/O), using the page maps created in mem.c
3.9 *
3.10 @@ -49,11 +49,11 @@
3.11 #define CHECK_WRITE_WATCH( addr, size )
3.12 #endif
3.13
3.14 -#define TRACE_IO( str, p, r, ... ) if(io_rgn[(uint32_t)p]->trace_flag) \
3.15 -TRACE( str " [%s.%s: %s]", __VA_ARGS__, \
3.16 +#define TRACE_IO( str, p, r, ... ) if(io_rgn[(uint32_t)p]->trace_flag && !MMIO_NOTRACE_BYNUM((uint32_t)p,r)) \
3.17 + TRACE( str " [%s.%s: %s]", __VA_ARGS__, \
3.18 MMIO_NAME_BYNUM((uint32_t)p), MMIO_REGID_BYNUM((uint32_t)p, r), \
3.19 MMIO_REGDESC_BYNUM((uint32_t)p, r) )
3.20 -#define TRACE_P4IO( str, io, r, ... ) if(io->trace_flag) \
3.21 +#define TRACE_P4IO( str, io, r, ... ) if(io->trace_flag && !MMIO_NOTRACE_IOBYNUM(io,r)) \
3.22 TRACE( str " [%s.%s: %s]", __VA_ARGS__, \
3.23 io->id, MMIO_REGID_IOBYNUM(io, r), \
3.24 MMIO_REGDESC_IOBYNUM(io, r) )
.