revision 991:60c7fab9c880
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raw | bz2 | zip | gz changeset | 991:60c7fab9c880 |
parent | 990:ae329de3c8ab |
child | 992:7c15f8a71995 |
author | nkeynes |
date | Wed Mar 04 23:12:21 2009 +0000 (15 years ago) |
Move xltcache to xlat/ src directory
Commit new and improved x86 opcode file - cleaned up and added support for amd64 extended registers
Commit new and improved x86 opcode file - cleaned up and added support for amd64 extended registers
src/Makefile.am | view | annotate | diff | log | ||
src/Makefile.in | view | annotate | diff | log | ||
src/sdram.c | view | annotate | diff | log | ||
src/sh4/ia32abi.h | view | annotate | diff | log | ||
src/sh4/ia64abi.h | view | annotate | diff | log | ||
src/sh4/mmux86.c | view | annotate | diff | log | ||
src/sh4/sh4.c | view | annotate | diff | log | ||
src/sh4/sh4mem.c | view | annotate | diff | log | ||
src/sh4/sh4trans.c | view | annotate | diff | log | ||
src/sh4/sh4trans.h | view | annotate | diff | log | ||
src/sh4/sh4x86.in | view | annotate | diff | log | ||
src/sh4/x86op.h | view | annotate | diff | log | ||
src/sh4/xltcache.c | view | annotate | diff | log | ||
src/sh4/xltcache.h | view | annotate | diff | log | ||
src/test/testxlt.c | view | annotate | diff | log | ||
src/xlat/x86/x86op.h | view | annotate | diff | log | ||
src/xlat/xltcache.c | view | annotate | diff | log | ||
src/xlat/xltcache.h | view | annotate | diff | log |
1.1 --- a/src/Makefile.am Wed Mar 04 23:04:54 2009 +00001.2 +++ b/src/Makefile.am Wed Mar 04 23:12:21 2009 +00001.3 @@ -45,7 +45,7 @@1.4 sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \1.5 sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \1.6 sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \1.7 - sh4/xltcache.c sh4/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \1.8 + xlat/xltcache.c xlat/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \1.9 sh4/cache.c sh4/mmu.h \1.10 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armdasm.h aica/armmem.c \1.11 aica/aica.c aica/aica.h aica/audio.c aica/audio.h \1.12 @@ -64,7 +64,7 @@1.15 if BUILD_SH4X861.16 -lxdream_SOURCES += sh4/sh4x86.c sh4/x86op.h \1.17 +lxdream_SOURCES += sh4/sh4x86.c xlat/x86/x86op.h \1.18 sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h \1.19 sh4/sh4trans.c sh4/sh4trans.h sh4/mmux86.c \1.20 x86dasm/x86dasm.c x86dasm/x86dasm.h \1.21 @@ -76,8 +76,8 @@1.22 test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \1.23 x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \1.24 x86dasm/dis-buf.c \1.25 - sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \1.26 - sh4/xltcache.h mem.c util.c1.27 + sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c \1.28 + xlat/xltcache.h mem.c util.c1.30 check_PROGRAMS += test/testsh4x861.31 endif1.32 @@ -155,7 +155,7 @@1.33 genglsl_LDADD = @GLIB_LIBS@ @GTK_LIBS@ $(INTLLIBS)1.36 -test_testxlt_SOURCES = test/testxlt.c sh4/xltcache.c sh4/xltcache.h1.37 +test_testxlt_SOURCES = test/testxlt.c xlat/xltcache.c xlat/xltcache.h1.39 sh4/sh4core.c: gendec sh4/sh4.def sh4/sh4core.in1.40 mkdir -p `dirname $@`
2.1 --- a/src/Makefile.in Wed Mar 04 23:04:54 2009 +00002.2 +++ b/src/Makefile.in Wed Mar 04 23:12:21 2009 +00002.3 @@ -39,7 +39,7 @@2.4 bin_PROGRAMS = lxdream$(EXEEXT)2.5 noinst_PROGRAMS = gendec$(EXEEXT) genglsl$(EXEEXT)2.6 check_PROGRAMS = test/testxlt$(EXEEXT) $(am__EXEEXT_1)2.7 -@BUILD_SH4X86_TRUE@am__append_1 = sh4/sh4x86.c sh4/x86op.h \2.8 +@BUILD_SH4X86_TRUE@am__append_1 = sh4/sh4x86.c xlat/x86/x86op.h \2.9 @BUILD_SH4X86_TRUE@ sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h \2.10 @BUILD_SH4X86_TRUE@ sh4/sh4trans.c sh4/sh4trans.h sh4/mmux86.c \2.11 @BUILD_SH4X86_TRUE@ x86dasm/x86dasm.c x86dasm/x86dasm.h \2.12 @@ -106,7 +106,7 @@2.13 sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c \2.14 sh4/dmac.c sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c \2.15 sh4/sh4dasm.h sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c \2.16 - sh4/sh4stat.c sh4/sh4stat.h sh4/xltcache.c sh4/xltcache.h \2.17 + sh4/sh4stat.c sh4/sh4stat.h xlat/xltcache.c xlat/xltcache.h \2.18 sh4/sh4.h sh4/dmac.h sh4/pmm.c sh4/cache.c sh4/mmu.h \2.19 aica/armcore.c aica/armcore.h aica/armdasm.c aica/armdasm.h \2.20 aica/armmem.c aica/aica.c aica/aica.h aica/audio.c \2.21 @@ -121,7 +121,7 @@2.22 display.h dckeysyms.h drivers/audio_null.c \2.23 drivers/video_null.c drivers/video_gl.c drivers/video_gl.h \2.24 drivers/gl_fbo.c sh4/sh4.def sh4/sh4core.in sh4/sh4x86.in \2.25 - sh4/sh4dasm.in sh4/sh4stat.in sh4/sh4x86.c sh4/x86op.h \2.26 + sh4/sh4dasm.in sh4/sh4stat.in sh4/sh4x86.c xlat/x86/x86op.h \2.27 sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h sh4/sh4trans.c \2.28 sh4/sh4trans.h sh4/mmux86.c x86dasm/x86dasm.c \2.29 x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \2.30 @@ -197,8 +197,8 @@2.31 lxdream_DEPENDENCIES = $(am__DEPENDENCIES_1)2.32 am__test_testsh4x86_SOURCES_DIST = test/testsh4x86.c x86dasm/x86dasm.c \2.33 x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \2.34 - x86dasm/dis-buf.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \2.35 - sh4/xltcache.h mem.c util.c2.36 + x86dasm/dis-buf.c sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c \2.37 + xlat/xltcache.h mem.c util.c2.38 @BUILD_SH4X86_TRUE@am_test_testsh4x86_OBJECTS = testsh4x86.$(OBJEXT) \2.39 @BUILD_SH4X86_TRUE@ x86dasm.$(OBJEXT) i386-dis.$(OBJEXT) \2.40 @BUILD_SH4X86_TRUE@ dis-init.$(OBJEXT) dis-buf.$(OBJEXT) \2.41 @@ -437,7 +437,7 @@2.42 sh4/sh4mem.c sh4/timer.c sh4/dmac.c sh4/mmu.c sh4/sh4core.c \2.43 sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h sh4/sh4mmio.c \2.44 sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \2.45 - sh4/xltcache.c sh4/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \2.46 + xlat/xltcache.c xlat/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \2.47 sh4/cache.c sh4/mmu.h aica/armcore.c aica/armcore.h \2.48 aica/armdasm.c aica/armdasm.h aica/armmem.c aica/aica.c \2.49 aica/aica.h aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \2.50 @@ -461,13 +461,13 @@2.51 @BUILD_SH4X86_TRUE@test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \2.52 @BUILD_SH4X86_TRUE@ x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \2.53 @BUILD_SH4X86_TRUE@ x86dasm/dis-buf.c \2.54 -@BUILD_SH4X86_TRUE@ sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \2.55 -@BUILD_SH4X86_TRUE@ sh4/xltcache.h mem.c util.c2.56 +@BUILD_SH4X86_TRUE@ sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c \2.57 +@BUILD_SH4X86_TRUE@ xlat/xltcache.h mem.c util.c2.59 lxdream_LDADD = @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@ @PULSE_LIBS@ @ESOUND_LIBS@ @ALSA_LIBS@ @SDL_LIBS@ $(INTLLIBS)2.60 gendec_LDADD = @GLIB_LIBS@ @GTK_LIBS@ $(INTLLIBS)2.61 genglsl_LDADD = @GLIB_LIBS@ @GTK_LIBS@ $(INTLLIBS)2.62 -test_testxlt_SOURCES = test/testxlt.c sh4/xltcache.c sh4/xltcache.h2.63 +test_testxlt_SOURCES = test/testxlt.c xlat/xltcache.c xlat/xltcache.h2.64 all: $(BUILT_SOURCES)2.65 $(MAKE) $(AM_MAKEFLAGS) all-am2.67 @@ -1003,19 +1003,19 @@2.68 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.69 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o sh4stat.obj `if test -f 'sh4/sh4stat.c'; then $(CYGPATH_W) 'sh4/sh4stat.c'; else $(CYGPATH_W) '$(srcdir)/sh4/sh4stat.c'; fi`2.71 -xltcache.o: sh4/xltcache.c2.72 -@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xltcache.o -MD -MP -MF "$(DEPDIR)/xltcache.Tpo" -c -o xltcache.o `test -f 'sh4/xltcache.c' || echo '$(srcdir)/'`sh4/xltcache.c; \2.73 +xltcache.o: xlat/xltcache.c2.74 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xltcache.o -MD -MP -MF "$(DEPDIR)/xltcache.Tpo" -c -o xltcache.o `test -f 'xlat/xltcache.c' || echo '$(srcdir)/'`xlat/xltcache.c; \2.75 @am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/xltcache.Tpo" "$(DEPDIR)/xltcache.Po"; else rm -f "$(DEPDIR)/xltcache.Tpo"; exit 1; fi2.76 -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/xltcache.c' object='xltcache.o' libtool=no @AMDEPBACKSLASH@2.77 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/xltcache.c' object='xltcache.o' libtool=no @AMDEPBACKSLASH@2.78 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.79 -@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xltcache.o `test -f 'sh4/xltcache.c' || echo '$(srcdir)/'`sh4/xltcache.c2.80 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xltcache.o `test -f 'xlat/xltcache.c' || echo '$(srcdir)/'`xlat/xltcache.c2.82 -xltcache.obj: sh4/xltcache.c2.83 -@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xltcache.obj -MD -MP -MF "$(DEPDIR)/xltcache.Tpo" -c -o xltcache.obj `if test -f 'sh4/xltcache.c'; then $(CYGPATH_W) 'sh4/xltcache.c'; else $(CYGPATH_W) '$(srcdir)/sh4/xltcache.c'; fi`; \2.84 +xltcache.obj: xlat/xltcache.c2.85 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xltcache.obj -MD -MP -MF "$(DEPDIR)/xltcache.Tpo" -c -o xltcache.obj `if test -f 'xlat/xltcache.c'; then $(CYGPATH_W) 'xlat/xltcache.c'; else $(CYGPATH_W) '$(srcdir)/xlat/xltcache.c'; fi`; \2.86 @am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/xltcache.Tpo" "$(DEPDIR)/xltcache.Po"; else rm -f "$(DEPDIR)/xltcache.Tpo"; exit 1; fi2.87 -@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='sh4/xltcache.c' object='xltcache.obj' libtool=no @AMDEPBACKSLASH@2.88 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/xltcache.c' object='xltcache.obj' libtool=no @AMDEPBACKSLASH@2.89 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@2.90 -@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xltcache.obj `if test -f 'sh4/xltcache.c'; then $(CYGPATH_W) 'sh4/xltcache.c'; else $(CYGPATH_W) '$(srcdir)/sh4/xltcache.c'; fi`2.91 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xltcache.obj `if test -f 'xlat/xltcache.c'; then $(CYGPATH_W) 'xlat/xltcache.c'; else $(CYGPATH_W) '$(srcdir)/xlat/xltcache.c'; fi`2.93 pmm.o: sh4/pmm.c2.94 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT pmm.o -MD -MP -MF "$(DEPDIR)/pmm.Tpo" -c -o pmm.o `test -f 'sh4/pmm.c' || echo '$(srcdir)/'`sh4/pmm.c; \
3.1 --- a/src/sdram.c Wed Mar 04 23:04:54 2009 +00003.2 +++ b/src/sdram.c Wed Mar 04 23:12:21 2009 +00003.3 @@ -20,7 +20,7 @@3.4 #include "lxdream.h"3.5 #include "mem.h"3.6 #include "dreamcast.h"3.7 -#include "sh4/xltcache.h"3.8 +#include "xlat/xltcache.h"3.9 #include <string.h>
4.1 --- a/src/sh4/ia32abi.h Wed Mar 04 23:04:54 2009 +00004.2 +++ b/src/sh4/ia32abi.h Wed Mar 04 23:12:21 2009 +00004.3 @@ -27,9 +27,9 @@4.4 static inline void decode_address( int addr_reg )4.5 {4.6 uintptr_t base = (sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space;4.7 - MOV_r32_r32( addr_reg, R_ECX );4.8 - SHR_imm8_r32( 12, R_ECX );4.9 - MOV_r32disp32x4_r32( R_ECX, base, R_ECX );4.10 + MOVL_r32_r32( addr_reg, REG_ECX );4.11 + SHRL_imm_r32( 12, REG_ECX );4.12 + MOVP_sib_rptr( 2, REG_ECX, -1, base, REG_ECX );4.13 }4.15 /**4.16 @@ -38,134 +38,138 @@4.17 */4.18 static inline void call_func0( void *ptr )4.19 {4.20 - load_imm32(R_ECX, (uint32_t)ptr);4.21 - CALL_r32(R_ECX);4.22 + load_imm32(REG_ECX, (uint32_t)ptr);4.23 + CALL_r32(REG_ECX);4.24 }4.26 #ifdef HAVE_FASTCALL4.27 static inline void call_func1( void *ptr, int arg1 )4.28 {4.29 - if( arg1 != R_EAX ) {4.30 - MOV_r32_r32( arg1, R_EAX );4.31 + if( arg1 != REG_EAX ) {4.32 + MOVL_r32_r32( arg1, REG_EAX );4.33 }4.34 - load_imm32(R_ECX, (uint32_t)ptr);4.35 - CALL_r32(R_ECX);4.36 + MOVP_immptr_rptr((uintptr_t)ptr, REG_ECX);4.37 + CALL_r32(REG_ECX);4.38 }4.40 static inline void call_func1_r32( int addr_reg, int arg1 )4.41 {4.42 - if( arg1 != R_EAX ) {4.43 - MOV_r32_r32( arg1, R_EAX );4.44 + if( arg1 != REG_EAX ) {4.45 + MOVL_r32_r32( arg1, REG_EAX );4.46 }4.47 CALL_r32(addr_reg);4.48 }4.50 static inline void call_func1_r32disp8( int preg, uint32_t disp8, int arg1 )4.51 {4.52 - if( arg1 != R_EAX ) {4.53 - MOV_r32_r32( arg1, R_EAX );4.54 + if( arg1 != REG_EAX ) {4.55 + MOVL_r32_r32( arg1, REG_EAX );4.56 }4.57 - CALL_r32disp8(preg, disp8);4.58 + CALL_r32disp(preg, disp8);4.59 }4.61 static inline void call_func1_r32disp8_exc( int preg, uint32_t disp8, int arg1, int pc )4.62 {4.63 - if( arg1 != R_EAX ) {4.64 - MOV_r32_r32( arg1, R_EAX );4.65 + if( arg1 != REG_EAX ) {4.66 + MOVL_r32_r32( arg1, REG_EAX );4.67 }4.68 - load_exc_backpatch(R_EDX);4.69 - CALL_r32disp8(preg, disp8);4.70 + MOVP_immptr_rptr(0,REG_EDX);4.71 + sh4_x86_add_backpatch(xlat_output, pc, -2);4.72 + CALL_r32disp(preg, disp8);4.73 }4.75 static inline void call_func2( void *ptr, int arg1, int arg2 )4.76 {4.77 - if( arg2 != R_EDX ) {4.78 - MOV_r32_r32( arg2, R_EDX );4.79 + if( arg2 != REG_EDX ) {4.80 + MOVL_r32_r32( arg2, REG_EDX );4.81 }4.82 - if( arg1 != R_EAX ) {4.83 - MOV_r32_r32( arg1, R_EAX );4.84 + if( arg1 != REG_EAX ) {4.85 + MOVL_r32_r32( arg1, REG_EAX );4.86 }4.87 - load_imm32(R_ECX, (uint32_t)ptr);4.88 - CALL_r32(R_ECX);4.89 + MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);4.90 + CALL_r32(REG_ECX);4.91 }4.93 static inline void call_func2_r32( int addr_reg, int arg1, int arg2 )4.94 {4.95 - if( arg2 != R_EDX ) {4.96 - MOV_r32_r32( arg2, R_EDX );4.97 + if( arg2 != REG_EDX ) {4.98 + MOVL_r32_r32( arg2, REG_EDX );4.99 }4.100 - if( arg1 != R_EAX ) {4.101 - MOV_r32_r32( arg1, R_EAX );4.102 + if( arg1 != REG_EAX ) {4.103 + MOVL_r32_r32( arg1, REG_EAX );4.104 }4.105 CALL_r32(addr_reg);4.106 }4.108 static inline void call_func2_r32disp8( int preg, uint32_t disp8, int arg1, int arg2 )4.109 {4.110 - if( arg2 != R_EDX ) {4.111 - MOV_r32_r32( arg2, R_EDX );4.112 + if( arg2 != REG_EDX ) {4.113 + MOVL_r32_r32( arg2, REG_EDX );4.114 }4.115 - if( arg1 != R_EAX ) {4.116 - MOV_r32_r32( arg1, R_EAX );4.117 + if( arg1 != REG_EAX ) {4.118 + MOVL_r32_r32( arg1, REG_EAX );4.119 }4.120 - CALL_r32disp8(preg, disp8);4.121 + CALL_r32disp(preg, disp8);4.122 }4.124 static inline void call_func2_r32disp8_exc( int preg, uint32_t disp8, int arg1, int arg2, int pc )4.125 {4.126 - if( arg2 != R_EDX ) {4.127 - MOV_r32_r32( arg2, R_EDX );4.128 + if( arg2 != REG_EDX ) {4.129 + MOVL_r32_r32( arg2, REG_EDX );4.130 }4.131 - if( arg1 != R_EAX ) {4.132 - MOV_r32_r32( arg1, R_EAX );4.133 + if( arg1 != REG_EAX ) {4.134 + MOVL_r32_r32( arg1, REG_EAX );4.135 }4.136 - MOV_backpatch_esp8( 0 );4.137 - CALL_r32disp8(preg, disp8);4.138 + MOVL_imm32_rspdisp(0,0);4.139 + sh4_x86_add_backpatch(xlat_output, pc, -2);4.140 + CALL_r32disp(preg, disp8);4.141 }4.145 static inline void call_func1_exc( void *ptr, int arg1, int pc )4.146 {4.147 - if( arg1 != R_EAX ) {4.148 - MOV_r32_r32( arg1, R_EAX );4.149 + if( arg1 != REG_EAX ) {4.150 + MOVL_r32_r32( arg1, REG_EAX );4.151 }4.152 - load_exc_backpatch(R_EDX);4.153 - load_imm32(R_ECX, (uint32_t)ptr);4.154 - CALL_r32(R_ECX);4.155 + MOVP_immptr_rptr(0,REG_EDX);4.156 + sh4_x86_add_backpatch(xlat_output, pc, -2);4.157 + MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);4.158 + CALL_r32(REG_ECX);4.159 }4.161 static inline void call_func2_exc( void *ptr, int arg1, int arg2, int pc )4.162 {4.163 - if( arg2 != R_EDX ) {4.164 - MOV_r32_r32( arg2, R_EDX );4.165 + if( arg2 != REG_EDX ) {4.166 + MOVL_r32_r32( arg2, REG_EDX );4.167 }4.168 - if( arg1 != R_EAX ) {4.169 - MOV_r32_r32( arg1, R_EAX );4.170 + if( arg1 != REG_EAX ) {4.171 + MOVL_r32_r32( arg1, REG_EAX );4.172 }4.173 - MOV_backpatch_esp8(0);4.174 - load_imm32(R_ECX, (uint32_t)ptr);4.175 - CALL_r32(R_ECX);4.176 + MOVL_imm32_rspdisp(0,0);4.177 + sh4_x86_add_backpatch(xlat_output, pc, -2);4.178 + MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);4.179 + CALL_r32(REG_ECX);4.180 }4.182 #else4.183 static inline void call_func1( void *ptr, int arg1 )4.184 {4.185 - SUB_imm8s_r32( 12, R_ESP );4.186 + SUBL_imms_r32( 12, REG_ESP );4.187 PUSH_r32(arg1);4.188 - load_imm32(R_ECX, (uint32_t)ptr);4.189 - CALL_r32(R_ECX);4.190 - ADD_imm8s_r32( 16, R_ESP );4.191 + MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);4.192 + CALL_r32(REG_ECX);4.193 + ADDL_imms_r32( 16, REG_ESP );4.194 }4.196 static inline void call_func2( void *ptr, int arg1, int arg2 )4.197 {4.198 - SUB_imm8s_r32( 8, R_ESP );4.199 + SUBL_imms_r32( 8, REG_ESP );4.200 PUSH_r32(arg2);4.201 PUSH_r32(arg1);4.202 - load_imm32(R_ECX, (uint32_t)ptr);4.203 - CALL_r32(R_ECX);4.204 - ADD_imm8s_r32( 16, R_ESP );4.205 + MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);4.206 + CALL_r32(REG_ECX);4.207 + ADDL_imms_r32( 16, REG_ESP );4.208 }4.210 #endif4.211 @@ -178,15 +182,15 @@4.212 */4.213 void enter_block( )4.214 {4.215 - PUSH_r32(R_EBP);4.216 - load_ptr( R_EBP, ((uint8_t *)&sh4r) + 128 );4.217 - SUB_imm8s_r32( 8, R_ESP );4.218 + PUSH_r32(REG_EBP);4.219 + load_ptr( REG_EBP, ((uint8_t *)&sh4r) + 128 );4.220 + SUBL_imms_r32( 8, REG_ESP );4.221 }4.223 static inline void exit_block( )4.224 {4.225 - ADD_imm8s_r32( 8, R_ESP );4.226 - POP_r32(R_EBP);4.227 + ADDL_imms_r32( 8, REG_ESP );4.228 + POP_r32(REG_EBP);4.229 RET();4.230 }4.232 @@ -195,13 +199,13 @@4.233 */4.234 void exit_block_pcset( sh4addr_t pc )4.235 {4.236 - load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.237 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 64.238 - load_spreg( R_EAX, R_PC );4.239 + load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.240 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 64.241 + load_spreg( REG_EAX, R_PC );4.242 if( sh4_x86.tlb_on ) {4.243 - call_func1(xlat_get_code_by_vma,R_EAX);4.244 + call_func1(xlat_get_code_by_vma,REG_EAX);4.245 } else {4.246 - call_func1(xlat_get_code,R_EAX);4.247 + call_func1(xlat_get_code,REG_EAX);4.248 }4.249 exit_block();4.250 }4.251 @@ -211,14 +215,14 @@4.252 */4.253 void exit_block_newpcset( sh4addr_t pc )4.254 {4.255 - load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.256 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 64.257 - load_spreg( R_EAX, R_NEW_PC );4.258 - store_spreg( R_EAX, R_PC );4.259 + load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.260 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 64.261 + load_spreg( REG_EAX, R_NEW_PC );4.262 + store_spreg( REG_EAX, R_PC );4.263 if( sh4_x86.tlb_on ) {4.264 - call_func1(xlat_get_code_by_vma,R_EAX);4.265 + call_func1(xlat_get_code_by_vma,REG_EAX);4.266 } else {4.267 - call_func1(xlat_get_code,R_EAX);4.268 + call_func1(xlat_get_code,REG_EAX);4.269 }4.270 exit_block();4.271 }4.272 @@ -229,18 +233,18 @@4.273 */4.274 void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )4.275 {4.276 - load_imm32( R_ECX, pc ); // 54.277 - store_spreg( R_ECX, REG_OFFSET(pc) ); // 34.278 + load_imm32( REG_ECX, pc ); // 54.279 + store_spreg( REG_ECX, REG_OFFSET(pc) ); // 34.280 if( IS_IN_ICACHE(pc) ) {4.281 - MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 54.282 - AND_imm8s_r32( 0xFC, R_EAX ); // 34.283 + MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 54.284 + ANDL_imms_r32( 0xFFFFFFFC, REG_EAX ); // 34.285 } else if( sh4_x86.tlb_on ) {4.286 - call_func1(xlat_get_code_by_vma,R_ECX);4.287 + call_func1(xlat_get_code_by_vma,REG_ECX);4.288 } else {4.289 - call_func1(xlat_get_code,R_ECX);4.290 + call_func1(xlat_get_code,REG_ECX);4.291 }4.292 - load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.293 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 64.294 + load_imm32( REG_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.295 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 64.296 exit_block();4.297 }4.299 @@ -249,19 +253,19 @@4.300 */4.301 void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )4.302 {4.303 - load_imm32( R_ECX, pc - sh4_x86.block_start_pc ); // 54.304 - ADD_sh4r_r32( R_PC, R_ECX );4.305 - store_spreg( R_ECX, REG_OFFSET(pc) ); // 34.306 + load_imm32( REG_ECX, pc - sh4_x86.block_start_pc ); // 54.307 + ADDL_rbpdisp_r32( R_PC, REG_ECX );4.308 + store_spreg( REG_ECX, R_PC ); // 34.309 if( IS_IN_ICACHE(pc) ) {4.310 - MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 54.311 - AND_imm8s_r32( 0xFC, R_EAX ); // 34.312 + MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 54.313 + ANDL_imms_r32( 0xFFFFFFFC, REG_EAX ); // 34.314 } else if( sh4_x86.tlb_on ) {4.315 - call_func1(xlat_get_code_by_vma,R_ECX);4.316 + call_func1(xlat_get_code_by_vma,REG_ECX);4.317 } else {4.318 - call_func1(xlat_get_code,R_ECX);4.319 + call_func1(xlat_get_code,REG_ECX);4.320 }4.321 - load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.322 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 64.323 + load_imm32( REG_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.324 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 64.325 exit_block();4.326 }4.328 @@ -270,18 +274,18 @@4.329 */4.330 void exit_block_exc( int code, sh4addr_t pc )4.331 {4.332 - load_imm32( R_ECX, pc - sh4_x86.block_start_pc ); // 54.333 - ADD_r32_sh4r( R_ECX, R_PC );4.334 - load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.335 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 64.336 - load_imm32( R_EAX, code );4.337 - call_func1( sh4_raise_exception, R_EAX );4.338 + load_imm32( REG_ECX, pc - sh4_x86.block_start_pc ); // 54.339 + ADDL_r32_rbpdisp( REG_ECX, R_PC );4.340 + load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 54.341 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 64.342 + load_imm32( REG_EAX, code );4.343 + call_func1( sh4_raise_exception, REG_EAX );4.345 - load_spreg( R_EAX, R_PC );4.346 + load_spreg( REG_EAX, R_PC );4.347 if( sh4_x86.tlb_on ) {4.348 - call_func1(xlat_get_code_by_vma,R_EAX);4.349 + call_func1(xlat_get_code_by_vma,REG_EAX);4.350 } else {4.351 - call_func1(xlat_get_code,R_EAX);4.352 + call_func1(xlat_get_code,REG_EAX);4.353 }4.355 exit_block();4.356 @@ -299,36 +303,36 @@4.357 unsigned int i;4.358 // Raise exception4.359 uint8_t *end_ptr = xlat_output;4.360 - MOV_r32_r32( R_EDX, R_ECX );4.361 - ADD_r32_r32( R_EDX, R_ECX );4.362 - ADD_r32_sh4r( R_ECX, R_PC );4.363 - MOV_moff32_EAX( &sh4_cpu_period );4.364 - MUL_r32( R_EDX );4.365 - ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );4.366 + MOVL_r32_r32( REG_EDX, REG_ECX );4.367 + ADDL_r32_r32( REG_EDX, REG_ECX );4.368 + ADDL_r32_rbpdisp( REG_ECX, R_PC );4.369 + MOVL_moffptr_eax( &sh4_cpu_period );4.370 + MULL_r32( REG_EDX );4.371 + ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );4.373 - POP_r32(R_EAX);4.374 - call_func1( sh4_raise_exception, R_EAX );4.375 - load_spreg( R_EAX, R_PC );4.376 + POP_r32(REG_EAX);4.377 + call_func1( sh4_raise_exception, REG_EAX );4.378 + load_spreg( REG_EAX, R_PC );4.379 if( sh4_x86.tlb_on ) {4.380 - call_func1(xlat_get_code_by_vma,R_EAX);4.381 + call_func1(xlat_get_code_by_vma,REG_EAX);4.382 } else {4.383 - call_func1(xlat_get_code,R_EAX);4.384 + call_func1(xlat_get_code,REG_EAX);4.385 }4.386 exit_block();4.388 // Exception already raised - just cleanup4.389 uint8_t *preexc_ptr = xlat_output;4.390 - MOV_r32_r32( R_EDX, R_ECX );4.391 - ADD_r32_r32( R_EDX, R_ECX );4.392 - ADD_r32_sh4r( R_ECX, R_SPC );4.393 - MOV_moff32_EAX( &sh4_cpu_period );4.394 - MUL_r32( R_EDX );4.395 - ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );4.396 - load_spreg( R_EAX, R_PC );4.397 + MOVL_r32_r32( REG_EDX, REG_ECX );4.398 + ADDL_r32_r32( REG_EDX, REG_ECX );4.399 + ADDL_r32_rbpdisp( REG_ECX, R_SPC );4.400 + MOVL_moffptr_eax( &sh4_cpu_period );4.401 + MULL_r32( REG_EDX );4.402 + ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );4.403 + load_spreg( REG_EAX, R_PC );4.404 if( sh4_x86.tlb_on ) {4.405 - call_func1(xlat_get_code_by_vma,R_EAX);4.406 + call_func1(xlat_get_code_by_vma,REG_EAX);4.407 } else {4.408 - call_func1(xlat_get_code,R_EAX);4.409 + call_func1(xlat_get_code,REG_EAX);4.410 }4.411 exit_block();4.413 @@ -340,15 +344,15 @@4.414 } else {4.415 *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;4.416 }4.417 - load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );4.418 + load_imm32( REG_EDX, sh4_x86.backpatch_list[i].fixup_icount );4.419 int rel = preexc_ptr - xlat_output;4.420 - JMP_rel(rel);4.421 + JMP_prerel(rel);4.422 } else {4.423 *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;4.424 PUSH_imm32( sh4_x86.backpatch_list[i].exc_code );4.425 - load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );4.426 + load_imm32( REG_EDX, sh4_x86.backpatch_list[i].fixup_icount );4.427 int rel = end_ptr - xlat_output;4.428 - JMP_rel(rel);4.429 + JMP_prerel(rel);4.430 }4.431 }4.432 }
5.1 --- a/src/sh4/ia64abi.h Wed Mar 04 23:04:54 2009 +00005.2 +++ b/src/sh4/ia64abi.h Wed Mar 04 23:12:21 2009 +00005.3 @@ -24,13 +24,13 @@5.5 #define load_ptr( reg, ptr ) load_imm64( reg, (uint64_t)ptr );5.7 -static inline decode_address( int addr_reg )5.8 +static inline void decode_address( int addr_reg )5.9 {5.10 uintptr_t base = (sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space;5.11 - MOV_r32_r32( addr_reg, R_ECX );5.12 - SHR_imm8_r32( 12, R_ECX );5.13 - load_ptr( R_EDI, base );5.14 - REXW(); OP(0x8B); OP(0x0C); OP(0xCF); // mov.q [%rdi + %rcx*8], %rcx5.15 + MOVL_r32_r32( addr_reg, REG_RCX );5.16 + SHRL_imm_r32( 12, REG_RCX );5.17 + MOVP_immptr_rptr( base, REG_RDI );5.18 + MOVP_sib_rptr(3, REG_RCX, REG_RDI, 0, REG_RCX);5.19 }5.21 /**5.22 @@ -41,58 +41,59 @@5.23 #define CALL_FUNC0_SIZE 125.24 static inline void call_func0( void *ptr )5.25 {5.26 - load_imm64(R_EAX, (uint64_t)ptr);5.27 - CALL_r32(R_EAX);5.28 + MOVQ_imm64_r64((uint64_t)ptr, REG_RAX);5.29 + CALL_r32(REG_RAX);5.30 }5.32 -#define CALL_FUNC1_SIZE 145.33 static inline void call_func1( void *ptr, int arg1 )5.34 {5.35 - REXW(); MOV_r32_r32(arg1, R_EDI);5.36 + MOVQ_r64_r64(arg1, REG_RDI);5.37 call_func0(ptr);5.38 }5.40 static inline void call_func1_exc( void *ptr, int arg1, int pc )5.41 {5.42 - REXW(); MOV_r32_r32(arg1, R_EDI);5.43 - load_exc_backpatch(R_ESI);5.44 + MOVQ_r64_r64(arg1, REG_RDI);5.45 + MOVP_immptr_rptr(0, REG_RSI);5.46 + sh4_x86_add_backpatch( xlat_output, pc, -2 );5.47 call_func0(ptr);5.48 }5.50 static inline void call_func1_r32disp8( int preg, uint32_t disp8, int arg1 )5.51 {5.52 - REXW(); MOV_r32_r32(arg1, R_EDI);5.53 - CALL_r32disp8(preg, disp8);5.54 + MOVQ_r64_r64(arg1, REG_RDI);5.55 + CALL_r32disp(preg, disp8);5.56 }5.58 static inline void call_func1_r32disp8_exc( int preg, uint32_t disp8, int arg1, int pc )5.59 {5.60 - REXW(); MOV_r32_r32(arg1, R_EDI);5.61 - load_exc_backpatch(R_ESI);5.62 - CALL_r32disp8(preg, disp8);5.63 + MOVQ_r64_r64(arg1, REG_RDI);5.64 + MOVP_immptr_rptr(0, REG_RSI);5.65 + sh4_x86_add_backpatch( xlat_output, pc, -2 );5.66 + CALL_r32disp(preg, disp8);5.67 }5.69 -#define CALL_FUNC2_SIZE 165.70 static inline void call_func2( void *ptr, int arg1, int arg2 )5.71 {5.72 - REXW(); MOV_r32_r32(arg1, R_EDI);5.73 - REXW(); MOV_r32_r32(arg2, R_ESI);5.74 + MOVQ_r64_r64(arg1, REG_RDI);5.75 + MOVQ_r64_r64(arg2, REG_RSI);5.76 call_func0(ptr);5.77 }5.79 static inline void call_func2_r32disp8( int preg, uint32_t disp8, int arg1, int arg2 )5.80 {5.81 - REXW(); MOV_r32_r32(arg1, R_EDI);5.82 - REXW(); MOV_r32_r32(arg2, R_ESI);5.83 - CALL_r32disp8(preg, disp8);5.84 + MOVQ_r64_r64(arg1, REG_RDI);5.85 + MOVQ_r64_r64(arg2, REG_RSI);5.86 + CALL_r32disp(preg, disp8);5.87 }5.89 static inline void call_func2_r32disp8_exc( int preg, uint32_t disp8, int arg1, int arg2, int pc )5.90 {5.91 - REXW(); MOV_r32_r32(arg1, R_EDI);5.92 - REXW(); MOV_r32_r32(arg2, R_ESI);5.93 - load_exc_backpatch(R_EDX);5.94 - CALL_r32disp8(preg, disp8);5.95 + MOVQ_r64_r64(arg1, REG_RDI);5.96 + MOVQ_r64_r64(arg2, REG_RSI);5.97 + MOVP_immptr_rptr(0, REG_RDX);5.98 + sh4_x86_add_backpatch( xlat_output, pc, -2 );5.99 + CALL_r32disp(preg, disp8);5.100 }5.103 @@ -103,16 +104,16 @@5.104 */5.105 void enter_block( )5.106 {5.107 - PUSH_r32(R_EBP);5.108 - load_ptr( R_EBP, ((uint8_t *)&sh4r) + 128 );5.109 + PUSH_r32(REG_RBP);5.110 + load_ptr( REG_RBP, ((uint8_t *)&sh4r) + 128 );5.111 // Minimum aligned allocation is 16 bytes5.112 - REXW(); SUB_imm8s_r32( 16, R_ESP );5.113 + SUBQ_imms_r64( 16, REG_RSP );5.114 }5.116 static inline void exit_block( )5.117 {5.118 - REXW(); ADD_imm8s_r32( 16, R_ESP );5.119 - POP_r32(R_EBP);5.120 + ADDQ_imms_r64( 16, REG_RSP );5.121 + POP_r32(REG_RBP);5.122 RET();5.123 }5.125 @@ -121,13 +122,13 @@5.126 */5.127 void exit_block_pcset( sh4addr_t pc )5.128 {5.129 - load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.130 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 65.131 - load_spreg( R_EAX, R_PC );5.132 + load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.133 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 65.134 + load_spreg( REG_RAX, R_PC );5.135 if( sh4_x86.tlb_on ) {5.136 - call_func1(xlat_get_code_by_vma,R_EAX);5.137 + call_func1(xlat_get_code_by_vma,REG_RAX);5.138 } else {5.139 - call_func1(xlat_get_code,R_EAX);5.140 + call_func1(xlat_get_code,REG_RAX);5.141 }5.142 exit_block();5.143 }5.144 @@ -137,14 +138,14 @@5.145 */5.146 void exit_block_newpcset( sh4addr_t pc )5.147 {5.148 - load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.149 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 65.150 - load_spreg( R_EAX, R_NEW_PC );5.151 - store_spreg( R_EAX, R_PC );5.152 + load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.153 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 65.154 + load_spreg( REG_RAX, R_NEW_PC );5.155 + store_spreg( REG_RAX, R_PC );5.156 if( sh4_x86.tlb_on ) {5.157 - call_func1(xlat_get_code_by_vma,R_EAX);5.158 + call_func1(xlat_get_code_by_vma,REG_RAX);5.159 } else {5.160 - call_func1(xlat_get_code,R_EAX);5.161 + call_func1(xlat_get_code,REG_RAX);5.162 }5.163 exit_block();5.164 }5.165 @@ -155,18 +156,18 @@5.166 */5.167 void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )5.168 {5.169 - load_imm32( R_ECX, pc ); // 55.170 - store_spreg( R_ECX, REG_OFFSET(pc) ); // 35.171 + load_imm32( REG_RCX, pc ); // 55.172 + store_spreg( REG_RCX, REG_OFFSET(pc) ); // 35.173 if( IS_IN_ICACHE(pc) ) {5.174 - REXW(); MOV_moff32_EAX( xlat_get_lut_entry(pc) );5.175 - REXW(); AND_imm8s_r32( 0xFC, R_EAX ); // 45.176 + MOVP_moffptr_rax( xlat_get_lut_entry(pc) );5.177 + ANDQ_imms_r64( 0xFFFFFFFC, REG_RAX ); // 45.178 } else if( sh4_x86.tlb_on ) {5.179 - call_func1(xlat_get_code_by_vma, R_ECX);5.180 + call_func1(xlat_get_code_by_vma, REG_RCX);5.181 } else {5.182 - call_func1(xlat_get_code,R_ECX);5.183 + call_func1(xlat_get_code,REG_RCX);5.184 }5.185 - load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.186 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 65.187 + load_imm32( REG_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.188 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 65.189 exit_block();5.190 }5.192 @@ -178,19 +179,19 @@5.193 */5.194 void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )5.195 {5.196 - load_imm32( R_ECX, pc - sh4_x86.block_start_pc ); // 55.197 - ADD_sh4r_r32( R_PC, R_ECX );5.198 - store_spreg( R_ECX, REG_OFFSET(pc) ); // 35.199 + load_imm32( REG_ECX, pc - sh4_x86.block_start_pc ); // 55.200 + ADDL_rbpdisp_r32( R_PC, REG_ECX );5.201 + store_spreg( REG_ECX, REG_OFFSET(pc) ); // 35.202 if( IS_IN_ICACHE(pc) ) {5.203 - REXW(); MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 55.204 - REXW(); AND_imm8s_r32( 0xFC, R_EAX ); // 45.205 + MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 55.206 + ANDQ_imms_r64( 0xFFFFFFFC, REG_RAX ); // 45.207 } else if( sh4_x86.tlb_on ) {5.208 - call_func1(xlat_get_code_by_vma,R_ECX);5.209 + call_func1(xlat_get_code_by_vma,REG_RCX);5.210 } else {5.211 - call_func1(xlat_get_code,R_ECX);5.212 + call_func1(xlat_get_code,REG_RCX);5.213 }5.214 - load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.215 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 65.216 + load_imm32( REG_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.217 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 65.218 exit_block();5.219 }5.221 @@ -199,18 +200,18 @@5.222 */5.223 void exit_block_exc( int code, sh4addr_t pc )5.224 {5.225 - load_imm32( R_ECX, pc - sh4_x86.block_start_pc ); // 55.226 - ADD_r32_sh4r( R_ECX, R_PC );5.227 - load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.228 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 65.229 - load_imm32( R_EAX, code );5.230 - call_func1( sh4_raise_exception, R_EAX );5.231 + load_imm32( REG_ECX, pc - sh4_x86.block_start_pc ); // 55.232 + ADDL_r32_rbpdisp( REG_ECX, R_PC );5.233 + load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 55.234 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 65.235 + load_imm32( REG_RAX, code );5.236 + call_func1( sh4_raise_exception, REG_RAX );5.238 - load_spreg( R_EAX, R_PC );5.239 + load_spreg( REG_RAX, R_PC );5.240 if( sh4_x86.tlb_on ) {5.241 - call_func1(xlat_get_code_by_vma,R_EAX);5.242 + call_func1(xlat_get_code_by_vma,REG_RAX);5.243 } else {5.244 - call_func1(xlat_get_code,R_EAX);5.245 + call_func1(xlat_get_code,REG_RAX);5.246 }5.248 exit_block();5.249 @@ -229,31 +230,31 @@5.250 unsigned int i;5.251 // Raise exception5.252 uint8_t *end_ptr = xlat_output;5.253 - MOV_r32_r32( R_EDX, R_ECX );5.254 - ADD_r32_r32( R_EDX, R_ECX );5.255 - ADD_r32_sh4r( R_ECX, R_PC );5.256 - MOV_moff32_EAX( &sh4_cpu_period );5.257 - MUL_r32( R_EDX );5.258 - ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );5.259 + MOVL_r32_r32( REG_RDX, REG_RCX );5.260 + ADDL_r32_r32( REG_RDX, REG_RCX );5.261 + ADDL_r32_rbpdisp( REG_RCX, R_PC );5.262 + MOVL_moffptr_eax( &sh4_cpu_period );5.263 + MULL_r32( REG_RDX );5.264 + ADDL_r32_rbpdisp( REG_RAX, REG_OFFSET(slice_cycle) );5.266 call_func0( sh4_raise_exception );5.267 - load_spreg( R_EAX, R_PC );5.268 + load_spreg( REG_RAX, R_PC );5.269 if( sh4_x86.tlb_on ) {5.270 - call_func1(xlat_get_code_by_vma,R_EAX);5.271 + call_func1(xlat_get_code_by_vma,REG_RAX);5.272 } else {5.273 - call_func1(xlat_get_code,R_EAX);5.274 + call_func1(xlat_get_code,REG_RAX);5.275 }5.276 exit_block();5.278 // Exception already raised - just cleanup5.279 uint8_t *preexc_ptr = xlat_output;5.280 - MOV_r32_r32( R_EDX, R_ECX );5.281 - ADD_r32_r32( R_EDX, R_ECX );5.282 - ADD_r32_sh4r( R_ECX, R_SPC );5.283 - MOV_moff32_EAX( &sh4_cpu_period );5.284 - MUL_r32( R_EDX );5.285 - ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );5.286 - load_spreg( R_EDI, R_PC );5.287 + MOVL_r32_r32( REG_EDX, REG_ECX );5.288 + ADDL_r32_r32( REG_EDX, REG_ECX );5.289 + ADDL_r32_rbpdisp( REG_ECX, R_SPC );5.290 + MOVL_moffptr_eax( &sh4_cpu_period );5.291 + MULL_r32( REG_EDX );5.292 + ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );5.293 + load_spreg( REG_RDI, R_PC );5.294 if( sh4_x86.tlb_on ) {5.295 call_func0(xlat_get_code_by_vma);5.296 } else {5.297 @@ -269,15 +270,15 @@5.298 } else {5.299 *fixup_addr = xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;5.300 }5.301 - load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );5.302 + load_imm32( REG_RDX, sh4_x86.backpatch_list[i].fixup_icount );5.303 int rel = preexc_ptr - xlat_output;5.304 - JMP_rel(rel);5.305 + JMP_prerel(rel);5.306 } else {5.307 *fixup_addr = xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;5.308 - load_imm32( R_EDI, sh4_x86.backpatch_list[i].exc_code );5.309 - load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );5.310 + load_imm32( REG_RDI, sh4_x86.backpatch_list[i].exc_code );5.311 + load_imm32( REG_RDX, sh4_x86.backpatch_list[i].fixup_icount );5.312 int rel = end_ptr - xlat_output;5.313 - JMP_rel(rel);5.314 + JMP_prerel(rel);5.315 }5.316 }5.317 }
6.1 --- a/src/sh4/mmux86.c Wed Mar 04 23:04:54 2009 +00006.2 +++ b/src/sh4/mmux86.c Wed Mar 04 23:12:21 2009 +00006.3 @@ -22,19 +22,24 @@6.4 #include "sh4/sh4mmio.h"6.5 #include "sh4/sh4trans.h"6.6 #include "sh4/mmu.h"6.7 -#include "sh4/x86op.h"6.8 +#include "xlat/x86/x86op.h"6.10 #if SIZEOF_VOID_P == 86.11 -#define ARG1 R_EDI6.12 -#define ARG2 R_ESI6.13 -#define DECODE() \6.14 - MOV_imm64_r32((uintptr_t)addr_space, R_EAX); /* movq ptr, %rax */ \6.15 - REXW(); OP(0x8B); OP(0x0C); OP(0xC8) /* movq [%rax + %rcx*8], %rcx */6.16 +#define ARG1 REG_RDI6.17 +#define ARG2 REG_RSI6.18 +#define XLAT(addr_space, reg) \6.19 + MOVQ_imm64_r64( (uintptr_t)addr_space, REG_RAX ); \6.20 + MOVP_sib_rptr( 3, reg, REG_RAX, 0, reg );6.21 +#define ADDP_imms_ptr(imm,p) \6.22 + MOVQ_imm64_r64((uintptr_t)p, REG_EAX ); \6.23 + ADDL_imms_r32disp(imm, REG_EAX, 0);6.24 #else6.25 -#define ARG1 R_EAX6.26 +#define ARG1 REG_EAX6.27 #define ARG2 R_EDX6.28 -#define DECODE() \6.29 - MOV_r32disp32x4_r32( R_ECX, (uintptr_t)addr_space, R_ECX );6.30 +#define XLAT(addr_space, reg) \6.31 + MOVP_sib_rptr( 2, reg, -1, (uintptr_t)addr_space, reg );6.32 +#define ADDP_imms_ptr(imm,p) \6.33 + ADDL_imms_r32disp(imm, -1, (uintptr_t)p);6.34 #endif6.36 void mmu_utlb_init_vtable( struct utlb_entry *ent, struct utlb_page_entry *page, gboolean writable )6.37 @@ -61,23 +66,18 @@6.38 for( i=0; i<10; i+= inc, fn += inc, out += inc ) {6.39 *out = xlat_output;6.40 if( i != 9 ) { /* read_byte_for_write doesn't increment mmu_urc, everything else does */6.41 -#if SIZEOF_VOID_P == 86.42 - MOV_imm64_r32((uintptr_t)&mmu_urc, R_EAX );6.43 - OP(0x83); OP(0x00); OP(0x01); // ADD #1, [RAX]6.44 -#else6.45 - OP(0x83); MODRM_r32_disp32(0, (uintptr_t)&mmu_urc); OP(0x01); // ADD #1, mmu_urc6.46 -#endif6.47 + ADDP_imms_ptr(1, &mmu_urc);6.48 }6.49 - ADD_imm32_r32( ppn-vpn, ARG1 ); // 66.50 + ADDL_imms_r32( ppn-vpn, ARG1 ); // 66.51 if( ent->mask >= 0xFFFFF000 ) {6.52 // Maps to a single page, so jump directly there6.53 int rel = (*fn - xlat_output);6.54 - JMP_rel( rel ); // 56.55 + JMP_prerel( rel ); // 56.56 } else {6.57 - MOV_r32_r32( ARG1, R_ECX ); // 26.58 - SHR_imm8_r32( 12, R_ECX ); // 36.59 - DECODE(); // 146.60 - JMP_r32disp8(R_ECX, (((uintptr_t)out) - ((uintptr_t)&page->fn)) ); // 36.61 + MOVL_r32_r32( ARG1, REG_ECX ); // 26.62 + SHRL_imm_r32( 12, REG_ECX ); // 36.63 + XLAT(addr_space, REG_ECX); // 146.64 + JMP_r32disp(REG_ECX, (((uintptr_t)out) - ((uintptr_t)&page->fn)) ); // 36.65 }6.66 }6.68 @@ -95,15 +95,10 @@6.69 memcpy( page, &p4_region_storequeue, sizeof(struct mem_region_fn) );6.71 page->fn.prefetch = (mem_prefetch_fn_t)xlat_output;6.72 -#if SIZEOF_VOID_P == 86.73 - MOV_imm64_r32((uintptr_t)&mmu_urc, R_EAX );6.74 - OP(0x83); OP(0x00); OP(0x01); // ADD #1, [RAX]6.75 -#else6.76 - OP(0x83); MODRM_r32_disp32(0, (uintptr_t)&mmu_urc); OP(0x01); // ADD #1, mmu_urc6.77 -#endif6.78 - ADD_imm32_r32( ppn-vpn, ARG1 );6.79 + ADDP_imms_ptr(1, &mmu_urc);6.80 + ADDL_imms_r32( ppn-vpn, ARG1 );6.81 int rel = ((uint8_t *)ccn_storequeue_prefetch_tlb) - xlat_output;6.82 - JMP_rel( rel );6.83 + JMP_prerel( rel );6.84 }6.86 void mmu_utlb_1k_init_vtable( struct utlb_1k_entry *entry )6.87 @@ -114,31 +109,21 @@6.89 for( i=0; i<9; i++, out++ ) {6.90 *out = xlat_output;6.91 - MOV_r32_r32( ARG1, R_ECX );6.92 - SHR_imm8_r32( 10, R_ECX );6.93 - AND_imm8s_r32( 0x3, R_ECX );6.94 -#if SIZEOF_VOID_P == 86.95 - MOV_imm64_r32( (uintptr_t)&entry->subpages[0], R_EAX );6.96 - REXW(); OP(0x8B); OP(0x0C); OP(0xC8); /* movq [%rax + %rcx*8], %rcx */6.97 -#else6.98 - MOV_r32disp32x4_r32( R_ECX, ((uintptr_t)&entry->subpages[0]), R_ECX );6.99 -#endif6.100 - JMP_r32disp8(R_ECX, (((uintptr_t)out) - ((uintptr_t)&entry->fn)) ); // 36.101 + MOVL_r32_r32( ARG1, REG_ECX );6.102 + SHRL_imm_r32( 10, REG_ECX );6.103 + ANDL_imms_r32( 0x3, REG_ECX );6.104 + XLAT( (uintptr_t)&entry->subpages[0], REG_ECX );6.105 + JMP_r32disp(REG_ECX, (((uintptr_t)out) - ((uintptr_t)&entry->fn)) ); // 36.106 }6.108 out = (uint8_t **)&entry->user_fn;6.109 for( i=0; i<9; i++, out++ ) {6.110 *out = xlat_output;6.111 - MOV_r32_r32( ARG1, R_ECX );6.112 - SHR_imm8_r32( 10, R_ECX );6.113 - AND_imm8s_r32( 0x3, R_ECX );6.114 -#if SIZEOF_VOID_P == 86.115 - MOV_imm64_r32( (uintptr_t)&entry->user_subpages[0], R_EAX );6.116 - REXW(); OP(0x8B); OP(0x0C); OP(0xC8); /* movq [%rax + %rcx*8], %rcx */6.117 -#else6.118 - MOV_r32disp32x4_r32( R_ECX, ((uintptr_t)&entry->user_subpages[0]), R_ECX );6.119 -#endif6.120 - JMP_r32disp8(R_ECX, (((uintptr_t)out) - ((uintptr_t)&entry->user_fn)) ); // 36.121 + MOVL_r32_r32( ARG1, REG_ECX );6.122 + SHRL_imm_r32( 10, REG_ECX );6.123 + ANDL_imms_r32( 0x3, REG_ECX );6.124 + XLAT( (uintptr_t)&entry->user_subpages[0], REG_ECX );6.125 + JMP_r32disp(REG_ECX, (((uintptr_t)out) - ((uintptr_t)&entry->user_fn)) ); // 36.126 }6.128 }
7.1 --- a/src/sh4/sh4.c Wed Mar 04 23:04:54 2009 +00007.2 +++ b/src/sh4/sh4.c Wed Mar 04 23:12:21 2009 +00007.3 @@ -33,7 +33,7 @@7.4 #include "sh4/sh4mmio.h"7.5 #include "sh4/sh4stat.h"7.6 #include "sh4/sh4trans.h"7.7 -#include "sh4/xltcache.h"7.8 +#include "xlat/xltcache.h"7.10 #ifndef M_PI7.11 #define M_PI 3.14159265358979323846264338327950288
8.1 --- a/src/sh4/sh4mem.c Wed Mar 04 23:04:54 2009 +00008.2 +++ b/src/sh4/sh4mem.c Wed Mar 04 23:12:21 2009 +00008.3 @@ -27,9 +27,9 @@8.4 #include "dreamcast.h"8.5 #include "sh4/sh4core.h"8.6 #include "sh4/sh4mmio.h"8.7 -#include "sh4/xltcache.h"8.8 #include "sh4/mmu.h"8.9 #include "pvr2/pvr2.h"8.10 +#include "xlat/xltcache.h"8.12 /************** Obsolete methods ***************/
9.1 --- a/src/sh4/sh4trans.c Wed Mar 04 23:04:54 2009 +00009.2 +++ b/src/sh4/sh4trans.c Wed Mar 04 23:12:21 2009 +00009.3 @@ -23,9 +23,9 @@9.4 #include "dreamcast.h"9.5 #include "sh4/sh4core.h"9.6 #include "sh4/sh4trans.h"9.7 -#include "sh4/xltcache.h"9.8 #include "sh4/sh4mmio.h"9.9 #include "sh4/mmu.h"9.10 +#include "xlat/xltcache.h"9.12 /**9.13 * Execute a timeslice using translated code only (ie translate/execute loop)
10.1 --- a/src/sh4/sh4trans.h Wed Mar 04 23:04:54 2009 +000010.2 +++ b/src/sh4/sh4trans.h Wed Mar 04 23:12:21 2009 +000010.3 @@ -19,7 +19,7 @@10.4 #ifndef lxdream_sh4trans_H10.5 #define lxdream_sh4trans_H 110.7 -#include "sh4/xltcache.h"10.8 +#include "xlat/xltcache.h"10.9 #include "dream.h"10.10 #include "mem.h"
11.1 --- a/src/sh4/sh4x86.in Wed Mar 04 23:04:54 2009 +000011.2 +++ b/src/sh4/sh4x86.in Wed Mar 04 23:12:21 2009 +000011.3 @@ -26,17 +26,39 @@11.4 #endif11.6 #include "lxdream.h"11.7 -#include "sh4/xltcache.h"11.8 #include "sh4/sh4core.h"11.9 #include "sh4/sh4trans.h"11.10 #include "sh4/sh4stat.h"11.11 #include "sh4/sh4mmio.h"11.12 -#include "sh4/x86op.h"11.13 #include "sh4/mmu.h"11.14 +#include "xlat/xltcache.h"11.15 +#include "xlat/x86/x86op.h"11.16 #include "clock.h"11.18 #define DEFAULT_BACKPATCH_SIZE 409611.20 +/* Offset of a reg relative to the sh4r structure */11.21 +#define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)11.22 +11.23 +#define R_T REG_OFFSET(t)11.24 +#define R_Q REG_OFFSET(q)11.25 +#define R_S REG_OFFSET(s)11.26 +#define R_M REG_OFFSET(m)11.27 +#define R_SR REG_OFFSET(sr)11.28 +#define R_GBR REG_OFFSET(gbr)11.29 +#define R_SSR REG_OFFSET(ssr)11.30 +#define R_SPC REG_OFFSET(spc)11.31 +#define R_VBR REG_OFFSET(vbr)11.32 +#define R_MACH REG_OFFSET(mac)+411.33 +#define R_MACL REG_OFFSET(mac)11.34 +#define R_PC REG_OFFSET(pc)11.35 +#define R_NEW_PC REG_OFFSET(new_pc)11.36 +#define R_PR REG_OFFSET(pr)11.37 +#define R_SGR REG_OFFSET(sgr)11.38 +#define R_FPUL REG_OFFSET(fpul)11.39 +#define R_FPSCR REG_OFFSET(fpscr)11.40 +#define R_DBR REG_OFFSET(dbr)11.41 +11.42 struct backpatch_record {11.43 uint32_t fixup_offset;11.44 uint32_t fixup_icount;11.45 @@ -72,32 +94,6 @@11.46 uint32_t backpatch_size;11.47 };11.49 -#define TSTATE_NONE -111.50 -#define TSTATE_O 011.51 -#define TSTATE_C 211.52 -#define TSTATE_E 411.53 -#define TSTATE_NE 511.54 -#define TSTATE_G 0xF11.55 -#define TSTATE_GE 0xD11.56 -#define TSTATE_A 711.57 -#define TSTATE_AE 311.58 -11.59 -#ifdef ENABLE_SH4STATS11.60 -#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE11.61 -#else11.62 -#define COUNT_INST(id)11.63 -#endif11.64 -11.65 -/** Branch if T is set (either in the current cflags, or in sh4r.t) */11.66 -#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \11.67 - CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \11.68 - OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)11.69 -11.70 -/** Branch if T is clear (either in the current cflags or in sh4r.t) */11.71 -#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \11.72 - CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \11.73 - OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)11.74 -11.75 static struct sh4_x86_state sh4_x86;11.77 static uint32_t max_int = 0x7FFFFFFF;11.78 @@ -125,6 +121,12 @@11.80 static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )11.81 {11.82 + int reloc_size = 4;11.83 +11.84 + if( exc_code == -2 ) {11.85 + reloc_size = sizeof(void *);11.86 + }11.87 +11.88 if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {11.89 sh4_x86.backpatch_size <<= 1;11.90 sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list,11.91 @@ -134,106 +136,107 @@11.92 if( sh4_x86.in_delay_slot ) {11.93 fixup_pc -= 2;11.94 }11.95 +11.96 sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset =11.97 - ((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);11.98 + (((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;11.99 sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;11.100 sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;11.101 sh4_x86.backpatch_posn++;11.102 }11.104 -/**11.105 - * Emit an instruction to load an SH4 reg into a real register11.106 - */11.107 -static inline void load_reg( int x86reg, int sh4reg )11.108 -{11.109 - /* mov [bp+n], reg */11.110 - OP(0x8B);11.111 - OP(0x45 + (x86reg<<3));11.112 - OP(REG_OFFSET(r[sh4reg]));11.113 -}11.114 +#define TSTATE_NONE -111.115 +#define TSTATE_O 011.116 +#define TSTATE_C 211.117 +#define TSTATE_E 411.118 +#define TSTATE_NE 511.119 +#define TSTATE_G 0xF11.120 +#define TSTATE_GE 0xD11.121 +#define TSTATE_A 711.122 +#define TSTATE_AE 311.124 -static inline void load_reg16s( int x86reg, int sh4reg )11.125 -{11.126 - OP(0x0F);11.127 - OP(0xBF);11.128 - MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));11.129 -}11.130 +#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)11.131 +#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)11.133 -static inline void load_reg16u( int x86reg, int sh4reg )11.134 -{11.135 - OP(0x0F);11.136 - OP(0xB7);11.137 - MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));11.138 +/* Convenience instructions */11.139 +#define LDC_t() CMPB_imms_rbpdisp(1,R_T); CMC()11.140 +#define SETE_t() SETCCB_cc_rbpdisp(X86_COND_E,R_T)11.141 +#define SETA_t() SETCCB_cc_rbpdisp(X86_COND_A,R_T)11.142 +#define SETAE_t() SETCCB_cc_rbpdisp(X86_COND_AE,R_T)11.143 +#define SETG_t() SETCCB_cc_rbpdisp(X86_COND_G,R_T)11.144 +#define SETGE_t() SETCCB_cc_rbpdisp(X86_COND_GE,R_T)11.145 +#define SETC_t() SETCCB_cc_rbpdisp(X86_COND_C,R_T)11.146 +#define SETO_t() SETCCB_cc_rbpdisp(X86_COND_O,R_T)11.147 +#define SETNE_t() SETCCB_cc_rbpdisp(X86_COND_NE,R_T)11.148 +#define SETC_r8(r1) SETCCB_cc_r8(X86_COND_C, r1)11.149 +#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)11.150 +#define JE_label(label) JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)11.151 +#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)11.152 +#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)11.153 +#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)11.154 +#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)11.155 +#define JS_label(label) JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)11.156 +#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)11.157 +#define JNE_exc(exc) JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)11.159 -}11.160 +/** Branch if T is set (either in the current cflags, or in sh4r.t) */11.161 +#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \11.162 + CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \11.163 + JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)11.165 -#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )11.166 -#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )11.167 -/**11.168 - * Emit an instruction to load an immediate value into a register11.169 - */11.170 -static inline void load_imm32( int x86reg, uint32_t value ) {11.171 - /* mov #value, reg */11.172 - OP(0xB8 + x86reg);11.173 - OP32(value);11.174 -}11.175 +/** Branch if T is clear (either in the current cflags or in sh4r.t) */11.176 +#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \11.177 + CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \11.178 + JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)11.180 -11.181 -/**11.182 - * Load an immediate 64-bit quantity (note: x86-64 only)11.183 - */11.184 -static inline void load_imm64( int x86reg, uint64_t value ) {11.185 - /* mov #value, reg */11.186 - REXW();11.187 - OP(0xB8 + x86reg);11.188 - OP64(value);11.189 -}11.190 -11.191 -/**11.192 - * Emit an instruction to store an SH4 reg (RN)11.193 - */11.194 -void static inline store_reg( int x86reg, int sh4reg ) {11.195 - /* mov reg, [bp+n] */11.196 - OP(0x89);11.197 - OP(0x45 + (x86reg<<3));11.198 - OP(REG_OFFSET(r[sh4reg]));11.199 -}11.200 +#define load_reg16s(x86reg,sh4reg) MOVSXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )11.201 +#define load_reg16u(x86reg,sh4reg) MOVZXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )11.202 +#define load_imm32(x86reg,value) MOVL_imm32_r32(value,x86reg)11.203 +#define load_imm64(x86reg,value) MOVQ_imm64_r64(value,x86reg)11.204 +#define load_reg(x86reg,sh4reg) MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )11.205 +#define store_reg(x86reg,sh4reg) MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )11.206 +#define load_spreg(x86reg, regoff) MOVL_rbpdisp_r32( regoff, x86reg )11.207 +#define store_spreg(x86reg, regoff) MOVL_r32_rbpdisp( x86reg, regoff )11.209 /**11.210 * Load an FR register (single-precision floating point) into an integer x8611.211 * register (eg for register-to-register moves)11.212 */11.213 -#define load_fr(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )11.214 -#define load_xf(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )11.215 +#define load_fr(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )11.216 +#define load_xf(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )11.218 /**11.219 * Load the low half of a DR register (DR or XD) into an integer x86 register11.220 */11.221 -#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )11.222 -#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )11.223 +#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )11.224 +#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )11.226 /**11.227 * Store an FR register (single-precision floating point) from an integer x86+11.228 * register (eg for register-to-register moves)11.229 */11.230 -#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )11.231 -#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )11.232 +#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )11.233 +#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )11.235 -#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )11.236 -#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )11.237 +#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )11.238 +#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )11.241 -#define push_fpul() FLDF_sh4r(R_FPUL)11.242 -#define pop_fpul() FSTPF_sh4r(R_FPUL)11.243 -#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )11.244 -#define pop_fr(frm) FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )11.245 -#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )11.246 -#define pop_xf(frm) FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )11.247 -#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )11.248 -#define pop_dr(frm) FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )11.249 -#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )11.250 -#define pop_xdr(frm) FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )11.251 +#define push_fpul() FLDF_rbpdisp(R_FPUL)11.252 +#define pop_fpul() FSTPF_rbpdisp(R_FPUL)11.253 +#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )11.254 +#define pop_fr(frm) FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )11.255 +#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )11.256 +#define pop_xf(frm) FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )11.257 +#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )11.258 +#define pop_dr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )11.259 +#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )11.260 +#define pop_xdr(frm) FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )11.262 +#ifdef ENABLE_SH4STATS11.263 +#define COUNT_INST(id) load_imm32(REG_EAX,id); call_func1(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE11.264 +#else11.265 +#define COUNT_INST(id)11.266 +#endif11.269 /* Exception checks - Note that all exception checks will clobber EAX */11.270 @@ -253,8 +256,8 @@11.271 #define check_fpuen( ) \11.272 if( !sh4_x86.fpuen_checked ) {\11.273 sh4_x86.fpuen_checked = TRUE;\11.274 - load_spreg( R_EAX, R_SR );\11.275 - AND_imm32_r32( SR_FD, R_EAX );\11.276 + load_spreg( REG_EAX, R_SR );\11.277 + ANDL_imms_r32( SR_FD, REG_EAX );\11.278 if( sh4_x86.in_delay_slot ) {\11.279 JNE_exc(EXC_SLOT_FPU_DISABLED);\11.280 } else {\11.281 @@ -264,46 +267,46 @@11.282 }11.284 #define check_ralign16( x86reg ) \11.285 - TEST_imm32_r32( 0x00000001, x86reg ); \11.286 + TESTL_imms_r32( 0x00000001, x86reg ); \11.287 JNE_exc(EXC_DATA_ADDR_READ)11.289 #define check_walign16( x86reg ) \11.290 - TEST_imm32_r32( 0x00000001, x86reg ); \11.291 + TESTL_imms_r32( 0x00000001, x86reg ); \11.292 JNE_exc(EXC_DATA_ADDR_WRITE);11.294 #define check_ralign32( x86reg ) \11.295 - TEST_imm32_r32( 0x00000003, x86reg ); \11.296 + TESTL_imms_r32( 0x00000003, x86reg ); \11.297 JNE_exc(EXC_DATA_ADDR_READ)11.299 #define check_walign32( x86reg ) \11.300 - TEST_imm32_r32( 0x00000003, x86reg ); \11.301 + TESTL_imms_r32( 0x00000003, x86reg ); \11.302 JNE_exc(EXC_DATA_ADDR_WRITE);11.304 #define check_ralign64( x86reg ) \11.305 - TEST_imm32_r32( 0x00000007, x86reg ); \11.306 + TESTL_imms_r32( 0x00000007, x86reg ); \11.307 JNE_exc(EXC_DATA_ADDR_READ)11.309 #define check_walign64( x86reg ) \11.310 - TEST_imm32_r32( 0x00000007, x86reg ); \11.311 + TESTL_imms_r32( 0x00000007, x86reg ); \11.312 JNE_exc(EXC_DATA_ADDR_WRITE);11.314 #define UNDEF(ir)11.315 #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )11.316 -#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }11.317 +#define MEM_RESULT(value_reg) if(value_reg != REG_EAX) { MOVL_r32_r32(REG_EAX,value_reg); }11.318 /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so11.319 * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.11.320 */11.322 #ifdef HAVE_FRAME_ADDRESS11.323 #define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \11.324 - call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \11.325 - call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); }11.326 + call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \11.327 + call_func1_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, pc); }11.328 #define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \11.329 - call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \11.330 - call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }11.331 + call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \11.332 + call_func2_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }11.333 #else11.334 -#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg)11.335 -#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)11.336 +#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg)11.337 +#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)11.338 #endif11.340 #define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)11.341 @@ -354,8 +357,8 @@11.342 */11.343 void sh4_translate_emit_breakpoint( sh4vma_t pc )11.344 {11.345 - load_imm32( R_EAX, pc );11.346 - call_func1( sh4_translate_breakpoint_hit, R_EAX );11.347 + load_imm32( REG_EAX, pc );11.348 + call_func1( sh4_translate_breakpoint_hit, REG_EAX );11.349 sh4_x86.tstate = TSTATE_NONE;11.350 }11.352 @@ -376,20 +379,20 @@11.353 */11.354 void exit_block_emu( sh4vma_t endpc )11.355 {11.356 - load_imm32( R_ECX, endpc - sh4_x86.block_start_pc ); // 511.357 - ADD_r32_sh4r( R_ECX, R_PC );11.358 + load_imm32( REG_ECX, endpc - sh4_x86.block_start_pc ); // 511.359 + ADDL_r32_rbpdisp( REG_ECX, R_PC );11.361 - load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 511.362 - ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) ); // 611.363 - load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );11.364 - store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );11.365 + load_imm32( REG_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 511.366 + ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) ); // 611.367 + load_imm32( REG_ECX, sh4_x86.in_delay_slot ? 1 : 0 );11.368 + store_spreg( REG_ECX, REG_OFFSET(in_delay_slot) );11.370 call_func0( sh4_execute_instruction );11.371 - load_spreg( R_EAX, R_PC );11.372 + load_spreg( REG_EAX, R_PC );11.373 if( sh4_x86.tlb_on ) {11.374 - call_func1(xlat_get_code_by_vma,R_EAX);11.375 + call_func1(xlat_get_code_by_vma,REG_EAX);11.376 } else {11.377 - call_func1(xlat_get_code,R_EAX);11.378 + call_func1(xlat_get_code,REG_EAX);11.379 }11.380 exit_block();11.381 }11.382 @@ -417,15 +420,15 @@11.383 /* ALU operations */11.384 ADD Rm, Rn {:11.385 COUNT_INST(I_ADD);11.386 - load_reg( R_EAX, Rm );11.387 - load_reg( R_ECX, Rn );11.388 - ADD_r32_r32( R_EAX, R_ECX );11.389 - store_reg( R_ECX, Rn );11.390 + load_reg( REG_EAX, Rm );11.391 + load_reg( REG_ECX, Rn );11.392 + ADDL_r32_r32( REG_EAX, REG_ECX );11.393 + store_reg( REG_ECX, Rn );11.394 sh4_x86.tstate = TSTATE_NONE;11.395 :}11.396 ADD #imm, Rn {:11.397 COUNT_INST(I_ADDI);11.398 - ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) );11.399 + ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );11.400 sh4_x86.tstate = TSTATE_NONE;11.401 :}11.402 ADDC Rm, Rn {:11.403 @@ -433,122 +436,122 @@11.404 if( sh4_x86.tstate != TSTATE_C ) {11.405 LDC_t();11.406 }11.407 - load_reg( R_EAX, Rm );11.408 - load_reg( R_ECX, Rn );11.409 - ADC_r32_r32( R_EAX, R_ECX );11.410 - store_reg( R_ECX, Rn );11.411 + load_reg( REG_EAX, Rm );11.412 + load_reg( REG_ECX, Rn );11.413 + ADCL_r32_r32( REG_EAX, REG_ECX );11.414 + store_reg( REG_ECX, Rn );11.415 SETC_t();11.416 sh4_x86.tstate = TSTATE_C;11.417 :}11.418 ADDV Rm, Rn {:11.419 COUNT_INST(I_ADDV);11.420 - load_reg( R_EAX, Rm );11.421 - load_reg( R_ECX, Rn );11.422 - ADD_r32_r32( R_EAX, R_ECX );11.423 - store_reg( R_ECX, Rn );11.424 + load_reg( REG_EAX, Rm );11.425 + load_reg( REG_ECX, Rn );11.426 + ADDL_r32_r32( REG_EAX, REG_ECX );11.427 + store_reg( REG_ECX, Rn );11.428 SETO_t();11.429 sh4_x86.tstate = TSTATE_O;11.430 :}11.431 AND Rm, Rn {:11.432 COUNT_INST(I_AND);11.433 - load_reg( R_EAX, Rm );11.434 - load_reg( R_ECX, Rn );11.435 - AND_r32_r32( R_EAX, R_ECX );11.436 - store_reg( R_ECX, Rn );11.437 + load_reg( REG_EAX, Rm );11.438 + load_reg( REG_ECX, Rn );11.439 + ANDL_r32_r32( REG_EAX, REG_ECX );11.440 + store_reg( REG_ECX, Rn );11.441 sh4_x86.tstate = TSTATE_NONE;11.442 :}11.443 AND #imm, R0 {:11.444 COUNT_INST(I_ANDI);11.445 - load_reg( R_EAX, 0 );11.446 - AND_imm32_r32(imm, R_EAX);11.447 - store_reg( R_EAX, 0 );11.448 + load_reg( REG_EAX, 0 );11.449 + ANDL_imms_r32(imm, REG_EAX);11.450 + store_reg( REG_EAX, 0 );11.451 sh4_x86.tstate = TSTATE_NONE;11.452 :}11.453 AND.B #imm, @(R0, GBR) {:11.454 COUNT_INST(I_ANDB);11.455 - load_reg( R_EAX, 0 );11.456 - ADD_sh4r_r32( R_GBR, R_EAX );11.457 - MOV_r32_esp8(R_EAX, 0);11.458 - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );11.459 - MOV_esp8_r32(0, R_EAX);11.460 - AND_imm32_r32(imm, R_EDX );11.461 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.462 + load_reg( REG_EAX, 0 );11.463 + ADDL_rbpdisp_r32( R_GBR, REG_EAX );11.464 + MOVL_r32_rspdisp(REG_EAX, 0);11.465 + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );11.466 + MOVL_rspdisp_r32(0, REG_EAX);11.467 + ANDL_imms_r32(imm, REG_EDX );11.468 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.469 sh4_x86.tstate = TSTATE_NONE;11.470 :}11.471 CMP/EQ Rm, Rn {:11.472 COUNT_INST(I_CMPEQ);11.473 - load_reg( R_EAX, Rm );11.474 - load_reg( R_ECX, Rn );11.475 - CMP_r32_r32( R_EAX, R_ECX );11.476 + load_reg( REG_EAX, Rm );11.477 + load_reg( REG_ECX, Rn );11.478 + CMPL_r32_r32( REG_EAX, REG_ECX );11.479 SETE_t();11.480 sh4_x86.tstate = TSTATE_E;11.481 :}11.482 CMP/EQ #imm, R0 {:11.483 COUNT_INST(I_CMPEQI);11.484 - load_reg( R_EAX, 0 );11.485 - CMP_imm8s_r32(imm, R_EAX);11.486 + load_reg( REG_EAX, 0 );11.487 + CMPL_imms_r32(imm, REG_EAX);11.488 SETE_t();11.489 sh4_x86.tstate = TSTATE_E;11.490 :}11.491 CMP/GE Rm, Rn {:11.492 COUNT_INST(I_CMPGE);11.493 - load_reg( R_EAX, Rm );11.494 - load_reg( R_ECX, Rn );11.495 - CMP_r32_r32( R_EAX, R_ECX );11.496 + load_reg( REG_EAX, Rm );11.497 + load_reg( REG_ECX, Rn );11.498 + CMPL_r32_r32( REG_EAX, REG_ECX );11.499 SETGE_t();11.500 sh4_x86.tstate = TSTATE_GE;11.501 :}11.502 CMP/GT Rm, Rn {:11.503 COUNT_INST(I_CMPGT);11.504 - load_reg( R_EAX, Rm );11.505 - load_reg( R_ECX, Rn );11.506 - CMP_r32_r32( R_EAX, R_ECX );11.507 + load_reg( REG_EAX, Rm );11.508 + load_reg( REG_ECX, Rn );11.509 + CMPL_r32_r32( REG_EAX, REG_ECX );11.510 SETG_t();11.511 sh4_x86.tstate = TSTATE_G;11.512 :}11.513 CMP/HI Rm, Rn {:11.514 COUNT_INST(I_CMPHI);11.515 - load_reg( R_EAX, Rm );11.516 - load_reg( R_ECX, Rn );11.517 - CMP_r32_r32( R_EAX, R_ECX );11.518 + load_reg( REG_EAX, Rm );11.519 + load_reg( REG_ECX, Rn );11.520 + CMPL_r32_r32( REG_EAX, REG_ECX );11.521 SETA_t();11.522 sh4_x86.tstate = TSTATE_A;11.523 :}11.524 CMP/HS Rm, Rn {:11.525 COUNT_INST(I_CMPHS);11.526 - load_reg( R_EAX, Rm );11.527 - load_reg( R_ECX, Rn );11.528 - CMP_r32_r32( R_EAX, R_ECX );11.529 + load_reg( REG_EAX, Rm );11.530 + load_reg( REG_ECX, Rn );11.531 + CMPL_r32_r32( REG_EAX, REG_ECX );11.532 SETAE_t();11.533 sh4_x86.tstate = TSTATE_AE;11.534 :}11.535 CMP/PL Rn {:11.536 COUNT_INST(I_CMPPL);11.537 - load_reg( R_EAX, Rn );11.538 - CMP_imm8s_r32( 0, R_EAX );11.539 + load_reg( REG_EAX, Rn );11.540 + CMPL_imms_r32( 0, REG_EAX );11.541 SETG_t();11.542 sh4_x86.tstate = TSTATE_G;11.543 :}11.544 CMP/PZ Rn {:11.545 COUNT_INST(I_CMPPZ);11.546 - load_reg( R_EAX, Rn );11.547 - CMP_imm8s_r32( 0, R_EAX );11.548 + load_reg( REG_EAX, Rn );11.549 + CMPL_imms_r32( 0, REG_EAX );11.550 SETGE_t();11.551 sh4_x86.tstate = TSTATE_GE;11.552 :}11.553 CMP/STR Rm, Rn {:11.554 COUNT_INST(I_CMPSTR);11.555 - load_reg( R_EAX, Rm );11.556 - load_reg( R_ECX, Rn );11.557 - XOR_r32_r32( R_ECX, R_EAX );11.558 - TEST_r8_r8( R_AL, R_AL );11.559 - JE_rel8(target1);11.560 - TEST_r8_r8( R_AH, R_AH );11.561 - JE_rel8(target2);11.562 - SHR_imm8_r32( 16, R_EAX );11.563 - TEST_r8_r8( R_AL, R_AL );11.564 - JE_rel8(target3);11.565 - TEST_r8_r8( R_AH, R_AH );11.566 + load_reg( REG_EAX, Rm );11.567 + load_reg( REG_ECX, Rn );11.568 + XORL_r32_r32( REG_ECX, REG_EAX );11.569 + TESTB_r8_r8( REG_AL, REG_AL );11.570 + JE_label(target1);11.571 + TESTB_r8_r8( REG_AH, REG_AH );11.572 + JE_label(target2);11.573 + SHRL_imm_r32( 16, REG_EAX );11.574 + TESTB_r8_r8( REG_AL, REG_AL );11.575 + JE_label(target3);11.576 + TESTB_r8_r8( REG_AH, REG_AH );11.577 JMP_TARGET(target1);11.578 JMP_TARGET(target2);11.579 JMP_TARGET(target3);11.580 @@ -557,130 +560,130 @@11.581 :}11.582 DIV0S Rm, Rn {:11.583 COUNT_INST(I_DIV0S);11.584 - load_reg( R_EAX, Rm );11.585 - load_reg( R_ECX, Rn );11.586 - SHR_imm8_r32( 31, R_EAX );11.587 - SHR_imm8_r32( 31, R_ECX );11.588 - store_spreg( R_EAX, R_M );11.589 - store_spreg( R_ECX, R_Q );11.590 - CMP_r32_r32( R_EAX, R_ECX );11.591 + load_reg( REG_EAX, Rm );11.592 + load_reg( REG_ECX, Rn );11.593 + SHRL_imm_r32( 31, REG_EAX );11.594 + SHRL_imm_r32( 31, REG_ECX );11.595 + store_spreg( REG_EAX, R_M );11.596 + store_spreg( REG_ECX, R_Q );11.597 + CMPL_r32_r32( REG_EAX, REG_ECX );11.598 SETNE_t();11.599 sh4_x86.tstate = TSTATE_NE;11.600 :}11.601 DIV0U {:11.602 COUNT_INST(I_DIV0U);11.603 - XOR_r32_r32( R_EAX, R_EAX );11.604 - store_spreg( R_EAX, R_Q );11.605 - store_spreg( R_EAX, R_M );11.606 - store_spreg( R_EAX, R_T );11.607 + XORL_r32_r32( REG_EAX, REG_EAX );11.608 + store_spreg( REG_EAX, R_Q );11.609 + store_spreg( REG_EAX, R_M );11.610 + store_spreg( REG_EAX, R_T );11.611 sh4_x86.tstate = TSTATE_C; // works for DIV111.612 :}11.613 DIV1 Rm, Rn {:11.614 COUNT_INST(I_DIV1);11.615 - load_spreg( R_ECX, R_M );11.616 - load_reg( R_EAX, Rn );11.617 + load_spreg( REG_ECX, R_M );11.618 + load_reg( REG_EAX, Rn );11.619 if( sh4_x86.tstate != TSTATE_C ) {11.620 LDC_t();11.621 }11.622 - RCL1_r32( R_EAX );11.623 - SETC_r8( R_DL ); // Q'11.624 - CMP_sh4r_r32( R_Q, R_ECX );11.625 - JE_rel8(mqequal);11.626 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );11.627 - JMP_rel8(end);11.628 + RCLL_imm_r32( 1, REG_EAX );11.629 + SETC_r8( REG_DL ); // Q'11.630 + CMPL_rbpdisp_r32( R_Q, REG_ECX );11.631 + JE_label(mqequal);11.632 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );11.633 + JMP_label(end);11.634 JMP_TARGET(mqequal);11.635 - SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );11.636 + SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );11.637 JMP_TARGET(end);11.638 - store_reg( R_EAX, Rn ); // Done with Rn now11.639 - SETC_r8(R_AL); // tmp111.640 - XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp111.641 - XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M11.642 - store_spreg( R_ECX, R_Q );11.643 - XOR_imm8s_r32( 1, R_AL ); // T = !Q'11.644 - MOVZX_r8_r32( R_AL, R_EAX );11.645 - store_spreg( R_EAX, R_T );11.646 + store_reg( REG_EAX, Rn ); // Done with Rn now11.647 + SETC_r8(REG_AL); // tmp111.648 + XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp111.649 + XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M11.650 + store_spreg( REG_ECX, R_Q );11.651 + XORL_imms_r32( 1, REG_AL ); // T = !Q'11.652 + MOVZXL_r8_r32( REG_AL, REG_EAX );11.653 + store_spreg( REG_EAX, R_T );11.654 sh4_x86.tstate = TSTATE_NONE;11.655 :}11.656 DMULS.L Rm, Rn {:11.657 COUNT_INST(I_DMULS);11.658 - load_reg( R_EAX, Rm );11.659 - load_reg( R_ECX, Rn );11.660 - IMUL_r32(R_ECX);11.661 - store_spreg( R_EDX, R_MACH );11.662 - store_spreg( R_EAX, R_MACL );11.663 + load_reg( REG_EAX, Rm );11.664 + load_reg( REG_ECX, Rn );11.665 + IMULL_r32(REG_ECX);11.666 + store_spreg( REG_EDX, R_MACH );11.667 + store_spreg( REG_EAX, R_MACL );11.668 sh4_x86.tstate = TSTATE_NONE;11.669 :}11.670 DMULU.L Rm, Rn {:11.671 COUNT_INST(I_DMULU);11.672 - load_reg( R_EAX, Rm );11.673 - load_reg( R_ECX, Rn );11.674 - MUL_r32(R_ECX);11.675 - store_spreg( R_EDX, R_MACH );11.676 - store_spreg( R_EAX, R_MACL );11.677 + load_reg( REG_EAX, Rm );11.678 + load_reg( REG_ECX, Rn );11.679 + MULL_r32(REG_ECX);11.680 + store_spreg( REG_EDX, R_MACH );11.681 + store_spreg( REG_EAX, R_MACL );11.682 sh4_x86.tstate = TSTATE_NONE;11.683 :}11.684 DT Rn {:11.685 COUNT_INST(I_DT);11.686 - load_reg( R_EAX, Rn );11.687 - ADD_imm8s_r32( -1, R_EAX );11.688 - store_reg( R_EAX, Rn );11.689 + load_reg( REG_EAX, Rn );11.690 + ADDL_imms_r32( -1, REG_EAX );11.691 + store_reg( REG_EAX, Rn );11.692 SETE_t();11.693 sh4_x86.tstate = TSTATE_E;11.694 :}11.695 EXTS.B Rm, Rn {:11.696 COUNT_INST(I_EXTSB);11.697 - load_reg( R_EAX, Rm );11.698 - MOVSX_r8_r32( R_EAX, R_EAX );11.699 - store_reg( R_EAX, Rn );11.700 + load_reg( REG_EAX, Rm );11.701 + MOVSXL_r8_r32( REG_EAX, REG_EAX );11.702 + store_reg( REG_EAX, Rn );11.703 :}11.704 EXTS.W Rm, Rn {:11.705 COUNT_INST(I_EXTSW);11.706 - load_reg( R_EAX, Rm );11.707 - MOVSX_r16_r32( R_EAX, R_EAX );11.708 - store_reg( R_EAX, Rn );11.709 + load_reg( REG_EAX, Rm );11.710 + MOVSXL_r16_r32( REG_EAX, REG_EAX );11.711 + store_reg( REG_EAX, Rn );11.712 :}11.713 EXTU.B Rm, Rn {:11.714 COUNT_INST(I_EXTUB);11.715 - load_reg( R_EAX, Rm );11.716 - MOVZX_r8_r32( R_EAX, R_EAX );11.717 - store_reg( R_EAX, Rn );11.718 + load_reg( REG_EAX, Rm );11.719 + MOVZXL_r8_r32( REG_EAX, REG_EAX );11.720 + store_reg( REG_EAX, Rn );11.721 :}11.722 EXTU.W Rm, Rn {:11.723 COUNT_INST(I_EXTUW);11.724 - load_reg( R_EAX, Rm );11.725 - MOVZX_r16_r32( R_EAX, R_EAX );11.726 - store_reg( R_EAX, Rn );11.727 + load_reg( REG_EAX, Rm );11.728 + MOVZXL_r16_r32( REG_EAX, REG_EAX );11.729 + store_reg( REG_EAX, Rn );11.730 :}11.731 MAC.L @Rm+, @Rn+ {:11.732 COUNT_INST(I_MACL);11.733 if( Rm == Rn ) {11.734 - load_reg( R_EAX, Rm );11.735 - check_ralign32( R_EAX );11.736 - MEM_READ_LONG( R_EAX, R_EAX );11.737 - MOV_r32_esp8(R_EAX, 0);11.738 - load_reg( R_EAX, Rm );11.739 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );11.740 - MEM_READ_LONG( R_EAX, R_EAX );11.741 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );11.742 + load_reg( REG_EAX, Rm );11.743 + check_ralign32( REG_EAX );11.744 + MEM_READ_LONG( REG_EAX, REG_EAX );11.745 + MOVL_r32_rspdisp(REG_EAX, 0);11.746 + load_reg( REG_EAX, Rm );11.747 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );11.748 + MEM_READ_LONG( REG_EAX, REG_EAX );11.749 + ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );11.750 } else {11.751 - load_reg( R_EAX, Rm );11.752 - check_ralign32( R_EAX );11.753 - MEM_READ_LONG( R_EAX, R_EAX );11.754 - MOV_r32_esp8( R_EAX, 0 );11.755 - load_reg( R_EAX, Rn );11.756 - check_ralign32( R_EAX );11.757 - MEM_READ_LONG( R_EAX, R_EAX );11.758 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );11.759 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.760 + load_reg( REG_EAX, Rm );11.761 + check_ralign32( REG_EAX );11.762 + MEM_READ_LONG( REG_EAX, REG_EAX );11.763 + MOVL_r32_rspdisp( REG_EAX, 0 );11.764 + load_reg( REG_EAX, Rn );11.765 + check_ralign32( REG_EAX );11.766 + MEM_READ_LONG( REG_EAX, REG_EAX );11.767 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );11.768 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.769 }11.771 - IMUL_esp8( 0 );11.772 - ADD_r32_sh4r( R_EAX, R_MACL );11.773 - ADC_r32_sh4r( R_EDX, R_MACH );11.774 + IMULL_rspdisp( 0 );11.775 + ADDL_r32_rbpdisp( REG_EAX, R_MACL );11.776 + ADCL_r32_rbpdisp( REG_EDX, R_MACH );11.778 - load_spreg( R_ECX, R_S );11.779 - TEST_r32_r32(R_ECX, R_ECX);11.780 - JE_rel8( nosat );11.781 + load_spreg( REG_ECX, R_S );11.782 + TESTL_r32_r32(REG_ECX, REG_ECX);11.783 + JE_label( nosat );11.784 call_func0( signsat48 );11.785 JMP_TARGET( nosat );11.786 sh4_x86.tstate = TSTATE_NONE;11.787 @@ -688,49 +691,49 @@11.788 MAC.W @Rm+, @Rn+ {:11.789 COUNT_INST(I_MACW);11.790 if( Rm == Rn ) {11.791 - load_reg( R_EAX, Rm );11.792 - check_ralign16( R_EAX );11.793 - MEM_READ_WORD( R_EAX, R_EAX );11.794 - MOV_r32_esp8( R_EAX, 0 );11.795 - load_reg( R_EAX, Rm );11.796 - LEA_r32disp8_r32( R_EAX, 2, R_EAX );11.797 - MEM_READ_WORD( R_EAX, R_EAX );11.798 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );11.799 + load_reg( REG_EAX, Rm );11.800 + check_ralign16( REG_EAX );11.801 + MEM_READ_WORD( REG_EAX, REG_EAX );11.802 + MOVL_r32_rspdisp( REG_EAX, 0 );11.803 + load_reg( REG_EAX, Rm );11.804 + LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );11.805 + MEM_READ_WORD( REG_EAX, REG_EAX );11.806 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );11.807 // Note translate twice in case of page boundaries. Maybe worth11.808 // adding a page-boundary check to skip the second translation11.809 } else {11.810 - load_reg( R_EAX, Rm );11.811 - check_ralign16( R_EAX );11.812 - MEM_READ_WORD( R_EAX, R_EAX );11.813 - MOV_r32_esp8( R_EAX, 0 );11.814 - load_reg( R_EAX, Rn );11.815 - check_ralign16( R_EAX );11.816 - MEM_READ_WORD( R_EAX, R_EAX );11.817 - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );11.818 - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );11.819 + load_reg( REG_EAX, Rm );11.820 + check_ralign16( REG_EAX );11.821 + MEM_READ_WORD( REG_EAX, REG_EAX );11.822 + MOVL_r32_rspdisp( REG_EAX, 0 );11.823 + load_reg( REG_EAX, Rn );11.824 + check_ralign16( REG_EAX );11.825 + MEM_READ_WORD( REG_EAX, REG_EAX );11.826 + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );11.827 + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );11.828 }11.829 - IMUL_esp8( 0 );11.830 - load_spreg( R_ECX, R_S );11.831 - TEST_r32_r32( R_ECX, R_ECX );11.832 - JE_rel8( nosat );11.833 + IMULL_rspdisp( 0 );11.834 + load_spreg( REG_ECX, R_S );11.835 + TESTL_r32_r32( REG_ECX, REG_ECX );11.836 + JE_label( nosat );11.838 - ADD_r32_sh4r( R_EAX, R_MACL ); // 611.839 - JNO_rel8( end ); // 211.840 - load_imm32( R_EDX, 1 ); // 511.841 - store_spreg( R_EDX, R_MACH ); // 611.842 - JS_rel8( positive ); // 211.843 - load_imm32( R_EAX, 0x80000000 );// 511.844 - store_spreg( R_EAX, R_MACL ); // 611.845 - JMP_rel8(end2); // 211.846 + ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 611.847 + JNO_label( end ); // 211.848 + load_imm32( REG_EDX, 1 ); // 511.849 + store_spreg( REG_EDX, R_MACH ); // 611.850 + JS_label( positive ); // 211.851 + load_imm32( REG_EAX, 0x80000000 );// 511.852 + store_spreg( REG_EAX, R_MACL ); // 611.853 + JMP_label(end2); // 211.855 JMP_TARGET(positive);11.856 - load_imm32( R_EAX, 0x7FFFFFFF );// 511.857 - store_spreg( R_EAX, R_MACL ); // 611.858 - JMP_rel8(end3); // 211.859 + load_imm32( REG_EAX, 0x7FFFFFFF );// 511.860 + store_spreg( REG_EAX, R_MACL ); // 611.861 + JMP_label(end3); // 211.863 JMP_TARGET(nosat);11.864 - ADD_r32_sh4r( R_EAX, R_MACL ); // 611.865 - ADC_r32_sh4r( R_EDX, R_MACH ); // 611.866 + ADDL_r32_rbpdisp( REG_EAX, R_MACL ); // 611.867 + ADCL_r32_rbpdisp( REG_EDX, R_MACH ); // 611.868 JMP_TARGET(end);11.869 JMP_TARGET(end2);11.870 JMP_TARGET(end3);11.871 @@ -738,556 +741,556 @@11.872 :}11.873 MOVT Rn {:11.874 COUNT_INST(I_MOVT);11.875 - load_spreg( R_EAX, R_T );11.876 - store_reg( R_EAX, Rn );11.877 + load_spreg( REG_EAX, R_T );11.878 + store_reg( REG_EAX, Rn );11.879 :}11.880 MUL.L Rm, Rn {:11.881 COUNT_INST(I_MULL);11.882 - load_reg( R_EAX, Rm );11.883 - load_reg( R_ECX, Rn );11.884 - MUL_r32( R_ECX );11.885 - store_spreg( R_EAX, R_MACL );11.886 + load_reg( REG_EAX, Rm );11.887 + load_reg( REG_ECX, Rn );11.888 + MULL_r32( REG_ECX );11.889 + store_spreg( REG_EAX, R_MACL );11.890 sh4_x86.tstate = TSTATE_NONE;11.891 :}11.892 MULS.W Rm, Rn {:11.893 COUNT_INST(I_MULSW);11.894 - load_reg16s( R_EAX, Rm );11.895 - load_reg16s( R_ECX, Rn );11.896 - MUL_r32( R_ECX );11.897 - store_spreg( R_EAX, R_MACL );11.898 + load_reg16s( REG_EAX, Rm );11.899 + load_reg16s( REG_ECX, Rn );11.900 + MULL_r32( REG_ECX );11.901 + store_spreg( REG_EAX, R_MACL );11.902 sh4_x86.tstate = TSTATE_NONE;11.903 :}11.904 MULU.W Rm, Rn {:11.905 COUNT_INST(I_MULUW);11.906 - load_reg16u( R_EAX, Rm );11.907 - load_reg16u( R_ECX, Rn );11.908 - MUL_r32( R_ECX );11.909 - store_spreg( R_EAX, R_MACL );11.910 + load_reg16u( REG_EAX, Rm );11.911 + load_reg16u( REG_ECX, Rn );11.912 + MULL_r32( REG_ECX );11.913 + store_spreg( REG_EAX, R_MACL );11.914 sh4_x86.tstate = TSTATE_NONE;11.915 :}11.916 NEG Rm, Rn {:11.917 COUNT_INST(I_NEG);11.918 - load_reg( R_EAX, Rm );11.919 - NEG_r32( R_EAX );11.920 - store_reg( R_EAX, Rn );11.921 + load_reg( REG_EAX, Rm );11.922 + NEGL_r32( REG_EAX );11.923 + store_reg( REG_EAX, Rn );11.924 sh4_x86.tstate = TSTATE_NONE;11.925 :}11.926 NEGC Rm, Rn {:11.927 COUNT_INST(I_NEGC);11.928 - load_reg( R_EAX, Rm );11.929 - XOR_r32_r32( R_ECX, R_ECX );11.930 + load_reg( REG_EAX, Rm );11.931 + XORL_r32_r32( REG_ECX, REG_ECX );11.932 LDC_t();11.933 - SBB_r32_r32( R_EAX, R_ECX );11.934 - store_reg( R_ECX, Rn );11.935 + SBBL_r32_r32( REG_EAX, REG_ECX );11.936 + store_reg( REG_ECX, Rn );11.937 SETC_t();11.938 sh4_x86.tstate = TSTATE_C;11.939 :}11.940 NOT Rm, Rn {:11.941 COUNT_INST(I_NOT);11.942 - load_reg( R_EAX, Rm );11.943 - NOT_r32( R_EAX );11.944 - store_reg( R_EAX, Rn );11.945 + load_reg( REG_EAX, Rm );11.946 + NOTL_r32( REG_EAX );11.947 + store_reg( REG_EAX, Rn );11.948 sh4_x86.tstate = TSTATE_NONE;11.949 :}11.950 OR Rm, Rn {:11.951 COUNT_INST(I_OR);11.952 - load_reg( R_EAX, Rm );11.953 - load_reg( R_ECX, Rn );11.954 - OR_r32_r32( R_EAX, R_ECX );11.955 - store_reg( R_ECX, Rn );11.956 + load_reg( REG_EAX, Rm );11.957 + load_reg( REG_ECX, Rn );11.958 + ORL_r32_r32( REG_EAX, REG_ECX );11.959 + store_reg( REG_ECX, Rn );11.960 sh4_x86.tstate = TSTATE_NONE;11.961 :}11.962 OR #imm, R0 {:11.963 COUNT_INST(I_ORI);11.964 - load_reg( R_EAX, 0 );11.965 - OR_imm32_r32(imm, R_EAX);11.966 - store_reg( R_EAX, 0 );11.967 + load_reg( REG_EAX, 0 );11.968 + ORL_imms_r32(imm, REG_EAX);11.969 + store_reg( REG_EAX, 0 );11.970 sh4_x86.tstate = TSTATE_NONE;11.971 :}11.972 OR.B #imm, @(R0, GBR) {:11.973 COUNT_INST(I_ORB);11.974 - load_reg( R_EAX, 0 );11.975 - ADD_sh4r_r32( R_GBR, R_EAX );11.976 - MOV_r32_esp8( R_EAX, 0 );11.977 - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );11.978 - MOV_esp8_r32( 0, R_EAX );11.979 - OR_imm32_r32(imm, R_EDX );11.980 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.981 + load_reg( REG_EAX, 0 );11.982 + ADDL_rbpdisp_r32( R_GBR, REG_EAX );11.983 + MOVL_r32_rspdisp( REG_EAX, 0 );11.984 + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );11.985 + MOVL_rspdisp_r32( 0, REG_EAX );11.986 + ORL_imms_r32(imm, REG_EDX );11.987 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.988 sh4_x86.tstate = TSTATE_NONE;11.989 :}11.990 ROTCL Rn {:11.991 COUNT_INST(I_ROTCL);11.992 - load_reg( R_EAX, Rn );11.993 + load_reg( REG_EAX, Rn );11.994 if( sh4_x86.tstate != TSTATE_C ) {11.995 LDC_t();11.996 }11.997 - RCL1_r32( R_EAX );11.998 - store_reg( R_EAX, Rn );11.999 + RCLL_imm_r32( 1, REG_EAX );11.1000 + store_reg( REG_EAX, Rn );11.1001 SETC_t();11.1002 sh4_x86.tstate = TSTATE_C;11.1003 :}11.1004 ROTCR Rn {:11.1005 COUNT_INST(I_ROTCR);11.1006 - load_reg( R_EAX, Rn );11.1007 + load_reg( REG_EAX, Rn );11.1008 if( sh4_x86.tstate != TSTATE_C ) {11.1009 LDC_t();11.1010 }11.1011 - RCR1_r32( R_EAX );11.1012 - store_reg( R_EAX, Rn );11.1013 + RCRL_imm_r32( 1, REG_EAX );11.1014 + store_reg( REG_EAX, Rn );11.1015 SETC_t();11.1016 sh4_x86.tstate = TSTATE_C;11.1017 :}11.1018 ROTL Rn {:11.1019 COUNT_INST(I_ROTL);11.1020 - load_reg( R_EAX, Rn );11.1021 - ROL1_r32( R_EAX );11.1022 - store_reg( R_EAX, Rn );11.1023 + load_reg( REG_EAX, Rn );11.1024 + ROLL_imm_r32( 1, REG_EAX );11.1025 + store_reg( REG_EAX, Rn );11.1026 SETC_t();11.1027 sh4_x86.tstate = TSTATE_C;11.1028 :}11.1029 ROTR Rn {:11.1030 COUNT_INST(I_ROTR);11.1031 - load_reg( R_EAX, Rn );11.1032 - ROR1_r32( R_EAX );11.1033 - store_reg( R_EAX, Rn );11.1034 + load_reg( REG_EAX, Rn );11.1035 + RORL_imm_r32( 1, REG_EAX );11.1036 + store_reg( REG_EAX, Rn );11.1037 SETC_t();11.1038 sh4_x86.tstate = TSTATE_C;11.1039 :}11.1040 SHAD Rm, Rn {:11.1041 COUNT_INST(I_SHAD);11.1042 /* Annoyingly enough, not directly convertible */11.1043 - load_reg( R_EAX, Rn );11.1044 - load_reg( R_ECX, Rm );11.1045 - CMP_imm32_r32( 0, R_ECX );11.1046 - JGE_rel8(doshl);11.1047 + load_reg( REG_EAX, Rn );11.1048 + load_reg( REG_ECX, Rm );11.1049 + CMPL_imms_r32( 0, REG_ECX );11.1050 + JGE_label(doshl);11.1052 - NEG_r32( R_ECX ); // 211.1053 - AND_imm8_r8( 0x1F, R_CL ); // 311.1054 - JE_rel8(emptysar); // 211.1055 - SAR_r32_CL( R_EAX ); // 211.1056 - JMP_rel8(end); // 211.1057 + NEGL_r32( REG_ECX ); // 211.1058 + ANDB_imms_r8( 0x1F, REG_CL ); // 311.1059 + JE_label(emptysar); // 211.1060 + SARL_cl_r32( REG_EAX ); // 211.1061 + JMP_label(end); // 211.1063 JMP_TARGET(emptysar);11.1064 - SAR_imm8_r32(31, R_EAX ); // 311.1065 - JMP_rel8(end2);11.1066 + SARL_imm_r32(31, REG_EAX ); // 311.1067 + JMP_label(end2);11.1069 JMP_TARGET(doshl);11.1070 - AND_imm8_r8( 0x1F, R_CL ); // 311.1071 - SHL_r32_CL( R_EAX ); // 211.1072 + ANDB_imms_r8( 0x1F, REG_CL ); // 311.1073 + SHLL_cl_r32( REG_EAX ); // 211.1074 JMP_TARGET(end);11.1075 JMP_TARGET(end2);11.1076 - store_reg( R_EAX, Rn );11.1077 + store_reg( REG_EAX, Rn );11.1078 sh4_x86.tstate = TSTATE_NONE;11.1079 :}11.1080 SHLD Rm, Rn {:11.1081 COUNT_INST(I_SHLD);11.1082 - load_reg( R_EAX, Rn );11.1083 - load_reg( R_ECX, Rm );11.1084 - CMP_imm32_r32( 0, R_ECX );11.1085 - JGE_rel8(doshl);11.1086 + load_reg( REG_EAX, Rn );11.1087 + load_reg( REG_ECX, Rm );11.1088 + CMPL_imms_r32( 0, REG_ECX );11.1089 + JGE_label(doshl);11.1091 - NEG_r32( R_ECX ); // 211.1092 - AND_imm8_r8( 0x1F, R_CL ); // 311.1093 - JE_rel8(emptyshr );11.1094 - SHR_r32_CL( R_EAX ); // 211.1095 - JMP_rel8(end); // 211.1096 + NEGL_r32( REG_ECX ); // 211.1097 + ANDB_imms_r8( 0x1F, REG_CL ); // 311.1098 + JE_label(emptyshr );11.1099 + SHRL_cl_r32( REG_EAX ); // 211.1100 + JMP_label(end); // 211.1102 JMP_TARGET(emptyshr);11.1103 - XOR_r32_r32( R_EAX, R_EAX );11.1104 - JMP_rel8(end2);11.1105 + XORL_r32_r32( REG_EAX, REG_EAX );11.1106 + JMP_label(end2);11.1108 JMP_TARGET(doshl);11.1109 - AND_imm8_r8( 0x1F, R_CL ); // 311.1110 - SHL_r32_CL( R_EAX ); // 211.1111 + ANDB_imms_r8( 0x1F, REG_CL ); // 311.1112 + SHLL_cl_r32( REG_EAX ); // 211.1113 JMP_TARGET(end);11.1114 JMP_TARGET(end2);11.1115 - store_reg( R_EAX, Rn );11.1116 + store_reg( REG_EAX, Rn );11.1117 sh4_x86.tstate = TSTATE_NONE;11.1118 :}11.1119 SHAL Rn {:11.1120 COUNT_INST(I_SHAL);11.1121 - load_reg( R_EAX, Rn );11.1122 - SHL1_r32( R_EAX );11.1123 + load_reg( REG_EAX, Rn );11.1124 + SHLL_imm_r32( 1, REG_EAX );11.1125 SETC_t();11.1126 - store_reg( R_EAX, Rn );11.1127 + store_reg( REG_EAX, Rn );11.1128 sh4_x86.tstate = TSTATE_C;11.1129 :}11.1130 SHAR Rn {:11.1131 COUNT_INST(I_SHAR);11.1132 - load_reg( R_EAX, Rn );11.1133 - SAR1_r32( R_EAX );11.1134 + load_reg( REG_EAX, Rn );11.1135 + SARL_imm_r32( 1, REG_EAX );11.1136 SETC_t();11.1137 - store_reg( R_EAX, Rn );11.1138 + store_reg( REG_EAX, Rn );11.1139 sh4_x86.tstate = TSTATE_C;11.1140 :}11.1141 SHLL Rn {:11.1142 COUNT_INST(I_SHLL);11.1143 - load_reg( R_EAX, Rn );11.1144 - SHL1_r32( R_EAX );11.1145 + load_reg( REG_EAX, Rn );11.1146 + SHLL_imm_r32( 1, REG_EAX );11.1147 SETC_t();11.1148 - store_reg( R_EAX, Rn );11.1149 + store_reg( REG_EAX, Rn );11.1150 sh4_x86.tstate = TSTATE_C;11.1151 :}11.1152 SHLL2 Rn {:11.1153 COUNT_INST(I_SHLL);11.1154 - load_reg( R_EAX, Rn );11.1155 - SHL_imm8_r32( 2, R_EAX );11.1156 - store_reg( R_EAX, Rn );11.1157 + load_reg( REG_EAX, Rn );11.1158 + SHLL_imm_r32( 2, REG_EAX );11.1159 + store_reg( REG_EAX, Rn );11.1160 sh4_x86.tstate = TSTATE_NONE;11.1161 :}11.1162 SHLL8 Rn {:11.1163 COUNT_INST(I_SHLL);11.1164 - load_reg( R_EAX, Rn );11.1165 - SHL_imm8_r32( 8, R_EAX );11.1166 - store_reg( R_EAX, Rn );11.1167 + load_reg( REG_EAX, Rn );11.1168 + SHLL_imm_r32( 8, REG_EAX );11.1169 + store_reg( REG_EAX, Rn );11.1170 sh4_x86.tstate = TSTATE_NONE;11.1171 :}11.1172 SHLL16 Rn {:11.1173 COUNT_INST(I_SHLL);11.1174 - load_reg( R_EAX, Rn );11.1175 - SHL_imm8_r32( 16, R_EAX );11.1176 - store_reg( R_EAX, Rn );11.1177 + load_reg( REG_EAX, Rn );11.1178 + SHLL_imm_r32( 16, REG_EAX );11.1179 + store_reg( REG_EAX, Rn );11.1180 sh4_x86.tstate = TSTATE_NONE;11.1181 :}11.1182 SHLR Rn {:11.1183 COUNT_INST(I_SHLR);11.1184 - load_reg( R_EAX, Rn );11.1185 - SHR1_r32( R_EAX );11.1186 + load_reg( REG_EAX, Rn );11.1187 + SHRL_imm_r32( 1, REG_EAX );11.1188 SETC_t();11.1189 - store_reg( R_EAX, Rn );11.1190 + store_reg( REG_EAX, Rn );11.1191 sh4_x86.tstate = TSTATE_C;11.1192 :}11.1193 SHLR2 Rn {:11.1194 COUNT_INST(I_SHLR);11.1195 - load_reg( R_EAX, Rn );11.1196 - SHR_imm8_r32( 2, R_EAX );11.1197 - store_reg( R_EAX, Rn );11.1198 + load_reg( REG_EAX, Rn );11.1199 + SHRL_imm_r32( 2, REG_EAX );11.1200 + store_reg( REG_EAX, Rn );11.1201 sh4_x86.tstate = TSTATE_NONE;11.1202 :}11.1203 SHLR8 Rn {:11.1204 COUNT_INST(I_SHLR);11.1205 - load_reg( R_EAX, Rn );11.1206 - SHR_imm8_r32( 8, R_EAX );11.1207 - store_reg( R_EAX, Rn );11.1208 + load_reg( REG_EAX, Rn );11.1209 + SHRL_imm_r32( 8, REG_EAX );11.1210 + store_reg( REG_EAX, Rn );11.1211 sh4_x86.tstate = TSTATE_NONE;11.1212 :}11.1213 SHLR16 Rn {:11.1214 COUNT_INST(I_SHLR);11.1215 - load_reg( R_EAX, Rn );11.1216 - SHR_imm8_r32( 16, R_EAX );11.1217 - store_reg( R_EAX, Rn );11.1218 + load_reg( REG_EAX, Rn );11.1219 + SHRL_imm_r32( 16, REG_EAX );11.1220 + store_reg( REG_EAX, Rn );11.1221 sh4_x86.tstate = TSTATE_NONE;11.1222 :}11.1223 SUB Rm, Rn {:11.1224 COUNT_INST(I_SUB);11.1225 - load_reg( R_EAX, Rm );11.1226 - load_reg( R_ECX, Rn );11.1227 - SUB_r32_r32( R_EAX, R_ECX );11.1228 - store_reg( R_ECX, Rn );11.1229 + load_reg( REG_EAX, Rm );11.1230 + load_reg( REG_ECX, Rn );11.1231 + SUBL_r32_r32( REG_EAX, REG_ECX );11.1232 + store_reg( REG_ECX, Rn );11.1233 sh4_x86.tstate = TSTATE_NONE;11.1234 :}11.1235 SUBC Rm, Rn {:11.1236 COUNT_INST(I_SUBC);11.1237 - load_reg( R_EAX, Rm );11.1238 - load_reg( R_ECX, Rn );11.1239 + load_reg( REG_EAX, Rm );11.1240 + load_reg( REG_ECX, Rn );11.1241 if( sh4_x86.tstate != TSTATE_C ) {11.1242 LDC_t();11.1243 }11.1244 - SBB_r32_r32( R_EAX, R_ECX );11.1245 - store_reg( R_ECX, Rn );11.1246 + SBBL_r32_r32( REG_EAX, REG_ECX );11.1247 + store_reg( REG_ECX, Rn );11.1248 SETC_t();11.1249 sh4_x86.tstate = TSTATE_C;11.1250 :}11.1251 SUBV Rm, Rn {:11.1252 COUNT_INST(I_SUBV);11.1253 - load_reg( R_EAX, Rm );11.1254 - load_reg( R_ECX, Rn );11.1255 - SUB_r32_r32( R_EAX, R_ECX );11.1256 - store_reg( R_ECX, Rn );11.1257 + load_reg( REG_EAX, Rm );11.1258 + load_reg( REG_ECX, Rn );11.1259 + SUBL_r32_r32( REG_EAX, REG_ECX );11.1260 + store_reg( REG_ECX, Rn );11.1261 SETO_t();11.1262 sh4_x86.tstate = TSTATE_O;11.1263 :}11.1264 SWAP.B Rm, Rn {:11.1265 COUNT_INST(I_SWAPB);11.1266 - load_reg( R_EAX, Rm );11.1267 - XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS11.1268 - store_reg( R_EAX, Rn );11.1269 + load_reg( REG_EAX, Rm );11.1270 + XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS11.1271 + store_reg( REG_EAX, Rn );11.1272 :}11.1273 SWAP.W Rm, Rn {:11.1274 COUNT_INST(I_SWAPB);11.1275 - load_reg( R_EAX, Rm );11.1276 - MOV_r32_r32( R_EAX, R_ECX );11.1277 - SHL_imm8_r32( 16, R_ECX );11.1278 - SHR_imm8_r32( 16, R_EAX );11.1279 - OR_r32_r32( R_EAX, R_ECX );11.1280 - store_reg( R_ECX, Rn );11.1281 + load_reg( REG_EAX, Rm );11.1282 + MOVL_r32_r32( REG_EAX, REG_ECX );11.1283 + SHLL_imm_r32( 16, REG_ECX );11.1284 + SHRL_imm_r32( 16, REG_EAX );11.1285 + ORL_r32_r32( REG_EAX, REG_ECX );11.1286 + store_reg( REG_ECX, Rn );11.1287 sh4_x86.tstate = TSTATE_NONE;11.1288 :}11.1289 TAS.B @Rn {:11.1290 COUNT_INST(I_TASB);11.1291 - load_reg( R_EAX, Rn );11.1292 - MOV_r32_esp8( R_EAX, 0 );11.1293 - MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );11.1294 - TEST_r8_r8( R_DL, R_DL );11.1295 + load_reg( REG_EAX, Rn );11.1296 + MOVL_r32_rspdisp( REG_EAX, 0 );11.1297 + MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );11.1298 + TESTB_r8_r8( REG_DL, REG_DL );11.1299 SETE_t();11.1300 - OR_imm8_r8( 0x80, R_DL );11.1301 - MOV_esp8_r32( 0, R_EAX );11.1302 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.1303 + ORB_imms_r8( 0x80, REG_DL );11.1304 + MOVL_rspdisp_r32( 0, REG_EAX );11.1305 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.1306 sh4_x86.tstate = TSTATE_NONE;11.1307 :}11.1308 TST Rm, Rn {:11.1309 COUNT_INST(I_TST);11.1310 - load_reg( R_EAX, Rm );11.1311 - load_reg( R_ECX, Rn );11.1312 - TEST_r32_r32( R_EAX, R_ECX );11.1313 + load_reg( REG_EAX, Rm );11.1314 + load_reg( REG_ECX, Rn );11.1315 + TESTL_r32_r32( REG_EAX, REG_ECX );11.1316 SETE_t();11.1317 sh4_x86.tstate = TSTATE_E;11.1318 :}11.1319 TST #imm, R0 {:11.1320 COUNT_INST(I_TSTI);11.1321 - load_reg( R_EAX, 0 );11.1322 - TEST_imm32_r32( imm, R_EAX );11.1323 + load_reg( REG_EAX, 0 );11.1324 + TESTL_imms_r32( imm, REG_EAX );11.1325 SETE_t();11.1326 sh4_x86.tstate = TSTATE_E;11.1327 :}11.1328 TST.B #imm, @(R0, GBR) {:11.1329 COUNT_INST(I_TSTB);11.1330 - load_reg( R_EAX, 0);11.1331 - ADD_sh4r_r32( R_GBR, R_EAX );11.1332 - MEM_READ_BYTE( R_EAX, R_EAX );11.1333 - TEST_imm8_r8( imm, R_AL );11.1334 + load_reg( REG_EAX, 0);11.1335 + ADDL_rbpdisp_r32( R_GBR, REG_EAX );11.1336 + MEM_READ_BYTE( REG_EAX, REG_EAX );11.1337 + TESTB_imms_r8( imm, REG_AL );11.1338 SETE_t();11.1339 sh4_x86.tstate = TSTATE_E;11.1340 :}11.1341 XOR Rm, Rn {:11.1342 COUNT_INST(I_XOR);11.1343 - load_reg( R_EAX, Rm );11.1344 - load_reg( R_ECX, Rn );11.1345 - XOR_r32_r32( R_EAX, R_ECX );11.1346 - store_reg( R_ECX, Rn );11.1347 + load_reg( REG_EAX, Rm );11.1348 + load_reg( REG_ECX, Rn );11.1349 + XORL_r32_r32( REG_EAX, REG_ECX );11.1350 + store_reg( REG_ECX, Rn );11.1351 sh4_x86.tstate = TSTATE_NONE;11.1352 :}11.1353 XOR #imm, R0 {:11.1354 COUNT_INST(I_XORI);11.1355 - load_reg( R_EAX, 0 );11.1356 - XOR_imm32_r32( imm, R_EAX );11.1357 - store_reg( R_EAX, 0 );11.1358 + load_reg( REG_EAX, 0 );11.1359 + XORL_imms_r32( imm, REG_EAX );11.1360 + store_reg( REG_EAX, 0 );11.1361 sh4_x86.tstate = TSTATE_NONE;11.1362 :}11.1363 XOR.B #imm, @(R0, GBR) {:11.1364 COUNT_INST(I_XORB);11.1365 - load_reg( R_EAX, 0 );11.1366 - ADD_sh4r_r32( R_GBR, R_EAX );11.1367 - MOV_r32_esp8( R_EAX, 0 );11.1368 - MEM_READ_BYTE_FOR_WRITE(R_EAX, R_EDX);11.1369 - MOV_esp8_r32( 0, R_EAX );11.1370 - XOR_imm32_r32( imm, R_EDX );11.1371 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.1372 + load_reg( REG_EAX, 0 );11.1373 + ADDL_rbpdisp_r32( R_GBR, REG_EAX );11.1374 + MOVL_r32_rspdisp( REG_EAX, 0 );11.1375 + MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);11.1376 + MOVL_rspdisp_r32( 0, REG_EAX );11.1377 + XORL_imms_r32( imm, REG_EDX );11.1378 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.1379 sh4_x86.tstate = TSTATE_NONE;11.1380 :}11.1381 XTRCT Rm, Rn {:11.1382 COUNT_INST(I_XTRCT);11.1383 - load_reg( R_EAX, Rm );11.1384 - load_reg( R_ECX, Rn );11.1385 - SHL_imm8_r32( 16, R_EAX );11.1386 - SHR_imm8_r32( 16, R_ECX );11.1387 - OR_r32_r32( R_EAX, R_ECX );11.1388 - store_reg( R_ECX, Rn );11.1389 + load_reg( REG_EAX, Rm );11.1390 + load_reg( REG_ECX, Rn );11.1391 + SHLL_imm_r32( 16, REG_EAX );11.1392 + SHRL_imm_r32( 16, REG_ECX );11.1393 + ORL_r32_r32( REG_EAX, REG_ECX );11.1394 + store_reg( REG_ECX, Rn );11.1395 sh4_x86.tstate = TSTATE_NONE;11.1396 :}11.1398 /* Data move instructions */11.1399 MOV Rm, Rn {:11.1400 COUNT_INST(I_MOV);11.1401 - load_reg( R_EAX, Rm );11.1402 - store_reg( R_EAX, Rn );11.1403 + load_reg( REG_EAX, Rm );11.1404 + store_reg( REG_EAX, Rn );11.1405 :}11.1406 MOV #imm, Rn {:11.1407 COUNT_INST(I_MOVI);11.1408 - load_imm32( R_EAX, imm );11.1409 - store_reg( R_EAX, Rn );11.1410 + load_imm32( REG_EAX, imm );11.1411 + store_reg( REG_EAX, Rn );11.1412 :}11.1413 MOV.B Rm, @Rn {:11.1414 COUNT_INST(I_MOVB);11.1415 - load_reg( R_EAX, Rn );11.1416 - load_reg( R_EDX, Rm );11.1417 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.1418 + load_reg( REG_EAX, Rn );11.1419 + load_reg( REG_EDX, Rm );11.1420 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.1421 sh4_x86.tstate = TSTATE_NONE;11.1422 :}11.1423 MOV.B Rm, @-Rn {:11.1424 COUNT_INST(I_MOVB);11.1425 - load_reg( R_EAX, Rn );11.1426 - LEA_r32disp8_r32( R_EAX, -1, R_EAX );11.1427 - load_reg( R_EDX, Rm );11.1428 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.1429 - ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );11.1430 + load_reg( REG_EAX, Rn );11.1431 + LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );11.1432 + load_reg( REG_EDX, Rm );11.1433 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.1434 + ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );11.1435 sh4_x86.tstate = TSTATE_NONE;11.1436 :}11.1437 MOV.B Rm, @(R0, Rn) {:11.1438 COUNT_INST(I_MOVB);11.1439 - load_reg( R_EAX, 0 );11.1440 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );11.1441 - load_reg( R_EDX, Rm );11.1442 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.1443 + load_reg( REG_EAX, 0 );11.1444 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );11.1445 + load_reg( REG_EDX, Rm );11.1446 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.1447 sh4_x86.tstate = TSTATE_NONE;11.1448 :}11.1449 MOV.B R0, @(disp, GBR) {:11.1450 COUNT_INST(I_MOVB);11.1451 - load_spreg( R_EAX, R_GBR );11.1452 - ADD_imm32_r32( disp, R_EAX );11.1453 - load_reg( R_EDX, 0 );11.1454 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.1455 + load_spreg( REG_EAX, R_GBR );11.1456 + ADDL_imms_r32( disp, REG_EAX );11.1457 + load_reg( REG_EDX, 0 );11.1458 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.1459 sh4_x86.tstate = TSTATE_NONE;11.1460 :}11.1461 MOV.B R0, @(disp, Rn) {:11.1462 COUNT_INST(I_MOVB);11.1463 - load_reg( R_EAX, Rn );11.1464 - ADD_imm32_r32( disp, R_EAX );11.1465 - load_reg( R_EDX, 0 );11.1466 - MEM_WRITE_BYTE( R_EAX, R_EDX );11.1467 + load_reg( REG_EAX, Rn );11.1468 + ADDL_imms_r32( disp, REG_EAX );11.1469 + load_reg( REG_EDX, 0 );11.1470 + MEM_WRITE_BYTE( REG_EAX, REG_EDX );11.1471 sh4_x86.tstate = TSTATE_NONE;11.1472 :}11.1473 MOV.B @Rm, Rn {:11.1474 COUNT_INST(I_MOVB);11.1475 - load_reg( R_EAX, Rm );11.1476 - MEM_READ_BYTE( R_EAX, R_EAX );11.1477 - store_reg( R_EAX, Rn );11.1478 + load_reg( REG_EAX, Rm );11.1479 + MEM_READ_BYTE( REG_EAX, REG_EAX );11.1480 + store_reg( REG_EAX, Rn );11.1481 sh4_x86.tstate = TSTATE_NONE;11.1482 :}11.1483 MOV.B @Rm+, Rn {:11.1484 COUNT_INST(I_MOVB);11.1485 - load_reg( R_EAX, Rm );11.1486 - MEM_READ_BYTE( R_EAX, R_EAX );11.1487 + load_reg( REG_EAX, Rm );11.1488 + MEM_READ_BYTE( REG_EAX, REG_EAX );11.1489 if( Rm != Rn ) {11.1490 - ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );11.1491 + ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );11.1492 }11.1493 - store_reg( R_EAX, Rn );11.1494 + store_reg( REG_EAX, Rn );11.1495 sh4_x86.tstate = TSTATE_NONE;11.1496 :}11.1497 MOV.B @(R0, Rm), Rn {:11.1498 COUNT_INST(I_MOVB);11.1499 - load_reg( R_EAX, 0 );11.1500 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );11.1501 - MEM_READ_BYTE( R_EAX, R_EAX );11.1502 - store_reg( R_EAX, Rn );11.1503 + load_reg( REG_EAX, 0 );11.1504 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );11.1505 + MEM_READ_BYTE( REG_EAX, REG_EAX );11.1506 + store_reg( REG_EAX, Rn );11.1507 sh4_x86.tstate = TSTATE_NONE;11.1508 :}11.1509 MOV.B @(disp, GBR), R0 {:11.1510 COUNT_INST(I_MOVB);11.1511 - load_spreg( R_EAX, R_GBR );11.1512 - ADD_imm32_r32( disp, R_EAX );11.1513 - MEM_READ_BYTE( R_EAX, R_EAX );11.1514 - store_reg( R_EAX, 0 );11.1515 + load_spreg( REG_EAX, R_GBR );11.1516 + ADDL_imms_r32( disp, REG_EAX );11.1517 + MEM_READ_BYTE( REG_EAX, REG_EAX );11.1518 + store_reg( REG_EAX, 0 );11.1519 sh4_x86.tstate = TSTATE_NONE;11.1520 :}11.1521 MOV.B @(disp, Rm), R0 {:11.1522 COUNT_INST(I_MOVB);11.1523 - load_reg( R_EAX, Rm );11.1524 - ADD_imm32_r32( disp, R_EAX );11.1525 - MEM_READ_BYTE( R_EAX, R_EAX );11.1526 - store_reg( R_EAX, 0 );11.1527 + load_reg( REG_EAX, Rm );11.1528 + ADDL_imms_r32( disp, REG_EAX );11.1529 + MEM_READ_BYTE( REG_EAX, REG_EAX );11.1530 + store_reg( REG_EAX, 0 );11.1531 sh4_x86.tstate = TSTATE_NONE;11.1532 :}11.1533 MOV.L Rm, @Rn {:11.1534 COUNT_INST(I_MOVL);11.1535 - load_reg( R_EAX, Rn );11.1536 - check_walign32(R_EAX);11.1537 - MOV_r32_r32( R_EAX, R_ECX );11.1538 - AND_imm32_r32( 0xFC000000, R_ECX );11.1539 - CMP_imm32_r32( 0xE0000000, R_ECX );11.1540 - JNE_rel8( notsq );11.1541 - AND_imm8s_r32( 0x3C, R_EAX );11.1542 - load_reg( R_EDX, Rm );11.1543 - MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );11.1544 - JMP_rel8(end);11.1545 + load_reg( REG_EAX, Rn );11.1546 + check_walign32(REG_EAX);11.1547 + MOVL_r32_r32( REG_EAX, REG_ECX );11.1548 + ANDL_imms_r32( 0xFC000000, REG_ECX );11.1549 + CMPL_imms_r32( 0xE0000000, REG_ECX );11.1550 + JNE_label( notsq );11.1551 + ANDL_imms_r32( 0x3C, REG_EAX );11.1552 + load_reg( REG_EDX, Rm );11.1553 + MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );11.1554 + JMP_label(end);11.1555 JMP_TARGET(notsq);11.1556 - load_reg( R_EDX, Rm );11.1557 - MEM_WRITE_LONG( R_EAX, R_EDX );11.1558 + load_reg( REG_EDX, Rm );11.1559 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.1560 JMP_TARGET(end);11.1561 sh4_x86.tstate = TSTATE_NONE;11.1562 :}11.1563 MOV.L Rm, @-Rn {:11.1564 COUNT_INST(I_MOVL);11.1565 - load_reg( R_EAX, Rn );11.1566 - ADD_imm8s_r32( -4, R_EAX );11.1567 - check_walign32( R_EAX );11.1568 - load_reg( R_EDX, Rm );11.1569 - MEM_WRITE_LONG( R_EAX, R_EDX );11.1570 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.1571 + load_reg( REG_EAX, Rn );11.1572 + ADDL_imms_r32( -4, REG_EAX );11.1573 + check_walign32( REG_EAX );11.1574 + load_reg( REG_EDX, Rm );11.1575 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.1576 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.1577 sh4_x86.tstate = TSTATE_NONE;11.1578 :}11.1579 MOV.L Rm, @(R0, Rn) {:11.1580 COUNT_INST(I_MOVL);11.1581 - load_reg( R_EAX, 0 );11.1582 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );11.1583 - check_walign32( R_EAX );11.1584 - load_reg( R_EDX, Rm );11.1585 - MEM_WRITE_LONG( R_EAX, R_EDX );11.1586 + load_reg( REG_EAX, 0 );11.1587 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );11.1588 + check_walign32( REG_EAX );11.1589 + load_reg( REG_EDX, Rm );11.1590 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.1591 sh4_x86.tstate = TSTATE_NONE;11.1592 :}11.1593 MOV.L R0, @(disp, GBR) {:11.1594 COUNT_INST(I_MOVL);11.1595 - load_spreg( R_EAX, R_GBR );11.1596 - ADD_imm32_r32( disp, R_EAX );11.1597 - check_walign32( R_EAX );11.1598 - load_reg( R_EDX, 0 );11.1599 - MEM_WRITE_LONG( R_EAX, R_EDX );11.1600 + load_spreg( REG_EAX, R_GBR );11.1601 + ADDL_imms_r32( disp, REG_EAX );11.1602 + check_walign32( REG_EAX );11.1603 + load_reg( REG_EDX, 0 );11.1604 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.1605 sh4_x86.tstate = TSTATE_NONE;11.1606 :}11.1607 MOV.L Rm, @(disp, Rn) {:11.1608 COUNT_INST(I_MOVL);11.1609 - load_reg( R_EAX, Rn );11.1610 - ADD_imm32_r32( disp, R_EAX );11.1611 - check_walign32( R_EAX );11.1612 - MOV_r32_r32( R_EAX, R_ECX );11.1613 - AND_imm32_r32( 0xFC000000, R_ECX );11.1614 - CMP_imm32_r32( 0xE0000000, R_ECX );11.1615 - JNE_rel8( notsq );11.1616 - AND_imm8s_r32( 0x3C, R_EAX );11.1617 - load_reg( R_EDX, Rm );11.1618 - MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );11.1619 - JMP_rel8(end);11.1620 + load_reg( REG_EAX, Rn );11.1621 + ADDL_imms_r32( disp, REG_EAX );11.1622 + check_walign32( REG_EAX );11.1623 + MOVL_r32_r32( REG_EAX, REG_ECX );11.1624 + ANDL_imms_r32( 0xFC000000, REG_ECX );11.1625 + CMPL_imms_r32( 0xE0000000, REG_ECX );11.1626 + JNE_label( notsq );11.1627 + ANDL_imms_r32( 0x3C, REG_EAX );11.1628 + load_reg( REG_EDX, Rm );11.1629 + MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );11.1630 + JMP_label(end);11.1631 JMP_TARGET(notsq);11.1632 - load_reg( R_EDX, Rm );11.1633 - MEM_WRITE_LONG( R_EAX, R_EDX );11.1634 + load_reg( REG_EDX, Rm );11.1635 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.1636 JMP_TARGET(end);11.1637 sh4_x86.tstate = TSTATE_NONE;11.1638 :}11.1639 MOV.L @Rm, Rn {:11.1640 COUNT_INST(I_MOVL);11.1641 - load_reg( R_EAX, Rm );11.1642 - check_ralign32( R_EAX );11.1643 - MEM_READ_LONG( R_EAX, R_EAX );11.1644 - store_reg( R_EAX, Rn );11.1645 + load_reg( REG_EAX, Rm );11.1646 + check_ralign32( REG_EAX );11.1647 + MEM_READ_LONG( REG_EAX, REG_EAX );11.1648 + store_reg( REG_EAX, Rn );11.1649 sh4_x86.tstate = TSTATE_NONE;11.1650 :}11.1651 MOV.L @Rm+, Rn {:11.1652 COUNT_INST(I_MOVL);11.1653 - load_reg( R_EAX, Rm );11.1654 - check_ralign32( R_EAX );11.1655 - MEM_READ_LONG( R_EAX, R_EAX );11.1656 + load_reg( REG_EAX, Rm );11.1657 + check_ralign32( REG_EAX );11.1658 + MEM_READ_LONG( REG_EAX, REG_EAX );11.1659 if( Rm != Rn ) {11.1660 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.1661 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.1662 }11.1663 - store_reg( R_EAX, Rn );11.1664 + store_reg( REG_EAX, Rn );11.1665 sh4_x86.tstate = TSTATE_NONE;11.1666 :}11.1667 MOV.L @(R0, Rm), Rn {:11.1668 COUNT_INST(I_MOVL);11.1669 - load_reg( R_EAX, 0 );11.1670 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );11.1671 - check_ralign32( R_EAX );11.1672 - MEM_READ_LONG( R_EAX, R_EAX );11.1673 - store_reg( R_EAX, Rn );11.1674 + load_reg( REG_EAX, 0 );11.1675 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );11.1676 + check_ralign32( REG_EAX );11.1677 + MEM_READ_LONG( REG_EAX, REG_EAX );11.1678 + store_reg( REG_EAX, Rn );11.1679 sh4_x86.tstate = TSTATE_NONE;11.1680 :}11.1681 MOV.L @(disp, GBR), R0 {:11.1682 COUNT_INST(I_MOVL);11.1683 - load_spreg( R_EAX, R_GBR );11.1684 - ADD_imm32_r32( disp, R_EAX );11.1685 - check_ralign32( R_EAX );11.1686 - MEM_READ_LONG( R_EAX, R_EAX );11.1687 - store_reg( R_EAX, 0 );11.1688 + load_spreg( REG_EAX, R_GBR );11.1689 + ADDL_imms_r32( disp, REG_EAX );11.1690 + check_ralign32( REG_EAX );11.1691 + MEM_READ_LONG( REG_EAX, REG_EAX );11.1692 + store_reg( REG_EAX, 0 );11.1693 sh4_x86.tstate = TSTATE_NONE;11.1694 :}11.1695 MOV.L @(disp, PC), Rn {:11.1696 @@ -1307,108 +1310,108 @@11.1697 // behaviour to confirm) Unlikely to be anyone depending on this11.1698 // behaviour though.11.1699 sh4ptr_t ptr = GET_ICACHE_PTR(target);11.1700 - MOV_moff32_EAX( ptr );11.1701 + MOVL_moffptr_eax( ptr );11.1702 } else {11.1703 // Note: we use sh4r.pc for the calc as we could be running at a11.1704 // different virtual address than the translation was done with,11.1705 // but we can safely assume that the low bits are the same.11.1706 - load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );11.1707 - ADD_sh4r_r32( R_PC, R_EAX );11.1708 - MEM_READ_LONG( R_EAX, R_EAX );11.1709 + load_imm32( REG_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );11.1710 + ADDL_rbpdisp_r32( R_PC, REG_EAX );11.1711 + MEM_READ_LONG( REG_EAX, REG_EAX );11.1712 sh4_x86.tstate = TSTATE_NONE;11.1713 }11.1714 - store_reg( R_EAX, Rn );11.1715 + store_reg( REG_EAX, Rn );11.1716 }11.1717 :}11.1718 MOV.L @(disp, Rm), Rn {:11.1719 COUNT_INST(I_MOVL);11.1720 - load_reg( R_EAX, Rm );11.1721 - ADD_imm8s_r32( disp, R_EAX );11.1722 - check_ralign32( R_EAX );11.1723 - MEM_READ_LONG( R_EAX, R_EAX );11.1724 - store_reg( R_EAX, Rn );11.1725 + load_reg( REG_EAX, Rm );11.1726 + ADDL_imms_r32( disp, REG_EAX );11.1727 + check_ralign32( REG_EAX );11.1728 + MEM_READ_LONG( REG_EAX, REG_EAX );11.1729 + store_reg( REG_EAX, Rn );11.1730 sh4_x86.tstate = TSTATE_NONE;11.1731 :}11.1732 MOV.W Rm, @Rn {:11.1733 COUNT_INST(I_MOVW);11.1734 - load_reg( R_EAX, Rn );11.1735 - check_walign16( R_EAX );11.1736 - load_reg( R_EDX, Rm );11.1737 - MEM_WRITE_WORD( R_EAX, R_EDX );11.1738 + load_reg( REG_EAX, Rn );11.1739 + check_walign16( REG_EAX );11.1740 + load_reg( REG_EDX, Rm );11.1741 + MEM_WRITE_WORD( REG_EAX, REG_EDX );11.1742 sh4_x86.tstate = TSTATE_NONE;11.1743 :}11.1744 MOV.W Rm, @-Rn {:11.1745 COUNT_INST(I_MOVW);11.1746 - load_reg( R_EAX, Rn );11.1747 - check_walign16( R_EAX );11.1748 - LEA_r32disp8_r32( R_EAX, -2, R_EAX );11.1749 - load_reg( R_EDX, Rm );11.1750 - MEM_WRITE_WORD( R_EAX, R_EDX );11.1751 - ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );11.1752 + load_reg( REG_EAX, Rn );11.1753 + check_walign16( REG_EAX );11.1754 + LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );11.1755 + load_reg( REG_EDX, Rm );11.1756 + MEM_WRITE_WORD( REG_EAX, REG_EDX );11.1757 + ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );11.1758 sh4_x86.tstate = TSTATE_NONE;11.1759 :}11.1760 MOV.W Rm, @(R0, Rn) {:11.1761 COUNT_INST(I_MOVW);11.1762 - load_reg( R_EAX, 0 );11.1763 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );11.1764 - check_walign16( R_EAX );11.1765 - load_reg( R_EDX, Rm );11.1766 - MEM_WRITE_WORD( R_EAX, R_EDX );11.1767 + load_reg( REG_EAX, 0 );11.1768 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );11.1769 + check_walign16( REG_EAX );11.1770 + load_reg( REG_EDX, Rm );11.1771 + MEM_WRITE_WORD( REG_EAX, REG_EDX );11.1772 sh4_x86.tstate = TSTATE_NONE;11.1773 :}11.1774 MOV.W R0, @(disp, GBR) {:11.1775 COUNT_INST(I_MOVW);11.1776 - load_spreg( R_EAX, R_GBR );11.1777 - ADD_imm32_r32( disp, R_EAX );11.1778 - check_walign16( R_EAX );11.1779 - load_reg( R_EDX, 0 );11.1780 - MEM_WRITE_WORD( R_EAX, R_EDX );11.1781 + load_spreg( REG_EAX, R_GBR );11.1782 + ADDL_imms_r32( disp, REG_EAX );11.1783 + check_walign16( REG_EAX );11.1784 + load_reg( REG_EDX, 0 );11.1785 + MEM_WRITE_WORD( REG_EAX, REG_EDX );11.1786 sh4_x86.tstate = TSTATE_NONE;11.1787 :}11.1788 MOV.W R0, @(disp, Rn) {:11.1789 COUNT_INST(I_MOVW);11.1790 - load_reg( R_EAX, Rn );11.1791 - ADD_imm32_r32( disp, R_EAX );11.1792 - check_walign16( R_EAX );11.1793 - load_reg( R_EDX, 0 );11.1794 - MEM_WRITE_WORD( R_EAX, R_EDX );11.1795 + load_reg( REG_EAX, Rn );11.1796 + ADDL_imms_r32( disp, REG_EAX );11.1797 + check_walign16( REG_EAX );11.1798 + load_reg( REG_EDX, 0 );11.1799 + MEM_WRITE_WORD( REG_EAX, REG_EDX );11.1800 sh4_x86.tstate = TSTATE_NONE;11.1801 :}11.1802 MOV.W @Rm, Rn {:11.1803 COUNT_INST(I_MOVW);11.1804 - load_reg( R_EAX, Rm );11.1805 - check_ralign16( R_EAX );11.1806 - MEM_READ_WORD( R_EAX, R_EAX );11.1807 - store_reg( R_EAX, Rn );11.1808 + load_reg( REG_EAX, Rm );11.1809 + check_ralign16( REG_EAX );11.1810 + MEM_READ_WORD( REG_EAX, REG_EAX );11.1811 + store_reg( REG_EAX, Rn );11.1812 sh4_x86.tstate = TSTATE_NONE;11.1813 :}11.1814 MOV.W @Rm+, Rn {:11.1815 COUNT_INST(I_MOVW);11.1816 - load_reg( R_EAX, Rm );11.1817 - check_ralign16( R_EAX );11.1818 - MEM_READ_WORD( R_EAX, R_EAX );11.1819 + load_reg( REG_EAX, Rm );11.1820 + check_ralign16( REG_EAX );11.1821 + MEM_READ_WORD( REG_EAX, REG_EAX );11.1822 if( Rm != Rn ) {11.1823 - ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );11.1824 + ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );11.1825 }11.1826 - store_reg( R_EAX, Rn );11.1827 + store_reg( REG_EAX, Rn );11.1828 sh4_x86.tstate = TSTATE_NONE;11.1829 :}11.1830 MOV.W @(R0, Rm), Rn {:11.1831 COUNT_INST(I_MOVW);11.1832 - load_reg( R_EAX, 0 );11.1833 - ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );11.1834 - check_ralign16( R_EAX );11.1835 - MEM_READ_WORD( R_EAX, R_EAX );11.1836 - store_reg( R_EAX, Rn );11.1837 + load_reg( REG_EAX, 0 );11.1838 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );11.1839 + check_ralign16( REG_EAX );11.1840 + MEM_READ_WORD( REG_EAX, REG_EAX );11.1841 + store_reg( REG_EAX, Rn );11.1842 sh4_x86.tstate = TSTATE_NONE;11.1843 :}11.1844 MOV.W @(disp, GBR), R0 {:11.1845 COUNT_INST(I_MOVW);11.1846 - load_spreg( R_EAX, R_GBR );11.1847 - ADD_imm32_r32( disp, R_EAX );11.1848 - check_ralign16( R_EAX );11.1849 - MEM_READ_WORD( R_EAX, R_EAX );11.1850 - store_reg( R_EAX, 0 );11.1851 + load_spreg( REG_EAX, R_GBR );11.1852 + ADDL_imms_r32( disp, REG_EAX );11.1853 + check_ralign16( REG_EAX );11.1854 + MEM_READ_WORD( REG_EAX, REG_EAX );11.1855 + store_reg( REG_EAX, 0 );11.1856 sh4_x86.tstate = TSTATE_NONE;11.1857 :}11.1858 MOV.W @(disp, PC), Rn {:11.1859 @@ -1420,24 +1423,24 @@11.1860 uint32_t target = pc + disp + 4;11.1861 if( IS_IN_ICACHE(target) ) {11.1862 sh4ptr_t ptr = GET_ICACHE_PTR(target);11.1863 - MOV_moff32_EAX( ptr );11.1864 - MOVSX_r16_r32( R_EAX, R_EAX );11.1865 + MOVL_moffptr_eax( ptr );11.1866 + MOVSXL_r16_r32( REG_EAX, REG_EAX );11.1867 } else {11.1868 - load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );11.1869 - ADD_sh4r_r32( R_PC, R_EAX );11.1870 - MEM_READ_WORD( R_EAX, R_EAX );11.1871 + load_imm32( REG_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );11.1872 + ADDL_rbpdisp_r32( R_PC, REG_EAX );11.1873 + MEM_READ_WORD( REG_EAX, REG_EAX );11.1874 sh4_x86.tstate = TSTATE_NONE;11.1875 }11.1876 - store_reg( R_EAX, Rn );11.1877 + store_reg( REG_EAX, Rn );11.1878 }11.1879 :}11.1880 MOV.W @(disp, Rm), R0 {:11.1881 COUNT_INST(I_MOVW);11.1882 - load_reg( R_EAX, Rm );11.1883 - ADD_imm32_r32( disp, R_EAX );11.1884 - check_ralign16( R_EAX );11.1885 - MEM_READ_WORD( R_EAX, R_EAX );11.1886 - store_reg( R_EAX, 0 );11.1887 + load_reg( REG_EAX, Rm );11.1888 + ADDL_imms_r32( disp, REG_EAX );11.1889 + check_ralign16( REG_EAX );11.1890 + MEM_READ_WORD( REG_EAX, REG_EAX );11.1891 + store_reg( REG_EAX, 0 );11.1892 sh4_x86.tstate = TSTATE_NONE;11.1893 :}11.1894 MOVA @(disp, PC), R0 {:11.1895 @@ -1445,18 +1448,18 @@11.1896 if( sh4_x86.in_delay_slot ) {11.1897 SLOTILLEGAL();11.1898 } else {11.1899 - load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );11.1900 - ADD_sh4r_r32( R_PC, R_ECX );11.1901 - store_reg( R_ECX, 0 );11.1902 + load_imm32( REG_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );11.1903 + ADDL_rbpdisp_r32( R_PC, REG_ECX );11.1904 + store_reg( REG_ECX, 0 );11.1905 sh4_x86.tstate = TSTATE_NONE;11.1906 }11.1907 :}11.1908 MOVCA.L R0, @Rn {:11.1909 COUNT_INST(I_MOVCA);11.1910 - load_reg( R_EAX, Rn );11.1911 - check_walign32( R_EAX );11.1912 - load_reg( R_EDX, 0 );11.1913 - MEM_WRITE_LONG( R_EAX, R_EDX );11.1914 + load_reg( REG_EAX, Rn );11.1915 + check_walign32( REG_EAX );11.1916 + load_reg( REG_EDX, 0 );11.1917 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.1918 sh4_x86.tstate = TSTATE_NONE;11.1919 :}11.1921 @@ -1467,7 +1470,7 @@11.1922 SLOTILLEGAL();11.1923 } else {11.1924 sh4vma_t target = disp + pc + 4;11.1925 - JT_rel8( nottaken );11.1926 + JT_label( nottaken );11.1927 exit_block_rel(target, pc+2 );11.1928 JMP_TARGET(nottaken);11.1929 return 2;11.1930 @@ -1480,22 +1483,23 @@11.1931 } else {11.1932 sh4_x86.in_delay_slot = DELAY_PC;11.1933 if( UNTRANSLATABLE(pc+2) ) {11.1934 - load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );11.1935 - JT_rel8(nottaken);11.1936 - ADD_imm32_r32( disp, R_EAX );11.1937 + load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc );11.1938 + JT_label(nottaken);11.1939 + ADDL_imms_r32( disp, REG_EAX );11.1940 JMP_TARGET(nottaken);11.1941 - ADD_sh4r_r32( R_PC, R_EAX );11.1942 - store_spreg( R_EAX, R_NEW_PC );11.1943 + ADDL_rbpdisp_r32( R_PC, REG_EAX );11.1944 + store_spreg( REG_EAX, R_NEW_PC );11.1945 exit_block_emu(pc+2);11.1946 sh4_x86.branch_taken = TRUE;11.1947 return 2;11.1948 } else {11.1949 if( sh4_x86.tstate == TSTATE_NONE ) {11.1950 - CMP_imm8s_sh4r( 1, R_T );11.1951 + CMPL_imms_rbpdisp( 1, R_T );11.1952 sh4_x86.tstate = TSTATE_E;11.1953 }11.1954 sh4vma_t target = disp + pc + 4;11.1955 - OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel3211.1956 + JCC_cc_rel32(sh4_x86.tstate,0);11.1957 + uint32_t *patch = ((uint32_t *)xlat_output)-1;11.1958 int save_tstate = sh4_x86.tstate;11.1959 sh4_translate_instruction(pc+2);11.1960 exit_block_rel( target, pc+4 );11.1961 @@ -1516,9 +1520,9 @@11.1962 sh4_x86.in_delay_slot = DELAY_PC;11.1963 sh4_x86.branch_taken = TRUE;11.1964 if( UNTRANSLATABLE(pc+2) ) {11.1965 - load_spreg( R_EAX, R_PC );11.1966 - ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );11.1967 - store_spreg( R_EAX, R_NEW_PC );11.1968 + load_spreg( REG_EAX, R_PC );11.1969 + ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );11.1970 + store_spreg( REG_EAX, R_NEW_PC );11.1971 exit_block_emu(pc+2);11.1972 return 2;11.1973 } else {11.1974 @@ -1533,10 +1537,10 @@11.1975 if( sh4_x86.in_delay_slot ) {11.1976 SLOTILLEGAL();11.1977 } else {11.1978 - load_spreg( R_EAX, R_PC );11.1979 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );11.1980 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );11.1981 - store_spreg( R_EAX, R_NEW_PC );11.1982 + load_spreg( REG_EAX, R_PC );11.1983 + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );11.1984 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );11.1985 + store_spreg( REG_EAX, R_NEW_PC );11.1986 sh4_x86.in_delay_slot = DELAY_PC;11.1987 sh4_x86.tstate = TSTATE_NONE;11.1988 sh4_x86.branch_taken = TRUE;11.1989 @@ -1555,15 +1559,15 @@11.1990 if( sh4_x86.in_delay_slot ) {11.1991 SLOTILLEGAL();11.1992 } else {11.1993 - load_spreg( R_EAX, R_PC );11.1994 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );11.1995 - store_spreg( R_EAX, R_PR );11.1996 + load_spreg( REG_EAX, R_PC );11.1997 + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );11.1998 + store_spreg( REG_EAX, R_PR );11.1999 sh4_x86.in_delay_slot = DELAY_PC;11.2000 sh4_x86.branch_taken = TRUE;11.2001 sh4_x86.tstate = TSTATE_NONE;11.2002 if( UNTRANSLATABLE(pc+2) ) {11.2003 - ADD_imm32_r32( disp, R_EAX );11.2004 - store_spreg( R_EAX, R_NEW_PC );11.2005 + ADDL_imms_r32( disp, REG_EAX );11.2006 + store_spreg( REG_EAX, R_NEW_PC );11.2007 exit_block_emu(pc+2);11.2008 return 2;11.2009 } else {11.2010 @@ -1578,11 +1582,11 @@11.2011 if( sh4_x86.in_delay_slot ) {11.2012 SLOTILLEGAL();11.2013 } else {11.2014 - load_spreg( R_EAX, R_PC );11.2015 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );11.2016 - store_spreg( R_EAX, R_PR );11.2017 - ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );11.2018 - store_spreg( R_EAX, R_NEW_PC );11.2019 + load_spreg( REG_EAX, R_PC );11.2020 + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );11.2021 + store_spreg( REG_EAX, R_PR );11.2022 + ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );11.2023 + store_spreg( REG_EAX, R_NEW_PC );11.2025 sh4_x86.in_delay_slot = DELAY_PC;11.2026 sh4_x86.tstate = TSTATE_NONE;11.2027 @@ -1603,7 +1607,7 @@11.2028 SLOTILLEGAL();11.2029 } else {11.2030 sh4vma_t target = disp + pc + 4;11.2031 - JF_rel8( nottaken );11.2032 + JF_label( nottaken );11.2033 exit_block_rel(target, pc+2 );11.2034 JMP_TARGET(nottaken);11.2035 return 2;11.2036 @@ -1616,21 +1620,23 @@11.2037 } else {11.2038 sh4_x86.in_delay_slot = DELAY_PC;11.2039 if( UNTRANSLATABLE(pc+2) ) {11.2040 - load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );11.2041 - JF_rel8(nottaken);11.2042 - ADD_imm32_r32( disp, R_EAX );11.2043 + load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc );11.2044 + JF_label(nottaken);11.2045 + ADDL_imms_r32( disp, REG_EAX );11.2046 JMP_TARGET(nottaken);11.2047 - ADD_sh4r_r32( R_PC, R_EAX );11.2048 - store_spreg( R_EAX, R_NEW_PC );11.2049 + ADDL_rbpdisp_r32( R_PC, REG_EAX );11.2050 + store_spreg( REG_EAX, R_NEW_PC );11.2051 exit_block_emu(pc+2);11.2052 sh4_x86.branch_taken = TRUE;11.2053 return 2;11.2054 } else {11.2055 if( sh4_x86.tstate == TSTATE_NONE ) {11.2056 - CMP_imm8s_sh4r( 1, R_T );11.2057 + CMPL_imms_rbpdisp( 1, R_T );11.2058 sh4_x86.tstate = TSTATE_E;11.2059 }11.2060 - OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel3211.2061 + JCC_cc_rel32(sh4_x86.tstate^1,0);11.2062 + uint32_t *patch = ((uint32_t *)xlat_output)-1;11.2063 +11.2064 int save_tstate = sh4_x86.tstate;11.2065 sh4_translate_instruction(pc+2);11.2066 exit_block_rel( disp + pc + 4, pc+4 );11.2067 @@ -1647,8 +1653,8 @@11.2068 if( sh4_x86.in_delay_slot ) {11.2069 SLOTILLEGAL();11.2070 } else {11.2071 - load_reg( R_ECX, Rn );11.2072 - store_spreg( R_ECX, R_NEW_PC );11.2073 + load_reg( REG_ECX, Rn );11.2074 + store_spreg( REG_ECX, R_NEW_PC );11.2075 sh4_x86.in_delay_slot = DELAY_PC;11.2076 sh4_x86.branch_taken = TRUE;11.2077 if( UNTRANSLATABLE(pc+2) ) {11.2078 @@ -1666,11 +1672,11 @@11.2079 if( sh4_x86.in_delay_slot ) {11.2080 SLOTILLEGAL();11.2081 } else {11.2082 - load_spreg( R_EAX, R_PC );11.2083 - ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );11.2084 - store_spreg( R_EAX, R_PR );11.2085 - load_reg( R_ECX, Rn );11.2086 - store_spreg( R_ECX, R_NEW_PC );11.2087 + load_spreg( REG_EAX, R_PC );11.2088 + ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );11.2089 + store_spreg( REG_EAX, R_PR );11.2090 + load_reg( REG_ECX, Rn );11.2091 + store_spreg( REG_ECX, R_NEW_PC );11.2092 sh4_x86.in_delay_slot = DELAY_PC;11.2093 sh4_x86.branch_taken = TRUE;11.2094 sh4_x86.tstate = TSTATE_NONE;11.2095 @@ -1690,10 +1696,10 @@11.2096 SLOTILLEGAL();11.2097 } else {11.2098 check_priv();11.2099 - load_spreg( R_ECX, R_SPC );11.2100 - store_spreg( R_ECX, R_NEW_PC );11.2101 - load_spreg( R_EAX, R_SSR );11.2102 - call_func1( sh4_write_sr, R_EAX );11.2103 + load_spreg( REG_ECX, R_SPC );11.2104 + store_spreg( REG_ECX, R_NEW_PC );11.2105 + load_spreg( REG_EAX, R_SSR );11.2106 + call_func1( sh4_write_sr, REG_EAX );11.2107 sh4_x86.in_delay_slot = DELAY_PC;11.2108 sh4_x86.fpuen_checked = FALSE;11.2109 sh4_x86.tstate = TSTATE_NONE;11.2110 @@ -1713,8 +1719,8 @@11.2111 if( sh4_x86.in_delay_slot ) {11.2112 SLOTILLEGAL();11.2113 } else {11.2114 - load_spreg( R_ECX, R_PR );11.2115 - store_spreg( R_ECX, R_NEW_PC );11.2116 + load_spreg( REG_ECX, R_PR );11.2117 + store_spreg( REG_ECX, R_NEW_PC );11.2118 sh4_x86.in_delay_slot = DELAY_PC;11.2119 sh4_x86.branch_taken = TRUE;11.2120 if( UNTRANSLATABLE(pc+2) ) {11.2121 @@ -1732,10 +1738,10 @@11.2122 if( sh4_x86.in_delay_slot ) {11.2123 SLOTILLEGAL();11.2124 } else {11.2125 - load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc ); // 511.2126 - ADD_r32_sh4r( R_ECX, R_PC );11.2127 - load_imm32( R_EAX, imm );11.2128 - call_func1( sh4_raise_trap, R_EAX );11.2129 + load_imm32( REG_ECX, pc+2 - sh4_x86.block_start_pc ); // 511.2130 + ADDL_r32_rbpdisp( REG_ECX, R_PC );11.2131 + load_imm32( REG_EAX, imm );11.2132 + call_func1( sh4_raise_trap, REG_EAX );11.2133 sh4_x86.tstate = TSTATE_NONE;11.2134 exit_block_pcset(pc+2);11.2135 sh4_x86.branch_taken = TRUE;11.2136 @@ -1754,15 +1760,15 @@11.2138 CLRMAC {:11.2139 COUNT_INST(I_CLRMAC);11.2140 - XOR_r32_r32(R_EAX, R_EAX);11.2141 - store_spreg( R_EAX, R_MACL );11.2142 - store_spreg( R_EAX, R_MACH );11.2143 + XORL_r32_r32(REG_EAX, REG_EAX);11.2144 + store_spreg( REG_EAX, R_MACL );11.2145 + store_spreg( REG_EAX, R_MACH );11.2146 sh4_x86.tstate = TSTATE_NONE;11.2147 :}11.2148 CLRS {:11.2149 COUNT_INST(I_CLRS);11.2150 CLC();11.2151 - SETC_sh4r(R_S);11.2152 + SETCCB_cc_rbpdisp(X86_COND_C, R_S);11.2153 sh4_x86.tstate = TSTATE_NONE;11.2154 :}11.2155 CLRT {:11.2156 @@ -1774,7 +1780,7 @@11.2157 SETS {:11.2158 COUNT_INST(I_SETS);11.2159 STC();11.2160 - SETC_sh4r(R_S);11.2161 + SETCCB_cc_rbpdisp(X86_COND_C, R_S);11.2162 sh4_x86.tstate = TSTATE_NONE;11.2163 :}11.2164 SETT {:11.2165 @@ -1789,136 +1795,136 @@11.2166 COUNT_INST(I_FMOV1);11.2167 check_fpuen();11.2168 if( sh4_x86.double_size ) {11.2169 - load_dr0( R_EAX, FRm );11.2170 - load_dr1( R_ECX, FRm );11.2171 - store_dr0( R_EAX, FRn );11.2172 - store_dr1( R_ECX, FRn );11.2173 + load_dr0( REG_EAX, FRm );11.2174 + load_dr1( REG_ECX, FRm );11.2175 + store_dr0( REG_EAX, FRn );11.2176 + store_dr1( REG_ECX, FRn );11.2177 } else {11.2178 - load_fr( R_EAX, FRm ); // SZ=0 branch11.2179 - store_fr( R_EAX, FRn );11.2180 + load_fr( REG_EAX, FRm ); // SZ=0 branch11.2181 + store_fr( REG_EAX, FRn );11.2182 }11.2183 :}11.2184 FMOV FRm, @Rn {:11.2185 COUNT_INST(I_FMOV2);11.2186 check_fpuen();11.2187 - load_reg( R_EAX, Rn );11.2188 + load_reg( REG_EAX, Rn );11.2189 if( sh4_x86.double_size ) {11.2190 - check_walign64( R_EAX );11.2191 - load_dr0( R_EDX, FRm );11.2192 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2193 - load_reg( R_EAX, Rn );11.2194 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );11.2195 - load_dr1( R_EDX, FRm );11.2196 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2197 + check_walign64( REG_EAX );11.2198 + load_dr0( REG_EDX, FRm );11.2199 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2200 + load_reg( REG_EAX, Rn );11.2201 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );11.2202 + load_dr1( REG_EDX, FRm );11.2203 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2204 } else {11.2205 - check_walign32( R_EAX );11.2206 - load_fr( R_EDX, FRm );11.2207 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2208 + check_walign32( REG_EAX );11.2209 + load_fr( REG_EDX, FRm );11.2210 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2211 }11.2212 sh4_x86.tstate = TSTATE_NONE;11.2213 :}11.2214 FMOV @Rm, FRn {:11.2215 COUNT_INST(I_FMOV5);11.2216 check_fpuen();11.2217 - load_reg( R_EAX, Rm );11.2218 + load_reg( REG_EAX, Rm );11.2219 if( sh4_x86.double_size ) {11.2220 - check_ralign64( R_EAX );11.2221 - MEM_READ_LONG( R_EAX, R_EAX );11.2222 - store_dr0( R_EAX, FRn );11.2223 - load_reg( R_EAX, Rm );11.2224 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );11.2225 - MEM_READ_LONG( R_EAX, R_EAX );11.2226 - store_dr1( R_EAX, FRn );11.2227 + check_ralign64( REG_EAX );11.2228 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2229 + store_dr0( REG_EAX, FRn );11.2230 + load_reg( REG_EAX, Rm );11.2231 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );11.2232 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2233 + store_dr1( REG_EAX, FRn );11.2234 } else {11.2235 - check_ralign32( R_EAX );11.2236 - MEM_READ_LONG( R_EAX, R_EAX );11.2237 - store_fr( R_EAX, FRn );11.2238 + check_ralign32( REG_EAX );11.2239 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2240 + store_fr( REG_EAX, FRn );11.2241 }11.2242 sh4_x86.tstate = TSTATE_NONE;11.2243 :}11.2244 FMOV FRm, @-Rn {:11.2245 COUNT_INST(I_FMOV3);11.2246 check_fpuen();11.2247 - load_reg( R_EAX, Rn );11.2248 + load_reg( REG_EAX, Rn );11.2249 if( sh4_x86.double_size ) {11.2250 - check_walign64( R_EAX );11.2251 - LEA_r32disp8_r32( R_EAX, -8, R_EAX );11.2252 - load_dr0( R_EDX, FRm );11.2253 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2254 - load_reg( R_EAX, Rn );11.2255 - LEA_r32disp8_r32( R_EAX, -4, R_EAX );11.2256 - load_dr1( R_EDX, FRm );11.2257 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2258 - ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));11.2259 + check_walign64( REG_EAX );11.2260 + LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );11.2261 + load_dr0( REG_EDX, FRm );11.2262 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2263 + load_reg( REG_EAX, Rn );11.2264 + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );11.2265 + load_dr1( REG_EDX, FRm );11.2266 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2267 + ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));11.2268 } else {11.2269 - check_walign32( R_EAX );11.2270 - LEA_r32disp8_r32( R_EAX, -4, R_EAX );11.2271 - load_fr( R_EDX, FRm );11.2272 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2273 - ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));11.2274 + check_walign32( REG_EAX );11.2275 + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );11.2276 + load_fr( REG_EDX, FRm );11.2277 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2278 + ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));11.2279 }11.2280 sh4_x86.tstate = TSTATE_NONE;11.2281 :}11.2282 FMOV @Rm+, FRn {:11.2283 COUNT_INST(I_FMOV6);11.2284 check_fpuen();11.2285 - load_reg( R_EAX, Rm );11.2286 + load_reg( REG_EAX, Rm );11.2287 if( sh4_x86.double_size ) {11.2288 - check_ralign64( R_EAX );11.2289 - MEM_READ_LONG( R_EAX, R_EAX );11.2290 - store_dr0( R_EAX, FRn );11.2291 - load_reg( R_EAX, Rm );11.2292 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );11.2293 - MEM_READ_LONG( R_EAX, R_EAX );11.2294 - store_dr1( R_EAX, FRn );11.2295 - ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );11.2296 + check_ralign64( REG_EAX );11.2297 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2298 + store_dr0( REG_EAX, FRn );11.2299 + load_reg( REG_EAX, Rm );11.2300 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );11.2301 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2302 + store_dr1( REG_EAX, FRn );11.2303 + ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );11.2304 } else {11.2305 - check_ralign32( R_EAX );11.2306 - MEM_READ_LONG( R_EAX, R_EAX );11.2307 - store_fr( R_EAX, FRn );11.2308 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2309 + check_ralign32( REG_EAX );11.2310 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2311 + store_fr( REG_EAX, FRn );11.2312 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2313 }11.2314 sh4_x86.tstate = TSTATE_NONE;11.2315 :}11.2316 FMOV FRm, @(R0, Rn) {:11.2317 COUNT_INST(I_FMOV4);11.2318 check_fpuen();11.2319 - load_reg( R_EAX, Rn );11.2320 - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );11.2321 + load_reg( REG_EAX, Rn );11.2322 + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );11.2323 if( sh4_x86.double_size ) {11.2324 - check_walign64( R_EAX );11.2325 - load_dr0( R_EDX, FRm );11.2326 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2327 - load_reg( R_EAX, Rn );11.2328 - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );11.2329 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );11.2330 - load_dr1( R_EDX, FRm );11.2331 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2332 + check_walign64( REG_EAX );11.2333 + load_dr0( REG_EDX, FRm );11.2334 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2335 + load_reg( REG_EAX, Rn );11.2336 + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );11.2337 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );11.2338 + load_dr1( REG_EDX, FRm );11.2339 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2340 } else {11.2341 - check_walign32( R_EAX );11.2342 - load_fr( R_EDX, FRm );11.2343 - MEM_WRITE_LONG( R_EAX, R_EDX ); // 1211.2344 + check_walign32( REG_EAX );11.2345 + load_fr( REG_EDX, FRm );11.2346 + MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 1211.2347 }11.2348 sh4_x86.tstate = TSTATE_NONE;11.2349 :}11.2350 FMOV @(R0, Rm), FRn {:11.2351 COUNT_INST(I_FMOV7);11.2352 check_fpuen();11.2353 - load_reg( R_EAX, Rm );11.2354 - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );11.2355 + load_reg( REG_EAX, Rm );11.2356 + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );11.2357 if( sh4_x86.double_size ) {11.2358 - check_ralign64( R_EAX );11.2359 - MEM_READ_LONG( R_EAX, R_EAX );11.2360 - store_dr0( R_EAX, FRn );11.2361 - load_reg( R_EAX, Rm );11.2362 - ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );11.2363 - LEA_r32disp8_r32( R_EAX, 4, R_EAX );11.2364 - MEM_READ_LONG( R_EAX, R_EAX );11.2365 - store_dr1( R_EAX, FRn );11.2366 + check_ralign64( REG_EAX );11.2367 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2368 + store_dr0( REG_EAX, FRn );11.2369 + load_reg( REG_EAX, Rm );11.2370 + ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );11.2371 + LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );11.2372 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2373 + store_dr1( REG_EAX, FRn );11.2374 } else {11.2375 - check_ralign32( R_EAX );11.2376 - MEM_READ_LONG( R_EAX, R_EAX );11.2377 - store_fr( R_EAX, FRn );11.2378 + check_ralign32( REG_EAX );11.2379 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2380 + store_fr( REG_EAX, FRn );11.2381 }11.2382 sh4_x86.tstate = TSTATE_NONE;11.2383 :}11.2384 @@ -1926,8 +1932,8 @@11.2385 COUNT_INST(I_FLDI0);11.2386 check_fpuen();11.2387 if( sh4_x86.double_prec == 0 ) {11.2388 - XOR_r32_r32( R_EAX, R_EAX );11.2389 - store_fr( R_EAX, FRn );11.2390 + XORL_r32_r32( REG_EAX, REG_EAX );11.2391 + store_fr( REG_EAX, FRn );11.2392 }11.2393 sh4_x86.tstate = TSTATE_NONE;11.2394 :}11.2395 @@ -1935,15 +1941,15 @@11.2396 COUNT_INST(I_FLDI1);11.2397 check_fpuen();11.2398 if( sh4_x86.double_prec == 0 ) {11.2399 - load_imm32(R_EAX, 0x3F800000);11.2400 - store_fr( R_EAX, FRn );11.2401 + load_imm32(REG_EAX, 0x3F800000);11.2402 + store_fr( REG_EAX, FRn );11.2403 }11.2404 :}11.2406 FLOAT FPUL, FRn {:11.2407 COUNT_INST(I_FLOAT);11.2408 check_fpuen();11.2409 - FILD_sh4r(R_FPUL);11.2410 + FILD_rbpdisp(R_FPUL);11.2411 if( sh4_x86.double_prec ) {11.2412 pop_dr( FRn );11.2413 } else {11.2414 @@ -1958,26 +1964,26 @@11.2415 } else {11.2416 push_fr( FRm );11.2417 }11.2418 - load_ptr( R_ECX, &max_int );11.2419 - FILD_r32ind( R_ECX );11.2420 + load_ptr( REG_ECX, &max_int );11.2421 + FILD_r32disp( REG_ECX, 0 );11.2422 FCOMIP_st(1);11.2423 - JNA_rel8( sat );11.2424 - load_ptr( R_ECX, &min_int ); // 511.2425 - FILD_r32ind( R_ECX ); // 211.2426 + JNA_label( sat );11.2427 + load_ptr( REG_ECX, &min_int ); // 511.2428 + FILD_r32disp( REG_ECX, 0 ); // 211.2429 FCOMIP_st(1); // 211.2430 - JAE_rel8( sat2 ); // 211.2431 - load_ptr( R_EAX, &save_fcw );11.2432 - FNSTCW_r32ind( R_EAX );11.2433 - load_ptr( R_EDX, &trunc_fcw );11.2434 - FLDCW_r32ind( R_EDX );11.2435 - FISTP_sh4r(R_FPUL); // 311.2436 - FLDCW_r32ind( R_EAX );11.2437 - JMP_rel8(end); // 211.2438 + JAE_label( sat2 ); // 211.2439 + load_ptr( REG_EAX, &save_fcw );11.2440 + FNSTCW_r32disp( REG_EAX, 0 );11.2441 + load_ptr( REG_EDX, &trunc_fcw );11.2442 + FLDCW_r32disp( REG_EDX, 0 );11.2443 + FISTP_rbpdisp(R_FPUL); // 311.2444 + FLDCW_r32disp( REG_EAX, 0 );11.2445 + JMP_label(end); // 211.2447 JMP_TARGET(sat);11.2448 JMP_TARGET(sat2);11.2449 - MOV_r32ind_r32( R_ECX, R_ECX ); // 211.2450 - store_spreg( R_ECX, R_FPUL );11.2451 + MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 211.2452 + store_spreg( REG_ECX, R_FPUL );11.2453 FPOP_st();11.2454 JMP_TARGET(end);11.2455 sh4_x86.tstate = TSTATE_NONE;11.2456 @@ -1985,14 +1991,14 @@11.2457 FLDS FRm, FPUL {:11.2458 COUNT_INST(I_FLDS);11.2459 check_fpuen();11.2460 - load_fr( R_EAX, FRm );11.2461 - store_spreg( R_EAX, R_FPUL );11.2462 + load_fr( REG_EAX, FRm );11.2463 + store_spreg( REG_EAX, R_FPUL );11.2464 :}11.2465 FSTS FPUL, FRn {:11.2466 COUNT_INST(I_FSTS);11.2467 check_fpuen();11.2468 - load_spreg( R_EAX, R_FPUL );11.2469 - store_fr( R_EAX, FRn );11.2470 + load_spreg( REG_EAX, R_FPUL );11.2471 + store_fr( REG_EAX, FRn );11.2472 :}11.2473 FCNVDS FRm, FPUL {:11.2474 COUNT_INST(I_FCNVDS);11.2475 @@ -2178,9 +2184,9 @@11.2476 COUNT_INST(I_FSCA);11.2477 check_fpuen();11.2478 if( sh4_x86.double_prec == 0 ) {11.2479 - LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );11.2480 - load_spreg( R_EAX, R_FPUL );11.2481 - call_func2( sh4_fsca, R_EAX, R_EDX );11.2482 + LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );11.2483 + load_spreg( REG_EAX, R_FPUL );11.2484 + call_func2( sh4_fsca, REG_EAX, REG_EDX );11.2485 }11.2486 sh4_x86.tstate = TSTATE_NONE;11.2487 :}11.2488 @@ -2189,11 +2195,11 @@11.2489 check_fpuen();11.2490 if( sh4_x86.double_prec == 0 ) {11.2491 if( sh4_x86.sse3_enabled ) {11.2492 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );11.2493 - MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );11.2494 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );11.2495 + MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );11.2496 HADDPS_xmm_xmm( 4, 4 );11.2497 HADDPS_xmm_xmm( 4, 4 );11.2498 - MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );11.2499 + MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );11.2500 } else {11.2501 push_fr( FVm<<2 );11.2502 push_fr( FVn<<2 );11.2503 @@ -2219,15 +2225,15 @@11.2504 check_fpuen();11.2505 if( sh4_x86.double_prec == 0 ) {11.2506 if( sh4_x86.sse3_enabled ) {11.2507 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M211.2508 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M611.2509 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M1011.2510 - MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M1411.2511 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1 M0 M3 M211.2512 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5 M4 M7 M611.2513 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9 M8 M11 M1011.2514 + MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M1411.2516 - MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V311.2517 - MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V211.2518 - MOVAPS_xmm_xmm( 4, 6 );11.2519 - MOVAPS_xmm_xmm( 5, 7 );11.2520 + MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V311.2521 + MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V211.2522 + MOV_xmm_xmm( 4, 6 );11.2523 + MOV_xmm_xmm( 5, 7 );11.2524 MOVLHPS_xmm_xmm( 4, 4 ); // V1 V1 V1 V111.2525 MOVHLPS_xmm_xmm( 6, 6 ); // V3 V3 V3 V311.2526 MOVLHPS_xmm_xmm( 5, 5 ); // V0 V0 V0 V011.2527 @@ -2239,10 +2245,10 @@11.2528 ADDPS_xmm_xmm( 5, 4 );11.2529 ADDPS_xmm_xmm( 7, 6 );11.2530 ADDPS_xmm_xmm( 6, 4 );11.2531 - MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );11.2532 + MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );11.2533 } else {11.2534 - LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );11.2535 - call_func1( sh4_ftrv, R_EAX );11.2536 + LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );11.2537 + call_func1( sh4_ftrv, REG_EAX );11.2538 }11.2539 }11.2540 sh4_x86.tstate = TSTATE_NONE;11.2541 @@ -2251,15 +2257,15 @@11.2542 FRCHG {:11.2543 COUNT_INST(I_FRCHG);11.2544 check_fpuen();11.2545 - XOR_imm32_sh4r( FPSCR_FR, R_FPSCR );11.2546 + XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );11.2547 call_func0( sh4_switch_fr_banks );11.2548 sh4_x86.tstate = TSTATE_NONE;11.2549 :}11.2550 FSCHG {:11.2551 COUNT_INST(I_FSCHG);11.2552 check_fpuen();11.2553 - XOR_imm32_sh4r( FPSCR_SZ, R_FPSCR);11.2554 - XOR_imm32_sh4r( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );11.2555 + XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);11.2556 + XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );11.2557 sh4_x86.tstate = TSTATE_NONE;11.2558 sh4_x86.double_size = !sh4_x86.double_size;11.2559 :}11.2560 @@ -2271,8 +2277,8 @@11.2561 SLOTILLEGAL();11.2562 } else {11.2563 check_priv();11.2564 - load_reg( R_EAX, Rm );11.2565 - call_func1( sh4_write_sr, R_EAX );11.2566 + load_reg( REG_EAX, Rm );11.2567 + call_func1( sh4_write_sr, REG_EAX );11.2568 sh4_x86.fpuen_checked = FALSE;11.2569 sh4_x86.tstate = TSTATE_NONE;11.2570 return 2;11.2571 @@ -2280,58 +2286,58 @@11.2572 :}11.2573 LDC Rm, GBR {:11.2574 COUNT_INST(I_LDC);11.2575 - load_reg( R_EAX, Rm );11.2576 - store_spreg( R_EAX, R_GBR );11.2577 + load_reg( REG_EAX, Rm );11.2578 + store_spreg( REG_EAX, R_GBR );11.2579 :}11.2580 LDC Rm, VBR {:11.2581 COUNT_INST(I_LDC);11.2582 check_priv();11.2583 - load_reg( R_EAX, Rm );11.2584 - store_spreg( R_EAX, R_VBR );11.2585 + load_reg( REG_EAX, Rm );11.2586 + store_spreg( REG_EAX, R_VBR );11.2587 sh4_x86.tstate = TSTATE_NONE;11.2588 :}11.2589 LDC Rm, SSR {:11.2590 COUNT_INST(I_LDC);11.2591 check_priv();11.2592 - load_reg( R_EAX, Rm );11.2593 - store_spreg( R_EAX, R_SSR );11.2594 + load_reg( REG_EAX, Rm );11.2595 + store_spreg( REG_EAX, R_SSR );11.2596 sh4_x86.tstate = TSTATE_NONE;11.2597 :}11.2598 LDC Rm, SGR {:11.2599 COUNT_INST(I_LDC);11.2600 check_priv();11.2601 - load_reg( R_EAX, Rm );11.2602 - store_spreg( R_EAX, R_SGR );11.2603 + load_reg( REG_EAX, Rm );11.2604 + store_spreg( REG_EAX, R_SGR );11.2605 sh4_x86.tstate = TSTATE_NONE;11.2606 :}11.2607 LDC Rm, SPC {:11.2608 COUNT_INST(I_LDC);11.2609 check_priv();11.2610 - load_reg( R_EAX, Rm );11.2611 - store_spreg( R_EAX, R_SPC );11.2612 + load_reg( REG_EAX, Rm );11.2613 + store_spreg( REG_EAX, R_SPC );11.2614 sh4_x86.tstate = TSTATE_NONE;11.2615 :}11.2616 LDC Rm, DBR {:11.2617 COUNT_INST(I_LDC);11.2618 check_priv();11.2619 - load_reg( R_EAX, Rm );11.2620 - store_spreg( R_EAX, R_DBR );11.2621 + load_reg( REG_EAX, Rm );11.2622 + store_spreg( REG_EAX, R_DBR );11.2623 sh4_x86.tstate = TSTATE_NONE;11.2624 :}11.2625 LDC Rm, Rn_BANK {:11.2626 COUNT_INST(I_LDC);11.2627 check_priv();11.2628 - load_reg( R_EAX, Rm );11.2629 - store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );11.2630 + load_reg( REG_EAX, Rm );11.2631 + store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );11.2632 sh4_x86.tstate = TSTATE_NONE;11.2633 :}11.2634 LDC.L @Rm+, GBR {:11.2635 COUNT_INST(I_LDCM);11.2636 - load_reg( R_EAX, Rm );11.2637 - check_ralign32( R_EAX );11.2638 - MEM_READ_LONG( R_EAX, R_EAX );11.2639 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2640 - store_spreg( R_EAX, R_GBR );11.2641 + load_reg( REG_EAX, Rm );11.2642 + check_ralign32( REG_EAX );11.2643 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2644 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2645 + store_spreg( REG_EAX, R_GBR );11.2646 sh4_x86.tstate = TSTATE_NONE;11.2647 :}11.2648 LDC.L @Rm+, SR {:11.2649 @@ -2340,11 +2346,11 @@11.2650 SLOTILLEGAL();11.2651 } else {11.2652 check_priv();11.2653 - load_reg( R_EAX, Rm );11.2654 - check_ralign32( R_EAX );11.2655 - MEM_READ_LONG( R_EAX, R_EAX );11.2656 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2657 - call_func1( sh4_write_sr, R_EAX );11.2658 + load_reg( REG_EAX, Rm );11.2659 + check_ralign32( REG_EAX );11.2660 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2661 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2662 + call_func1( sh4_write_sr, REG_EAX );11.2663 sh4_x86.fpuen_checked = FALSE;11.2664 sh4_x86.tstate = TSTATE_NONE;11.2665 return 2;11.2666 @@ -2353,138 +2359,138 @@11.2667 LDC.L @Rm+, VBR {:11.2668 COUNT_INST(I_LDCM);11.2669 check_priv();11.2670 - load_reg( R_EAX, Rm );11.2671 - check_ralign32( R_EAX );11.2672 - MEM_READ_LONG( R_EAX, R_EAX );11.2673 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2674 - store_spreg( R_EAX, R_VBR );11.2675 + load_reg( REG_EAX, Rm );11.2676 + check_ralign32( REG_EAX );11.2677 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2678 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2679 + store_spreg( REG_EAX, R_VBR );11.2680 sh4_x86.tstate = TSTATE_NONE;11.2681 :}11.2682 LDC.L @Rm+, SSR {:11.2683 COUNT_INST(I_LDCM);11.2684 check_priv();11.2685 - load_reg( R_EAX, Rm );11.2686 - check_ralign32( R_EAX );11.2687 - MEM_READ_LONG( R_EAX, R_EAX );11.2688 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2689 - store_spreg( R_EAX, R_SSR );11.2690 + load_reg( REG_EAX, Rm );11.2691 + check_ralign32( REG_EAX );11.2692 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2693 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2694 + store_spreg( REG_EAX, R_SSR );11.2695 sh4_x86.tstate = TSTATE_NONE;11.2696 :}11.2697 LDC.L @Rm+, SGR {:11.2698 COUNT_INST(I_LDCM);11.2699 check_priv();11.2700 - load_reg( R_EAX, Rm );11.2701 - check_ralign32( R_EAX );11.2702 - MEM_READ_LONG( R_EAX, R_EAX );11.2703 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2704 - store_spreg( R_EAX, R_SGR );11.2705 + load_reg( REG_EAX, Rm );11.2706 + check_ralign32( REG_EAX );11.2707 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2708 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2709 + store_spreg( REG_EAX, R_SGR );11.2710 sh4_x86.tstate = TSTATE_NONE;11.2711 :}11.2712 LDC.L @Rm+, SPC {:11.2713 COUNT_INST(I_LDCM);11.2714 check_priv();11.2715 - load_reg( R_EAX, Rm );11.2716 - check_ralign32( R_EAX );11.2717 - MEM_READ_LONG( R_EAX, R_EAX );11.2718 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2719 - store_spreg( R_EAX, R_SPC );11.2720 + load_reg( REG_EAX, Rm );11.2721 + check_ralign32( REG_EAX );11.2722 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2723 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2724 + store_spreg( REG_EAX, R_SPC );11.2725 sh4_x86.tstate = TSTATE_NONE;11.2726 :}11.2727 LDC.L @Rm+, DBR {:11.2728 COUNT_INST(I_LDCM);11.2729 check_priv();11.2730 - load_reg( R_EAX, Rm );11.2731 - check_ralign32( R_EAX );11.2732 - MEM_READ_LONG( R_EAX, R_EAX );11.2733 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2734 - store_spreg( R_EAX, R_DBR );11.2735 + load_reg( REG_EAX, Rm );11.2736 + check_ralign32( REG_EAX );11.2737 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2738 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2739 + store_spreg( REG_EAX, R_DBR );11.2740 sh4_x86.tstate = TSTATE_NONE;11.2741 :}11.2742 LDC.L @Rm+, Rn_BANK {:11.2743 COUNT_INST(I_LDCM);11.2744 check_priv();11.2745 - load_reg( R_EAX, Rm );11.2746 - check_ralign32( R_EAX );11.2747 - MEM_READ_LONG( R_EAX, R_EAX );11.2748 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2749 - store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );11.2750 + load_reg( REG_EAX, Rm );11.2751 + check_ralign32( REG_EAX );11.2752 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2753 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2754 + store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );11.2755 sh4_x86.tstate = TSTATE_NONE;11.2756 :}11.2757 LDS Rm, FPSCR {:11.2758 COUNT_INST(I_LDSFPSCR);11.2759 check_fpuen();11.2760 - load_reg( R_EAX, Rm );11.2761 - call_func1( sh4_write_fpscr, R_EAX );11.2762 + load_reg( REG_EAX, Rm );11.2763 + call_func1( sh4_write_fpscr, REG_EAX );11.2764 sh4_x86.tstate = TSTATE_NONE;11.2765 return 2;11.2766 :}11.2767 LDS.L @Rm+, FPSCR {:11.2768 COUNT_INST(I_LDSFPSCRM);11.2769 check_fpuen();11.2770 - load_reg( R_EAX, Rm );11.2771 - check_ralign32( R_EAX );11.2772 - MEM_READ_LONG( R_EAX, R_EAX );11.2773 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2774 - call_func1( sh4_write_fpscr, R_EAX );11.2775 + load_reg( REG_EAX, Rm );11.2776 + check_ralign32( REG_EAX );11.2777 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2778 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2779 + call_func1( sh4_write_fpscr, REG_EAX );11.2780 sh4_x86.tstate = TSTATE_NONE;11.2781 return 2;11.2782 :}11.2783 LDS Rm, FPUL {:11.2784 COUNT_INST(I_LDS);11.2785 check_fpuen();11.2786 - load_reg( R_EAX, Rm );11.2787 - store_spreg( R_EAX, R_FPUL );11.2788 + load_reg( REG_EAX, Rm );11.2789 + store_spreg( REG_EAX, R_FPUL );11.2790 :}11.2791 LDS.L @Rm+, FPUL {:11.2792 COUNT_INST(I_LDSM);11.2793 check_fpuen();11.2794 - load_reg( R_EAX, Rm );11.2795 - check_ralign32( R_EAX );11.2796 - MEM_READ_LONG( R_EAX, R_EAX );11.2797 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2798 - store_spreg( R_EAX, R_FPUL );11.2799 + load_reg( REG_EAX, Rm );11.2800 + check_ralign32( REG_EAX );11.2801 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2802 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2803 + store_spreg( REG_EAX, R_FPUL );11.2804 sh4_x86.tstate = TSTATE_NONE;11.2805 :}11.2806 LDS Rm, MACH {:11.2807 COUNT_INST(I_LDS);11.2808 - load_reg( R_EAX, Rm );11.2809 - store_spreg( R_EAX, R_MACH );11.2810 + load_reg( REG_EAX, Rm );11.2811 + store_spreg( REG_EAX, R_MACH );11.2812 :}11.2813 LDS.L @Rm+, MACH {:11.2814 COUNT_INST(I_LDSM);11.2815 - load_reg( R_EAX, Rm );11.2816 - check_ralign32( R_EAX );11.2817 - MEM_READ_LONG( R_EAX, R_EAX );11.2818 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2819 - store_spreg( R_EAX, R_MACH );11.2820 + load_reg( REG_EAX, Rm );11.2821 + check_ralign32( REG_EAX );11.2822 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2823 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2824 + store_spreg( REG_EAX, R_MACH );11.2825 sh4_x86.tstate = TSTATE_NONE;11.2826 :}11.2827 LDS Rm, MACL {:11.2828 COUNT_INST(I_LDS);11.2829 - load_reg( R_EAX, Rm );11.2830 - store_spreg( R_EAX, R_MACL );11.2831 + load_reg( REG_EAX, Rm );11.2832 + store_spreg( REG_EAX, R_MACL );11.2833 :}11.2834 LDS.L @Rm+, MACL {:11.2835 COUNT_INST(I_LDSM);11.2836 - load_reg( R_EAX, Rm );11.2837 - check_ralign32( R_EAX );11.2838 - MEM_READ_LONG( R_EAX, R_EAX );11.2839 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2840 - store_spreg( R_EAX, R_MACL );11.2841 + load_reg( REG_EAX, Rm );11.2842 + check_ralign32( REG_EAX );11.2843 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2844 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2845 + store_spreg( REG_EAX, R_MACL );11.2846 sh4_x86.tstate = TSTATE_NONE;11.2847 :}11.2848 LDS Rm, PR {:11.2849 COUNT_INST(I_LDS);11.2850 - load_reg( R_EAX, Rm );11.2851 - store_spreg( R_EAX, R_PR );11.2852 + load_reg( REG_EAX, Rm );11.2853 + store_spreg( REG_EAX, R_PR );11.2854 :}11.2855 LDS.L @Rm+, PR {:11.2856 COUNT_INST(I_LDSM);11.2857 - load_reg( R_EAX, Rm );11.2858 - check_ralign32( R_EAX );11.2859 - MEM_READ_LONG( R_EAX, R_EAX );11.2860 - ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );11.2861 - store_spreg( R_EAX, R_PR );11.2862 + load_reg( REG_EAX, Rm );11.2863 + check_ralign32( REG_EAX );11.2864 + MEM_READ_LONG( REG_EAX, REG_EAX );11.2865 + ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );11.2866 + store_spreg( REG_EAX, R_PR );11.2867 sh4_x86.tstate = TSTATE_NONE;11.2868 :}11.2869 LDTLB {:11.2870 @@ -2503,8 +2509,8 @@11.2871 :}11.2872 PREF @Rn {:11.2873 COUNT_INST(I_PREF);11.2874 - load_reg( R_EAX, Rn );11.2875 - MEM_PREFETCH( R_EAX );11.2876 + load_reg( REG_EAX, Rn );11.2877 + MEM_PREFETCH( REG_EAX );11.2878 sh4_x86.tstate = TSTATE_NONE;11.2879 :}11.2880 SLEEP {:11.2881 @@ -2519,221 +2525,221 @@11.2882 COUNT_INST(I_STCSR);11.2883 check_priv();11.2884 call_func0(sh4_read_sr);11.2885 - store_reg( R_EAX, Rn );11.2886 + store_reg( REG_EAX, Rn );11.2887 sh4_x86.tstate = TSTATE_NONE;11.2888 :}11.2889 STC GBR, Rn {:11.2890 COUNT_INST(I_STC);11.2891 - load_spreg( R_EAX, R_GBR );11.2892 - store_reg( R_EAX, Rn );11.2893 + load_spreg( REG_EAX, R_GBR );11.2894 + store_reg( REG_EAX, Rn );11.2895 :}11.2896 STC VBR, Rn {:11.2897 COUNT_INST(I_STC);11.2898 check_priv();11.2899 - load_spreg( R_EAX, R_VBR );11.2900 - store_reg( R_EAX, Rn );11.2901 + load_spreg( REG_EAX, R_VBR );11.2902 + store_reg( REG_EAX, Rn );11.2903 sh4_x86.tstate = TSTATE_NONE;11.2904 :}11.2905 STC SSR, Rn {:11.2906 COUNT_INST(I_STC);11.2907 check_priv();11.2908 - load_spreg( R_EAX, R_SSR );11.2909 - store_reg( R_EAX, Rn );11.2910 + load_spreg( REG_EAX, R_SSR );11.2911 + store_reg( REG_EAX, Rn );11.2912 sh4_x86.tstate = TSTATE_NONE;11.2913 :}11.2914 STC SPC, Rn {:11.2915 COUNT_INST(I_STC);11.2916 check_priv();11.2917 - load_spreg( R_EAX, R_SPC );11.2918 - store_reg( R_EAX, Rn );11.2919 + load_spreg( REG_EAX, R_SPC );11.2920 + store_reg( REG_EAX, Rn );11.2921 sh4_x86.tstate = TSTATE_NONE;11.2922 :}11.2923 STC SGR, Rn {:11.2924 COUNT_INST(I_STC);11.2925 check_priv();11.2926 - load_spreg( R_EAX, R_SGR );11.2927 - store_reg( R_EAX, Rn );11.2928 + load_spreg( REG_EAX, R_SGR );11.2929 + store_reg( REG_EAX, Rn );11.2930 sh4_x86.tstate = TSTATE_NONE;11.2931 :}11.2932 STC DBR, Rn {:11.2933 COUNT_INST(I_STC);11.2934 check_priv();11.2935 - load_spreg( R_EAX, R_DBR );11.2936 - store_reg( R_EAX, Rn );11.2937 + load_spreg( REG_EAX, R_DBR );11.2938 + store_reg( REG_EAX, Rn );11.2939 sh4_x86.tstate = TSTATE_NONE;11.2940 :}11.2941 STC Rm_BANK, Rn {:11.2942 COUNT_INST(I_STC);11.2943 check_priv();11.2944 - load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );11.2945 - store_reg( R_EAX, Rn );11.2946 + load_spreg( REG_EAX, REG_OFFSET(r_bank[Rm_BANK]) );11.2947 + store_reg( REG_EAX, Rn );11.2948 sh4_x86.tstate = TSTATE_NONE;11.2949 :}11.2950 STC.L SR, @-Rn {:11.2951 COUNT_INST(I_STCSRM);11.2952 check_priv();11.2953 call_func0( sh4_read_sr );11.2954 - MOV_r32_r32( R_EAX, R_EDX );11.2955 - load_reg( R_EAX, Rn );11.2956 - check_walign32( R_EAX );11.2957 - LEA_r32disp8_r32( R_EAX, -4, R_EAX );11.2958 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2959 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.2960 + MOVL_r32_r32( REG_EAX, REG_EDX );11.2961 + load_reg( REG_EAX, Rn );11.2962 + check_walign32( REG_EAX );11.2963 + LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );11.2964 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2965 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.2966 sh4_x86.tstate = TSTATE_NONE;11.2967 :}11.2968 STC.L VBR, @-Rn {:11.2969 COUNT_INST(I_STCM);11.2970 check_priv();11.2971 - load_reg( R_EAX, Rn );11.2972 - check_walign32( R_EAX );11.2973 - ADD_imm8s_r32( -4, R_EAX );11.2974 - load_spreg( R_EDX, R_VBR );11.2975 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2976 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.2977 + load_reg( REG_EAX, Rn );11.2978 + check_walign32( REG_EAX );11.2979 + ADDL_imms_r32( -4, REG_EAX );11.2980 + load_spreg( REG_EDX, R_VBR );11.2981 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2982 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.2983 sh4_x86.tstate = TSTATE_NONE;11.2984 :}11.2985 STC.L SSR, @-Rn {:11.2986 COUNT_INST(I_STCM);11.2987 check_priv();11.2988 - load_reg( R_EAX, Rn );11.2989 - check_walign32( R_EAX );11.2990 - ADD_imm8s_r32( -4, R_EAX );11.2991 - load_spreg( R_EDX, R_SSR );11.2992 - MEM_WRITE_LONG( R_EAX, R_EDX );11.2993 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.2994 + load_reg( REG_EAX, Rn );11.2995 + check_walign32( REG_EAX );11.2996 + ADDL_imms_r32( -4, REG_EAX );11.2997 + load_spreg( REG_EDX, R_SSR );11.2998 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.2999 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3000 sh4_x86.tstate = TSTATE_NONE;11.3001 :}11.3002 STC.L SPC, @-Rn {:11.3003 COUNT_INST(I_STCM);11.3004 check_priv();11.3005 - load_reg( R_EAX, Rn );11.3006 - check_walign32( R_EAX );11.3007 - ADD_imm8s_r32( -4, R_EAX );11.3008 - load_spreg( R_EDX, R_SPC );11.3009 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3010 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3011 + load_reg( REG_EAX, Rn );11.3012 + check_walign32( REG_EAX );11.3013 + ADDL_imms_r32( -4, REG_EAX );11.3014 + load_spreg( REG_EDX, R_SPC );11.3015 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3016 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3017 sh4_x86.tstate = TSTATE_NONE;11.3018 :}11.3019 STC.L SGR, @-Rn {:11.3020 COUNT_INST(I_STCM);11.3021 check_priv();11.3022 - load_reg( R_EAX, Rn );11.3023 - check_walign32( R_EAX );11.3024 - ADD_imm8s_r32( -4, R_EAX );11.3025 - load_spreg( R_EDX, R_SGR );11.3026 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3027 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3028 + load_reg( REG_EAX, Rn );11.3029 + check_walign32( REG_EAX );11.3030 + ADDL_imms_r32( -4, REG_EAX );11.3031 + load_spreg( REG_EDX, R_SGR );11.3032 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3033 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3034 sh4_x86.tstate = TSTATE_NONE;11.3035 :}11.3036 STC.L DBR, @-Rn {:11.3037 COUNT_INST(I_STCM);11.3038 check_priv();11.3039 - load_reg( R_EAX, Rn );11.3040 - check_walign32( R_EAX );11.3041 - ADD_imm8s_r32( -4, R_EAX );11.3042 - load_spreg( R_EDX, R_DBR );11.3043 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3044 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3045 + load_reg( REG_EAX, Rn );11.3046 + check_walign32( REG_EAX );11.3047 + ADDL_imms_r32( -4, REG_EAX );11.3048 + load_spreg( REG_EDX, R_DBR );11.3049 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3050 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3051 sh4_x86.tstate = TSTATE_NONE;11.3052 :}11.3053 STC.L Rm_BANK, @-Rn {:11.3054 COUNT_INST(I_STCM);11.3055 check_priv();11.3056 - load_reg( R_EAX, Rn );11.3057 - check_walign32( R_EAX );11.3058 - ADD_imm8s_r32( -4, R_EAX );11.3059 - load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );11.3060 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3061 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3062 + load_reg( REG_EAX, Rn );11.3063 + check_walign32( REG_EAX );11.3064 + ADDL_imms_r32( -4, REG_EAX );11.3065 + load_spreg( REG_EDX, REG_OFFSET(r_bank[Rm_BANK]) );11.3066 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3067 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3068 sh4_x86.tstate = TSTATE_NONE;11.3069 :}11.3070 STC.L GBR, @-Rn {:11.3071 COUNT_INST(I_STCM);11.3072 - load_reg( R_EAX, Rn );11.3073 - check_walign32( R_EAX );11.3074 - ADD_imm8s_r32( -4, R_EAX );11.3075 - load_spreg( R_EDX, R_GBR );11.3076 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3077 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3078 + load_reg( REG_EAX, Rn );11.3079 + check_walign32( REG_EAX );11.3080 + ADDL_imms_r32( -4, REG_EAX );11.3081 + load_spreg( REG_EDX, R_GBR );11.3082 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3083 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3084 sh4_x86.tstate = TSTATE_NONE;11.3085 :}11.3086 STS FPSCR, Rn {:11.3087 COUNT_INST(I_STSFPSCR);11.3088 check_fpuen();11.3089 - load_spreg( R_EAX, R_FPSCR );11.3090 - store_reg( R_EAX, Rn );11.3091 + load_spreg( REG_EAX, R_FPSCR );11.3092 + store_reg( REG_EAX, Rn );11.3093 :}11.3094 STS.L FPSCR, @-Rn {:11.3095 COUNT_INST(I_STSFPSCRM);11.3096 check_fpuen();11.3097 - load_reg( R_EAX, Rn );11.3098 - check_walign32( R_EAX );11.3099 - ADD_imm8s_r32( -4, R_EAX );11.3100 - load_spreg( R_EDX, R_FPSCR );11.3101 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3102 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3103 + load_reg( REG_EAX, Rn );11.3104 + check_walign32( REG_EAX );11.3105 + ADDL_imms_r32( -4, REG_EAX );11.3106 + load_spreg( REG_EDX, R_FPSCR );11.3107 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3108 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3109 sh4_x86.tstate = TSTATE_NONE;11.3110 :}11.3111 STS FPUL, Rn {:11.3112 COUNT_INST(I_STS);11.3113 check_fpuen();11.3114 - load_spreg( R_EAX, R_FPUL );11.3115 - store_reg( R_EAX, Rn );11.3116 + load_spreg( REG_EAX, R_FPUL );11.3117 + store_reg( REG_EAX, Rn );11.3118 :}11.3119 STS.L FPUL, @-Rn {:11.3120 COUNT_INST(I_STSM);11.3121 check_fpuen();11.3122 - load_reg( R_EAX, Rn );11.3123 - check_walign32( R_EAX );11.3124 - ADD_imm8s_r32( -4, R_EAX );11.3125 - load_spreg( R_EDX, R_FPUL );11.3126 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3127 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3128 + load_reg( REG_EAX, Rn );11.3129 + check_walign32( REG_EAX );11.3130 + ADDL_imms_r32( -4, REG_EAX );11.3131 + load_spreg( REG_EDX, R_FPUL );11.3132 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3133 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3134 sh4_x86.tstate = TSTATE_NONE;11.3135 :}11.3136 STS MACH, Rn {:11.3137 COUNT_INST(I_STS);11.3138 - load_spreg( R_EAX, R_MACH );11.3139 - store_reg( R_EAX, Rn );11.3140 + load_spreg( REG_EAX, R_MACH );11.3141 + store_reg( REG_EAX, Rn );11.3142 :}11.3143 STS.L MACH, @-Rn {:11.3144 COUNT_INST(I_STSM);11.3145 - load_reg( R_EAX, Rn );11.3146 - check_walign32( R_EAX );11.3147 - ADD_imm8s_r32( -4, R_EAX );11.3148 - load_spreg( R_EDX, R_MACH );11.3149 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3150 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3151 + load_reg( REG_EAX, Rn );11.3152 + check_walign32( REG_EAX );11.3153 + ADDL_imms_r32( -4, REG_EAX );11.3154 + load_spreg( REG_EDX, R_MACH );11.3155 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3156 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3157 sh4_x86.tstate = TSTATE_NONE;11.3158 :}11.3159 STS MACL, Rn {:11.3160 COUNT_INST(I_STS);11.3161 - load_spreg( R_EAX, R_MACL );11.3162 - store_reg( R_EAX, Rn );11.3163 + load_spreg( REG_EAX, R_MACL );11.3164 + store_reg( REG_EAX, Rn );11.3165 :}11.3166 STS.L MACL, @-Rn {:11.3167 COUNT_INST(I_STSM);11.3168 - load_reg( R_EAX, Rn );11.3169 - check_walign32( R_EAX );11.3170 - ADD_imm8s_r32( -4, R_EAX );11.3171 - load_spreg( R_EDX, R_MACL );11.3172 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3173 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3174 + load_reg( REG_EAX, Rn );11.3175 + check_walign32( REG_EAX );11.3176 + ADDL_imms_r32( -4, REG_EAX );11.3177 + load_spreg( REG_EDX, R_MACL );11.3178 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3179 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3180 sh4_x86.tstate = TSTATE_NONE;11.3181 :}11.3182 STS PR, Rn {:11.3183 COUNT_INST(I_STS);11.3184 - load_spreg( R_EAX, R_PR );11.3185 - store_reg( R_EAX, Rn );11.3186 + load_spreg( REG_EAX, R_PR );11.3187 + store_reg( REG_EAX, Rn );11.3188 :}11.3189 STS.L PR, @-Rn {:11.3190 COUNT_INST(I_STSM);11.3191 - load_reg( R_EAX, Rn );11.3192 - check_walign32( R_EAX );11.3193 - ADD_imm8s_r32( -4, R_EAX );11.3194 - load_spreg( R_EDX, R_PR );11.3195 - MEM_WRITE_LONG( R_EAX, R_EDX );11.3196 - ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );11.3197 + load_reg( REG_EAX, Rn );11.3198 + check_walign32( REG_EAX );11.3199 + ADDL_imms_r32( -4, REG_EAX );11.3200 + load_spreg( REG_EDX, R_PR );11.3201 + MEM_WRITE_LONG( REG_EAX, REG_EDX );11.3202 + ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );11.3203 sh4_x86.tstate = TSTATE_NONE;11.3204 :}
12.1 --- a/src/sh4/x86op.h Wed Mar 04 23:04:54 2009 +000012.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +000012.3 @@ -1,357 +0,0 @@12.4 -/**12.5 - * $Id$12.6 - *12.7 - * Definitions of x86 opcodes for use by the translator.12.8 - *12.9 - * Copyright (c) 2007 Nathan Keynes.12.10 - *12.11 - * This program is free software; you can redistribute it and/or modify12.12 - * it under the terms of the GNU General Public License as published by12.13 - * the Free Software Foundation; either version 2 of the License, or12.14 - * (at your option) any later version.12.15 - *12.16 - * This program is distributed in the hope that it will be useful,12.17 - * but WITHOUT ANY WARRANTY; without even the implied warranty of12.18 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the12.19 - * GNU General Public License for more details.12.20 - */12.21 -12.22 -#ifndef lxdream_x86op_H12.23 -#define lxdream_x86op_H 112.24 -12.25 -#ifdef __cplusplus12.26 -extern "C" {12.27 -#endif12.28 -12.29 -#define R_NONE -112.30 -#define R_EAX 012.31 -#define R_ECX 112.32 -#define R_EDX 212.33 -#define R_EBX 312.34 -#define R_ESP 412.35 -#define R_EBP 512.36 -#define R_ESI 612.37 -#define R_EDI 712.38 -12.39 -#define R_AL 012.40 -#define R_CL 112.41 -#define R_DL 212.42 -#define R_BL 312.43 -#define R_AH 412.44 -#define R_CH 512.45 -#define R_DH 612.46 -#define R_BH 712.47 -12.48 -#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = xlat_output12.49 -#define MARK_JMP32(x) uint32_t *_mark_jmp_##x = (uint32_t *)xlat_output12.50 -#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)12.51 -12.52 -#define OP(x) *xlat_output++ = (x)12.53 -#define OP32(x) *((uint32_t *)xlat_output) = (x); xlat_output+=412.54 -#define OP64(x) *((uint64_t *)xlat_output) = (x); xlat_output+=812.55 -#if SIZEOF_VOID_P == 812.56 -#define OPPTR(x) OP64((uint64_t)(x))12.57 -#define AND_imm8s_rptr(imm, r1) REXW(); AND_imm8s_r32( imm, r1 )12.58 -#define LEA_sh4r_rptr(disp, r1) REXW(); LEA_sh4r_r32(disp,r1)12.59 -#define MOV_moffptr_EAX(offptr) REXW(); MOV_moff32_EAX( offptr )12.60 -#define load_exc_backpatch( x86reg ) REXW(); OP(0xB8 + x86reg); sh4_x86_add_backpatch( xlat_output, pc, -2 ); OP64( 0 )12.61 -#define MOV_backpatch_esp8( disp ) REXW(); OP(0xC7); MODRM_r32_esp8(0, disp); sh4_x86_add_backpatch( xlat_output, pc, -2); OP64(0)12.62 -12.63 -/* imm64 operations are only defined for x86-64 */12.64 -#define MOV_imm64_r32(i64,r1) REXW(); OP(0xB8+r1); OP64(i64)12.65 -12.66 -#else /* 32-bit system */12.67 -#define OPPTR(x) OP32((uint32_t)(x))12.68 -#define AND_imm8s_rptr(imm, r1) AND_imm8s_r32( imm, r1 )12.69 -#define LEA_sh4r_rptr(disp, r1) LEA_sh4r_r32(disp,r1)12.70 -#define MOV_moffptr_EAX(offptr) MOV_moff32_EAX( offptr )12.71 -#define load_exc_backpatch( x86reg ) OP(0xB8 + x86reg); sh4_x86_add_backpatch( xlat_output, pc, -2 ); OP32( 0 )12.72 -#define MOV_backpatch_esp8( disp ) OP(0xC7); MODRM_r32_esp8(0, disp); sh4_x86_add_backpatch( xlat_output, pc, -2); OP32(0)12.73 -#endif12.74 -#define STACK_ALIGN 1612.75 -#define POP_r32(r1) OP(0x58 + r1)12.76 -#define PUSH_r32(r1) OP(0x50 + r1)12.77 -#define PUSH_imm32(imm) OP(0x68); OP32(imm)12.78 -#define PUSH_imm64(imm) REXW(); OP(0x68); OP64(imm);12.79 -12.80 -#ifdef STACK_ALIGN12.81 -#else12.82 -#define POP_r32(r1) OP(0x58 + r1)12.83 -#define PUSH_r32(r1) OP(0x50 + r1)12.84 -#endif12.85 -12.86 -12.87 -/* Offset of a reg relative to the sh4r structure */12.88 -#define REG_OFFSET(reg) (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)12.89 -12.90 -#define R_T REG_OFFSET(t)12.91 -#define R_Q REG_OFFSET(q)12.92 -#define R_S REG_OFFSET(s)12.93 -#define R_M REG_OFFSET(m)12.94 -#define R_SR REG_OFFSET(sr)12.95 -#define R_GBR REG_OFFSET(gbr)12.96 -#define R_SSR REG_OFFSET(ssr)12.97 -#define R_SPC REG_OFFSET(spc)12.98 -#define R_VBR REG_OFFSET(vbr)12.99 -#define R_MACH REG_OFFSET(mac)+412.100 -#define R_MACL REG_OFFSET(mac)12.101 -#define R_PC REG_OFFSET(pc)12.102 -#define R_NEW_PC REG_OFFSET(new_pc)12.103 -#define R_PR REG_OFFSET(pr)12.104 -#define R_SGR REG_OFFSET(sgr)12.105 -#define R_FPUL REG_OFFSET(fpul)12.106 -#define R_FPSCR REG_OFFSET(fpscr)12.107 -#define R_DBR REG_OFFSET(dbr)12.108 -12.109 -/**************** Basic X86 operations *********************/12.110 -/* Note: operands follow SH4 convention (source, dest) rather than x8612.111 - * conventions (dest, source)12.112 - */12.113 -12.114 -/* Two-reg modrm form - first arg is the r32 reg, second arg is the r/m32 reg */12.115 -#define MODRM_r32_rm32(r1,r2) OP(0xC0 | (r1<<3) | r2)12.116 -#define MODRM_rm32_r32(r1,r2) OP(0xC0 | (r2<<3) | r1)12.117 -12.118 -/* ebp+disp8 modrm form */12.119 -#define MODRM_r32_ebp8(r1,disp) OP(0x45 | (r1<<3)); OP(disp)12.120 -12.121 -/* ebp+disp32 modrm form */12.122 -#define MODRM_r32_ebp32(r1,disp) OP(0x85 | (r1<<3)); OP32(disp)12.123 -12.124 -/* esp+disp8 modrm+sib form */12.125 -#define MODRM_r32_esp8(r1,disp) OP(0x44 | (r1<<3)); OP(0x24); OP(disp)12.126 -12.127 -#define MODRM_r32_sh4r(r1,disp) if(disp>127){ MODRM_r32_ebp32(r1,disp);}else{ MODRM_r32_ebp8(r1,(unsigned char)disp); }12.128 -12.129 -/* Absolute displacement (no base) */12.130 -#define MODRM_r32_disp32(r1,disp) OP(0x05 | (r1<<3)); OP32(disp)12.131 -12.132 -#define REXW() OP(0x48)12.133 -12.134 -/* Major opcodes */12.135 -#define ADD_sh4r_r32(disp,r1) OP(0x03); MODRM_r32_sh4r(r1,disp)12.136 -#define ADD_r32_sh4r(r1,disp) OP(0x01); MODRM_r32_sh4r(r1,disp)12.137 -#define ADD_r32_r32(r1,r2) OP(0x03); MODRM_rm32_r32(r1,r2)12.138 -#define ADD_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1, 0); OP(imm)12.139 -#define ADD_imm8s_sh4r(imm,disp) OP(0x83); MODRM_r32_sh4r(0,disp); OP(imm)12.140 -#define ADD_imm8s_esp8(imm,disp) OP(0x83); MODRM_r32_esp8(0,disp); OP(imm)12.141 -#define ADD_imm32_r32(imm32,r1) OP(0x81); MODRM_rm32_r32(r1,0); OP32(imm32)12.142 -#define ADC_r32_r32(r1,r2) OP(0x13); MODRM_rm32_r32(r1,r2)12.143 -#define ADC_sh4r_r32(disp,r1) OP(0x13); MODRM_r32_sh4r(r1,disp)12.144 -#define ADC_r32_sh4r(r1,disp) OP(0x11); MODRM_r32_sh4r(r1,disp)12.145 -#define AND_r32_r32(r1,r2) OP(0x23); MODRM_rm32_r32(r1,r2)12.146 -#define AND_imm8_r8(imm8, r1) OP(0x80); MODRM_rm32_r32(r1,4); OP(imm8)12.147 -#define AND_imm8s_r32(imm8,r1) OP(0x83); MODRM_rm32_r32(r1,4); OP(imm8)12.148 -#define AND_imm8s_sh4r(imm8,disp) OP(0x83); MODRM_r32_sh4r(4,disp); OP(imm8)12.149 -#define AND_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,4); OP32(imm)12.150 -#define AND_sh4r_r32(disp,r1) OP(0x23); MODRM_r32_sh4r(r1, disp)12.151 -#define CALL_r32(r1) OP(0xFF); MODRM_rm32_r32(r1,2)12.152 -#define CALL_ptr(ptr) OP(0xE8); OP32( (((char *)ptr) - (char *)xlat_output) - 4)12.153 -#define CALL_sh4r(disp) OP(0xFF); MODRM_r32_sh4r(2, disp)12.154 -#define CALL_r32disp8(r1,disp) OP(0xFF); OP(0x50 + r1); OP(disp)12.155 -#define CLC() OP(0xF8)12.156 -#define CMC() OP(0xF5)12.157 -#define CMP_sh4r_r32(disp,r1) OP(0x3B); MODRM_r32_sh4r(r1,disp)12.158 -#define CMP_r32_r32(r1,r2) OP(0x3B); MODRM_rm32_r32(r1,r2)12.159 -#define CMP_imm32_r32(imm32, r1) OP(0x81); MODRM_rm32_r32(r1,7); OP32(imm32)12.160 -#define CMP_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1,7); OP(imm)12.161 -#define CMP_imm8s_sh4r(imm,disp) OP(0x83); MODRM_r32_sh4r(7,disp) OP(imm)12.162 -#define DEC_r32(r1) OP(0x48+r1)12.163 -#define IMUL_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,5)12.164 -#define IMUL_esp8(disp) OP(0xF7); MODRM_r32_esp8(5,disp)12.165 -#define INC_r32(r1) OP(0x40+r1)12.166 -#define JMP_rel8(label) OP(0xEB); MARK_JMP8(label); OP(-1);12.167 -#define JMP_r32disp8(r1,disp) OP(0xFF); OP(0x60 + r1); OP(disp)12.168 -#define LEA_sh4r_r32(disp,r1) OP(0x8D); MODRM_r32_sh4r(r1,disp)12.169 -#define LEA_r32disp8_r32(r1, disp, r2) OP(0x8D); OP( 0x40 + (r2<<3) + r1); OP(disp)12.170 -#define MOV_imm32_r32(i32,r1) OP(0xB8+r1); OP32(i32)12.171 -#define MOV_r32_r32(r1,r2) OP(0x89); MODRM_r32_rm32(r1,r2)12.172 -#define MOV_r32_sh4r(r1,disp) OP(0x89); MODRM_r32_sh4r(r1,disp)12.173 -#define MOV_moff32_EAX(off) OP(0xA1); OPPTR(off)12.174 -#define MOV_sh4r_r32(disp, r1) OP(0x8B); MODRM_r32_sh4r(r1,disp)12.175 -#define MOV_r32_r32ind(r2,r1) OP(0x89); OP(0 + (r2<<3) + r1 )12.176 -#define MOV_r32ind_r32(r1,r2) OP(0x8B); OP(0 + (r2<<3) + r1 )12.177 -#define MOV_r32_r32disp32(r2,r1,disp) OP(0x89); OP(0x80 + (r2<<3) + r1); OP32(disp)12.178 -#define MOV_r32_ebpr32disp32(r2,r1,disp) OP(0x89); OP(0x84 + (r2<<3)); OP(0x05 + (r1<<3)); OP32(disp)12.179 -#define MOV_r32disp32_r32(r1,disp,r2) OP(0x8B); OP(0x80 + (r2<<3) + r1); OP32(disp)12.180 -#define MOV_r32disp32x4_r32(r1,disp,r2) OP(0x8B); OP(0x04 + (r2<<3)); OP(0x85+(r1<<3)); OP32(disp)12.181 -#define MOV_r32_esp8(r1,disp) OP(0x89); MODRM_r32_esp8(r1,disp)12.182 -#define MOV_esp8_r32(disp,r1) OP(0x8B); MODRM_r32_esp8(r1,disp)12.183 -#define MOVSX_r8_r32(r1,r2) OP(0x0F); OP(0xBE); MODRM_rm32_r32(r1,r2)12.184 -#define MOVSX_r16_r32(r1,r2) OP(0x0F); OP(0xBF); MODRM_rm32_r32(r1,r2)12.185 -#define MOVZX_r8_r32(r1,r2) OP(0x0F); OP(0xB6); MODRM_rm32_r32(r1,r2)12.186 -#define MOVZX_r16_r32(r1,r2) OP(0x0F); OP(0xB7); MODRM_rm32_r32(r1,r2)12.187 -#define MOVZX_sh4r8_r32(disp,r1) OP(0x0F); OP(0xB6); MODRM_r32_sh4r(r1,disp)12.188 -#define MOVZX_sh4r16_r32(disp,r1) OP(0x0F); OP(0xB7); MODRM_r32_sh4r(r1,disp)12.189 -#define MUL_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,4)12.190 -#define NEG_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,3)12.191 -#define NOT_r32(r1) OP(0xF7); MODRM_rm32_r32(r1,2)12.192 -#define OR_r32_r32(r1,r2) OP(0x0B); MODRM_rm32_r32(r1,r2)12.193 -#define OR_imm8_r8(imm,r1) OP(0x80); MODRM_rm32_r32(r1,1); OP(imm)12.194 -#define OR_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,1); OP32(imm)12.195 -#define OR_sh4r_r32(disp,r1) OP(0x0B); MODRM_r32_sh4r(r1,disp)12.196 -#define RCL1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,2)12.197 -#define RCR1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,3)12.198 -#define RET() OP(0xC3)12.199 -#define ROL1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,0)12.200 -#define ROR1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,1)12.201 -#define SAR1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,7)12.202 -#define SAR_imm8_r32(imm,r1) OP(0xC1); MODRM_rm32_r32(r1,7); OP(imm)12.203 -#define SAR_r32_CL(r1) OP(0xD3); MODRM_rm32_r32(r1,7)12.204 -#define SBB_r32_r32(r1,r2) OP(0x1B); MODRM_rm32_r32(r1,r2)12.205 -#define SHL1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,4)12.206 -#define SHL_r32_CL(r1) OP(0xD3); MODRM_rm32_r32(r1,4)12.207 -#define SHL_imm8_r32(imm,r1) OP(0xC1); MODRM_rm32_r32(r1,4); OP(imm)12.208 -#define SHR1_r32(r1) OP(0xD1); MODRM_rm32_r32(r1,5)12.209 -#define SHR_r32_CL(r1) OP(0xD3); MODRM_rm32_r32(r1,5)12.210 -#define SHR_imm8_r32(imm,r1) OP(0xC1); MODRM_rm32_r32(r1,5); OP(imm)12.211 -#define STC() OP(0xF9)12.212 -#define SUB_r32_r32(r1,r2) OP(0x2B); MODRM_rm32_r32(r1,r2)12.213 -#define SUB_sh4r_r32(disp,r1) OP(0x2B); MODRM_r32_sh4r(r1, disp)12.214 -#define SUB_imm8s_r32(imm,r1) ADD_imm8s_r32(-(imm),r1)12.215 -#define TEST_r8_r8(r1,r2) OP(0x84); MODRM_r32_rm32(r1,r2)12.216 -#define TEST_r32_r32(r1,r2) OP(0x85); MODRM_rm32_r32(r1,r2)12.217 -#define TEST_imm8_r8(imm8,r1) OP(0xF6); MODRM_rm32_r32(r1,0); OP(imm8)12.218 -#define TEST_imm32_r32(imm,r1) OP(0xF7); MODRM_rm32_r32(r1,0); OP32(imm)12.219 -#define XCHG_r8_r8(r1,r2) OP(0x86); MODRM_rm32_r32(r1,r2)12.220 -#define XOR_r8_r8(r1,r2) OP(0x32); MODRM_rm32_r32(r1,r2)12.221 -#define XOR_imm8s_r32(imm,r1) OP(0x83); MODRM_rm32_r32(r1,6); OP(imm)12.222 -#define XOR_r32_r32(r1,r2) OP(0x33); MODRM_rm32_r32(r1,r2)12.223 -#define XOR_sh4r_r32(disp,r1) OP(0x33); MODRM_r32_sh4r(r1,disp)12.224 -#define XOR_imm32_r32(imm,r1) OP(0x81); MODRM_rm32_r32(r1,6); OP32(imm)12.225 -#define XOR_imm32_sh4r(imm,disp) OP(0x81); MODRM_r32_sh4r(6, disp); OP32(imm)12.226 -12.227 -12.228 -/* Floating point ops */12.229 -#define FABS_st0() OP(0xD9); OP(0xE1)12.230 -#define FADDP_st(st) OP(0xDE); OP(0xC0+st)12.231 -#define FCHS_st0() OP(0xD9); OP(0xE0)12.232 -#define FCOMIP_st(st) OP(0xDF); OP(0xF0+st)12.233 -#define FDIVP_st(st) OP(0xDE); OP(0xF8+st)12.234 -#define FILD_r32ind(r32) OP(0xDB); OP(0x00+r32)12.235 -#define FLD0_st0() OP(0xD9); OP(0xEE);12.236 -#define FLD1_st0() OP(0xD9); OP(0xE8);12.237 -#define FLDf_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(0, disp)12.238 -#define FLDd_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(0, disp)12.239 -#define FLDCW_r32ind(r32) OP(0xD9); OP(0x28+r32)12.240 -#define FMULP_st(st) OP(0xDE); OP(0xC8+st)12.241 -#define FNSTCW_r32ind(r32) OP(0xD9); OP(0x38+r32)12.242 -#define FPOP_st() OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)12.243 -#define FSTPf_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(3, disp)12.244 -#define FSTPd_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(3, disp)12.245 -#define FSUBP_st(st) OP(0xDE); OP(0xE8+st)12.246 -#define FSQRT_st0() OP(0xD9); OP(0xFA)12.247 -12.248 -#define FILD_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(0, disp)12.249 -#define FLDF_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(0, disp)12.250 -#define FLDD_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(0, disp)12.251 -#define FISTP_sh4r(disp) OP(0xDB); MODRM_r32_sh4r(3, disp)12.252 -#define FSTPF_sh4r(disp) OP(0xD9); MODRM_r32_sh4r(3,disp)12.253 -#define FSTPD_sh4r(disp) OP(0xDD); MODRM_r32_sh4r(3,disp)12.254 -12.255 -/* Conditional branches */12.256 -#define JE_rel8(label) OP(0x74); MARK_JMP8(label); OP(-1)12.257 -#define JA_rel8(label) OP(0x77); MARK_JMP8(label); OP(-1)12.258 -#define JAE_rel8(label) OP(0x73); MARK_JMP8(label); OP(-1)12.259 -#define JG_rel8(label) OP(0x7F); MARK_JMP8(label); OP(-1)12.260 -#define JGE_rel8(label) OP(0x7D); MARK_JMP8(label); OP(-1)12.261 -#define JC_rel8(label) OP(0x72); MARK_JMP8(label); OP(-1)12.262 -#define JO_rel8(label) OP(0x70); MARK_JMP8(label); OP(-1)12.263 -#define JNE_rel8(label) OP(0x75); MARK_JMP8(label); OP(-1)12.264 -#define JNA_rel8(label) OP(0x76); MARK_JMP8(label); OP(-1)12.265 -#define JNAE_rel8(label) OP(0x72); MARK_JMP8(label); OP(-1)12.266 -#define JNG_rel8(label) OP(0x7E); MARK_JMP8(label); OP(-1)12.267 -#define JNGE_rel8(label) OP(0x7C); MARK_JMP8(label); OP(-1)12.268 -#define JNC_rel8(label) OP(0x73); MARK_JMP8(label); OP(-1)12.269 -#define JNO_rel8(label) OP(0x71); MARK_JMP8(label); OP(-1)12.270 -#define JNS_rel8(label) OP(0x79); MARK_JMP8(label); OP(-1)12.271 -#define JS_rel8(label) OP(0x78); MARK_JMP8(label); OP(-1)12.272 -12.273 -/** JMP relative 8 or 32 depending on size of rel. rel offset12.274 - * from the start of the instruction (not end)12.275 - */12.276 -#define JMP_rel(rel) if((rel)<-126||(rel)>129) { OP(0xE9); OP32((rel)-5); } else { OP(0xEB); OP((rel)-2); }12.277 -12.278 -/* 32-bit long forms w/ backpatching to an exception routine */12.279 -#define JMP_exc(exc) OP(0xE9); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.280 -#define JE_exc(exc) OP(0x0F); OP(0x84); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.281 -#define JA_exc(exc) OP(0x0F); OP(0x87); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.282 -#define JAE_exc(exc) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.283 -#define JG_exc(exc) OP(0x0F); OP(0x8F); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.284 -#define JGE_exc(exc) OP(0x0F); OP(0x8D); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.285 -#define JC_exc(exc) OP(0x0F); OP(0x82); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.286 -#define JO_exc(exc) OP(0x0F); OP(0x80); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.287 -#define JNE_exc(exc) OP(0x0F); OP(0x85); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.288 -#define JNA_exc(exc) OP(0x0F); OP(0x86); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.289 -#define JNAE_exc(exc) OP(0x0F);OP(0x82); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.290 -#define JNG_exc(exc) OP(0x0F); OP(0x8E); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.291 -#define JNGE_exc(exc) OP(0x0F);OP(0x8C); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.292 -#define JNC_exc(exc) OP(0x0F); OP(0x83); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.293 -#define JNO_exc(exc) OP(0x0F); OP(0x81); sh4_x86_add_backpatch(xlat_output, pc, exc); OP32(0)12.294 -12.295 -#define EXPJE_rel8(label) OP(0x3E); JE_rel8(label)12.296 -12.297 -/* Conditional moves ebp-rel */12.298 -#define CMOVE_r32_r32(r1,r2) OP(0x0F); OP(0x44); MODRM_rm32_r32(r1,r2)12.299 -#define CMOVA_r32_r32(r1,r2) OP(0x0F); OP(0x47); MODRM_rm32_r32(r1,r2)12.300 -#define CMOVAE_r32_r32(r1,r2) OP(0x0F); OP(0x43); MODRM_rm32_r32(r1,r2)12.301 -#define CMOVG_r32_r32(r1,r2) OP(0x0F); OP(0x4F); MODRM_rm32_r32(r1,r2)12.302 -#define CMOVGE_r32_r32(r1,r2) OP(0x0F); OP(0x4D); MODRM_rm32_r32(r1,r2)12.303 -#define CMOVC_r32_r32(r1,r2) OP(0x0F); OP(0x42); MODRM_rm32_r32(r1,r2)12.304 -#define CMOVO_r32_r32(r1,r2) OP(0x0F); OP(0x40); MODRM_rm32_r32(r1,r2)12.305 -12.306 -12.307 -/* Conditional setcc - writeback to sh4r.t */12.308 -#define SETE_sh4r(disp) OP(0x0F); OP(0x94); MODRM_r32_sh4r(0, disp);12.309 -#define SETA_sh4r(disp) OP(0x0F); OP(0x97); MODRM_r32_sh4r(0, disp);12.310 -#define SETAE_sh4r(disp) OP(0x0F); OP(0x93); MODRM_r32_sh4r(0, disp);12.311 -#define SETG_sh4r(disp) OP(0x0F); OP(0x9F); MODRM_r32_sh4r(0, disp);12.312 -#define SETGE_sh4r(disp) OP(0x0F); OP(0x9D); MODRM_r32_sh4r(0, disp);12.313 -#define SETC_sh4r(disp) OP(0x0F); OP(0x92); MODRM_r32_sh4r(0, disp);12.314 -#define SETO_sh4r(disp) OP(0x0F); OP(0x90); MODRM_r32_sh4r(0, disp);12.315 -12.316 -#define SETNE_sh4r(disp) OP(0x0F); OP(0x95); MODRM_r32_sh4r(0, disp);12.317 -#define SETNA_sh4r(disp) OP(0x0F); OP(0x96); MODRM_r32_sh4r(0, disp);12.318 -#define SETNAE_sh4r(disp) OP(0x0F); OP(0x92); MODRM_r32_sh4r(0, disp);12.319 -#define SETNG_sh4r(disp) OP(0x0F); OP(0x9E); MODRM_r32_sh4r(0, disp);12.320 -#define SETNGE_sh4r(disp) OP(0x0F); OP(0x9C); MODRM_r32_sh4r(0, disp);12.321 -#define SETNC_sh4r(disp) OP(0x0F); OP(0x93); MODRM_r32_sh4r(0, disp);12.322 -#define SETNO_sh4r(disp) OP(0x0F); OP(0x91); MODRM_r32_sh4r(0, disp);12.323 -12.324 -#define SETE_t() SETE_sh4r(R_T)12.325 -#define SETA_t() SETA_sh4r(R_T)12.326 -#define SETAE_t() SETAE_sh4r(R_T)12.327 -#define SETG_t() SETG_sh4r(R_T)12.328 -#define SETGE_t() SETGE_sh4r(R_T)12.329 -#define SETC_t() SETC_sh4r(R_T)12.330 -#define SETO_t() SETO_sh4r(R_T)12.331 -#define SETNE_t() SETNE_sh4r(R_T)12.332 -12.333 -#define SETC_r8(r1) OP(0x0F); OP(0x92); MODRM_rm32_r32(r1, 0)12.334 -12.335 -/* Pseudo-op Load carry from T: CMP [EBP+t], #01 ; CMC */12.336 -#define LDC_t() OP(0x83); MODRM_r32_sh4r(7,R_T); OP(0x01); CMC()12.337 -12.338 -/* SSE instructions */12.339 -#define ADDPS_xmm_xmm(xmm1,xmm2) OP(0x0F); OP(0x58); MODRM_rm32_r32(xmm1,xmm2)12.340 -#define HADDPS_xmm_xmm(xmm1,xmm2) OP(0xF2); OP(0x0F); OP(0x7C); MODRM_rm32_r32(xmm1,xmm2)12.341 -#define MOVHLPS_xmm_xmm(xmm1,xmm2) OP(0x0F); OP(0x12); MODRM_rm32_r32(xmm1,xmm2)12.342 -#define MOVLHPS_xmm_xmm(xmm1,xmm2) OP(0x0F); OP(0x16); MODRM_rm32_r32(xmm1,xmm2)12.343 -#define MOVSHDUP_sh4r_xmm(disp,xmm) OP(0xF3); OP(0x0F); OP(0x16); MODRM_r32_sh4r(xmm,disp)12.344 -#define MOVSLDUP_sh4r_xmm(disp,xmm) OP(0xF3); OP(0x0F); OP(0x12); MODRM_r32_sh4r(xmm,disp)12.345 -#define MOVAPS_sh4r_xmm(disp, xmm) OP(0x0F); OP(0x28); MODRM_r32_sh4r(xmm,disp)12.346 -#define MOVAPS_xmm_sh4r(xmm,disp) OP(0x0F); OP(0x29); MODRM_r32_sh4r(xmm,disp)12.347 -#define MOVAPS_xmm_xmm(xmm1,xmm2) OP(0x0F); OP(0x28); MODRM_rm32_r32(xmm1,xmm2)12.348 -#define MOVSS_xmm_sh4r(xmm,disp) OP(0xF3); OP(0x0F); OP(0x11); MODRM_r32_sh4r(xmm,disp)12.349 -#define MULPS_sh4r_xmm(disp, xmm) OP(0x0F); OP(0x59); MODRM_r32_sh4r(xmm,disp)12.350 -#define MULPS_xmm_xmm(xmm1,xmm2) OP(0x0F); OP(0x59); MODRM_rm32_r32(xmm1,xmm2)12.351 -#define SHUFPS_sh4r_xmm(disp,xmm,imm8) OP(0x0F); OP(0xC6); MODRM_r32_sh4r(xmm, disp); OP(imm8)12.352 -#define SHUFPS_xmm_xmm(xmm1,xmm2,imm8) OP(0x0F); OP(0xC6); MODRM_rm32_r32(xmm1,xmm2); OP(imm8)12.353 -#define UNPCKHPS_xmm_xmm(xmm1,xmm2) OP(0x0F); OP(0x15); MODRM_rm32_r32(xmm1,xmm2)12.354 -#define UNPCKLPS_xmm_xmm(xmm1,xmm2) OP(0x0F); OP(0x14); MODRM_rm32_r32(xmm1,xmm2)12.355 -12.356 -#ifdef __cplusplus12.357 -}12.358 -#endif12.359 -12.360 -#endif /* !lxdream_x86op_H */
13.1 --- a/src/sh4/xltcache.c Wed Mar 04 23:04:54 2009 +000013.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +000013.3 @@ -1,497 +0,0 @@13.4 -/**13.5 - * $Id$13.6 - *13.7 - * Translation cache management. This part is architecture independent.13.8 - *13.9 - * Copyright (c) 2005 Nathan Keynes.13.10 - *13.11 - * This program is free software; you can redistribute it and/or modify13.12 - * it under the terms of the GNU General Public License as published by13.13 - * the Free Software Foundation; either version 2 of the License, or13.14 - * (at your option) any later version.13.15 - *13.16 - * This program is distributed in the hope that it will be useful,13.17 - * but WITHOUT ANY WARRANTY; without even the implied warranty of13.18 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the13.19 - * GNU General Public License for more details.13.20 - */13.21 -13.22 -#include <sys/types.h>13.23 -#include <sys/mman.h>13.24 -#include <assert.h>13.25 -13.26 -#include "dreamcast.h"13.27 -#include "sh4/sh4core.h"13.28 -#include "sh4/xltcache.h"13.29 -#include "x86dasm/x86dasm.h"13.30 -13.31 -#define XLAT_LUT_PAGE_BITS 1213.32 -#define XLAT_LUT_TOTAL_BITS 2813.33 -#define XLAT_LUT_PAGE(addr) (((addr)>>13) & 0xFFFF)13.34 -#define XLAT_LUT_ENTRY(addr) (((addr)&0x1FFE) >> 1)13.35 -13.36 -#define XLAT_LUT_PAGES (1<<(XLAT_LUT_TOTAL_BITS-XLAT_LUT_PAGE_BITS))13.37 -#define XLAT_LUT_PAGE_ENTRIES (1<<XLAT_LUT_PAGE_BITS)13.38 -#define XLAT_LUT_PAGE_SIZE (XLAT_LUT_PAGE_ENTRIES * sizeof(void *))13.39 -13.40 -#define XLAT_LUT_ENTRY_EMPTY (void *)013.41 -#define XLAT_LUT_ENTRY_USED (void *)113.42 -13.43 -#define NEXT(block) ( (xlat_cache_block_t)&((block)->code[(block)->size]))13.44 -#define IS_ENTRY_POINT(ent) (ent > XLAT_LUT_ENTRY_USED)13.45 -#define IS_ENTRY_USED(ent) (ent != XLAT_LUT_ENTRY_EMPTY)13.46 -13.47 -#define MIN_BLOCK_SIZE 3213.48 -#define MIN_TOTAL_SIZE (sizeof(struct xlat_cache_block)+MIN_BLOCK_SIZE)13.49 -13.50 -#define BLOCK_INACTIVE 013.51 -#define BLOCK_ACTIVE 113.52 -#define BLOCK_USED 213.53 -13.54 -xlat_cache_block_t xlat_new_cache;13.55 -xlat_cache_block_t xlat_new_cache_ptr;13.56 -xlat_cache_block_t xlat_new_create_ptr;13.57 -13.58 -#ifdef XLAT_GENERATIONAL_CACHE13.59 -xlat_cache_block_t xlat_temp_cache;13.60 -xlat_cache_block_t xlat_temp_cache_ptr;13.61 -xlat_cache_block_t xlat_old_cache;13.62 -xlat_cache_block_t xlat_old_cache_ptr;13.63 -#endif13.64 -13.65 -static void **xlat_lut[XLAT_LUT_PAGES];13.66 -static gboolean xlat_initialized = FALSE;13.67 -13.68 -void xlat_cache_init(void)13.69 -{13.70 - if( !xlat_initialized ) {13.71 - xlat_initialized = TRUE;13.72 - xlat_new_cache = (xlat_cache_block_t)mmap( NULL, XLAT_NEW_CACHE_SIZE, PROT_EXEC|PROT_READ|PROT_WRITE,13.73 - MAP_PRIVATE|MAP_ANON, -1, 0 );13.74 - xlat_new_cache_ptr = xlat_new_cache;13.75 - xlat_new_create_ptr = xlat_new_cache;13.76 -#ifdef XLAT_GENERATIONAL_CACHE13.77 - xlat_temp_cache = mmap( NULL, XLAT_TEMP_CACHE_SIZE, PROT_EXEC|PROT_READ|PROT_WRITE,13.78 - MAP_PRIVATE|MAP_ANON, -1, 0 );13.79 - xlat_old_cache = mmap( NULL, XLAT_OLD_CACHE_SIZE, PROT_EXEC|PROT_READ|PROT_WRITE,13.80 - MAP_PRIVATE|MAP_ANON, -1, 0 );13.81 - xlat_temp_cache_ptr = xlat_temp_cache;13.82 - xlat_old_cache_ptr = xlat_old_cache;13.83 -#endif13.84 -// xlat_lut = mmap( NULL, XLAT_LUT_PAGES*sizeof(void *), PROT_READ|PROT_WRITE,13.85 -// MAP_PRIVATE|MAP_ANON, -1, 0);13.86 - memset( xlat_lut, 0, XLAT_LUT_PAGES*sizeof(void *) );13.87 - }13.88 - xlat_flush_cache();13.89 -}13.90 -13.91 -/**13.92 - * Reset the cache structure to its default state13.93 - */13.94 -void xlat_flush_cache()13.95 -{13.96 - xlat_cache_block_t tmp;13.97 - int i;13.98 - xlat_new_cache_ptr = xlat_new_cache;13.99 - xlat_new_cache_ptr->active = 0;13.100 - xlat_new_cache_ptr->size = XLAT_NEW_CACHE_SIZE - 2*sizeof(struct xlat_cache_block);13.101 - tmp = NEXT(xlat_new_cache_ptr);13.102 - tmp->active = 1;13.103 - tmp->size = 0;13.104 -#ifdef XLAT_GENERATIONAL_CACHE13.105 - xlat_temp_cache_ptr = xlat_temp_cache;13.106 - xlat_temp_cache_ptr->active = 0;13.107 - xlat_temp_cache_ptr->size = XLAT_TEMP_CACHE_SIZE - 2*sizeof(struct xlat_cache_block);13.108 - tmp = NEXT(xlat_temp_cache_ptr);13.109 - tmp->active = 1;13.110 - tmp->size = 0;13.111 - xlat_old_cache_ptr = xlat_old_cache;13.112 - xlat_old_cache_ptr->active = 0;13.113 - xlat_old_cache_ptr->size = XLAT_OLD_CACHE_SIZE - 2*sizeof(struct xlat_cache_block);13.114 - tmp = NEXT(xlat_old_cache_ptr);13.115 - tmp->active = 1;13.116 - tmp->size = 0;13.117 -#endif13.118 - for( i=0; i<XLAT_LUT_PAGES; i++ ) {13.119 - if( xlat_lut[i] != NULL ) {13.120 - memset( xlat_lut[i], 0, XLAT_LUT_PAGE_SIZE );13.121 - }13.122 - }13.123 -}13.124 -13.125 -static void xlat_flush_page_by_lut( void **page )13.126 -{13.127 - int i;13.128 - for( i=0; i<XLAT_LUT_PAGE_ENTRIES; i++ ) {13.129 - if( IS_ENTRY_POINT(page[i]) ) {13.130 - XLAT_BLOCK_FOR_CODE(page[i])->active = 0;13.131 - }13.132 - page[i] = NULL;13.133 - }13.134 -}13.135 -13.136 -void FASTCALL xlat_invalidate_word( sh4addr_t addr )13.137 -{13.138 - void **page = xlat_lut[XLAT_LUT_PAGE(addr)];13.139 - if( page != NULL ) {13.140 - int entry = XLAT_LUT_ENTRY(addr);13.141 - if( page[entry] != NULL ) {13.142 - xlat_flush_page_by_lut(page);13.143 - }13.144 - }13.145 -}13.146 -13.147 -void FASTCALL xlat_invalidate_long( sh4addr_t addr )13.148 -{13.149 - void **page = xlat_lut[XLAT_LUT_PAGE(addr)];13.150 - if( page != NULL ) {13.151 - int entry = XLAT_LUT_ENTRY(addr);13.152 - if( *(uint64_t *)&page[entry] != 0 ) {13.153 - xlat_flush_page_by_lut(page);13.154 - }13.155 - }13.156 -}13.157 -13.158 -void FASTCALL xlat_invalidate_block( sh4addr_t address, size_t size )13.159 -{13.160 - int i;13.161 - int entry_count = size >> 1; // words;13.162 - uint32_t page_no = XLAT_LUT_PAGE(address);13.163 - int entry = XLAT_LUT_ENTRY(address);13.164 - do {13.165 - void **page = xlat_lut[page_no];13.166 - int page_entries = XLAT_LUT_PAGE_ENTRIES - entry;13.167 - if( entry_count < page_entries ) {13.168 - page_entries = entry_count;13.169 - }13.170 - if( page != NULL ) {13.171 - if( page_entries == XLAT_LUT_PAGE_ENTRIES ) {13.172 - /* Overwriting the entire page anyway */13.173 - xlat_flush_page_by_lut(page);13.174 - } else {13.175 - for( i=entry; i<entry+page_entries; i++ ) {13.176 - if( page[i] != NULL ) {13.177 - xlat_flush_page_by_lut(page);13.178 - break;13.179 - }13.180 - }13.181 - }13.182 - entry_count -= page_entries;13.183 - }13.184 - page_no ++;13.185 - entry_count -= page_entries;13.186 - entry = 0;13.187 - } while( entry_count > 0 );13.188 -}13.189 -13.190 -void FASTCALL xlat_flush_page( sh4addr_t address )13.191 -{13.192 - void **page = xlat_lut[XLAT_LUT_PAGE(address)];13.193 - if( page != NULL ) {13.194 - xlat_flush_page_by_lut(page);13.195 - }13.196 -}13.197 -13.198 -void * FASTCALL xlat_get_code( sh4addr_t address )13.199 -{13.200 - void *result = NULL;13.201 - void **page = xlat_lut[XLAT_LUT_PAGE(address)];13.202 - if( page != NULL ) {13.203 - result = (void *)(((uintptr_t)(page[XLAT_LUT_ENTRY(address)])) & (~((uintptr_t)0x03)));13.204 - }13.205 - return result;13.206 -}13.207 -13.208 -xlat_recovery_record_t xlat_get_pre_recovery( void *code, void *native_pc )13.209 -{13.210 - if( code != NULL ) {13.211 - uintptr_t pc_offset = ((uint8_t *)native_pc) - ((uint8_t *)code);13.212 - xlat_cache_block_t block = XLAT_BLOCK_FOR_CODE(code);13.213 - uint32_t count = block->recover_table_size;13.214 - xlat_recovery_record_t records = (xlat_recovery_record_t)(&block->code[block->recover_table_offset]);13.215 - uint32_t posn;13.216 - for( posn = 1; posn < count; posn++ ) {13.217 - if( records[posn].xlat_offset >= pc_offset ) {13.218 - return &records[posn-1];13.219 - }13.220 - }13.221 - return &records[count-1];13.222 - }13.223 - return NULL;13.224 -}13.225 -13.226 -void ** FASTCALL xlat_get_lut_entry( sh4addr_t address )13.227 -{13.228 - void **page = xlat_lut[XLAT_LUT_PAGE(address)];13.229 -13.230 - /* Add the LUT entry for the block */13.231 - if( page == NULL ) {13.232 - xlat_lut[XLAT_LUT_PAGE(address)] = page =13.233 - (void **)mmap( NULL, XLAT_LUT_PAGE_SIZE, PROT_READ|PROT_WRITE,13.234 - MAP_PRIVATE|MAP_ANON, -1, 0 );13.235 - memset( page, 0, XLAT_LUT_PAGE_SIZE );13.236 - }13.237 -13.238 - return &page[XLAT_LUT_ENTRY(address)];13.239 -}13.240 -13.241 -13.242 -13.243 -uint32_t FASTCALL xlat_get_block_size( void *block )13.244 -{13.245 - xlat_cache_block_t xlt = (xlat_cache_block_t)(((char *)block)-sizeof(struct xlat_cache_block));13.246 - return xlt->size;13.247 -}13.248 -13.249 -uint32_t FASTCALL xlat_get_code_size( void *block )13.250 -{13.251 - xlat_cache_block_t xlt = (xlat_cache_block_t)(((char *)block)-sizeof(struct xlat_cache_block));13.252 - if( xlt->recover_table_offset == 0 ) {13.253 - return xlt->size;13.254 - } else {13.255 - return xlt->recover_table_offset;13.256 - }13.257 -}13.258 -13.259 -/**13.260 - * Cut the specified block so that it has the given size, with the remaining data13.261 - * forming a new free block. If the free block would be less than the minimum size,13.262 - * the cut is not performed.13.263 - * @return the next block after the (possibly cut) block.13.264 - */13.265 -static inline xlat_cache_block_t xlat_cut_block( xlat_cache_block_t block, int cutsize )13.266 -{13.267 - cutsize = (cutsize + 3) & 0xFFFFFFFC; // force word alignment13.268 - assert( cutsize <= block->size );13.269 - if( block->size > cutsize + MIN_TOTAL_SIZE ) {13.270 - int oldsize = block->size;13.271 - block->size = cutsize;13.272 - xlat_cache_block_t next = NEXT(block);13.273 - next->active = 0;13.274 - next->size = oldsize - cutsize - sizeof(struct xlat_cache_block);13.275 - return next;13.276 - } else {13.277 - return NEXT(block);13.278 - }13.279 -}13.280 -13.281 -#ifdef XLAT_GENERATIONAL_CACHE13.282 -/**13.283 - * Promote a block in temp space (or elsewhere for that matter) to old space.13.284 - *13.285 - * @param block to promote.13.286 - */13.287 -static void xlat_promote_to_old_space( xlat_cache_block_t block )13.288 -{13.289 - int allocation = (int)-sizeof(struct xlat_cache_block);13.290 - int size = block->size;13.291 - xlat_cache_block_t curr = xlat_old_cache_ptr;13.292 - xlat_cache_block_t start_block = curr;13.293 - do {13.294 - allocation += curr->size + sizeof(struct xlat_cache_block);13.295 - curr = NEXT(curr);13.296 - if( allocation > size ) {13.297 - break; /* done */13.298 - }13.299 - if( curr->size == 0 ) { /* End-of-cache Sentinel */13.300 - /* Leave what we just released as free space and start again from the13.301 - * top of the cache13.302 - */13.303 - start_block->active = 0;13.304 - start_block->size = allocation;13.305 - allocation = (int)-sizeof(struct xlat_cache_block);13.306 - start_block = curr = xlat_old_cache;13.307 - }13.308 - } while(1);13.309 - start_block->active = 1;13.310 - start_block->size = allocation;13.311 - start_block->lut_entry = block->lut_entry;13.312 - start_block->fpscr_mask = block->fpscr_mask;13.313 - start_block->fpscr = block->fpscr;13.314 - start_block->recover_table_offset = block->recover_table_offset;13.315 - start_block->recover_table_size = block->recover_table_size;13.316 - *block->lut_entry = &start_block->code;13.317 - memcpy( start_block->code, block->code, block->size );13.318 - xlat_old_cache_ptr = xlat_cut_block(start_block, size );13.319 - if( xlat_old_cache_ptr->size == 0 ) {13.320 - xlat_old_cache_ptr = xlat_old_cache;13.321 - }13.322 -}13.323 -13.324 -/**13.325 - * Similarly to the above method, promotes a block to temp space.13.326 - * TODO: Try to combine these - they're nearly identical13.327 - */13.328 -void xlat_promote_to_temp_space( xlat_cache_block_t block )13.329 -{13.330 - int size = block->size;13.331 - int allocation = (int)-sizeof(struct xlat_cache_block);13.332 - xlat_cache_block_t curr = xlat_temp_cache_ptr;13.333 - xlat_cache_block_t start_block = curr;13.334 - do {13.335 - if( curr->active == BLOCK_USED ) {13.336 - xlat_promote_to_old_space( curr );13.337 - } else if( curr->active == BLOCK_ACTIVE ) {13.338 - // Active but not used, release block13.339 - *((uintptr_t *)curr->lut_entry) &= ((uintptr_t)0x03);13.340 - }13.341 - allocation += curr->size + sizeof(struct xlat_cache_block);13.342 - curr = NEXT(curr);13.343 - if( allocation > size ) {13.344 - break; /* done */13.345 - }13.346 - if( curr->size == 0 ) { /* End-of-cache Sentinel */13.347 - /* Leave what we just released as free space and start again from the13.348 - * top of the cache13.349 - */13.350 - start_block->active = 0;13.351 - start_block->size = allocation;13.352 - allocation = (int)-sizeof(struct xlat_cache_block);13.353 - start_block = curr = xlat_temp_cache;13.354 - }13.355 - } while(1);13.356 - start_block->active = 1;13.357 - start_block->size = allocation;13.358 - start_block->lut_entry = block->lut_entry;13.359 - start_block->fpscr_mask = block->fpscr_mask;13.360 - start_block->fpscr = block->fpscr;13.361 - start_block->recover_table_offset = block->recover_table_offset;13.362 - start_block->recover_table_size = block->recover_table_size;13.363 - *block->lut_entry = &start_block->code;13.364 - memcpy( start_block->code, block->code, block->size );13.365 - xlat_temp_cache_ptr = xlat_cut_block(start_block, size );13.366 - if( xlat_temp_cache_ptr->size == 0 ) {13.367 - xlat_temp_cache_ptr = xlat_temp_cache;13.368 - }13.369 -13.370 -}13.371 -#else13.372 -void xlat_promote_to_temp_space( xlat_cache_block_t block )13.373 -{13.374 - *block->lut_entry = 0;13.375 -}13.376 -#endif13.377 -13.378 -/**13.379 - * Returns the next block in the new cache list that can be written to by the13.380 - * translator. If the next block is active, it is evicted first.13.381 - */13.382 -xlat_cache_block_t xlat_start_block( sh4addr_t address )13.383 -{13.384 - if( xlat_new_cache_ptr->size == 0 ) {13.385 - xlat_new_cache_ptr = xlat_new_cache;13.386 - }13.387 -13.388 - if( xlat_new_cache_ptr->active ) {13.389 - xlat_promote_to_temp_space( xlat_new_cache_ptr );13.390 - }13.391 - xlat_new_create_ptr = xlat_new_cache_ptr;13.392 - xlat_new_create_ptr->active = 1;13.393 - xlat_new_cache_ptr = NEXT(xlat_new_cache_ptr);13.394 -13.395 - /* Add the LUT entry for the block */13.396 - if( xlat_lut[XLAT_LUT_PAGE(address)] == NULL ) {13.397 - xlat_lut[XLAT_LUT_PAGE(address)] =13.398 - (void **)mmap( NULL, XLAT_LUT_PAGE_SIZE, PROT_READ|PROT_WRITE,13.399 - MAP_PRIVATE|MAP_ANON, -1, 0 );13.400 - memset( xlat_lut[XLAT_LUT_PAGE(address)], 0, XLAT_LUT_PAGE_SIZE );13.401 - }13.402 -13.403 - if( IS_ENTRY_POINT(xlat_lut[XLAT_LUT_PAGE(address)][XLAT_LUT_ENTRY(address)]) ) {13.404 - xlat_cache_block_t oldblock = XLAT_BLOCK_FOR_CODE(xlat_lut[XLAT_LUT_PAGE(address)][XLAT_LUT_ENTRY(address)]);13.405 - oldblock->active = 0;13.406 - }13.407 -13.408 - xlat_lut[XLAT_LUT_PAGE(address)][XLAT_LUT_ENTRY(address)] =13.409 - &xlat_new_create_ptr->code;13.410 - xlat_new_create_ptr->lut_entry = xlat_lut[XLAT_LUT_PAGE(address)] + XLAT_LUT_ENTRY(address);13.411 -13.412 - return xlat_new_create_ptr;13.413 -}13.414 -13.415 -xlat_cache_block_t xlat_extend_block( uint32_t newSize )13.416 -{13.417 - while( xlat_new_create_ptr->size < newSize ) {13.418 - if( xlat_new_cache_ptr->size == 0 ) {13.419 - /* Migrate to the front of the cache to keep it contiguous */13.420 - xlat_new_create_ptr->active = 0;13.421 - sh4ptr_t olddata = xlat_new_create_ptr->code;13.422 - int oldsize = xlat_new_create_ptr->size;13.423 - int size = oldsize + MIN_BLOCK_SIZE; /* minimum expansion */13.424 - void **lut_entry = xlat_new_create_ptr->lut_entry;13.425 - int allocation = (int)-sizeof(struct xlat_cache_block);13.426 - xlat_new_cache_ptr = xlat_new_cache;13.427 - do {13.428 - if( xlat_new_cache_ptr->active ) {13.429 - xlat_promote_to_temp_space( xlat_new_cache_ptr );13.430 - }13.431 - allocation += xlat_new_cache_ptr->size + sizeof(struct xlat_cache_block);13.432 - xlat_new_cache_ptr = NEXT(xlat_new_cache_ptr);13.433 - } while( allocation < size );13.434 - xlat_new_create_ptr = xlat_new_cache;13.435 - xlat_new_create_ptr->active = 1;13.436 - xlat_new_create_ptr->size = allocation;13.437 - xlat_new_create_ptr->lut_entry = lut_entry;13.438 - *lut_entry = &xlat_new_create_ptr->code;13.439 - memmove( xlat_new_create_ptr->code, olddata, oldsize );13.440 - } else {13.441 - if( xlat_new_cache_ptr->active ) {13.442 - xlat_promote_to_temp_space( xlat_new_cache_ptr );13.443 - }13.444 - xlat_new_create_ptr->size += xlat_new_cache_ptr->size + sizeof(struct xlat_cache_block);13.445 - xlat_new_cache_ptr = NEXT(xlat_new_cache_ptr);13.446 - }13.447 - }13.448 - return xlat_new_create_ptr;13.449 -13.450 -}13.451 -13.452 -void xlat_commit_block( uint32_t destsize, uint32_t srcsize )13.453 -{13.454 - void **ptr = xlat_new_create_ptr->lut_entry;13.455 - void **endptr = ptr + (srcsize>>2);13.456 - while( ptr < endptr ) {13.457 - if( *ptr == NULL ) {13.458 - *ptr = XLAT_LUT_ENTRY_USED;13.459 - }13.460 - ptr++;13.461 - }13.462 -13.463 - xlat_new_cache_ptr = xlat_cut_block( xlat_new_create_ptr, destsize );13.464 -}13.465 -13.466 -void xlat_delete_block( xlat_cache_block_t block )13.467 -{13.468 - block->active = 0;13.469 - *block->lut_entry = NULL;13.470 -}13.471 -13.472 -void xlat_check_cache_integrity( xlat_cache_block_t cache, xlat_cache_block_t ptr, int size )13.473 -{13.474 - int foundptr = 0;13.475 - xlat_cache_block_t tail =13.476 - (xlat_cache_block_t)(((char *)cache) + size - sizeof(struct xlat_cache_block));13.477 -13.478 - assert( tail->active == 1 );13.479 - assert( tail->size == 0 );13.480 - while( cache < tail ) {13.481 - assert( cache->active >= 0 && cache->active <= 2 );13.482 - assert( cache->size >= 0 && cache->size < size );13.483 - if( cache == ptr ) {13.484 - foundptr = 1;13.485 - }13.486 - cache = NEXT(cache);13.487 - }13.488 - assert( cache == tail );13.489 - assert( foundptr == 1 || tail == ptr );13.490 -}13.491 -13.492 -void xlat_check_integrity( )13.493 -{13.494 - xlat_check_cache_integrity( xlat_new_cache, xlat_new_cache_ptr, XLAT_NEW_CACHE_SIZE );13.495 -#ifdef XLAT_GENERATIONAL_CACHE13.496 - xlat_check_cache_integrity( xlat_temp_cache, xlat_temp_cache_ptr, XLAT_TEMP_CACHE_SIZE );13.497 - xlat_check_cache_integrity( xlat_old_cache, xlat_old_cache_ptr, XLAT_OLD_CACHE_SIZE );13.498 -#endif13.499 -}13.500 -
14.1 --- a/src/sh4/xltcache.h Wed Mar 04 23:04:54 2009 +000014.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +000014.3 @@ -1,176 +0,0 @@14.4 -/**14.5 - * $Id$14.6 - *14.7 - * Translation cache support (architecture independent)14.8 - *14.9 - * Copyright (c) 2005 Nathan Keynes.14.10 - *14.11 - * This program is free software; you can redistribute it and/or modify14.12 - * it under the terms of the GNU General Public License as published by14.13 - * the Free Software Foundation; either version 2 of the License, or14.14 - * (at your option) any later version.14.15 - *14.16 - * This program is distributed in the hope that it will be useful,14.17 - * but WITHOUT ANY WARRANTY; without even the implied warranty of14.18 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the14.19 - * GNU General Public License for more details.14.20 - */14.21 -14.22 -#include "dream.h"14.23 -#include "mem.h"14.24 -14.25 -#ifndef lxdream_xltcache_H14.26 -#define lxdream_xltcache_H 114.27 -14.28 -/**14.29 - * For now, recovery is purely a matter of mapping native pc => sh4 pc,14.30 - * and updating sh4r.pc & sh4r.slice_cycles accordingly. In future more14.31 - * detailed recovery may be required if the translator optimizes more14.32 - * agressively.14.33 - *14.34 - * The recovery table contains (at least) one entry per abortable instruction,14.35 - *14.36 - */14.37 -typedef struct xlat_recovery_record {14.38 - uint32_t xlat_offset; // native (translated) pc14.39 - uint32_t sh4_icount; // instruction number of the corresponding SH4 instruction14.40 - // (0 = first instruction, 1 = second instruction, ... )14.41 -} *xlat_recovery_record_t;14.42 -14.43 -struct xlat_cache_block {14.44 - int active; /* 0 = deleted, 1 = normal. 2 = accessed (temp-space only) */14.45 - uint32_t size;14.46 - void **lut_entry; /* For deletion */14.47 - uint32_t xlat_sh4_mode; /* comparison with sh4r.xlat_sh4_mode */14.48 - uint32_t recover_table_offset; // Offset from code[0] of the recovery table;14.49 - uint32_t recover_table_size;14.50 - unsigned char code[0];14.51 -} __attribute__((packed));14.52 -14.53 -typedef struct xlat_cache_block *xlat_cache_block_t;14.54 -14.55 -#define XLAT_BLOCK_FOR_CODE(code) (((xlat_cache_block_t)code)-1)14.56 -14.57 -#define XLAT_BLOCK_MODE(code) (XLAT_BLOCK_FOR_CODE(code)->xlat_sh4_mode)14.58 -14.59 -/**14.60 - * Initialize the translation cache14.61 - */14.62 -void xlat_cache_init(void);14.63 -14.64 -/**14.65 - * Returns the next block in the new cache list that can be written to by the14.66 - * translator.14.67 - */14.68 -xlat_cache_block_t xlat_start_block(sh4addr_t address);14.69 -14.70 -/**14.71 - * Increases the current block size (only valid between calls to xlat_start_block()14.72 - * and xlat_commit_block()).14.73 - * @return the new block, which may be different from the old block.14.74 - */14.75 -xlat_cache_block_t xlat_extend_block( uint32_t newSize );14.76 -14.77 -/**14.78 - * Commit the current translation block14.79 - * @param addr target address (for the lookup table)14.80 - * @param destsize final size of the translation in bytes.14.81 - * @param srcsize size of the original data that was translated in bytes14.82 - */14.83 -void xlat_commit_block( uint32_t destsize, uint32_t srcsize );14.84 -14.85 -/**14.86 - * Dump the disassembly of the specified code block to a stream14.87 - * (primarily for debugging purposes)14.88 - * @param out The stream to write the output to14.89 - * @param code a translated block14.90 - */14.91 -void xlat_disasm_block( FILE *out, void *code );14.92 -14.93 -14.94 -/**14.95 - * Delete (deactivate) the specified block from the cache. Caller is responsible14.96 - * for ensuring that there really is a block there.14.97 - */14.98 -void xlat_delete_block( xlat_cache_block_t block );14.99 -14.100 -/**14.101 - * Retrieve the entry point for the translated code corresponding to the given14.102 - * SH4 address, or NULL if there is no code for that address.14.103 - */14.104 -void * FASTCALL xlat_get_code( sh4addr_t address );14.105 -14.106 -/**14.107 - * Retrieve the pre-instruction recovery record corresponding to the given14.108 - * native address, or NULL if there is no recovery code for the address.14.109 - * @param code The code block containing the recovery table.14.110 - * @param native_pc A pointer that must be within the currently executing14.111 - * return the first record before or equal to the given pc.14.112 - * translation block.14.113 - */14.114 -struct xlat_recovery_record *xlat_get_pre_recovery( void *code, void *native_pc );14.115 -14.116 -14.117 -/**14.118 - * Retrieve the entry point for the translated code corresponding to the given14.119 - * SH4 virtual address, or NULL if there is no code for the address.14.120 - * If the virtual address cannot be resolved, this method will raise a TLB miss14.121 - * exception, and return NULL.14.122 - */14.123 -void * FASTCALL xlat_get_code_by_vma( sh4vma_t address );14.124 -14.125 -/**14.126 - * Retrieve the address of the lookup table entry corresponding to the14.127 - * given SH4 address.14.128 - */14.129 -void ** FASTCALL xlat_get_lut_entry( sh4addr_t address );14.130 -14.131 -/**14.132 - * Retrieve the current host address of the running translated code block.14.133 - * @return the host PC, or null if there is no currently executing translated14.134 - * block (or the stack is corrupted)14.135 - * Note: the implementation of this method is host (and calling-convention) specific.14.136 - * @param block_start start of the block the PC should be in14.137 - * @param block_size size of the code block in bytes.14.138 - */14.139 -void *xlat_get_native_pc( void *block_start, uint32_t block_size );14.140 -14.141 -/**14.142 - * Retrieve the size of the block starting at the specified pointer. If the14.143 - * pointer is not a valid code block, the return value is undefined.14.144 - */14.145 -uint32_t FASTCALL xlat_get_block_size( void *ptr );14.146 -14.147 -/**14.148 - * Retrieve the size of the code in the block starting at the specified14.149 - * pointer. Effectively this is xlat_get_block_size() minus the size of14.150 - * the recovery table. If the pointer is not a valid code block, the14.151 - * return value is undefined.14.152 - */14.153 -uint32_t FASTCALL xlat_get_code_size( void *ptr );14.154 -14.155 -/**14.156 - * Flush the code cache for the page containing the given address14.157 - */14.158 -void FASTCALL xlat_flush_page( sh4addr_t address );14.159 -14.160 -void FASTCALL xlat_invalidate_word( sh4addr_t address );14.161 -void FASTCALL xlat_invalidate_long( sh4addr_t address );14.162 -14.163 -14.164 -/**14.165 - * Invalidate the code cache for a memory region14.166 - */14.167 -void FASTCALL xlat_invalidate_block( sh4addr_t address, size_t bytes );14.168 -14.169 -/**14.170 - * Flush the entire code cache. This isn't as cheap as one might like14.171 - */14.172 -void xlat_flush_cache();14.173 -14.174 -/**14.175 - * Check the internal integrity of the cache14.176 - */14.177 -void xlat_check_integrity();14.178 -14.179 -#endif /* lxdream_xltcache_H */
15.1 --- a/src/test/testxlt.c Wed Mar 04 23:04:54 2009 +000015.2 +++ b/src/test/testxlt.c Wed Mar 04 23:12:21 2009 +000015.3 @@ -17,7 +17,7 @@15.4 */15.6 #include <assert.h>15.7 -#include "sh4/xltcache.h"15.8 +#include "xlat/xltcache.h"15.9 #include "dreamcast.h"15.11 extern xlat_cache_block_t xlat_new_cache;
16.1 --- /dev/null Thu Jan 01 00:00:00 1970 +000016.2 +++ b/src/xlat/x86/x86op.h Wed Mar 04 23:12:21 2009 +000016.3 @@ -0,0 +1,768 @@16.4 +/**16.5 + * $Id$16.6 + *16.7 + * x86/x86-64 Instruction generation macros16.8 + *16.9 + * Copyright (c) 2009 Nathan Keynes.16.10 + *16.11 + * This program is free software; you can redistribute it and/or modify16.12 + * it under the terms of the GNU General Public License as published by16.13 + * the Free Software Foundation; either version 2 of the License, or16.14 + * (at your option) any later version.16.15 + *16.16 + * This program is distributed in the hope that it will be useful,16.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of16.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the16.19 + * GNU General Public License for more details.16.20 + */16.21 +#include <stdint.h>16.22 +#include <assert.h>16.23 +16.24 +/******************************** Constants *****************************/16.25 +16.26 +#define REG_NONE -116.27 +16.28 +/* 64-bit general-purpose regs */16.29 +#define REG_RAX 016.30 +#define REG_RCX 116.31 +#define REG_RDX 216.32 +#define REG_RBX 316.33 +#define REG_RSP 416.34 +#define REG_RBP 516.35 +#define REG_RSI 616.36 +#define REG_RDI 716.37 +#define REG_R8 816.38 +#define REG_R9 916.39 +#define REG_R10 1016.40 +#define REG_R11 1116.41 +#define REG_R12 1216.42 +#define REG_R13 1316.43 +#define REG_R14 1416.44 +#define REG_R15 1516.45 +16.46 +/* 32-bit general-purpose regs */16.47 +#define REG_EAX 016.48 +#define REG_ECX 116.49 +#define REG_EDX 216.50 +#define REG_EBX 316.51 +#define REG_ESP 416.52 +#define REG_EBP 516.53 +#define REG_ESI 616.54 +#define REG_EDI 716.55 +#define REG_R8D 816.56 +#define REG_R9D 916.57 +#define REG_R10D 1016.58 +#define REG_R11D 1116.59 +#define REG_R12D 1216.60 +#define REG_R13D 1316.61 +#define REG_R14D 1416.62 +#define REG_R15D 1516.63 +16.64 +/* 8-bit general-purpose regs (no-rex prefix) */16.65 +#define REG_AL 016.66 +#define REG_CL 116.67 +#define REG_DL 216.68 +#define REG_BL 316.69 +#define REG_AH 416.70 +#define REG_CH 516.71 +#define REG_DH 616.72 +#define REG_BH 716.73 +16.74 +/* 8-bit general-purpose regs (rex-prefix) */16.75 +#define REG_SPL 416.76 +#define REG_BPL 516.77 +#define REG_SIL 616.78 +#define REG_DIL 716.79 +#define REG_R8L 816.80 +#define REG_R9L 916.81 +#define REG_R10L 1016.82 +#define REG_R11L 1116.83 +#define REG_R12L 1216.84 +#define REG_R13L 1316.85 +#define REG_R14L 1416.86 +#define REG_R15L 1516.87 +16.88 +/* Condition flag variants */16.89 +#define X86_COND_O 0x00 /* OF=1 */16.90 +#define X86_COND_NO 0x01 /* OF=0 */16.91 +#define X86_COND_B 0x02 /* CF=1 */16.92 +#define X86_COND_C 0x02 /* CF=1 */16.93 +#define X86_CONF_NAE 0x02 /* CF=1 */16.94 +#define X86_COND_AE 0x03 /* CF=0 */16.95 +#define X86_COND_NB 0x03 /* CF=0 */16.96 +#define X86_COND_NC 0x03 /* CF=0 */16.97 +#define X86_COND_E 0x04 /* ZF=1 */16.98 +#define X86_COND_Z 0x04 /* ZF=1 */16.99 +#define X86_COND_NE 0x05 /* ZF=0 */16.100 +#define X86_COND_NZ 0x05 /* ZF=0 */16.101 +#define X86_COND_BE 0x06 /* CF=1 || ZF=1 */16.102 +#define X86_COND_NA 0x06 /* CF=1 || ZF=1 */16.103 +#define X86_COND_A 0x07 /* CF=0 && ZF=0 */16.104 +#define X86_COND_NBE 0x07 /* CF=0 && ZF=0 */16.105 +#define X86_COND_S 0x08 /* SF=1 */16.106 +#define X86_COND_NS 0x09 /* SF=0 */16.107 +#define X86_COND_P 0x0A /* PF=1 */16.108 +#define X86_COND_PE 0x0A /* PF=1 */16.109 +#define X86_COND_NP 0x0B /* PF=0 */16.110 +#define X86_COND_PO 0x0B /* PF=0 */16.111 +#define X86_COND_L 0x0C /* SF!=OF */16.112 +#define X86_COND_NGE 0x0C /* SF!=OF */16.113 +#define X86_COND_GE 0x0D /* SF=OF */16.114 +#define X86_COND_NL 0x0D /* SF=OF */16.115 +#define X86_COND_LE 0x0E /* ZF=1 || SF!=OF */16.116 +#define X86_COND_NG 0x0E /* ZF=1 || SF!=OF */16.117 +#define X86_COND_G 0x0F /* ZF=0 && SF=OF */16.118 +#define X86_COND_NLE 0x0F /* ZF=0 && SF=OF */16.119 +16.120 +/* SSE floating pointer comparison variants */16.121 +#define SSE_CMP_EQ 0x0016.122 +#define SSE_CMP_LT 0x0116.123 +#define SSE_CMP_LE 0x0216.124 +#define SSE_CMP_UNORD 0x0316.125 +#define SSE_CMP_NE 0x0416.126 +#define SSE_CMP_NLT 0x0516.127 +#define SSE_CMP_NLE 0x0616.128 +#define SSE_CMP_ORD 0x0716.129 +16.130 +/************************** Internal definitions ***************************/16.131 +#define PREF_REXB 0x4116.132 +#define PREF_REXX 0x4216.133 +#define PREF_REXR 0x4416.134 +#define PREF_REXW 0x4816.135 +16.136 +extern unsigned char *xlat_output;16.137 +16.138 +#define OP(x) *xlat_output++ = (x)16.139 +#define OP16(x) *((uint16_t *)xlat_output) = (x); xlat_output+=216.140 +#define OP32(x) *((uint32_t *)xlat_output) = (x); xlat_output+=416.141 +#define OP64(x) *((uint64_t *)xlat_output) = (x); xlat_output+=816.142 +#define OPPTR(x) *((void **)xlat_output) = ((void *)x); xlat_output+=(sizeof(void*))16.143 +16.144 +/* Primary opcode emitter, eg OPCODE(0x0FBE) for MOVSX */16.145 +#define OPCODE(x) if( (x) > 0xFFFF ) { OP(x>>16); OP((x>>8)&0xFF); OP(x&0xFF); } else if( (x) > 0xFF ) { OP(x>>8); OP(x&0xFF); } else { OP(x); }16.146 +16.147 +/* Test if immediate value is representable as a signed 8-bit integer */16.148 +#define IS_INT8(imm) ((imm) >= INT8_MIN && (imm) <= INT8_MAX)16.149 +16.150 +/**16.151 + * Encode opcode+reg with no mod/rm (eg MOV imm64, r32)16.152 + */16.153 +static void x86_encode_opcodereg( int rexw, uint32_t opcode, int reg )16.154 +{16.155 + int rex = rexw;16.156 + reg &= 0x0F;16.157 + if( reg >= 8 ) {16.158 + rex |= PREF_REXB;16.159 + reg -= 8;16.160 + }16.161 + if( rex != 0 ) {16.162 + OP(rex);16.163 + }16.164 + OPCODE(opcode + reg);16.165 +}16.166 +16.167 +/**16.168 + * Encode opcode with mod/rm reg-reg operation.16.169 + * @param opcode primary instruction opcode16.170 + * @param rr reg field16.171 + * @param rb r/m field16.172 + */16.173 +static int x86_encode_reg_rm( int rexw, uint32_t opcode, int rr, int rb )16.174 +{16.175 + int rex = rexw;16.176 + rr &= 0x0F;16.177 + rb &= 0x0F;16.178 + if( rr >= 8 ) {16.179 + rex |= PREF_REXR;16.180 + rr -= 8;16.181 + }16.182 + if( rb >= 8 ) {16.183 + rex |= PREF_REXB;16.184 + rb -= 8;16.185 + }16.186 + if( rex != 0 ) {16.187 + OP(rex);16.188 + }16.189 + OPCODE(opcode);16.190 + OP(0xC0|(rr<<3)|rb);16.191 +}16.192 +16.193 +/**16.194 + * Encode opcode + 32-bit mod/rm memory address. (RIP-relative not supported here)16.195 + * @param rexw REX.W prefix is required, otherwise 016.196 + * @param rr Reg-field register (required).16.197 + * @param rb Base (unscaled) register, or -1 for no base register.16.198 + * @param rx Index (scaled) register, or -1 for no index register16.199 + * @param ss Scale shift (0..3) applied to index register (ignored if no index register)16.200 + * @param disp32 Signed displacement (0 for none)16.201 + */16.202 +static void x86_encode_modrm( int rexw, uint32_t opcode, int rr, int rb, int rx, int ss, int32_t disp32 )16.203 +{16.204 + /* Construct the rex prefix where necessary */16.205 + int rex = rexw;16.206 + rr &= 0x0F;16.207 + if( rr >= 8 ) {16.208 + rex |= PREF_REXR;16.209 + rr -= 8;16.210 + }16.211 + if( rb != -1 ) {16.212 + rb &= 0x0F;16.213 + if( rb >= 8 ) {16.214 + rex |= PREF_REXB;16.215 + rb -= 8;16.216 + }16.217 + }16.218 + if( rx != -1 ) {16.219 + rx &= 0x0F;16.220 + if( rx >= 8 ) {16.221 + rex |= PREF_REXX;16.222 + rx -= 8;16.223 + }16.224 + }16.225 +16.226 + if( rex != 0 ) {16.227 + OP(rex);16.228 + }16.229 + OPCODE(opcode);16.230 +16.231 + if( rx == -1 ) {16.232 + if( rb == -1 ) {16.233 + /* [disp32] displacement only - use SIB form for 64-bit mode safety */16.234 + OP(0x04|(rr<<3));16.235 + OP(0x25);16.236 + OP32(disp32);16.237 + } else if( rb == REG_ESP ) { /* [%esp + disp32] - SIB is mandatory for %esp/%r12 encodings */16.238 + if( disp32 == 0 ) {16.239 + OP(0x04|(rr<<3));16.240 + OP(0x24);16.241 + } else if( IS_INT8(disp32) ) {16.242 + OP(0x44|(rr<<3));16.243 + OP(0x24);16.244 + OP((int8_t)disp32);16.245 + } else {16.246 + OP(0x84|(rr<<3));16.247 + OP(0x24);16.248 + OP32(disp32);16.249 + }16.250 + } else {16.251 + if( disp32 == 0 && rb != REG_EBP ) { /* [%ebp] is encoded as [%ebp+0] */16.252 + OP((rr<<3)|rb);16.253 + } else if( IS_INT8(disp32) ) {16.254 + OP(0x40|(rr<<3)|rb);16.255 + OP((int8_t)disp32);16.256 + } else {16.257 + OP(0x80|(rr<<3)|rb);16.258 + OP32(disp32);16.259 + }16.260 + }16.261 + } else { /* We have a scaled index. Goody */16.262 + assert( ((rx != REG_ESP) || (rex&PREF_REXX)) && "Bug: attempt to index through %esp" ); /* Indexing by %esp is impossible */16.263 + if( rb == -1 ) { /* [disp32 + rx << ss] */16.264 + OP(0x04|(rr<<3));16.265 + OP(0x05|(ss<<6)|(rx<<3));16.266 + OP32(disp32);16.267 + } else if( disp32 == 0 && rb != REG_EBP ) { /* [rb + rx << ss]. (Again, %ebp needs to be %ebp+0) */16.268 + OP(0x04|(rr<<3));16.269 + OP((ss<<6)|(rx<<3)|rb);16.270 + } else if( IS_INT8(disp32) ) {16.271 + OP(0x44|(rr<<3));16.272 + OP((ss<<6)|(rx<<3)|rb);16.273 + OP((int8_t)disp32);16.274 + } else {16.275 + OP(0x84|(rr<<3));16.276 + OP((ss<<6)|(rx<<3)|rb);16.277 + OP32(disp32);16.278 + }16.279 + }16.280 +}16.281 +16.282 +/**16.283 + * Encode opcode + RIP-relative mod/rm (64-bit mode only)16.284 + * @param rexw PREF_REXW or 016.285 + * @param opcode primary instruction opcode16.286 + * @param rr mod/rm reg field16.287 + * @param disp32 RIP-relative displacement16.288 + */16.289 +static void x86_encode_modrm_rip(int rexw, uint32_t opcode, int rr, int32_t disp32)16.290 +{16.291 + int rex = rexw;16.292 + rr &= 0x0F;16.293 + if( rr >= 8 ) {16.294 + rex |= PREF_REXR;16.295 + rr -= 8;16.296 + }16.297 + if( rex != 0 ) {16.298 + OP(rex);16.299 + }16.300 + OPCODE(opcode);16.301 + OP(0x05|(rr<<3));16.302 + OP32(disp32);16.303 +}16.304 +16.305 +/* 32/64-bit op emitters. 64-bit versions include a rex.w prefix. Note that any16.306 + * other prefixes (mandatory or otherwise) need to be emitted prior to these16.307 + * functions16.308 + */16.309 +#define x86_encode_opcode64(opcode,reg) x86_encode_opcodereg(PREF_REXW, opcode,reg)16.310 +#define x86_encode_opcode32(opcode,reg) x86_encode_opcodereg(0,opcode,reg)16.311 +#define x86_encode_r32_rm32(opcode,rr,rb) x86_encode_reg_rm(0,opcode,rr,rb)16.312 +#define x86_encode_r64_rm64(opcode,rr,rb) x86_encode_reg_rm(PREF_REXW,opcode,rr,rb)16.313 +#define x86_encode_r32_mem32(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(0,opcode,rr,rb,rx,ss,disp32)16.314 +#define x86_encode_r64_mem64(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,rx,ss,disp32)16.315 +#define x86_encode_rptr_memptr(opcode,rr,rb,rx,ss,disp32) x86_encode_modrm( (sizeof(void *)==8) ? PREF_REXW : 0,opcode,rr,rb,rx,ss,disp32)16.316 +#define x86_encode_r32_mem32disp32(opcode,rr,rb,disp32) x86_encode_modrm(0,opcode,rr,rb,-1,0,disp32)16.317 +#define x86_encode_r64_mem64disp64(opcode,rr,rb,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,rb,-1,0,disp32)16.318 +#define x86_encode_r32_ripdisp32(opcode,rr,disp32) x86_encode_modrm_rip(0,opcode,rr,disp32)16.319 +#define x86_encode_r64_ripdisp64(opcode,rr,disp32) x86_encode_modrm_rip(PREF_REXW,opcode,rr,disp32)16.320 +16.321 +/* Convenience versions for the common rbp/rsp relative displacements */16.322 +#define x86_encode_r32_rbpdisp32(opcode,rr,disp32) x86_encode_modrm(0,opcode,rr,REG_RBP,-1,0,disp32)16.323 +#define x86_encode_r64_rbpdisp64(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RBP,-1,0,disp32)16.324 +#define x86_encode_r32_rspdisp32(opcode,rr,disp32) x86_encode_modrm(0,opcode,rr,REG_RSP,-1,0,disp32)16.325 +#define x86_encode_r64_rspdisp64(opcode,rr,disp32) x86_encode_modrm(PREF_REXW,opcode,rr,REG_RSP,-1,0,disp32)16.326 +16.327 +/* Immediate-selection variants (for instructions with imm8s/imm32 variants) */16.328 +#define x86_encode_imms_rm32(opcode8,opcode32,reg,imm,rb) \16.329 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_rm32(opcode8,reg,rb); OP((int8_t)imm); \16.330 + } else { x86_encode_r32_rm32(opcode32,reg,rb); OP32(imm); }16.331 +#define x86_encode_imms_rm64(opcode8,opcode32,reg,imm,rb) \16.332 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r64_rm64(opcode8,reg,rb); OP((int8_t)imm); \16.333 + } else { x86_encode_r64_rm64(opcode32,reg,rb); OP32(imm); }16.334 +#define x86_encode_imms_rbpdisp32(opcode8,opcode32,reg,imm,disp) \16.335 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_rbpdisp32(opcode8,reg,disp); OP((int8_t)imm); \16.336 + } else { x86_encode_r32_rbpdisp32(opcode32,reg,disp); OP32(imm); }16.337 +#define x86_encode_imms_r32disp32(opcode8,opcode32,reg,imm,rb,disp) \16.338 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r32_mem32disp32(opcode8,reg,rb,disp); OP((int8_t)imm); \16.339 + } else { x86_encode_r32_mem32disp32(opcode32,reg,rb,disp); OP32(imm); }16.340 +#define x86_encode_imms_rbpdisp64(opcode8,opcode32,reg,imm,disp) \16.341 + if( IS_INT8(((int32_t)imm)) ) { x86_encode_r64_rbpdisp64(opcode8,reg,disp); OP((int8_t)imm); \16.342 + } else { x86_encode_r64_rbpdisp64(opcode32,reg,disp); OP32(imm); }16.343 +16.344 +/*************************** Instruction definitions ***********************/16.345 +/* Note this does not try to be an exhaustive definition of the instruction -16.346 + * it generally only has the forms that we actually need here.16.347 + */16.348 +/* Core Integer instructions */16.349 +#define ADCB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 2, r1); OP(imm)16.350 +#define ADCB_r8_r8(r1,r2) x86_encode_r32_rm32(0x10, r1, r2)16.351 +#define ADCL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 2, imm, r1)16.352 +#define ADCL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 2, imm, disp)16.353 +#define ADCL_r32_r32(r1,r2) x86_encode_r32_rm32(0x11, r1, r2)16.354 +#define ADCL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x11, r1, disp)16.355 +#define ADCL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x13, r1, disp)16.356 +#define ADCQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 2, imm, r1)16.357 +#define ADCQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x11, r1, r2)16.358 +16.359 +#define ADDB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 0, r1); OP(imm)16.360 +#define ADDB_r8_r8(r1,r2) x86_encode_r32_rm32(0x00, r1, r2)16.361 +#define ADDL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 0, imm, r1)16.362 +#define ADDL_imms_r32disp(imm,rb,d) x86_encode_imms_r32disp32(0x83, 0x81, 0, imm, rb, d)16.363 +#define ADDL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 0, imm, disp)16.364 +#define ADDL_r32_r32(r1,r2) x86_encode_r32_rm32(0x01, r1, r2)16.365 +#define ADDL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x01, r1, disp)16.366 +#define ADDL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x01, r1, r2, dsp)16.367 +#define ADDL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x03, r1, disp)16.368 +#define ADDQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 0, imm, r1)16.369 +#define ADDQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x01, r1, r2)16.370 +16.371 +#define ANDB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 4, r1); OP(imm)16.372 +#define ANDB_r8_r8(r1,r2) x86_encode_r32_rm32(0x20, r1, r2)16.373 +#define ANDL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 4, imm, r1)16.374 +#define ANDL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,4,imm,disp)16.375 +#define ANDL_r32_r32(r1,r2) x86_encode_r32_rm32(0x21, r1, r2)16.376 +#define ANDL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x21, r1, disp)16.377 +#define ANDL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x23, r1, disp)16.378 +#define ANDQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x21, r1, r2)16.379 +#define ANDQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 4, imm, r1)16.380 +16.381 +#define CLC() OP(0xF8)16.382 +#define CLD() OP(0xFC)16.383 +#define CMC() OP(0xF5)16.384 +16.385 +#define CMOVCCL_cc_r32_r32(cc,r1,r2) x86_encode_r32_rm32(0x0F40+(cc), r2, r1)16.386 +#define CMOVCCL_cc_rbpdisp_r32(cc,d,r1) x86_encode_r32_rbpdisp32(0x0F40+(cc), r1, d)16.387 +16.388 +#define CMPB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 7, r1); OP(imm)16.389 +#define CMPB_imms_rbpdisp(imm,disp) x86_encode_r32_rbpdisp32(0x80, 7, disp); OP(imm)16.390 +#define CMPB_r8_r8(r1,r2) x86_encode_r32_rm32(0x38, r1, r2)16.391 +#define CMPL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 7, imm, r1)16.392 +#define CMPL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83, 0x81, 7, imm, disp)16.393 +#define CMPL_r32_r32(r1,r2) x86_encode_r32_rm32(0x39, r1, r2)16.394 +#define CMPL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x39, r1, disp)16.395 +#define CMPL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x3B, r1, disp)16.396 +#define CMPQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 7, imm, r1)16.397 +#define CMPQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x39, r1, r2)16.398 +16.399 +#define IDIVL_r32(r1) x86_encode_r32_rm32(0xF7, 7, r1)16.400 +#define IDIVL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 7, disp)16.401 +#define IDIVQ_r64(r1) x86_encode_r64_rm64(0xF7, 7, r1)16.402 +16.403 +#define IMULL_imms_r32(imm,r1) x86_encode_imms_rm32(0x6B,0x69, r1, imm, r1)16.404 +#define IMULL_r32(r1) x86_encode_r32_rm32(0xF7, 5, r1)16.405 +#define IMULL_r32_r32(r1,r2) x86_encode_r32_rm32(0x0FAF, r2, r1)16.406 +#define IMULL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7, 5, disp)16.407 +#define IMULL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FAF, r1, disp)16.408 +#define IMULL_rspdisp(disp) x86_encode_r32_rspdisp32(0xF7, 5, disp)16.409 +#define IMULL_rspdisp_r32(disp,r1) x86_encode_r32_rspdisp32(0x0FAF, r1, disp)16.410 +#define IMULQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x6B,0x69, r1, imm, r1)16.411 +#define IMULQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x0FAF, r2, r1)16.412 +16.413 +#define LEAL_r32disp_r32(r1,disp,r2) x86_encode_r32_mem32(0x8D, r2, r1, -1, 0, disp)16.414 +#define LEAL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x8D, r1, disp)16.415 +#define LEAL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8D, r1, bb, ii, ss, d)16.416 +#define LEAQ_r64disp_r64(r1,disp,r2) x86_encode_r64_mem64(0x8D, r2, r1, -1, 0, disp)16.417 +#define LEAQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8D, r1, disp)16.418 +#define LEAP_rptrdisp_rptr(r1,d,r2) x86_encode_rptr_memptr(0x8D, r2, r1, -1, 0, disp)16.419 +#define LEAP_rbpdisp_rptr(disp,r1) x86_encode_rptr_memptr(0x8D, r1, REG_RBP, -1, 0, disp)16.420 +#define LEAP_sib_rptr(ss,ii,bb,d,r1) x86_encode_rptr_memptr(0x8D, r1, bb, ii, ss, d)16.421 +16.422 +#define MOVB_r8_r8(r1,r2) x86_encode_r32_rm32(0x88, r1, r2)16.423 +#define MOVL_imm32_r32(i32,r1) x86_encode_opcode32(0xB8, r1); OP32(i32)16.424 +#define MOVL_imm32_rbpdisp(i,disp) x86_encode_r32_rbpdisp32(0xC7,0,disp); OP32(i)16.425 +#define MOVL_imm32_rspdisp(i,disp) x86_encode_r32_rspdisp32(0xC7,0,disp); OP32(i)16.426 +#define MOVL_moffptr_eax(p) OP(0xA1); OPPTR(p)16.427 +#define MOVL_r32_r32(r1,r2) x86_encode_r32_rm32(0x89, r1, r2)16.428 +#define MOVL_r32_r32disp(r1,r2,dsp) x86_encode_r32_mem32disp32(0x89, r1, r2, dsp)16.429 +#define MOVL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x89, r1, disp)16.430 +#define MOVL_r32_rspdisp(r1,disp) x86_encode_r32_rspdisp32(0x89, r1, disp)16.431 +#define MOVL_r32_sib(r1,ss,ii,bb,d) x86_encode_r32_mem32(0x89, r1, bb, ii, ss, d)16.432 +#define MOVL_r32disp_r32(r1,dsp,r2) x86_encode_r32_mem32disp32(0x8B, r2, r1, dsp)16.433 +#define MOVL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x8B, r1, disp)16.434 +#define MOVL_rspdisp_r32(disp,r1) x86_encode_r32_rspdisp32(0x8B, r1, disp)16.435 +#define MOVL_sib_r32(ss,ii,bb,d,r1) x86_encode_r32_mem32(0x8B, r1, bb, ii, ss, d)16.436 +#define MOVQ_imm64_r64(i64,r1) x86_encode_opcode64(0xB8, r1); OP64(i64)16.437 +#define MOVQ_moffptr_rax(p) OP(PREF_REXW); OP(0xA1); OPPTR(p)16.438 +#define MOVQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x89, r1, r2)16.439 +#define MOVQ_r64_rbpdisp(r1,disp) x86_encode_r64_rbpdisp64(0x89, r1, disp)16.440 +#define MOVQ_r64_rspdisp(r1,disp) x86_encode_r64_rspdisp64(0x89, r1, disp)16.441 +#define MOVQ_rbpdisp_r64(disp,r1) x86_encode_r64_rbpdisp64(0x8B, r1, disp)16.442 +#define MOVQ_rspdisp_r64(disp,r1) x86_encode_r64_rspdisp64(0x8B, r1, disp)16.443 +#define MOVP_immptr_rptr(p,r1) x86_encode_opcodereg( (sizeof(void*)==8 ? PREF_REXW : 0), 0xB8, r1); OPPTR(p)16.444 +#define MOVP_moffptr_rax(p) if( sizeof(void*)==8 ) { OP(PREF_REXW); } OP(0xA1); OPPTR(p)16.445 +#define MOVP_sib_rptr(ss,ii,bb,d,r1) x86_encode_rptr_memptr(0x8B, r1, bb, ii, ss, d)16.446 +16.447 +#define MOVSXL_r8_r32(r1,r2) x86_encode_r32_rm32(0x0FBE, r2, r1)16.448 +#define MOVSXL_r16_r32(r1,r2) x86_encode_r32_rm32(0x0FBF, r2, r1)16.449 +#define MOVSXL_rbpdisp8_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FBE, r1, disp)16.450 +#define MOVSXL_rbpdisp16_r32(dsp,r1) x86_encode_r32_rbpdisp32(0x0FBF, r1, dsp)16.451 +#define MOVSXQ_imm32_r64(i32,r1) x86_encode_r64_rm64(0xC7, 0, r1); OP32(i32) /* Technically a MOV */16.452 +#define MOVSXQ_r8_r64(r1,r2) x86_encode_r64_rm64(0x0FBE, r2, r1)16.453 +#define MOVSXQ_r16_r64(r1,r2) x86_encode_r64_rm64(0x0FBF, r2, r1)16.454 +#define MOVSXQ_r32_r64(r1,r2) x86_encode_r64_rm64(0x63, r2, r1)16.455 +#define MOVSXQ_rbpdisp32_r64(dsp,r1) x86_encode_r64_rbpdisp64(0x63, r1, dsp)16.456 +16.457 +#define MOVZXL_r8_r32(r1,r2) x86_encode_r32_rm32(0x0FB6, r2, r1)16.458 +#define MOVZXL_r16_r32(r1,r2) x86_encode_r32_rm32(0x0FB7, r2, r1)16.459 +#define MOVZXL_rbpdisp8_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0FB6, r1, disp)16.460 +#define MOVZXL_rbpdisp16_r32(dsp,r1) x86_encode_r32_rbpdisp32(0x0FB7, r1, dsp)16.461 +16.462 +#define MULL_r32(r1) x86_encode_r32_rm32(0xF7, 4, r1)16.463 +#define MULL_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xF7,4,disp)16.464 +#define MULL_rspdisp(disp) x86_encode_r32_rspdisp32(0xF7,4,disp)16.465 +16.466 +#define NEGB_r8(r1) x86_encode_r32_rm32(0xF6, 3, r1)16.467 +#define NEGL_r32(r1) x86_encode_r32_rm32(0xF7, 3, r1)16.468 +#define NEGL_rbpdisp(r1) x86_encode_r32_rbspdisp32(0xF7, 3, disp)16.469 +#define NEGQ_r64(r1) x86_encode_r64_rm64(0xF7, 3, r1)16.470 +16.471 +#define NOTB_r8(r1) x86_encode_r32_rm32(0xF6, 2, r1)16.472 +#define NOTL_r32(r1) x86_encode_r32_rm32(0xF7, 2, r1)16.473 +#define NOTL_rbpdisp(r1) x86_encode_r32_rbspdisp32(0xF7, 2, disp)16.474 +#define NOTQ_r64(r1) x86_encode_r64_rm64(0xF7, 2, r1)16.475 +16.476 +#define ORB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 1, r1); OP(imm)16.477 +#define ORB_r8_r8(r1,r2) x86_encode_r32_rm32(0x08, r1, r2)16.478 +#define ORL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 1, imm, r1)16.479 +#define ORL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,1,imm,disp)16.480 +#define ORL_r32_r32(r1,r2) x86_encode_r32_rm32(0x09, r1, r2)16.481 +#define ORL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x09, r1, disp)16.482 +#define ORL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x0B, r1, disp)16.483 +#define ORQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 1, imm, r1)16.484 +#define ORQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x09, r1, r2)16.485 +16.486 +#define POP_r32(r1) x86_encode_opcode32(0x58, r1)16.487 +16.488 +#define PUSH_imm32(imm) OP(0x68); OP32(imm)16.489 +#define PUSH_r32(r1) x86_encode_opcode32(0x50, r1)16.490 +16.491 +#define RCLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,2,r1)16.492 +#define RCLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,2,r1); } else { x86_encode_r32_rm32(0xC1,2,r1); OP(imm); }16.493 +#define RCLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,2,r1)16.494 +#define RCLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,2,r1); } else { x86_encode_r64_rm64(0xC1,2,r1); OP(imm); }16.495 +#define RCRL_cl_r32(r1) x86_encode_r32_rm32(0xD3,3,r1)16.496 +#define RCRL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,3,r1); } else { x86_encode_r32_rm32(0xC1,3,r1); OP(imm); }16.497 +#define RCRQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,3,r1)16.498 +#define RCRQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,3,r1); } else { x86_encode_r64_rm64(0xC1,3,r1); OP(imm); }16.499 +#define ROLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,0,r1)16.500 +#define ROLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,0,r1); } else { x86_encode_r32_rm32(0xC1,0,r1); OP(imm); }16.501 +#define ROLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,0,r1)16.502 +#define ROLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,0,r1); } else { x86_encode_r64_rm64(0xC1,0,r1); OP(imm); }16.503 +#define RORL_cl_r32(r1) x86_encode_r32_rm32(0xD3,1,r1)16.504 +#define RORL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,1,r1); } else { x86_encode_r32_rm32(0xC1,1,r1); OP(imm); }16.505 +#define RORQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,1,r1)16.506 +#define RORQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,1,r1); } else { x86_encode_r64_rm64(0xC1,1,r1); OP(imm); }16.507 +16.508 +#define SARL_cl_r32(r1) x86_encode_r32_rm32(0xD3,7,r1)16.509 +#define SARL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,7,r1); } else { x86_encode_r32_rm32(0xC1,7,r1); OP(imm); }16.510 +#define SARQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,7,r1)16.511 +#define SARQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,7,r1); } else { x86_encode_r64_rm64(0xC1,7,r1); OP(imm); }16.512 +#define SHLL_cl_r32(r1) x86_encode_r32_rm32(0xD3,4,r1)16.513 +#define SHLL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,4,r1); } else { x86_encode_r32_rm32(0xC1,4,r1); OP(imm); }16.514 +#define SHLQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,4,r1)16.515 +#define SHLQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,4,r1); } else { x86_encode_r64_rm64(0xC1,4,r1); OP(imm); }16.516 +#define SHRL_cl_r32(r1) x86_encode_r32_rm32(0xD3,5,r1)16.517 +#define SHRL_imm_r32(imm,r1) if( imm == 1 ) { x86_encode_r32_rm32(0xD1,5,r1); } else { x86_encode_r32_rm32(0xC1,5,r1); OP(imm); }16.518 +#define SHRQ_cl_r64(r1) x86_encode_r64_rm64(0xD3,5,r1)16.519 +#define SHRQ_imm_r64(imm,r1) if( imm == 1 ) { x86_encode_r64_rm64(0xD1,5,r1); } else { x86_encode_r64_rm64(0xC1,5,r1); OP(imm); }16.520 +16.521 +#define SBBB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 3, r1); OP(imm)16.522 +#define SBBB_r8_r8(r1,r2) x86_encode_r32_rm32(0x18, r1, r2)16.523 +#define SBBL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 3, imm, r1)16.524 +#define SBBL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,3,imm,disp)16.525 +#define SBBL_r32_r32(r1,r2) x86_encode_r32_rm32(0x19, r1, r2)16.526 +#define SBBL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x19, r1, disp)16.527 +#define SBBL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x1B, r1, disp)16.528 +#define SBBQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 3, imm, r1)16.529 +#define SBBQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x19, r1, r2)16.530 +16.531 +#define SETCCB_cc_r8(cc,r1) x86_encode_r32_rm32(0x0F90+(cc), 0, r1)16.532 +#define SETCCB_cc_rbpdisp(cc,disp) x86_encode_r32_rbpdisp32(0x0F90+(cc), 0, disp)16.533 +16.534 +#define STC() OP(0xF9)16.535 +#define STD() OP(0xFD)16.536 +16.537 +#define SUBB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 5, r1); OP(imm)16.538 +#define SUBB_r8_r8(r1,r2) x86_encode_r32_rm32(0x28, r1, r2)16.539 +#define SUBL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 5, imm, r1)16.540 +#define SUBL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,5,imm,disp)16.541 +#define SUBL_r32_r32(r1,r2) x86_encode_r32_rm32(0x29, r1, r2)16.542 +#define SUBL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x29, r1, disp)16.543 +#define SUBL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x2B, r1, disp)16.544 +#define SUBQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 5, imm, r1)16.545 +#define SUBQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x29, r1, r2)16.546 +16.547 +#define TESTB_imms_r8(imm,r1) x86_encode_r32_rm32(0xF6, 0, r1); OP(imm)16.548 +#define TESTB_r8_r8(r1,r2) x86_encode_r32_rm32(0x84, r1, r2)16.549 +#define TESTL_imms_r32(imm,r1) x86_encode_r32_rm32(0xF7, 0, r1); OP32(imm)16.550 +#define TESTL_imms_rbpdisp(imm,dsp) x86_encode_r32_rbpdisp32(0xF7, 0, dsp); OP32(imm)16.551 +#define TESTL_r32_r32(r1,r2) x86_encode_r32_rm32(0x85, r1, r2)16.552 +#define TESTL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x85, r1, disp)16.553 +#define TESTL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x85, r1, disp) /* Same OP */16.554 +#define TESTQ_imms_r64(imm,r1) x86_encode_r64_rm64(0xF7, 0, r1); OP32(imm)16.555 +#define TESTQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x85, r1, r2)16.556 +16.557 +#define XCHGB_r8_r8(r1,r2) x86_encode_r32_rm32(0x86, r1, r2)16.558 +#define XCHGL_r32_r32(r1,r2) x86_encode_r32_rm32(0x87, r1, r2)16.559 +#define XCHGQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x87, r1, r2)16.560 +16.561 +#define XORB_imms_r8(imm,r1) x86_encode_r32_rm32(0x80, 6, r1); OP(imm)16.562 +#define XORB_r8_r8(r1,r2) x86_encode_r32_rm32(0x30, r1, r2)16.563 +#define XORL_imms_r32(imm,r1) x86_encode_imms_rm32(0x83, 0x81, 6, imm, r1)16.564 +#define XORL_imms_rbpdisp(imm,disp) x86_encode_imms_rbpdisp32(0x83,0x81,6,imm,disp)16.565 +#define XORL_r32_r32(r1,r2) x86_encode_r32_rm32(0x31, r1, r2)16.566 +#define XORL_r32_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x31, r1, disp)16.567 +#define XORL_rbpdisp_r32(disp,r1) x86_encode_r32_rbpdisp32(0x33, r1, disp)16.568 +#define XORQ_imms_r64(imm,r1) x86_encode_imms_rm64(0x83, 0x81, 6, imm, r1)16.569 +#define XORQ_r64_r64(r1,r2) x86_encode_r64_rm64(0x31, r1, r2)16.570 +16.571 +/* Control flow */16.572 +#define CALL_rel(rel) OP(0xE8); OP32(rel)16.573 +#define CALL_imm32(ptr) x86_encode_r32_mem32disp32(0xFF, 2, -1, ptr)16.574 +#define CALL_r32(r1) x86_encode_r32_rm32(0xFF, 2, r1)16.575 +#define CALL_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 2, r1, disp)16.576 +16.577 +#define JCC_cc_rel8(cc,rel) OP(0x70+(cc)); OP(rel)16.578 +#define JCC_cc_rel32(cc,rel) OP(0x0F); OP(0x80+(cc)); OP32(rel)16.579 +#define JCC_cc_rel(cc,rel) if( IS_INT8(rel) ) { JCC_cc_rel8(cc,(int8_t)rel); } else { JCC_cc_rel32(cc,rel); }16.580 +16.581 +#define JMP_rel8(rel) OP(0xEB); OP(rel)16.582 +#define JMP_rel32(rel) OP(0xE9); OP32(rel)16.583 +#define JMP_rel(rel) if( IS_INT8(rel) ) { JMP_rel8((int8_t)rel); } else { JMP_rel32(rel); }16.584 +#define JMP_prerel(rel) if( IS_INT8(((int32_t)rel)-2) ) { JMP_rel8(((int8_t)rel)-2); } else { JMP_rel32(((int32_t)rel)-5); }16.585 +#define JMP_r32(r1,disp) x86_encode_r32_rm32(0xFF, 4, r1)16.586 +#define JMP_r32disp(r1,disp) x86_encode_r32_mem32disp32(0xFF, 4, r1, disp)16.587 +#define RET() OP(0xC3)16.588 +#define RET_imm(imm) OP(0xC2); OP16(imm)16.589 +16.590 +16.591 +/* x87 Floating point instructions */16.592 +#define FABS_st0() OP(0xD9); OP(0xE1)16.593 +#define FADDP_st(st) OP(0xDE); OP(0xC0+(st))16.594 +#define FCHS_st0() OP(0xD9); OP(0xE0)16.595 +#define FCOMIP_st(st) OP(0xDF); OP(0xF0+(st))16.596 +#define FDIVP_st(st) OP(0xDE); OP(0xF8+(st))16.597 +#define FILD_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xDB, 0, r32, disp)16.598 +#define FLD0_st0() OP(0xD9); OP(0xEE);16.599 +#define FLD1_st0() OP(0xD9); OP(0xE8);16.600 +#define FLDCW_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xD9, 5, r32, disp)16.601 +#define FMULP_st(st) OP(0xDE); OP(0xC8+(st))16.602 +#define FNSTCW_r32disp(r32, disp) x86_encode_r32_mem32disp32(0xD9, 7, r32, disp)16.603 +#define FPOP_st() OP(0xDD); OP(0xC0); OP(0xD9); OP(0xF7)16.604 +#define FSUBP_st(st) OP(0xDE); OP(0xE8+(st))16.605 +#define FSQRT_st0() OP(0xD9); OP(0xFA)16.606 +16.607 +#define FILD_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xDB, 0, disp)16.608 +#define FLDF_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD9, 0, disp)16.609 +#define FLDD_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xDD, 0, disp)16.610 +#define FISTP_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xDB, 3, disp)16.611 +#define FSTPF_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xD9, 3, disp)16.612 +#define FSTPD_rbpdisp(disp) x86_encode_r32_rbpdisp32(0xDD, 3, disp)16.613 +16.614 +16.615 +/* SSE Packed floating point instructions */16.616 +#define ADDPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F58, r1, disp)16.617 +#define ADDPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F58, r2, r1)16.618 +#define ANDPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F54, r1, disp)16.619 +#define ANDPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F54, r2, r1)16.620 +#define ANDNPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F55, r1, disp)16.621 +#define ANDNPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F55, r2, r1)16.622 +#define CMPPS_cc_rbpdisp_xmm(cc,d,r) x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)16.623 +#define CMPPS_cc_xmm_xmm(cc,r1,r2) x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)16.624 +#define DIVPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)16.625 +#define DIVPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5E, r2, r1)16.626 +#define MAXPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)16.627 +#define MAXPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5F, r2, r1)16.628 +#define MINPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)16.629 +#define MINPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5D, r2, r1)16.630 +#define MOV_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F28, r2, r1)16.631 +#define MOVAPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F28, r1, disp)16.632 +#define MOVAPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F29, r1, disp)16.633 +#define MOVHLPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F12, r2, r1)16.634 +#define MOVHPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F16, r1, disp)16.635 +#define MOVHPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F17, r1, disp)16.636 +#define MOVLHPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F16, r2, r1)16.637 +#define MOVLPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F12, r1, disp)16.638 +#define MOVLPS_xmm_rbpdisp(r1,disp) x86_encode_r32_rbpdisp32(0x0F13, r1, disp)16.639 +#define MOVUPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F10, r1, disp)16.640 +#define MOVUPS_xmm_rbpdisp(disp,r1) x86_encode_r32_rbpdisp32(0x0F11, r1, disp)16.641 +#define MULPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F59, r2, r1)16.642 +#define MULPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0xF59, r1, disp)16.643 +#define ORPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F56, r1, disp)16.644 +#define ORPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F56, r2, r1)16.645 +#define RCPPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0xF53, r1, disp)16.646 +#define RCPPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F53, r2, r1)16.647 +#define RSQRTPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F52, r1, disp)16.648 +#define RSQRTPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F52, r2, r1)16.649 +#define SHUFPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0FC6, r1, disp)16.650 +#define SHUFPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0FC6, r2, r1)16.651 +#define SQRTPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F51, r1, disp)16.652 +#define SQRTPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F51, r2, r1)16.653 +#define SUBPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)16.654 +#define SUBPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5C, r2, r1)16.655 +#define UNPCKHPS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F15, r1, disp)16.656 +#define UNPCKHPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F15, r2, r1)16.657 +#define UNPCKLPS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F14, r1, disp)16.658 +#define UNPCKLPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F14, r2, r1)16.659 +#define XORPS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F57, r1, disp)16.660 +#define XORPS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F57, r2, r1)16.661 +16.662 +/* SSE Scalar floating point instructions */16.663 +#define ADDSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)16.664 +#define ADDSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F58, r2, r1)16.665 +#define CMPSS_cc_rbpdisp_xmm(cc,d,r) OP(0xF3); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)16.666 +#define CMPSS_cc_xmm_xmm(cc,r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)16.667 +#define COMISS_rbpdisp_xmm(disp,r1) x86_encode_r32_rbpdisp32(0x0F2F, r1, disp)16.668 +#define COMISS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F2F, r2, r1)16.669 +#define DIVSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)16.670 +#define DIVSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5E, r2, r1)16.671 +#define MAXSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)16.672 +#define MAXSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5F, r2, r1)16.673 +#define MINSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)16.674 +#define MINSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5D, r2, r1)16.675 +#define MOVSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F10, r1, disp)16.676 +#define MOVSS_xmm_rbpdisp(r1,disp) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F11, r1, disp)16.677 +#define MOVSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F10, r2, r1)16.678 +#define MULSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0xF59, r1, disp)16.679 +#define MULSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F59, r2, r1)16.680 +#define RCPSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0xF53, r1, disp)16.681 +#define RCPSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F53, r2, r1)16.682 +#define RSQRTSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F52, r1, disp)16.683 +#define RSQRTSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F52, r2, r1)16.684 +#define SQRTSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F51, r1, disp)16.685 +#define SQRTSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F51, r2, r1)16.686 +#define SUBSS_rbpdisp_xmm(disp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)16.687 +#define SUBSS_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F5C, r2, r1)16.688 +#define UCOMISS_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F2E, r1, dsp)16.689 +#define UCOMISS_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F2E, r2, r1)16.690 +16.691 +/* SSE2 Packed floating point instructions */16.692 +#define ADDPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)16.693 +#define ADDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F58, r2, r1)16.694 +#define ANDPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F54, r1, disp)16.695 +#define ANDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F54, r2, r1)16.696 +#define ANDNPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F55, r1, disp)16.697 +#define ANDNPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F55, r2, r1)16.698 +#define CMPPD_cc_rbpdisp_xmm(cc,d,r) OP(0x66); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)16.699 +#define CMPPD_cc_xmm_xmm(cc,r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)16.700 +#define CVTPD2PS_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5A, r1, disp)16.701 +#define CVTPD2PS_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5A, r2, r1)16.702 +#define CVTPS2PD_rbpdisp_xmm(dsp,r1) x86_encode_r32_rbpdisp32(0x0F5A, r1, disp)16.703 +#define CVTPS2PD_xmm_xmm(r1,r2) x86_encode_r32_rm32(0x0F5A, r2, r1)16.704 +#define DIVPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)16.705 +#define DIVPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5E, r2, r1)16.706 +#define MAXPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)16.707 +#define MAXPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5F, r2, r1)16.708 +#define MINPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)16.709 +#define MINPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5D, r2, r1)16.710 +#define MOVHPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F16, r1, disp)16.711 +#define MOVHPD_xmm_rbpdisp(r1,disp) OP(0x66); x86_encode_r32_rbpdisp32(0x0F17, r1, disp)16.712 +#define MOVLPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F12, r1, disp)16.713 +#define MOVLPD_xmm_rbpdisp(r1,disp) OP(0x66); x86_encode_r32_rbpdisp32(0x0F13, r1, disp)16.714 +#define MULPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0xF59, r1, disp)16.715 +#define MULPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F59, r2, r1)16.716 +#define ORPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F56, r1, disp)16.717 +#define ORPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F56, r2, r1)16.718 +#define SHUFPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0FC6, r1, disp)16.719 +#define SHUFPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FC6, r2, r1)16.720 +#define SUBPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)16.721 +#define SUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F5C, r2, r1)16.722 +#define UNPCKHPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F15, r1, disp)16.723 +#define UNPCKHPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F15, r2, r1)16.724 +#define UNPCKLPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F14, r1, disp)16.725 +#define UNPCKLPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F14, r2, r1)16.726 +#define XORPD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F57, r1, disp)16.727 +#define XORPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F57, r2, r1)16.728 +16.729 +16.730 +/* SSE2 Scalar floating point instructions */16.731 +#define ADDSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F58, r1, disp)16.732 +#define ADDSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F58, r2, r1)16.733 +#define CMPSD_cc_rbpdisp_xmm(cc,d,r) OP(0xF2); x86_encode_r32_rbpdisp32(0x0FC2, r, d); OP(cc)16.734 +#define CMPSD_cc_xmm_xmm(cc,r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0FC2, r2, r1); OP(cc)16.735 +#define COMISD_rbpdisp_xmm(disp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F2F, r1, disp)16.736 +#define COMISD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F2F, r2, r1)16.737 +#define DIVSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5E, r1, disp)16.738 +#define DIVSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5E, r2, r1)16.739 +#define MAXSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5F, r1, disp)16.740 +#define MAXSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5F, r2, r1)16.741 +#define MINSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5D, r1, disp)16.742 +#define MINSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5D, r2, r1)16.743 +#define MOVSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F10, r1, disp)16.744 +#define MOVSD_xmm_rbpdisp(r1,disp) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F11, r1, disp)16.745 +#define MOVSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F10, r2, r1)16.746 +#define MULSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0xF59, r1, disp)16.747 +#define MULSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F59, r2, r1)16.748 +#define SQRTSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F51, r1, disp)16.749 +#define SQRTSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F51, r2, r1)16.750 +#define SUBSD_rbpdisp_xmm(disp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F5C, r1, disp)16.751 +#define SUBSD_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F5C, r2, r1)16.752 +#define UCOMISD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F2E, r1, dsp)16.753 +#define UCOMISD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F2E, r2, r1)16.754 +16.755 +/* SSE3 floating point instructions */16.756 +#define ADDSUBPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0FD0, r1, dsp)16.757 +#define ADDSUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0FD0, r2, r1)16.758 +#define ADDSUBPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0FD0, r1, dsp)16.759 +#define ADDSUBPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0FD0, r2, r1)16.760 +#define HADDPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F7C, r1, dsp)16.761 +#define HADDPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F7C, r2, r1)16.762 +#define HADDPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F7C, r1, dsp)16.763 +#define HADDPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F7C, r2, r1)16.764 +#define HSUBPD_rbpdisp_xmm(dsp,r1) OP(0x66); x86_encode_r32_rbpdisp32(0x0F7D, r1, dsp)16.765 +#define HSUBPD_xmm_xmm(r1,r2) OP(0x66); x86_encode_r32_rm32(0x0F7D, r2, r1)16.766 +#define HSUBPS_rbpdisp_xmm(dsp,r1) OP(0xF2); x86_encode_r32_rbpdisp32(0x0F7D, r1, dsp)16.767 +#define HSUBPS_xmm_xmm(r1,r2) OP(0xF2); x86_encode_r32_rm32(0x0F7D, r2, r1)16.768 +#define MOVSHDUP_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F16, r1, dsp)16.769 +#define MOVSHDUP_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F16, r2, r1)16.770 +#define MOVSLDUP_rbpdisp_xmm(dsp,r1) OP(0xF3); x86_encode_r32_rbpdisp32(0x0F12, r1, dsp)16.771 +#define MOVSLDUP_xmm_xmm(r1,r2) OP(0xF3); x86_encode_r32_rm32(0x0F12, r2, r1)
17.1 --- /dev/null Thu Jan 01 00:00:00 1970 +000017.2 +++ b/src/xlat/xltcache.c Wed Mar 04 23:12:21 2009 +000017.3 @@ -0,0 +1,497 @@17.4 +/**17.5 + * $Id$17.6 + *17.7 + * Translation cache management. This part is architecture independent.17.8 + *17.9 + * Copyright (c) 2005 Nathan Keynes.17.10 + *17.11 + * This program is free software; you can redistribute it and/or modify17.12 + * it under the terms of the GNU General Public License as published by17.13 + * the Free Software Foundation; either version 2 of the License, or17.14 + * (at your option) any later version.17.15 + *17.16 + * This program is distributed in the hope that it will be useful,17.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of17.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the17.19 + * GNU General Public License for more details.17.20 + */17.21 +17.22 +#include <sys/types.h>17.23 +#include <sys/mman.h>17.24 +#include <assert.h>17.25 +17.26 +#include "dreamcast.h"17.27 +#include "sh4/sh4core.h"17.28 +#include "xlat/xltcache.h"17.29 +#include "x86dasm/x86dasm.h"17.30 +17.31 +#define XLAT_LUT_PAGE_BITS 1217.32 +#define XLAT_LUT_TOTAL_BITS 2817.33 +#define XLAT_LUT_PAGE(addr) (((addr)>>13) & 0xFFFF)17.34 +#define XLAT_LUT_ENTRY(addr) (((addr)&0x1FFE) >> 1)17.35 +17.36 +#define XLAT_LUT_PAGES (1<<(XLAT_LUT_TOTAL_BITS-XLAT_LUT_PAGE_BITS))17.37 +#define XLAT_LUT_PAGE_ENTRIES (1<<XLAT_LUT_PAGE_BITS)17.38 +#define XLAT_LUT_PAGE_SIZE (XLAT_LUT_PAGE_ENTRIES * sizeof(void *))17.39 +17.40 +#define XLAT_LUT_ENTRY_EMPTY (void *)017.41 +#define XLAT_LUT_ENTRY_USED (void *)117.42 +17.43 +#define NEXT(block) ( (xlat_cache_block_t)&((block)->code[(block)->size]))17.44 +#define IS_ENTRY_POINT(ent) (ent > XLAT_LUT_ENTRY_USED)17.45 +#define IS_ENTRY_USED(ent) (ent != XLAT_LUT_ENTRY_EMPTY)17.46 +17.47 +#define MIN_BLOCK_SIZE 3217.48 +#define MIN_TOTAL_SIZE (sizeof(struct xlat_cache_block)+MIN_BLOCK_SIZE)17.49 +17.50 +#define BLOCK_INACTIVE 017.51 +#define BLOCK_ACTIVE 117.52 +#define BLOCK_USED 217.53 +17.54 +xlat_cache_block_t xlat_new_cache;17.55 +xlat_cache_block_t xlat_new_cache_ptr;17.56 +xlat_cache_block_t xlat_new_create_ptr;17.57 +17.58 +#ifdef XLAT_GENERATIONAL_CACHE17.59 +xlat_cache_block_t xlat_temp_cache;17.60 +xlat_cache_block_t xlat_temp_cache_ptr;17.61 +xlat_cache_block_t xlat_old_cache;17.62 +xlat_cache_block_t xlat_old_cache_ptr;17.63 +#endif17.64 +17.65 +static void **xlat_lut[XLAT_LUT_PAGES];17.66 +static gboolean xlat_initialized = FALSE;17.67 +17.68 +void xlat_cache_init(void)17.69 +{17.70 + if( !xlat_initialized ) {17.71 + xlat_initialized = TRUE;17.72 + xlat_new_cache = (xlat_cache_block_t)mmap( NULL, XLAT_NEW_CACHE_SIZE, PROT_EXEC|PROT_READ|PROT_WRITE,17.73 + MAP_PRIVATE|MAP_ANON, -1, 0 );17.74 + xlat_new_cache_ptr = xlat_new_cache;17.75 + xlat_new_create_ptr = xlat_new_cache;17.76 +#ifdef XLAT_GENERATIONAL_CACHE17.77 + xlat_temp_cache = mmap( NULL, XLAT_TEMP_CACHE_SIZE, PROT_EXEC|PROT_READ|PROT_WRITE,17.78 + MAP_PRIVATE|MAP_ANON, -1, 0 );17.79 + xlat_old_cache = mmap( NULL, XLAT_OLD_CACHE_SIZE, PROT_EXEC|PROT_READ|PROT_WRITE,17.80 + MAP_PRIVATE|MAP_ANON, -1, 0 );17.81 + xlat_temp_cache_ptr = xlat_temp_cache;17.82 + xlat_old_cache_ptr = xlat_old_cache;17.83 +#endif17.84 +// xlat_lut = mmap( NULL, XLAT_LUT_PAGES*sizeof(void *), PROT_READ|PROT_WRITE,17.85 +// MAP_PRIVATE|MAP_ANON, -1, 0);17.86 + memset( xlat_lut, 0, XLAT_LUT_PAGES*sizeof(void *) );17.87 + }17.88 + xlat_flush_cache();17.89 +}17.90 +17.91 +/**17.92 + * Reset the cache structure to its default state17.93 + */17.94 +void xlat_flush_cache()17.95 +{17.96 + xlat_cache_block_t tmp;17.97 + int i;17.98 + xlat_new_cache_ptr = xlat_new_cache;17.99 + xlat_new_cache_ptr->active = 0;17.100 + xlat_new_cache_ptr->size = XLAT_NEW_CACHE_SIZE - 2*sizeof(struct xlat_cache_block);17.101 + tmp = NEXT(xlat_new_cache_ptr);17.102 + tmp->active = 1;17.103 + tmp->size = 0;17.104 +#ifdef XLAT_GENERATIONAL_CACHE17.105 + xlat_temp_cache_ptr = xlat_temp_cache;17.106 + xlat_temp_cache_ptr->active = 0;17.107 + xlat_temp_cache_ptr->size = XLAT_TEMP_CACHE_SIZE - 2*sizeof(struct xlat_cache_block);17.108 + tmp = NEXT(xlat_temp_cache_ptr);17.109 + tmp->active = 1;17.110 + tmp->size = 0;17.111 + xlat_old_cache_ptr = xlat_old_cache;17.112 + xlat_old_cache_ptr->active = 0;17.113 + xlat_old_cache_ptr->size = XLAT_OLD_CACHE_SIZE - 2*sizeof(struct xlat_cache_block);17.114 + tmp = NEXT(xlat_old_cache_ptr);17.115 + tmp->active = 1;17.116 + tmp->size = 0;17.117 +#endif17.118 + for( i=0; i<XLAT_LUT_PAGES; i++ ) {17.119 + if( xlat_lut[i] != NULL ) {17.120 + memset( xlat_lut[i], 0, XLAT_LUT_PAGE_SIZE );17.121 + }17.122 + }17.123 +}17.124 +17.125 +static void xlat_flush_page_by_lut( void **page )17.126 +{17.127 + int i;17.128 + for( i=0; i<XLAT_LUT_PAGE_ENTRIES; i++ ) {17.129 + if( IS_ENTRY_POINT(page[i]) ) {17.130 + XLAT_BLOCK_FOR_CODE(page[i])->active = 0;17.131 + }17.132 + page[i] = NULL;17.133 + }17.134 +}17.135 +17.136 +void FASTCALL xlat_invalidate_word( sh4addr_t addr )17.137 +{17.138 + void **page = xlat_lut[XLAT_LUT_PAGE(addr)];17.139 + if( page != NULL ) {17.140 + int entry = XLAT_LUT_ENTRY(addr);17.141 + if( page[entry] != NULL ) {17.142 + xlat_flush_page_by_lut(page);17.143 + }17.144 + }17.145 +}17.146 +17.147 +void FASTCALL xlat_invalidate_long( sh4addr_t addr )17.148 +{17.149 + void **page = xlat_lut[XLAT_LUT_PAGE(addr)];17.150 + if( page != NULL ) {17.151 + int entry = XLAT_LUT_ENTRY(addr);17.152 + if( *(uint64_t *)&page[entry] != 0 ) {17.153 + xlat_flush_page_by_lut(page);17.154 + }17.155 + }17.156 +}17.157 +17.158 +void FASTCALL xlat_invalidate_block( sh4addr_t address, size_t size )17.159 +{17.160 + int i;17.161 + int entry_count = size >> 1; // words;17.162 + uint32_t page_no = XLAT_LUT_PAGE(address);17.163 + int entry = XLAT_LUT_ENTRY(address);17.164 + do {17.165 + void **page = xlat_lut[page_no];17.166 + int page_entries = XLAT_LUT_PAGE_ENTRIES - entry;17.167 + if( entry_count < page_entries ) {17.168 + page_entries = entry_count;17.169 + }17.170 + if( page != NULL ) {17.171 + if( page_entries == XLAT_LUT_PAGE_ENTRIES ) {17.172 + /* Overwriting the entire page anyway */17.173 + xlat_flush_page_by_lut(page);17.174 + } else {17.175 + for( i=entry; i<entry+page_entries; i++ ) {17.176 + if( page[i] != NULL ) {17.177 + xlat_flush_page_by_lut(page);17.178 + break;17.179 + }17.180 + }17.181 + }17.182 + entry_count -= page_entries;17.183 + }17.184 + page_no ++;17.185 + entry_count -= page_entries;17.186 + entry = 0;17.187 + } while( entry_count > 0 );17.188 +}17.189 +17.190 +void FASTCALL xlat_flush_page( sh4addr_t address )17.191 +{17.192 + void **page = xlat_lut[XLAT_LUT_PAGE(address)];17.193 + if( page != NULL ) {17.194 + xlat_flush_page_by_lut(page);17.195 + }17.196 +}17.197 +17.198 +void * FASTCALL xlat_get_code( sh4addr_t address )17.199 +{17.200 + void *result = NULL;17.201 + void **page = xlat_lut[XLAT_LUT_PAGE(address)];17.202 + if( page != NULL ) {17.203 + result = (void *)(((uintptr_t)(page[XLAT_LUT_ENTRY(address)])) & (~((uintptr_t)0x03)));17.204 + }17.205 + return result;17.206 +}17.207 +17.208 +xlat_recovery_record_t xlat_get_pre_recovery( void *code, void *native_pc )17.209 +{17.210 + if( code != NULL ) {17.211 + uintptr_t pc_offset = ((uint8_t *)native_pc) - ((uint8_t *)code);17.212 + xlat_cache_block_t block = XLAT_BLOCK_FOR_CODE(code);17.213 + uint32_t count = block->recover_table_size;17.214 + xlat_recovery_record_t records = (xlat_recovery_record_t)(&block->code[block->recover_table_offset]);17.215 + uint32_t posn;17.216 + for( posn = 1; posn < count; posn++ ) {17.217 + if( records[posn].xlat_offset >= pc_offset ) {17.218 + return &records[posn-1];17.219 + }17.220 + }17.221 + return &records[count-1];17.222 + }17.223 + return NULL;17.224 +}17.225 +17.226 +void ** FASTCALL xlat_get_lut_entry( sh4addr_t address )17.227 +{17.228 + void **page = xlat_lut[XLAT_LUT_PAGE(address)];17.229 +17.230 + /* Add the LUT entry for the block */17.231 + if( page == NULL ) {17.232 + xlat_lut[XLAT_LUT_PAGE(address)] = page =17.233 + (void **)mmap( NULL, XLAT_LUT_PAGE_SIZE, PROT_READ|PROT_WRITE,17.234 + MAP_PRIVATE|MAP_ANON, -1, 0 );17.235 + memset( page, 0, XLAT_LUT_PAGE_SIZE );17.236 + }17.237 +17.238 + return &page[XLAT_LUT_ENTRY(address)];17.239 +}17.240 +17.241 +17.242 +17.243 +uint32_t FASTCALL xlat_get_block_size( void *block )17.244 +{17.245 + xlat_cache_block_t xlt = (xlat_cache_block_t)(((char *)block)-sizeof(struct xlat_cache_block));17.246 + return xlt->size;17.247 +}17.248 +17.249 +uint32_t FASTCALL xlat_get_code_size( void *block )17.250 +{17.251 + xlat_cache_block_t xlt = (xlat_cache_block_t)(((char *)block)-sizeof(struct xlat_cache_block));17.252 + if( xlt->recover_table_offset == 0 ) {17.253 + return xlt->size;17.254 + } else {17.255 + return xlt->recover_table_offset;17.256 + }17.257 +}17.258 +17.259 +/**17.260 + * Cut the specified block so that it has the given size, with the remaining data17.261 + * forming a new free block. If the free block would be less than the minimum size,17.262 + * the cut is not performed.17.263 + * @return the next block after the (possibly cut) block.17.264 + */17.265 +static inline xlat_cache_block_t xlat_cut_block( xlat_cache_block_t block, int cutsize )17.266 +{17.267 + cutsize = (cutsize + 3) & 0xFFFFFFFC; // force word alignment17.268 + assert( cutsize <= block->size );17.269 + if( block->size > cutsize + MIN_TOTAL_SIZE ) {17.270 + int oldsize = block->size;17.271 + block->size = cutsize;17.272 + xlat_cache_block_t next = NEXT(block);17.273 + next->active = 0;17.274 + next->size = oldsize - cutsize - sizeof(struct xlat_cache_block);17.275 + return next;17.276 + } else {17.277 + return NEXT(block);17.278 + }17.279 +}17.280 +17.281 +#ifdef XLAT_GENERATIONAL_CACHE17.282 +/**17.283 + * Promote a block in temp space (or elsewhere for that matter) to old space.17.284 + *17.285 + * @param block to promote.17.286 + */17.287 +static void xlat_promote_to_old_space( xlat_cache_block_t block )17.288 +{17.289 + int allocation = (int)-sizeof(struct xlat_cache_block);17.290 + int size = block->size;17.291 + xlat_cache_block_t curr = xlat_old_cache_ptr;17.292 + xlat_cache_block_t start_block = curr;17.293 + do {17.294 + allocation += curr->size + sizeof(struct xlat_cache_block);17.295 + curr = NEXT(curr);17.296 + if( allocation > size ) {17.297 + break; /* done */17.298 + }17.299 + if( curr->size == 0 ) { /* End-of-cache Sentinel */17.300 + /* Leave what we just released as free space and start again from the17.301 + * top of the cache17.302 + */17.303 + start_block->active = 0;17.304 + start_block->size = allocation;17.305 + allocation = (int)-sizeof(struct xlat_cache_block);17.306 + start_block = curr = xlat_old_cache;17.307 + }17.308 + } while(1);17.309 + start_block->active = 1;17.310 + start_block->size = allocation;17.311 + start_block->lut_entry = block->lut_entry;17.312 + start_block->fpscr_mask = block->fpscr_mask;17.313 + start_block->fpscr = block->fpscr;17.314 + start_block->recover_table_offset = block->recover_table_offset;17.315 + start_block->recover_table_size = block->recover_table_size;17.316 + *block->lut_entry = &start_block->code;17.317 + memcpy( start_block->code, block->code, block->size );17.318 + xlat_old_cache_ptr = xlat_cut_block(start_block, size );17.319 + if( xlat_old_cache_ptr->size == 0 ) {17.320 + xlat_old_cache_ptr = xlat_old_cache;17.321 + }17.322 +}17.323 +17.324 +/**17.325 + * Similarly to the above method, promotes a block to temp space.17.326 + * TODO: Try to combine these - they're nearly identical17.327 + */17.328 +void xlat_promote_to_temp_space( xlat_cache_block_t block )17.329 +{17.330 + int size = block->size;17.331 + int allocation = (int)-sizeof(struct xlat_cache_block);17.332 + xlat_cache_block_t curr = xlat_temp_cache_ptr;17.333 + xlat_cache_block_t start_block = curr;17.334 + do {17.335 + if( curr->active == BLOCK_USED ) {17.336 + xlat_promote_to_old_space( curr );17.337 + } else if( curr->active == BLOCK_ACTIVE ) {17.338 + // Active but not used, release block17.339 + *((uintptr_t *)curr->lut_entry) &= ((uintptr_t)0x03);17.340 + }17.341 + allocation += curr->size + sizeof(struct xlat_cache_block);17.342 + curr = NEXT(curr);17.343 + if( allocation > size ) {17.344 + break; /* done */17.345 + }17.346 + if( curr->size == 0 ) { /* End-of-cache Sentinel */17.347 + /* Leave what we just released as free space and start again from the17.348 + * top of the cache17.349 + */17.350 + start_block->active = 0;17.351 + start_block->size = allocation;17.352 + allocation = (int)-sizeof(struct xlat_cache_block);17.353 + start_block = curr = xlat_temp_cache;17.354 + }17.355 + } while(1);17.356 + start_block->active = 1;17.357 + start_block->size = allocation;17.358 + start_block->lut_entry = block->lut_entry;17.359 + start_block->fpscr_mask = block->fpscr_mask;17.360 + start_block->fpscr = block->fpscr;17.361 + start_block->recover_table_offset = block->recover_table_offset;17.362 + start_block->recover_table_size = block->recover_table_size;17.363 + *block->lut_entry = &start_block->code;17.364 + memcpy( start_block->code, block->code, block->size );17.365 + xlat_temp_cache_ptr = xlat_cut_block(start_block, size );17.366 + if( xlat_temp_cache_ptr->size == 0 ) {17.367 + xlat_temp_cache_ptr = xlat_temp_cache;17.368 + }17.369 +17.370 +}17.371 +#else17.372 +void xlat_promote_to_temp_space( xlat_cache_block_t block )17.373 +{17.374 + *block->lut_entry = 0;17.375 +}17.376 +#endif17.377 +17.378 +/**17.379 + * Returns the next block in the new cache list that can be written to by the17.380 + * translator. If the next block is active, it is evicted first.17.381 + */17.382 +xlat_cache_block_t xlat_start_block( sh4addr_t address )17.383 +{17.384 + if( xlat_new_cache_ptr->size == 0 ) {17.385 + xlat_new_cache_ptr = xlat_new_cache;17.386 + }17.387 +17.388 + if( xlat_new_cache_ptr->active ) {17.389 + xlat_promote_to_temp_space( xlat_new_cache_ptr );17.390 + }17.391 + xlat_new_create_ptr = xlat_new_cache_ptr;17.392 + xlat_new_create_ptr->active = 1;17.393 + xlat_new_cache_ptr = NEXT(xlat_new_cache_ptr);17.394 +17.395 + /* Add the LUT entry for the block */17.396 + if( xlat_lut[XLAT_LUT_PAGE(address)] == NULL ) {17.397 + xlat_lut[XLAT_LUT_PAGE(address)] =17.398 + (void **)mmap( NULL, XLAT_LUT_PAGE_SIZE, PROT_READ|PROT_WRITE,17.399 + MAP_PRIVATE|MAP_ANON, -1, 0 );17.400 + memset( xlat_lut[XLAT_LUT_PAGE(address)], 0, XLAT_LUT_PAGE_SIZE );17.401 + }17.402 +17.403 + if( IS_ENTRY_POINT(xlat_lut[XLAT_LUT_PAGE(address)][XLAT_LUT_ENTRY(address)]) ) {17.404 + xlat_cache_block_t oldblock = XLAT_BLOCK_FOR_CODE(xlat_lut[XLAT_LUT_PAGE(address)][XLAT_LUT_ENTRY(address)]);17.405 + oldblock->active = 0;17.406 + }17.407 +17.408 + xlat_lut[XLAT_LUT_PAGE(address)][XLAT_LUT_ENTRY(address)] =17.409 + &xlat_new_create_ptr->code;17.410 + xlat_new_create_ptr->lut_entry = xlat_lut[XLAT_LUT_PAGE(address)] + XLAT_LUT_ENTRY(address);17.411 +17.412 + return xlat_new_create_ptr;17.413 +}17.414 +17.415 +xlat_cache_block_t xlat_extend_block( uint32_t newSize )17.416 +{17.417 + while( xlat_new_create_ptr->size < newSize ) {17.418 + if( xlat_new_cache_ptr->size == 0 ) {17.419 + /* Migrate to the front of the cache to keep it contiguous */17.420 + xlat_new_create_ptr->active = 0;17.421 + sh4ptr_t olddata = xlat_new_create_ptr->code;17.422 + int oldsize = xlat_new_create_ptr->size;17.423 + int size = oldsize + MIN_BLOCK_SIZE; /* minimum expansion */17.424 + void **lut_entry = xlat_new_create_ptr->lut_entry;17.425 + int allocation = (int)-sizeof(struct xlat_cache_block);17.426 + xlat_new_cache_ptr = xlat_new_cache;17.427 + do {17.428 + if( xlat_new_cache_ptr->active ) {17.429 + xlat_promote_to_temp_space( xlat_new_cache_ptr );17.430 + }17.431 + allocation += xlat_new_cache_ptr->size + sizeof(struct xlat_cache_block);17.432 + xlat_new_cache_ptr = NEXT(xlat_new_cache_ptr);17.433 + } while( allocation < size );17.434 + xlat_new_create_ptr = xlat_new_cache;17.435 + xlat_new_create_ptr->active = 1;17.436 + xlat_new_create_ptr->size = allocation;17.437 + xlat_new_create_ptr->lut_entry = lut_entry;17.438 + *lut_entry = &xlat_new_create_ptr->code;17.439 + memmove( xlat_new_create_ptr->code, olddata, oldsize );17.440 + } else {17.441 + if( xlat_new_cache_ptr->active ) {17.442 + xlat_promote_to_temp_space( xlat_new_cache_ptr );17.443 + }17.444 + xlat_new_create_ptr->size += xlat_new_cache_ptr->size + sizeof(struct xlat_cache_block);17.445 + xlat_new_cache_ptr = NEXT(xlat_new_cache_ptr);17.446 + }17.447 + }17.448 + return xlat_new_create_ptr;17.449 +17.450 +}17.451 +17.452 +void xlat_commit_block( uint32_t destsize, uint32_t srcsize )17.453 +{17.454 + void **ptr = xlat_new_create_ptr->lut_entry;17.455 + void **endptr = ptr + (srcsize>>2);17.456 + while( ptr < endptr ) {17.457 + if( *ptr == NULL ) {17.458 + *ptr = XLAT_LUT_ENTRY_USED;17.459 + }17.460 + ptr++;17.461 + }17.462 +17.463 + xlat_new_cache_ptr = xlat_cut_block( xlat_new_create_ptr, destsize );17.464 +}17.465 +17.466 +void xlat_delete_block( xlat_cache_block_t block )17.467 +{17.468 + block->active = 0;17.469 + *block->lut_entry = NULL;17.470 +}17.471 +17.472 +void xlat_check_cache_integrity( xlat_cache_block_t cache, xlat_cache_block_t ptr, int size )17.473 +{17.474 + int foundptr = 0;17.475 + xlat_cache_block_t tail =17.476 + (xlat_cache_block_t)(((char *)cache) + size - sizeof(struct xlat_cache_block));17.477 +17.478 + assert( tail->active == 1 );17.479 + assert( tail->size == 0 );17.480 + while( cache < tail ) {17.481 + assert( cache->active >= 0 && cache->active <= 2 );17.482 + assert( cache->size >= 0 && cache->size < size );17.483 + if( cache == ptr ) {17.484 + foundptr = 1;17.485 + }17.486 + cache = NEXT(cache);17.487 + }17.488 + assert( cache == tail );17.489 + assert( foundptr == 1 || tail == ptr );17.490 +}17.491 +17.492 +void xlat_check_integrity( )17.493 +{17.494 + xlat_check_cache_integrity( xlat_new_cache, xlat_new_cache_ptr, XLAT_NEW_CACHE_SIZE );17.495 +#ifdef XLAT_GENERATIONAL_CACHE17.496 + xlat_check_cache_integrity( xlat_temp_cache, xlat_temp_cache_ptr, XLAT_TEMP_CACHE_SIZE );17.497 + xlat_check_cache_integrity( xlat_old_cache, xlat_old_cache_ptr, XLAT_OLD_CACHE_SIZE );17.498 +#endif17.499 +}17.500 +
18.1 --- /dev/null Thu Jan 01 00:00:00 1970 +000018.2 +++ b/src/xlat/xltcache.h Wed Mar 04 23:12:21 2009 +000018.3 @@ -0,0 +1,176 @@18.4 +/**18.5 + * $Id$18.6 + *18.7 + * Translation cache support (architecture independent)18.8 + *18.9 + * Copyright (c) 2005 Nathan Keynes.18.10 + *18.11 + * This program is free software; you can redistribute it and/or modify18.12 + * it under the terms of the GNU General Public License as published by18.13 + * the Free Software Foundation; either version 2 of the License, or18.14 + * (at your option) any later version.18.15 + *18.16 + * This program is distributed in the hope that it will be useful,18.17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of18.18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the18.19 + * GNU General Public License for more details.18.20 + */18.21 +18.22 +#include "dream.h"18.23 +#include "mem.h"18.24 +18.25 +#ifndef lxdream_xltcache_H18.26 +#define lxdream_xltcache_H 118.27 +18.28 +/**18.29 + * For now, recovery is purely a matter of mapping native pc => sh4 pc,18.30 + * and updating sh4r.pc & sh4r.slice_cycles accordingly. In future more18.31 + * detailed recovery may be required if the translator optimizes more18.32 + * agressively.18.33 + *18.34 + * The recovery table contains (at least) one entry per abortable instruction,18.35 + *18.36 + */18.37 +typedef struct xlat_recovery_record {18.38 + uint32_t xlat_offset; // native (translated) pc18.39 + uint32_t sh4_icount; // instruction number of the corresponding SH4 instruction18.40 + // (0 = first instruction, 1 = second instruction, ... )18.41 +} *xlat_recovery_record_t;18.42 +18.43 +struct xlat_cache_block {18.44 + int active; /* 0 = deleted, 1 = normal. 2 = accessed (temp-space only) */18.45 + uint32_t size;18.46 + void **lut_entry; /* For deletion */18.47 + uint32_t xlat_sh4_mode; /* comparison with sh4r.xlat_sh4_mode */18.48 + uint32_t recover_table_offset; // Offset from code[0] of the recovery table;18.49 + uint32_t recover_table_size;18.50 + unsigned char code[0];18.51 +} __attribute__((packed));18.52 +18.53 +typedef struct xlat_cache_block *xlat_cache_block_t;18.54 +18.55 +#define XLAT_BLOCK_FOR_CODE(code) (((xlat_cache_block_t)code)-1)18.56 +18.57 +#define XLAT_BLOCK_MODE(code) (XLAT_BLOCK_FOR_CODE(code)->xlat_sh4_mode)18.58 +18.59 +/**18.60 + * Initialize the translation cache18.61 + */18.62 +void xlat_cache_init(void);18.63 +18.64 +/**18.65 + * Returns the next block in the new cache list that can be written to by the18.66 + * translator.18.67 + */18.68 +xlat_cache_block_t xlat_start_block(sh4addr_t address);18.69 +18.70 +/**18.71 + * Increases the current block size (only valid between calls to xlat_start_block()18.72 + * and xlat_commit_block()).18.73 + * @return the new block, which may be different from the old block.18.74 + */18.75 +xlat_cache_block_t xlat_extend_block( uint32_t newSize );18.76 +18.77 +/**18.78 + * Commit the current translation block18.79 + * @param addr target address (for the lookup table)18.80 + * @param destsize final size of the translation in bytes.18.81 + * @param srcsize size of the original data that was translated in bytes18.82 + */18.83 +void xlat_commit_block( uint32_t destsize, uint32_t srcsize );18.84 +18.85 +/**18.86 + * Dump the disassembly of the specified code block to a stream18.87 + * (primarily for debugging purposes)18.88 + * @param out The stream to write the output to18.89 + * @param code a translated block18.90 + */18.91 +void xlat_disasm_block( FILE *out, void *code );18.92 +18.93 +18.94 +/**18.95 + * Delete (deactivate) the specified block from the cache. Caller is responsible18.96 + * for ensuring that there really is a block there.18.97 + */18.98 +void xlat_delete_block( xlat_cache_block_t block );18.99 +18.100 +/**18.101 + * Retrieve the entry point for the translated code corresponding to the given18.102 + * SH4 address, or NULL if there is no code for that address.18.103 + */18.104 +void * FASTCALL xlat_get_code( sh4addr_t address );18.105 +18.106 +/**18.107 + * Retrieve the pre-instruction recovery record corresponding to the given18.108 + * native address, or NULL if there is no recovery code for the address.18.109 + * @param code The code block containing the recovery table.18.110 + * @param native_pc A pointer that must be within the currently executing18.111 + * return the first record before or equal to the given pc.18.112 + * translation block.18.113 + */18.114 +struct xlat_recovery_record *xlat_get_pre_recovery( void *code, void *native_pc );18.115 +18.116 +18.117 +/**18.118 + * Retrieve the entry point for the translated code corresponding to the given18.119 + * SH4 virtual address, or NULL if there is no code for the address.18.120 + * If the virtual address cannot be resolved, this method will raise a TLB miss18.121 + * exception, and return NULL.18.122 + */18.123 +void * FASTCALL xlat_get_code_by_vma( sh4vma_t address );18.124 +18.125 +/**18.126 + * Retrieve the address of the lookup table entry corresponding to the18.127 + * given SH4 address.18.128 + */18.129 +void ** FASTCALL xlat_get_lut_entry( sh4addr_t address );18.130 +18.131 +/**18.132 + * Retrieve the current host address of the running translated code block.18.133 + * @return the host PC, or null if there is no currently executing translated18.134 + * block (or the stack is corrupted)18.135 + * Note: the implementation of this method is host (and calling-convention) specific.18.136 + * @param block_start start of the block the PC should be in18.137 + * @param block_size size of the code block in bytes.18.138 + */18.139 +void *xlat_get_native_pc( void *block_start, uint32_t block_size );18.140 +18.141 +/**18.142 + * Retrieve the size of the block starting at the specified pointer. If the18.143 + * pointer is not a valid code block, the return value is undefined.18.144 + */18.145 +uint32_t FASTCALL xlat_get_block_size( void *ptr );18.146 +18.147 +/**18.148 + * Retrieve the size of the code in the block starting at the specified18.149 + * pointer. Effectively this is xlat_get_block_size() minus the size of18.150 + * the recovery table. If the pointer is not a valid code block, the18.151 + * return value is undefined.18.152 + */18.153 +uint32_t FASTCALL xlat_get_code_size( void *ptr );18.154 +18.155 +/**18.156 + * Flush the code cache for the page containing the given address18.157 + */18.158 +void FASTCALL xlat_flush_page( sh4addr_t address );18.159 +18.160 +void FASTCALL xlat_invalidate_word( sh4addr_t address );18.161 +void FASTCALL xlat_invalidate_long( sh4addr_t address );18.162 +18.163 +18.164 +/**18.165 + * Invalidate the code cache for a memory region18.166 + */18.167 +void FASTCALL xlat_invalidate_block( sh4addr_t address, size_t bytes );18.168 +18.169 +/**18.170 + * Flush the entire code cache. This isn't as cheap as one might like18.171 + */18.172 +void xlat_flush_cache();18.173 +18.174 +/**18.175 + * Check the internal integrity of the cache18.176 + */18.177 +void xlat_check_integrity();18.178 +18.179 +#endif /* lxdream_xltcache_H */
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