1.1 --- a/src/Makefile.am	Wed Mar 04 23:04:54 2009 +0000
     1.2 +++ b/src/Makefile.am	Wed Mar 04 23:12:21 2009 +0000
     1.3 @@ -45,7 +45,7 @@
     1.4          sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c sh4/dmac.c \
     1.5          sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h \
     1.6          sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
     1.7 -	sh4/xltcache.c sh4/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \
     1.8 +	xlat/xltcache.c xlat/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \
     1.9  	sh4/cache.c sh4/mmu.h \
    1.10          aica/armcore.c aica/armcore.h aica/armdasm.c aica/armdasm.h aica/armmem.c \
    1.11          aica/aica.c aica/aica.h aica/audio.c aica/audio.h \
    1.12 @@ -64,7 +64,7 @@
    1.13  	
    1.14  
    1.15  if BUILD_SH4X86
    1.16 -lxdream_SOURCES += sh4/sh4x86.c sh4/x86op.h \
    1.17 +lxdream_SOURCES += sh4/sh4x86.c xlat/x86/x86op.h \
    1.18          sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h \
    1.19          sh4/sh4trans.c sh4/sh4trans.h sh4/mmux86.c \
    1.20          x86dasm/x86dasm.c x86dasm/x86dasm.h \
    1.21 @@ -76,8 +76,8 @@
    1.22  test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \
    1.23  	x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
    1.24  	x86dasm/dis-buf.c \
    1.25 -	sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \
    1.26 -	sh4/xltcache.h mem.c util.c 
    1.27 +	sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c \
    1.28 +	xlat/xltcache.h mem.c util.c 
    1.29  
    1.30  check_PROGRAMS += test/testsh4x86
    1.31  endif
    1.32 @@ -155,7 +155,7 @@
    1.33  genglsl_LDADD = @GLIB_LIBS@ @GTK_LIBS@ $(INTLLIBS)
    1.34  
    1.35  
    1.36 -test_testxlt_SOURCES = test/testxlt.c sh4/xltcache.c sh4/xltcache.h
    1.37 +test_testxlt_SOURCES = test/testxlt.c xlat/xltcache.c xlat/xltcache.h
    1.38  
    1.39  sh4/sh4core.c: gendec sh4/sh4.def sh4/sh4core.in
    1.40  	mkdir -p `dirname $@`

     2.1 --- a/src/Makefile.in	Wed Mar 04 23:04:54 2009 +0000
     2.2 +++ b/src/Makefile.in	Wed Mar 04 23:12:21 2009 +0000
     2.3 @@ -39,7 +39,7 @@
     2.4  bin_PROGRAMS = lxdream$(EXEEXT)
     2.5  noinst_PROGRAMS = gendec$(EXEEXT) genglsl$(EXEEXT)
     2.6  check_PROGRAMS = test/testxlt$(EXEEXT) $(am__EXEEXT_1)
     2.7 -@BUILD_SH4X86_TRUE@am__append_1 = sh4/sh4x86.c sh4/x86op.h \
     2.8 +@BUILD_SH4X86_TRUE@am__append_1 = sh4/sh4x86.c xlat/x86/x86op.h \
     2.9  @BUILD_SH4X86_TRUE@        sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h \
    2.10  @BUILD_SH4X86_TRUE@        sh4/sh4trans.c sh4/sh4trans.h sh4/mmux86.c \
    2.11  @BUILD_SH4X86_TRUE@        x86dasm/x86dasm.c x86dasm/x86dasm.h \
    2.12 @@ -106,7 +106,7 @@
    2.13  	sh4/sh4.c sh4/intc.c sh4/intc.h sh4/sh4mem.c sh4/timer.c \
    2.14  	sh4/dmac.c sh4/mmu.c sh4/sh4core.c sh4/sh4core.h sh4/sh4dasm.c \
    2.15  	sh4/sh4dasm.h sh4/sh4mmio.c sh4/sh4mmio.h sh4/scif.c \
    2.16 -	sh4/sh4stat.c sh4/sh4stat.h sh4/xltcache.c sh4/xltcache.h \
    2.17 +	sh4/sh4stat.c sh4/sh4stat.h xlat/xltcache.c xlat/xltcache.h \
    2.18  	sh4/sh4.h sh4/dmac.h sh4/pmm.c sh4/cache.c sh4/mmu.h \
    2.19  	aica/armcore.c aica/armcore.h aica/armdasm.c aica/armdasm.h \
    2.20  	aica/armmem.c aica/aica.c aica/aica.h aica/audio.c \
    2.21 @@ -121,7 +121,7 @@
    2.22  	display.h dckeysyms.h drivers/audio_null.c \
    2.23  	drivers/video_null.c drivers/video_gl.c drivers/video_gl.h \
    2.24  	drivers/gl_fbo.c sh4/sh4.def sh4/sh4core.in sh4/sh4x86.in \
    2.25 -	sh4/sh4dasm.in sh4/sh4stat.in sh4/sh4x86.c sh4/x86op.h \
    2.26 +	sh4/sh4dasm.in sh4/sh4stat.in sh4/sh4x86.c xlat/x86/x86op.h \
    2.27  	sh4/ia32abi.h sh4/ia32mac.h sh4/ia64abi.h sh4/sh4trans.c \
    2.28  	sh4/sh4trans.h sh4/mmux86.c x86dasm/x86dasm.c \
    2.29  	x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
    2.30 @@ -197,8 +197,8 @@
    2.31  lxdream_DEPENDENCIES = $(am__DEPENDENCIES_1)
    2.32  am__test_testsh4x86_SOURCES_DIST = test/testsh4x86.c x86dasm/x86dasm.c \
    2.33  	x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
    2.34 -	x86dasm/dis-buf.c sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \
    2.35 -	sh4/xltcache.h mem.c util.c
    2.36 +	x86dasm/dis-buf.c sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c \
    2.37 +	xlat/xltcache.h mem.c util.c
    2.38  @BUILD_SH4X86_TRUE@am_test_testsh4x86_OBJECTS = testsh4x86.$(OBJEXT) \
    2.39  @BUILD_SH4X86_TRUE@	x86dasm.$(OBJEXT) i386-dis.$(OBJEXT) \
    2.40  @BUILD_SH4X86_TRUE@	dis-init.$(OBJEXT) dis-buf.$(OBJEXT) \
    2.41 @@ -437,7 +437,7 @@
    2.42  	sh4/sh4mem.c sh4/timer.c sh4/dmac.c sh4/mmu.c sh4/sh4core.c \
    2.43  	sh4/sh4core.h sh4/sh4dasm.c sh4/sh4dasm.h sh4/sh4mmio.c \
    2.44  	sh4/sh4mmio.h sh4/scif.c sh4/sh4stat.c sh4/sh4stat.h \
    2.45 -	sh4/xltcache.c sh4/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \
    2.46 +	xlat/xltcache.c xlat/xltcache.h sh4/sh4.h sh4/dmac.h sh4/pmm.c \
    2.47  	sh4/cache.c sh4/mmu.h aica/armcore.c aica/armcore.h \
    2.48  	aica/armdasm.c aica/armdasm.h aica/armmem.c aica/aica.c \
    2.49  	aica/aica.h aica/audio.c aica/audio.h pvr2/pvr2.c pvr2/pvr2.h \
    2.50 @@ -461,13 +461,13 @@
    2.51  @BUILD_SH4X86_TRUE@test_testsh4x86_SOURCES = test/testsh4x86.c x86dasm/x86dasm.c \
    2.52  @BUILD_SH4X86_TRUE@	x86dasm/x86dasm.h x86dasm/i386-dis.c x86dasm/dis-init.c \
    2.53  @BUILD_SH4X86_TRUE@	x86dasm/dis-buf.c \
    2.54 -@BUILD_SH4X86_TRUE@	sh4/sh4trans.c sh4/sh4x86.c sh4/xltcache.c \
    2.55 -@BUILD_SH4X86_TRUE@	sh4/xltcache.h mem.c util.c 
    2.56 +@BUILD_SH4X86_TRUE@	sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c \
    2.57 +@BUILD_SH4X86_TRUE@	xlat/xltcache.h mem.c util.c 
    2.58  
    2.59  lxdream_LDADD = @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@ @PULSE_LIBS@ @ESOUND_LIBS@ @ALSA_LIBS@ @SDL_LIBS@ $(INTLLIBS)
    2.60  gendec_LDADD = @GLIB_LIBS@ @GTK_LIBS@ $(INTLLIBS)
    2.61  genglsl_LDADD = @GLIB_LIBS@ @GTK_LIBS@ $(INTLLIBS)
    2.62 -test_testxlt_SOURCES = test/testxlt.c sh4/xltcache.c sh4/xltcache.h
    2.63 +test_testxlt_SOURCES = test/testxlt.c xlat/xltcache.c xlat/xltcache.h
    2.64  all: $(BUILT_SOURCES)
    2.65  	$(MAKE) $(AM_MAKEFLAGS) all-am
    2.66  
    2.67 @@ -1003,19 +1003,19 @@
    2.68  @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
    2.69  @am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o sh4stat.obj `if test -f 'sh4/sh4stat.c'; then $(CYGPATH_W) 'sh4/sh4stat.c'; else $(CYGPATH_W) '$(srcdir)/sh4/sh4stat.c'; fi`
    2.70  
    2.71 -xltcache.o: sh4/xltcache.c
    2.72 -@am__fastdepCC_TRUE@	if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xltcache.o -MD -MP -MF "$(DEPDIR)/xltcache.Tpo" -c -o xltcache.o `test -f 'sh4/xltcache.c' || echo '$(srcdir)/'`sh4/xltcache.c; \
    2.73 +xltcache.o: xlat/xltcache.c
    2.74 +@am__fastdepCC_TRUE@	if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xltcache.o -MD -MP -MF "$(DEPDIR)/xltcache.Tpo" -c -o xltcache.o `test -f 'xlat/xltcache.c' || echo '$(srcdir)/'`xlat/xltcache.c; \
    2.75  @am__fastdepCC_TRUE@	then mv -f "$(DEPDIR)/xltcache.Tpo" "$(DEPDIR)/xltcache.Po"; else rm -f "$(DEPDIR)/xltcache.Tpo"; exit 1; fi
    2.76 -@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='sh4/xltcache.c' object='xltcache.o' libtool=no @AMDEPBACKSLASH@
    2.77 +@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='xlat/xltcache.c' object='xltcache.o' libtool=no @AMDEPBACKSLASH@
    2.78  @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
    2.79 -@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xltcache.o `test -f 'sh4/xltcache.c' || echo '$(srcdir)/'`sh4/xltcache.c
    2.80 +@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xltcache.o `test -f 'xlat/xltcache.c' || echo '$(srcdir)/'`xlat/xltcache.c
    2.81  
    2.82 -xltcache.obj: sh4/xltcache.c
    2.83 -@am__fastdepCC_TRUE@	if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xltcache.obj -MD -MP -MF "$(DEPDIR)/xltcache.Tpo" -c -o xltcache.obj `if test -f 'sh4/xltcache.c'; then $(CYGPATH_W) 'sh4/xltcache.c'; else $(CYGPATH_W) '$(srcdir)/sh4/xltcache.c'; fi`; \
    2.84 +xltcache.obj: xlat/xltcache.c
    2.85 +@am__fastdepCC_TRUE@	if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT xltcache.obj -MD -MP -MF "$(DEPDIR)/xltcache.Tpo" -c -o xltcache.obj `if test -f 'xlat/xltcache.c'; then $(CYGPATH_W) 'xlat/xltcache.c'; else $(CYGPATH_W) '$(srcdir)/xlat/xltcache.c'; fi`; \
    2.86  @am__fastdepCC_TRUE@	then mv -f "$(DEPDIR)/xltcache.Tpo" "$(DEPDIR)/xltcache.Po"; else rm -f "$(DEPDIR)/xltcache.Tpo"; exit 1; fi
    2.87 -@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='sh4/xltcache.c' object='xltcache.obj' libtool=no @AMDEPBACKSLASH@
    2.88 +@AMDEP_TRUE@@am__fastdepCC_FALSE@	source='xlat/xltcache.c' object='xltcache.obj' libtool=no @AMDEPBACKSLASH@
    2.89  @AMDEP_TRUE@@am__fastdepCC_FALSE@	DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
    2.90 -@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xltcache.obj `if test -f 'sh4/xltcache.c'; then $(CYGPATH_W) 'sh4/xltcache.c'; else $(CYGPATH_W) '$(srcdir)/sh4/xltcache.c'; fi`
    2.91 +@am__fastdepCC_FALSE@	$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o xltcache.obj `if test -f 'xlat/xltcache.c'; then $(CYGPATH_W) 'xlat/xltcache.c'; else $(CYGPATH_W) '$(srcdir)/xlat/xltcache.c'; fi`
    2.92  
    2.93  pmm.o: sh4/pmm.c
    2.94  @am__fastdepCC_TRUE@	if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT pmm.o -MD -MP -MF "$(DEPDIR)/pmm.Tpo" -c -o pmm.o `test -f 'sh4/pmm.c' || echo '$(srcdir)/'`sh4/pmm.c; \

     3.1 --- a/src/sdram.c	Wed Mar 04 23:04:54 2009 +0000
     3.2 +++ b/src/sdram.c	Wed Mar 04 23:12:21 2009 +0000
     3.3 @@ -20,7 +20,7 @@
     3.4  #include "lxdream.h"
     3.5  #include "mem.h"
     3.6  #include "dreamcast.h"
     3.7 -#include "sh4/xltcache.h"
     3.8 +#include "xlat/xltcache.h"
     3.9  #include <string.h>
    3.10  
    3.11  

     4.1 --- a/src/sh4/ia32abi.h	Wed Mar 04 23:04:54 2009 +0000
     4.2 +++ b/src/sh4/ia32abi.h	Wed Mar 04 23:12:21 2009 +0000
     4.3 @@ -27,9 +27,9 @@
     4.4  static inline void decode_address( int addr_reg )
     4.5  {
     4.6      uintptr_t base = (sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space;
     4.7 -    MOV_r32_r32( addr_reg, R_ECX ); 
     4.8 -    SHR_imm8_r32( 12, R_ECX ); 
     4.9 -    MOV_r32disp32x4_r32( R_ECX, base, R_ECX );
    4.10 +    MOVL_r32_r32( addr_reg, REG_ECX ); 
    4.11 +    SHRL_imm_r32( 12, REG_ECX ); 
    4.12 +    MOVP_sib_rptr( 2, REG_ECX, -1, base, REG_ECX );
    4.13  }
    4.14  
    4.15  /**
    4.16 @@ -38,134 +38,138 @@
    4.17   */
    4.18  static inline void call_func0( void *ptr )
    4.19  {
    4.20 -    load_imm32(R_ECX, (uint32_t)ptr);
    4.21 -    CALL_r32(R_ECX);
    4.22 +    load_imm32(REG_ECX, (uint32_t)ptr);
    4.23 +    CALL_r32(REG_ECX);
    4.24  }
    4.25  
    4.26  #ifdef HAVE_FASTCALL
    4.27  static inline void call_func1( void *ptr, int arg1 )
    4.28  {
    4.29 -    if( arg1 != R_EAX ) {
    4.30 -        MOV_r32_r32( arg1, R_EAX );
    4.31 +    if( arg1 != REG_EAX ) {
    4.32 +        MOVL_r32_r32( arg1, REG_EAX );
    4.33      }
    4.34 -    load_imm32(R_ECX, (uint32_t)ptr);
    4.35 -    CALL_r32(R_ECX);
    4.36 +    MOVP_immptr_rptr((uintptr_t)ptr, REG_ECX);
    4.37 +    CALL_r32(REG_ECX);
    4.38  }
    4.39  
    4.40  static inline void call_func1_r32( int addr_reg, int arg1 )
    4.41  {
    4.42 -    if( arg1 != R_EAX ) {
    4.43 -        MOV_r32_r32( arg1, R_EAX );
    4.44 +    if( arg1 != REG_EAX ) {
    4.45 +        MOVL_r32_r32( arg1, REG_EAX );
    4.46      }
    4.47      CALL_r32(addr_reg);
    4.48  }
    4.49  
    4.50  static inline void call_func1_r32disp8( int preg, uint32_t disp8, int arg1 )
    4.51  {
    4.52 -    if( arg1 != R_EAX ) {
    4.53 -        MOV_r32_r32( arg1, R_EAX );
    4.54 +    if( arg1 != REG_EAX ) {
    4.55 +        MOVL_r32_r32( arg1, REG_EAX );
    4.56      }
    4.57 -    CALL_r32disp8(preg, disp8);
    4.58 +    CALL_r32disp(preg, disp8);
    4.59  }
    4.60  
    4.61  static inline void call_func1_r32disp8_exc( int preg, uint32_t disp8, int arg1, int pc )
    4.62  {
    4.63 -    if( arg1 != R_EAX ) {
    4.64 -        MOV_r32_r32( arg1, R_EAX );
    4.65 +    if( arg1 != REG_EAX ) {
    4.66 +        MOVL_r32_r32( arg1, REG_EAX );
    4.67      }
    4.68 -    load_exc_backpatch(R_EDX);
    4.69 -    CALL_r32disp8(preg, disp8);
    4.70 +    MOVP_immptr_rptr(0,REG_EDX);
    4.71 +    sh4_x86_add_backpatch(xlat_output, pc, -2);
    4.72 +    CALL_r32disp(preg, disp8);
    4.73  }
    4.74  
    4.75  static inline void call_func2( void *ptr, int arg1, int arg2 )
    4.76  {
    4.77 -    if( arg2 != R_EDX ) {
    4.78 -        MOV_r32_r32( arg2, R_EDX );
    4.79 +    if( arg2 != REG_EDX ) {
    4.80 +        MOVL_r32_r32( arg2, REG_EDX );
    4.81      }
    4.82 -    if( arg1 != R_EAX ) {
    4.83 -        MOV_r32_r32( arg1, R_EAX );
    4.84 +    if( arg1 != REG_EAX ) {
    4.85 +        MOVL_r32_r32( arg1, REG_EAX );
    4.86      }
    4.87 -    load_imm32(R_ECX, (uint32_t)ptr);
    4.88 -    CALL_r32(R_ECX);
    4.89 +    MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);
    4.90 +    CALL_r32(REG_ECX);
    4.91  }
    4.92  
    4.93  static inline void call_func2_r32( int addr_reg, int arg1, int arg2 )
    4.94  {
    4.95 -    if( arg2 != R_EDX ) {
    4.96 -        MOV_r32_r32( arg2, R_EDX );
    4.97 +    if( arg2 != REG_EDX ) {
    4.98 +        MOVL_r32_r32( arg2, REG_EDX );
    4.99      }
   4.100 -    if( arg1 != R_EAX ) {
   4.101 -        MOV_r32_r32( arg1, R_EAX );
   4.102 +    if( arg1 != REG_EAX ) {
   4.103 +        MOVL_r32_r32( arg1, REG_EAX );
   4.104      }
   4.105      CALL_r32(addr_reg);
   4.106  }
   4.107  
   4.108  static inline void call_func2_r32disp8( int preg, uint32_t disp8, int arg1, int arg2 )
   4.109  {
   4.110 -    if( arg2 != R_EDX ) {
   4.111 -        MOV_r32_r32( arg2, R_EDX );
   4.112 +    if( arg2 != REG_EDX ) {
   4.113 +        MOVL_r32_r32( arg2, REG_EDX );
   4.114      }
   4.115 -    if( arg1 != R_EAX ) {
   4.116 -        MOV_r32_r32( arg1, R_EAX );
   4.117 +    if( arg1 != REG_EAX ) {
   4.118 +        MOVL_r32_r32( arg1, REG_EAX );
   4.119      }
   4.120 -    CALL_r32disp8(preg, disp8);
   4.121 +    CALL_r32disp(preg, disp8);
   4.122  }
   4.123  
   4.124  static inline void call_func2_r32disp8_exc( int preg, uint32_t disp8, int arg1, int arg2, int pc )
   4.125  {
   4.126 -    if( arg2 != R_EDX ) {
   4.127 -        MOV_r32_r32( arg2, R_EDX );
   4.128 +    if( arg2 != REG_EDX ) {
   4.129 +        MOVL_r32_r32( arg2, REG_EDX );
   4.130      }
   4.131 -    if( arg1 != R_EAX ) {
   4.132 -        MOV_r32_r32( arg1, R_EAX );
   4.133 +    if( arg1 != REG_EAX ) {
   4.134 +        MOVL_r32_r32( arg1, REG_EAX );
   4.135      }
   4.136 -    MOV_backpatch_esp8( 0 );
   4.137 -    CALL_r32disp8(preg, disp8);
   4.138 +    MOVL_imm32_rspdisp(0,0);
   4.139 +    sh4_x86_add_backpatch(xlat_output, pc, -2);
   4.140 +    CALL_r32disp(preg, disp8);
   4.141  }
   4.142  
   4.143  
   4.144  
   4.145  static inline void call_func1_exc( void *ptr, int arg1, int pc )
   4.146  {
   4.147 -    if( arg1 != R_EAX ) {
   4.148 -        MOV_r32_r32( arg1, R_EAX );
   4.149 +    if( arg1 != REG_EAX ) {
   4.150 +        MOVL_r32_r32( arg1, REG_EAX );
   4.151      }
   4.152 -    load_exc_backpatch(R_EDX);
   4.153 -    load_imm32(R_ECX, (uint32_t)ptr);
   4.154 -    CALL_r32(R_ECX);
   4.155 +    MOVP_immptr_rptr(0,REG_EDX);
   4.156 +    sh4_x86_add_backpatch(xlat_output, pc, -2);
   4.157 +    MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);
   4.158 +    CALL_r32(REG_ECX);
   4.159  }   
   4.160  
   4.161  static inline void call_func2_exc( void *ptr, int arg1, int arg2, int pc )
   4.162  {
   4.163 -    if( arg2 != R_EDX ) {
   4.164 -        MOV_r32_r32( arg2, R_EDX );
   4.165 +    if( arg2 != REG_EDX ) {
   4.166 +        MOVL_r32_r32( arg2, REG_EDX );
   4.167      }
   4.168 -    if( arg1 != R_EAX ) {
   4.169 -        MOV_r32_r32( arg1, R_EAX );
   4.170 +    if( arg1 != REG_EAX ) {
   4.171 +        MOVL_r32_r32( arg1, REG_EAX );
   4.172      }
   4.173 -    MOV_backpatch_esp8(0);
   4.174 -    load_imm32(R_ECX, (uint32_t)ptr);
   4.175 -    CALL_r32(R_ECX);
   4.176 +    MOVL_imm32_rspdisp(0,0);
   4.177 +    sh4_x86_add_backpatch(xlat_output, pc, -2);
   4.178 +    MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);
   4.179 +    CALL_r32(REG_ECX);
   4.180  }
   4.181  
   4.182  #else
   4.183  static inline void call_func1( void *ptr, int arg1 )
   4.184  {
   4.185 -    SUB_imm8s_r32( 12, R_ESP );
   4.186 +    SUBL_imms_r32( 12, REG_ESP );
   4.187      PUSH_r32(arg1);
   4.188 -    load_imm32(R_ECX, (uint32_t)ptr);
   4.189 -    CALL_r32(R_ECX);
   4.190 -    ADD_imm8s_r32( 16, R_ESP );
   4.191 +    MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);
   4.192 +    CALL_r32(REG_ECX);
   4.193 +    ADDL_imms_r32( 16, REG_ESP );
   4.194  }
   4.195  
   4.196  static inline void call_func2( void *ptr, int arg1, int arg2 )
   4.197  {
   4.198 -    SUB_imm8s_r32( 8, R_ESP );
   4.199 +    SUBL_imms_r32( 8, REG_ESP );
   4.200      PUSH_r32(arg2);
   4.201      PUSH_r32(arg1);
   4.202 -    load_imm32(R_ECX, (uint32_t)ptr);
   4.203 -    CALL_r32(R_ECX);
   4.204 -    ADD_imm8s_r32( 16, R_ESP );
   4.205 +    MOVP_immptr_rptr((uint32_t)ptr, REG_ECX);
   4.206 +    CALL_r32(REG_ECX);
   4.207 +    ADDL_imms_r32( 16, REG_ESP );
   4.208  }
   4.209  
   4.210  #endif
   4.211 @@ -178,15 +182,15 @@
   4.212   */
   4.213  void enter_block( ) 
   4.214  {
   4.215 -    PUSH_r32(R_EBP);
   4.216 -    load_ptr( R_EBP, ((uint8_t *)&sh4r) + 128 );
   4.217 -    SUB_imm8s_r32( 8, R_ESP ); 
   4.218 +    PUSH_r32(REG_EBP);
   4.219 +    load_ptr( REG_EBP, ((uint8_t *)&sh4r) + 128 );
   4.220 +    SUBL_imms_r32( 8, REG_ESP ); 
   4.221  }
   4.222  
   4.223  static inline void exit_block( )
   4.224  {
   4.225 -    ADD_imm8s_r32( 8, R_ESP );
   4.226 -    POP_r32(R_EBP);
   4.227 +    ADDL_imms_r32( 8, REG_ESP );
   4.228 +    POP_r32(REG_EBP);
   4.229      RET();
   4.230  }
   4.231  
   4.232 @@ -195,13 +199,13 @@
   4.233   */
   4.234  void exit_block_pcset( sh4addr_t pc )
   4.235  {
   4.236 -    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.237 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   4.238 -    load_spreg( R_EAX, R_PC );
   4.239 +    load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.240 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );    // 6
   4.241 +    load_spreg( REG_EAX, R_PC );
   4.242      if( sh4_x86.tlb_on ) {
   4.243 -        call_func1(xlat_get_code_by_vma,R_EAX);
   4.244 +        call_func1(xlat_get_code_by_vma,REG_EAX);
   4.245      } else {
   4.246 -        call_func1(xlat_get_code,R_EAX);
   4.247 +        call_func1(xlat_get_code,REG_EAX);
   4.248      }
   4.249      exit_block();
   4.250  }
   4.251 @@ -211,14 +215,14 @@
   4.252   */
   4.253  void exit_block_newpcset( sh4addr_t pc )
   4.254  {
   4.255 -    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.256 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   4.257 -    load_spreg( R_EAX, R_NEW_PC );
   4.258 -    store_spreg( R_EAX, R_PC );
   4.259 +    load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.260 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );    // 6
   4.261 +    load_spreg( REG_EAX, R_NEW_PC );
   4.262 +    store_spreg( REG_EAX, R_PC );
   4.263      if( sh4_x86.tlb_on ) {
   4.264 -        call_func1(xlat_get_code_by_vma,R_EAX);
   4.265 +        call_func1(xlat_get_code_by_vma,REG_EAX);
   4.266      } else {
   4.267 -        call_func1(xlat_get_code,R_EAX);
   4.268 +        call_func1(xlat_get_code,REG_EAX);
   4.269      }
   4.270      exit_block();
   4.271  }
   4.272 @@ -229,18 +233,18 @@
   4.273   */
   4.274  void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
   4.275  {
   4.276 -    load_imm32( R_ECX, pc );                            // 5
   4.277 -    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   4.278 +    load_imm32( REG_ECX, pc );                            // 5
   4.279 +    store_spreg( REG_ECX, REG_OFFSET(pc) );               // 3
   4.280      if( IS_IN_ICACHE(pc) ) {
   4.281 -        MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
   4.282 -        AND_imm8s_r32( 0xFC, R_EAX ); // 3
   4.283 +        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
   4.284 +        ANDL_imms_r32( 0xFFFFFFFC, REG_EAX ); // 3
   4.285      } else if( sh4_x86.tlb_on ) {
   4.286 -        call_func1(xlat_get_code_by_vma,R_ECX);
   4.287 +        call_func1(xlat_get_code_by_vma,REG_ECX);
   4.288      } else {
   4.289 -        call_func1(xlat_get_code,R_ECX);
   4.290 +        call_func1(xlat_get_code,REG_ECX);
   4.291      }
   4.292 -    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.293 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   4.294 +    load_imm32( REG_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.295 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
   4.296      exit_block();
   4.297  }
   4.298  
   4.299 @@ -249,19 +253,19 @@
   4.300   */
   4.301  void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
   4.302  {
   4.303 -    load_imm32( R_ECX, pc - sh4_x86.block_start_pc );   // 5
   4.304 -    ADD_sh4r_r32( R_PC, R_ECX );
   4.305 -    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   4.306 +    load_imm32( REG_ECX, pc - sh4_x86.block_start_pc );   // 5
   4.307 +    ADDL_rbpdisp_r32( R_PC, REG_ECX );
   4.308 +    store_spreg( REG_ECX, R_PC );               // 3
   4.309      if( IS_IN_ICACHE(pc) ) {
   4.310 -        MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
   4.311 -        AND_imm8s_r32( 0xFC, R_EAX ); // 3
   4.312 +        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
   4.313 +        ANDL_imms_r32( 0xFFFFFFFC, REG_EAX ); // 3
   4.314      } else if( sh4_x86.tlb_on ) {
   4.315 -        call_func1(xlat_get_code_by_vma,R_ECX);
   4.316 +        call_func1(xlat_get_code_by_vma,REG_ECX);
   4.317      } else {
   4.318 -        call_func1(xlat_get_code,R_ECX);
   4.319 +        call_func1(xlat_get_code,REG_ECX);
   4.320      }
   4.321 -    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.322 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   4.323 +    load_imm32( REG_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.324 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
   4.325      exit_block();
   4.326  }
   4.327  
   4.328 @@ -270,18 +274,18 @@
   4.329   */
   4.330  void exit_block_exc( int code, sh4addr_t pc )
   4.331  {
   4.332 -    load_imm32( R_ECX, pc - sh4_x86.block_start_pc );   // 5
   4.333 -    ADD_r32_sh4r( R_ECX, R_PC );
   4.334 -    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.335 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   4.336 -    load_imm32( R_EAX, code );
   4.337 -    call_func1( sh4_raise_exception, R_EAX );
   4.338 +    load_imm32( REG_ECX, pc - sh4_x86.block_start_pc );   // 5
   4.339 +    ADDL_r32_rbpdisp( REG_ECX, R_PC );
   4.340 +    load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   4.341 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
   4.342 +    load_imm32( REG_EAX, code );
   4.343 +    call_func1( sh4_raise_exception, REG_EAX );
   4.344      
   4.345 -    load_spreg( R_EAX, R_PC );
   4.346 +    load_spreg( REG_EAX, R_PC );
   4.347      if( sh4_x86.tlb_on ) {
   4.348 -        call_func1(xlat_get_code_by_vma,R_EAX);
   4.349 +        call_func1(xlat_get_code_by_vma,REG_EAX);
   4.350      } else {
   4.351 -        call_func1(xlat_get_code,R_EAX);
   4.352 +        call_func1(xlat_get_code,REG_EAX);
   4.353      }
   4.354  
   4.355      exit_block();
   4.356 @@ -299,36 +303,36 @@
   4.357          unsigned int i;
   4.358          // Raise exception
   4.359          uint8_t *end_ptr = xlat_output;
   4.360 -        MOV_r32_r32( R_EDX, R_ECX );
   4.361 -        ADD_r32_r32( R_EDX, R_ECX );
   4.362 -        ADD_r32_sh4r( R_ECX, R_PC );
   4.363 -        MOV_moff32_EAX( &sh4_cpu_period );
   4.364 -        MUL_r32( R_EDX );
   4.365 -        ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
   4.366 +        MOVL_r32_r32( REG_EDX, REG_ECX );
   4.367 +        ADDL_r32_r32( REG_EDX, REG_ECX );
   4.368 +        ADDL_r32_rbpdisp( REG_ECX, R_PC );
   4.369 +        MOVL_moffptr_eax( &sh4_cpu_period );
   4.370 +        MULL_r32( REG_EDX );
   4.371 +        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
   4.372  
   4.373 -        POP_r32(R_EAX);
   4.374 -        call_func1( sh4_raise_exception, R_EAX );
   4.375 -        load_spreg( R_EAX, R_PC );
   4.376 +        POP_r32(REG_EAX);
   4.377 +        call_func1( sh4_raise_exception, REG_EAX );
   4.378 +        load_spreg( REG_EAX, R_PC );
   4.379          if( sh4_x86.tlb_on ) {
   4.380 -            call_func1(xlat_get_code_by_vma,R_EAX);
   4.381 +            call_func1(xlat_get_code_by_vma,REG_EAX);
   4.382          } else {
   4.383 -            call_func1(xlat_get_code,R_EAX);
   4.384 +            call_func1(xlat_get_code,REG_EAX);
   4.385          }
   4.386          exit_block();
   4.387  
   4.388          // Exception already raised - just cleanup
   4.389          uint8_t *preexc_ptr = xlat_output;
   4.390 -        MOV_r32_r32( R_EDX, R_ECX );
   4.391 -        ADD_r32_r32( R_EDX, R_ECX );
   4.392 -        ADD_r32_sh4r( R_ECX, R_SPC );
   4.393 -        MOV_moff32_EAX( &sh4_cpu_period );
   4.394 -        MUL_r32( R_EDX );
   4.395 -        ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
   4.396 -        load_spreg( R_EAX, R_PC );
   4.397 +        MOVL_r32_r32( REG_EDX, REG_ECX );
   4.398 +        ADDL_r32_r32( REG_EDX, REG_ECX );
   4.399 +        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
   4.400 +        MOVL_moffptr_eax( &sh4_cpu_period );
   4.401 +        MULL_r32( REG_EDX );
   4.402 +        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
   4.403 +        load_spreg( REG_EAX, R_PC );
   4.404          if( sh4_x86.tlb_on ) {
   4.405 -            call_func1(xlat_get_code_by_vma,R_EAX);
   4.406 +            call_func1(xlat_get_code_by_vma,REG_EAX);
   4.407          } else {
   4.408 -            call_func1(xlat_get_code,R_EAX);
   4.409 +            call_func1(xlat_get_code,REG_EAX);
   4.410          }
   4.411          exit_block();
   4.412  
   4.413 @@ -340,15 +344,15 @@
   4.414                  } else {
   4.415                      *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
   4.416                  }
   4.417 -                load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   4.418 +                load_imm32( REG_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   4.419                  int rel = preexc_ptr - xlat_output;
   4.420 -                JMP_rel(rel);
   4.421 +                JMP_prerel(rel);
   4.422              } else {
   4.423                  *fixup_addr += xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
   4.424                  PUSH_imm32( sh4_x86.backpatch_list[i].exc_code );
   4.425 -                load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   4.426 +                load_imm32( REG_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   4.427                  int rel = end_ptr - xlat_output;
   4.428 -                JMP_rel(rel);
   4.429 +                JMP_prerel(rel);
   4.430              }
   4.431          }
   4.432      }

     5.1 --- a/src/sh4/ia64abi.h	Wed Mar 04 23:04:54 2009 +0000
     5.2 +++ b/src/sh4/ia64abi.h	Wed Mar 04 23:12:21 2009 +0000
     5.3 @@ -24,13 +24,13 @@
     5.4  
     5.5  #define load_ptr( reg, ptr ) load_imm64( reg, (uint64_t)ptr );
     5.6  
     5.7 -static inline decode_address( int addr_reg )
     5.8 +static inline void decode_address( int addr_reg )
     5.9  {
    5.10      uintptr_t base = (sh4r.xlat_sh4_mode&SR_MD) ? (uintptr_t)sh4_address_space : (uintptr_t)sh4_user_address_space;
    5.11 -    MOV_r32_r32( addr_reg, R_ECX ); 
    5.12 -    SHR_imm8_r32( 12, R_ECX ); 
    5.13 -    load_ptr( R_EDI, base );
    5.14 -    REXW(); OP(0x8B); OP(0x0C); OP(0xCF);   // mov.q [%rdi + %rcx*8], %rcx
    5.15 +    MOVL_r32_r32( addr_reg, REG_RCX ); 
    5.16 +    SHRL_imm_r32( 12, REG_RCX ); 
    5.17 +    MOVP_immptr_rptr( base, REG_RDI );
    5.18 +    MOVP_sib_rptr(3, REG_RCX, REG_RDI, 0, REG_RCX);
    5.19  }
    5.20  
    5.21  /**
    5.22 @@ -41,58 +41,59 @@
    5.23  #define CALL_FUNC0_SIZE 12
    5.24  static inline void call_func0( void *ptr )
    5.25  {
    5.26 -    load_imm64(R_EAX, (uint64_t)ptr);
    5.27 -    CALL_r32(R_EAX);
    5.28 +    MOVQ_imm64_r64((uint64_t)ptr, REG_RAX);
    5.29 +    CALL_r32(REG_RAX);
    5.30  }
    5.31  
    5.32 -#define CALL_FUNC1_SIZE 14
    5.33  static inline void call_func1( void *ptr, int arg1 )
    5.34  {
    5.35 -    REXW(); MOV_r32_r32(arg1, R_EDI);
    5.36 +    MOVQ_r64_r64(arg1, REG_RDI);
    5.37      call_func0(ptr);
    5.38  }
    5.39  
    5.40  static inline void call_func1_exc( void *ptr, int arg1, int pc )
    5.41  {
    5.42 -    REXW(); MOV_r32_r32(arg1, R_EDI);
    5.43 -    load_exc_backpatch(R_ESI);
    5.44 +    MOVQ_r64_r64(arg1, REG_RDI);
    5.45 +    MOVP_immptr_rptr(0, REG_RSI);
    5.46 +    sh4_x86_add_backpatch( xlat_output, pc, -2 );
    5.47      call_func0(ptr);
    5.48  }
    5.49  
    5.50  static inline void call_func1_r32disp8( int preg, uint32_t disp8, int arg1 )
    5.51  {
    5.52 -    REXW(); MOV_r32_r32(arg1, R_EDI);
    5.53 -    CALL_r32disp8(preg, disp8);    
    5.54 +    MOVQ_r64_r64(arg1, REG_RDI);
    5.55 +    CALL_r32disp(preg, disp8);    
    5.56  }
    5.57  
    5.58  static inline void call_func1_r32disp8_exc( int preg, uint32_t disp8, int arg1, int pc )
    5.59  {
    5.60 -    REXW(); MOV_r32_r32(arg1, R_EDI);
    5.61 -    load_exc_backpatch(R_ESI);
    5.62 -    CALL_r32disp8(preg, disp8);
    5.63 +    MOVQ_r64_r64(arg1, REG_RDI);
    5.64 +    MOVP_immptr_rptr(0, REG_RSI);
    5.65 +    sh4_x86_add_backpatch( xlat_output, pc, -2 );
    5.66 +    CALL_r32disp(preg, disp8);
    5.67  }
    5.68  
    5.69 -#define CALL_FUNC2_SIZE 16
    5.70  static inline void call_func2( void *ptr, int arg1, int arg2 )
    5.71  {
    5.72 -    REXW(); MOV_r32_r32(arg1, R_EDI);
    5.73 -    REXW(); MOV_r32_r32(arg2, R_ESI);
    5.74 +    MOVQ_r64_r64(arg1, REG_RDI);
    5.75 +    MOVQ_r64_r64(arg2, REG_RSI);
    5.76      call_func0(ptr);
    5.77  }
    5.78  
    5.79  static inline void call_func2_r32disp8( int preg, uint32_t disp8, int arg1, int arg2 )
    5.80  {
    5.81 -    REXW(); MOV_r32_r32(arg1, R_EDI);
    5.82 -    REXW(); MOV_r32_r32(arg2, R_ESI);
    5.83 -    CALL_r32disp8(preg, disp8);    
    5.84 +    MOVQ_r64_r64(arg1, REG_RDI);
    5.85 +    MOVQ_r64_r64(arg2, REG_RSI);
    5.86 +    CALL_r32disp(preg, disp8);    
    5.87  }
    5.88  
    5.89  static inline void call_func2_r32disp8_exc( int preg, uint32_t disp8, int arg1, int arg2, int pc )
    5.90  {
    5.91 -    REXW(); MOV_r32_r32(arg1, R_EDI);
    5.92 -    REXW(); MOV_r32_r32(arg2, R_ESI);
    5.93 -    load_exc_backpatch(R_EDX);
    5.94 -    CALL_r32disp8(preg, disp8);
    5.95 +    MOVQ_r64_r64(arg1, REG_RDI);
    5.96 +    MOVQ_r64_r64(arg2, REG_RSI);
    5.97 +    MOVP_immptr_rptr(0, REG_RDX);
    5.98 +    sh4_x86_add_backpatch( xlat_output, pc, -2 );
    5.99 +    CALL_r32disp(preg, disp8);
   5.100  }
   5.101  
   5.102  
   5.103 @@ -103,16 +104,16 @@
   5.104   */
   5.105  void enter_block( ) 
   5.106  {
   5.107 -    PUSH_r32(R_EBP);
   5.108 -    load_ptr( R_EBP, ((uint8_t *)&sh4r) + 128 );
   5.109 +    PUSH_r32(REG_RBP);
   5.110 +    load_ptr( REG_RBP, ((uint8_t *)&sh4r) + 128 );
   5.111      // Minimum aligned allocation is 16 bytes
   5.112 -    REXW(); SUB_imm8s_r32( 16, R_ESP );
   5.113 +    SUBQ_imms_r64( 16, REG_RSP );
   5.114  }
   5.115  
   5.116  static inline void exit_block( )
   5.117  {
   5.118 -    REXW(); ADD_imm8s_r32( 16, R_ESP );
   5.119 -    POP_r32(R_EBP);
   5.120 +    ADDQ_imms_r64( 16, REG_RSP );
   5.121 +    POP_r32(REG_RBP);
   5.122      RET();
   5.123  }
   5.124  
   5.125 @@ -121,13 +122,13 @@
   5.126   */
   5.127  void exit_block_pcset( sh4addr_t pc )
   5.128  {
   5.129 -    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.130 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   5.131 -    load_spreg( R_EAX, R_PC );
   5.132 +    load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.133 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );    // 6
   5.134 +    load_spreg( REG_RAX, R_PC );
   5.135      if( sh4_x86.tlb_on ) {
   5.136 -        call_func1(xlat_get_code_by_vma,R_EAX);
   5.137 +        call_func1(xlat_get_code_by_vma,REG_RAX);
   5.138      } else {
   5.139 -        call_func1(xlat_get_code,R_EAX);
   5.140 +        call_func1(xlat_get_code,REG_RAX);
   5.141      }
   5.142      exit_block();
   5.143  }
   5.144 @@ -137,14 +138,14 @@
   5.145   */
   5.146  void exit_block_newpcset( sh4addr_t pc )
   5.147  {
   5.148 -    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.149 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );    // 6
   5.150 -    load_spreg( R_EAX, R_NEW_PC );
   5.151 -    store_spreg( R_EAX, R_PC );
   5.152 +    load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.153 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );    // 6
   5.154 +    load_spreg( REG_RAX, R_NEW_PC );
   5.155 +    store_spreg( REG_RAX, R_PC );
   5.156      if( sh4_x86.tlb_on ) {
   5.157 -        call_func1(xlat_get_code_by_vma,R_EAX);
   5.158 +        call_func1(xlat_get_code_by_vma,REG_RAX);
   5.159      } else {
   5.160 -        call_func1(xlat_get_code,R_EAX);
   5.161 +        call_func1(xlat_get_code,REG_RAX);
   5.162      }
   5.163      exit_block();
   5.164  }
   5.165 @@ -155,18 +156,18 @@
   5.166   */
   5.167  void exit_block_abs( sh4addr_t pc, sh4addr_t endpc )
   5.168  {
   5.169 -    load_imm32( R_ECX, pc );                            // 5
   5.170 -    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   5.171 +    load_imm32( REG_RCX, pc );                            // 5
   5.172 +    store_spreg( REG_RCX, REG_OFFSET(pc) );               // 3
   5.173      if( IS_IN_ICACHE(pc) ) {
   5.174 -        REXW(); MOV_moff32_EAX( xlat_get_lut_entry(pc) );
   5.175 -        REXW(); AND_imm8s_r32( 0xFC, R_EAX ); // 4
   5.176 +        MOVP_moffptr_rax( xlat_get_lut_entry(pc) );
   5.177 +        ANDQ_imms_r64( 0xFFFFFFFC, REG_RAX ); // 4
   5.178      } else if( sh4_x86.tlb_on ) {
   5.179 -        call_func1(xlat_get_code_by_vma, R_ECX);
   5.180 +        call_func1(xlat_get_code_by_vma, REG_RCX);
   5.181      } else {
   5.182 -        call_func1(xlat_get_code,R_ECX);
   5.183 +        call_func1(xlat_get_code,REG_RCX);
   5.184      }
   5.185 -    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.186 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   5.187 +    load_imm32( REG_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.188 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
   5.189      exit_block();
   5.190  }
   5.191  
   5.192 @@ -178,19 +179,19 @@
   5.193   */
   5.194  void exit_block_rel( sh4addr_t pc, sh4addr_t endpc )
   5.195  {
   5.196 -    load_imm32( R_ECX, pc - sh4_x86.block_start_pc );   // 5
   5.197 -    ADD_sh4r_r32( R_PC, R_ECX );
   5.198 -    store_spreg( R_ECX, REG_OFFSET(pc) );               // 3
   5.199 +    load_imm32( REG_ECX, pc - sh4_x86.block_start_pc );   // 5
   5.200 +    ADDL_rbpdisp_r32( R_PC, REG_ECX );
   5.201 +    store_spreg( REG_ECX, REG_OFFSET(pc) );               // 3
   5.202      if( IS_IN_ICACHE(pc) ) {
   5.203 -        REXW(); MOV_moff32_EAX( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
   5.204 -        REXW(); AND_imm8s_r32( 0xFC, R_EAX ); // 4
   5.205 +        MOVP_moffptr_rax( xlat_get_lut_entry(GET_ICACHE_PHYS(pc)) ); // 5
   5.206 +        ANDQ_imms_r64( 0xFFFFFFFC, REG_RAX ); // 4
   5.207      } else if( sh4_x86.tlb_on ) {
   5.208 -        call_func1(xlat_get_code_by_vma,R_ECX);
   5.209 +        call_func1(xlat_get_code_by_vma,REG_RCX);
   5.210      } else {
   5.211 -        call_func1(xlat_get_code,R_ECX);
   5.212 +        call_func1(xlat_get_code,REG_RCX);
   5.213      }
   5.214 -    load_imm32( R_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.215 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   5.216 +    load_imm32( REG_ECX, ((endpc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.217 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
   5.218      exit_block();
   5.219  }
   5.220  
   5.221 @@ -199,18 +200,18 @@
   5.222   */
   5.223  void exit_block_exc( int code, sh4addr_t pc )
   5.224  {
   5.225 -    load_imm32( R_ECX, pc - sh4_x86.block_start_pc );   // 5
   5.226 -    ADD_r32_sh4r( R_ECX, R_PC );
   5.227 -    load_imm32( R_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.228 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
   5.229 -    load_imm32( R_EAX, code );
   5.230 -    call_func1( sh4_raise_exception, R_EAX );
   5.231 +    load_imm32( REG_ECX, pc - sh4_x86.block_start_pc );   // 5
   5.232 +    ADDL_r32_rbpdisp( REG_ECX, R_PC );
   5.233 +    load_imm32( REG_ECX, ((pc - sh4_x86.block_start_pc)>>1)*sh4_cpu_period ); // 5
   5.234 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
   5.235 +    load_imm32( REG_RAX, code );
   5.236 +    call_func1( sh4_raise_exception, REG_RAX );
   5.237      
   5.238 -    load_spreg( R_EAX, R_PC );
   5.239 +    load_spreg( REG_RAX, R_PC );
   5.240      if( sh4_x86.tlb_on ) {
   5.241 -        call_func1(xlat_get_code_by_vma,R_EAX);
   5.242 +        call_func1(xlat_get_code_by_vma,REG_RAX);
   5.243      } else {
   5.244 -        call_func1(xlat_get_code,R_EAX);
   5.245 +        call_func1(xlat_get_code,REG_RAX);
   5.246      }
   5.247  
   5.248      exit_block();
   5.249 @@ -229,31 +230,31 @@
   5.250          unsigned int i;
   5.251          // Raise exception
   5.252          uint8_t *end_ptr = xlat_output;
   5.253 -        MOV_r32_r32( R_EDX, R_ECX );
   5.254 -        ADD_r32_r32( R_EDX, R_ECX );
   5.255 -        ADD_r32_sh4r( R_ECX, R_PC );
   5.256 -        MOV_moff32_EAX( &sh4_cpu_period );
   5.257 -        MUL_r32( R_EDX );
   5.258 -        ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
   5.259 +        MOVL_r32_r32( REG_RDX, REG_RCX );
   5.260 +        ADDL_r32_r32( REG_RDX, REG_RCX );
   5.261 +        ADDL_r32_rbpdisp( REG_RCX, R_PC );
   5.262 +        MOVL_moffptr_eax( &sh4_cpu_period );
   5.263 +        MULL_r32( REG_RDX );
   5.264 +        ADDL_r32_rbpdisp( REG_RAX, REG_OFFSET(slice_cycle) );
   5.265  
   5.266          call_func0( sh4_raise_exception );
   5.267 -        load_spreg( R_EAX, R_PC );
   5.268 +        load_spreg( REG_RAX, R_PC );
   5.269          if( sh4_x86.tlb_on ) {
   5.270 -            call_func1(xlat_get_code_by_vma,R_EAX);
   5.271 +            call_func1(xlat_get_code_by_vma,REG_RAX);
   5.272          } else {
   5.273 -            call_func1(xlat_get_code,R_EAX);
   5.274 +            call_func1(xlat_get_code,REG_RAX);
   5.275          }
   5.276          exit_block();
   5.277          
   5.278          // Exception already raised - just cleanup
   5.279          uint8_t *preexc_ptr = xlat_output;
   5.280 -        MOV_r32_r32( R_EDX, R_ECX );
   5.281 -        ADD_r32_r32( R_EDX, R_ECX );
   5.282 -        ADD_r32_sh4r( R_ECX, R_SPC );
   5.283 -        MOV_moff32_EAX( &sh4_cpu_period );
   5.284 -        MUL_r32( R_EDX );
   5.285 -        ADD_r32_sh4r( R_EAX, REG_OFFSET(slice_cycle) );
   5.286 -        load_spreg( R_EDI, R_PC );
   5.287 +        MOVL_r32_r32( REG_EDX, REG_ECX );
   5.288 +        ADDL_r32_r32( REG_EDX, REG_ECX );
   5.289 +        ADDL_r32_rbpdisp( REG_ECX, R_SPC );
   5.290 +        MOVL_moffptr_eax( &sh4_cpu_period );
   5.291 +        MULL_r32( REG_EDX );
   5.292 +        ADDL_r32_rbpdisp( REG_EAX, REG_OFFSET(slice_cycle) );
   5.293 +        load_spreg( REG_RDI, R_PC );
   5.294          if( sh4_x86.tlb_on ) {
   5.295              call_func0(xlat_get_code_by_vma);
   5.296          } else {
   5.297 @@ -269,15 +270,15 @@
   5.298                  } else {
   5.299                      *fixup_addr = xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
   5.300                  }
   5.301 -                load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   5.302 +                load_imm32( REG_RDX, sh4_x86.backpatch_list[i].fixup_icount );
   5.303                  int rel = preexc_ptr - xlat_output;
   5.304 -                JMP_rel(rel);
   5.305 +                JMP_prerel(rel);
   5.306              } else {
   5.307                  *fixup_addr = xlat_output - (uint8_t *)&xlat_current_block->code[sh4_x86.backpatch_list[i].fixup_offset] - 4;
   5.308 -                load_imm32( R_EDI, sh4_x86.backpatch_list[i].exc_code );
   5.309 -                load_imm32( R_EDX, sh4_x86.backpatch_list[i].fixup_icount );
   5.310 +                load_imm32( REG_RDI, sh4_x86.backpatch_list[i].exc_code );
   5.311 +                load_imm32( REG_RDX, sh4_x86.backpatch_list[i].fixup_icount );
   5.312                  int rel = end_ptr - xlat_output;
   5.313 -                JMP_rel(rel);
   5.314 +                JMP_prerel(rel);
   5.315              }
   5.316          }
   5.317      }

     6.1 --- a/src/sh4/mmux86.c	Wed Mar 04 23:04:54 2009 +0000
     6.2 +++ b/src/sh4/mmux86.c	Wed Mar 04 23:12:21 2009 +0000
     6.3 @@ -22,19 +22,24 @@
     6.4  #include "sh4/sh4mmio.h"
     6.5  #include "sh4/sh4trans.h"
     6.6  #include "sh4/mmu.h"
     6.7 -#include "sh4/x86op.h"
     6.8 +#include "xlat/x86/x86op.h"
     6.9  
    6.10  #if SIZEOF_VOID_P == 8
    6.11 -#define ARG1 R_EDI
    6.12 -#define ARG2 R_ESI
    6.13 -#define DECODE() \
    6.14 -    MOV_imm64_r32((uintptr_t)addr_space, R_EAX);     /* movq ptr, %rax */ \
    6.15 -    REXW(); OP(0x8B); OP(0x0C); OP(0xC8)                    /* movq [%rax + %rcx*8], %rcx */
    6.16 +#define ARG1 REG_RDI
    6.17 +#define ARG2 REG_RSI
    6.18 +#define XLAT(addr_space, reg) \
    6.19 +    MOVQ_imm64_r64( (uintptr_t)addr_space, REG_RAX ); \
    6.20 +    MOVP_sib_rptr( 3, reg, REG_RAX, 0, reg );
    6.21 +#define ADDP_imms_ptr(imm,p) \
    6.22 +    MOVQ_imm64_r64((uintptr_t)p, REG_EAX ); \
    6.23 +    ADDL_imms_r32disp(imm, REG_EAX, 0);
    6.24  #else
    6.25 -#define ARG1 R_EAX
    6.26 +#define ARG1 REG_EAX
    6.27  #define ARG2 R_EDX
    6.28 -#define DECODE() \
    6.29 -    MOV_r32disp32x4_r32( R_ECX, (uintptr_t)addr_space, R_ECX );
    6.30 +#define XLAT(addr_space, reg) \
    6.31 +    MOVP_sib_rptr( 2, reg, -1, (uintptr_t)addr_space, reg ); 
    6.32 +#define ADDP_imms_ptr(imm,p) \
    6.33 +    ADDL_imms_r32disp(imm, -1, (uintptr_t)p);
    6.34  #endif
    6.35  
    6.36  void mmu_utlb_init_vtable( struct utlb_entry *ent, struct utlb_page_entry *page, gboolean writable )
    6.37 @@ -61,23 +66,18 @@
    6.38      for( i=0; i<10; i+= inc, fn += inc, out += inc ) {
    6.39          *out = xlat_output;
    6.40          if( i != 9 ) { /* read_byte_for_write doesn't increment mmu_urc, everything else does */
    6.41 -#if SIZEOF_VOID_P == 8
    6.42 -            MOV_imm64_r32((uintptr_t)&mmu_urc, R_EAX );
    6.43 -            OP(0x83); OP(0x00); OP(0x01); // ADD #1, [RAX]
    6.44 -#else 
    6.45 -            OP(0x83); MODRM_r32_disp32(0, (uintptr_t)&mmu_urc); OP(0x01); // ADD #1, mmu_urc
    6.46 -#endif
    6.47 +            ADDP_imms_ptr(1, &mmu_urc);
    6.48          }
    6.49 -        ADD_imm32_r32( ppn-vpn, ARG1 ); // 6
    6.50 +        ADDL_imms_r32( ppn-vpn, ARG1 ); // 6
    6.51          if( ent->mask >= 0xFFFFF000 ) {
    6.52              // Maps to a single page, so jump directly there
    6.53              int rel = (*fn - xlat_output);
    6.54 -            JMP_rel( rel ); // 5
    6.55 +            JMP_prerel( rel ); // 5
    6.56          } else {
    6.57 -            MOV_r32_r32( ARG1, R_ECX ); // 2
    6.58 -            SHR_imm8_r32( 12, R_ECX );  // 3
    6.59 -            DECODE();                   // 14
    6.60 -            JMP_r32disp8(R_ECX, (((uintptr_t)out) - ((uintptr_t)&page->fn)) );    // 3
    6.61 +            MOVL_r32_r32( ARG1, REG_ECX ); // 2
    6.62 +            SHRL_imm_r32( 12, REG_ECX );  // 3
    6.63 +            XLAT(addr_space, REG_ECX);                   // 14
    6.64 +            JMP_r32disp(REG_ECX, (((uintptr_t)out) - ((uintptr_t)&page->fn)) );    // 3
    6.65          }
    6.66      }
    6.67      
    6.68 @@ -95,15 +95,10 @@
    6.69      memcpy( page, &p4_region_storequeue, sizeof(struct mem_region_fn) );
    6.70  
    6.71      page->fn.prefetch = (mem_prefetch_fn_t)xlat_output;
    6.72 -#if SIZEOF_VOID_P == 8
    6.73 -    MOV_imm64_r32((uintptr_t)&mmu_urc, R_EAX );
    6.74 -    OP(0x83); OP(0x00); OP(0x01); // ADD #1, [RAX]
    6.75 -#else 
    6.76 -    OP(0x83); MODRM_r32_disp32(0, (uintptr_t)&mmu_urc); OP(0x01); // ADD #1, mmu_urc
    6.77 -#endif
    6.78 -    ADD_imm32_r32( ppn-vpn, ARG1 );
    6.79 +    ADDP_imms_ptr(1, &mmu_urc);
    6.80 +    ADDL_imms_r32( ppn-vpn, ARG1 );
    6.81      int rel = ((uint8_t *)ccn_storequeue_prefetch_tlb) - xlat_output;
    6.82 -    JMP_rel( rel );
    6.83 +    JMP_prerel( rel );
    6.84  }
    6.85  
    6.86  void mmu_utlb_1k_init_vtable( struct utlb_1k_entry *entry )
    6.87 @@ -114,31 +109,21 @@
    6.88      
    6.89      for( i=0; i<9; i++, out++ ) {
    6.90          *out = xlat_output;
    6.91 -        MOV_r32_r32( ARG1, R_ECX );
    6.92 -        SHR_imm8_r32( 10, R_ECX );
    6.93 -        AND_imm8s_r32( 0x3, R_ECX );
    6.94 -#if SIZEOF_VOID_P == 8
    6.95 -        MOV_imm64_r32( (uintptr_t)&entry->subpages[0], R_EAX );
    6.96 -        REXW(); OP(0x8B); OP(0x0C); OP(0xC8);                   /* movq [%rax + %rcx*8], %rcx */
    6.97 -#else
    6.98 -        MOV_r32disp32x4_r32( R_ECX, ((uintptr_t)&entry->subpages[0]), R_ECX );
    6.99 -#endif                
   6.100 -        JMP_r32disp8(R_ECX, (((uintptr_t)out) - ((uintptr_t)&entry->fn)) );    // 3
   6.101 +        MOVL_r32_r32( ARG1, REG_ECX );
   6.102 +        SHRL_imm_r32( 10, REG_ECX );
   6.103 +        ANDL_imms_r32( 0x3, REG_ECX );
   6.104 +        XLAT( (uintptr_t)&entry->subpages[0], REG_ECX );
   6.105 +        JMP_r32disp(REG_ECX, (((uintptr_t)out) - ((uintptr_t)&entry->fn)) );    // 3
   6.106      }
   6.107  
   6.108      out = (uint8_t **)&entry->user_fn;
   6.109      for( i=0; i<9; i++, out++ ) {
   6.110          *out = xlat_output;
   6.111 -        MOV_r32_r32( ARG1, R_ECX );
   6.112 -        SHR_imm8_r32( 10, R_ECX );
   6.113 -        AND_imm8s_r32( 0x3, R_ECX );
   6.114 -#if SIZEOF_VOID_P == 8
   6.115 -        MOV_imm64_r32( (uintptr_t)&entry->user_subpages[0], R_EAX );
   6.116 -        REXW(); OP(0x8B); OP(0x0C); OP(0xC8);                   /* movq [%rax + %rcx*8], %rcx */
   6.117 -#else
   6.118 -        MOV_r32disp32x4_r32( R_ECX, ((uintptr_t)&entry->user_subpages[0]), R_ECX );
   6.119 -#endif                
   6.120 -        JMP_r32disp8(R_ECX, (((uintptr_t)out) - ((uintptr_t)&entry->user_fn)) );    // 3
   6.121 +        MOVL_r32_r32( ARG1, REG_ECX );
   6.122 +        SHRL_imm_r32( 10, REG_ECX );
   6.123 +        ANDL_imms_r32( 0x3, REG_ECX );
   6.124 +        XLAT( (uintptr_t)&entry->user_subpages[0], REG_ECX );
   6.125 +        JMP_r32disp(REG_ECX, (((uintptr_t)out) - ((uintptr_t)&entry->user_fn)) );    // 3
   6.126      }
   6.127  
   6.128  }

     7.1 --- a/src/sh4/sh4.c	Wed Mar 04 23:04:54 2009 +0000
     7.2 +++ b/src/sh4/sh4.c	Wed Mar 04 23:12:21 2009 +0000
     7.3 @@ -33,7 +33,7 @@
     7.4  #include "sh4/sh4mmio.h"
     7.5  #include "sh4/sh4stat.h"
     7.6  #include "sh4/sh4trans.h"
     7.7 -#include "sh4/xltcache.h"
     7.8 +#include "xlat/xltcache.h"
     7.9  
    7.10  #ifndef M_PI
    7.11  #define M_PI        3.14159265358979323846264338327950288

     8.1 --- a/src/sh4/sh4mem.c	Wed Mar 04 23:04:54 2009 +0000
     8.2 +++ b/src/sh4/sh4mem.c	Wed Mar 04 23:12:21 2009 +0000
     8.3 @@ -27,9 +27,9 @@
     8.4  #include "dreamcast.h"
     8.5  #include "sh4/sh4core.h"
     8.6  #include "sh4/sh4mmio.h"
     8.7 -#include "sh4/xltcache.h"
     8.8  #include "sh4/mmu.h"
     8.9  #include "pvr2/pvr2.h"
    8.10 +#include "xlat/xltcache.h"
    8.11  
    8.12  /************** Obsolete methods ***************/
    8.13  

     9.1 --- a/src/sh4/sh4trans.c	Wed Mar 04 23:04:54 2009 +0000
     9.2 +++ b/src/sh4/sh4trans.c	Wed Mar 04 23:12:21 2009 +0000
     9.3 @@ -23,9 +23,9 @@
     9.4  #include "dreamcast.h"
     9.5  #include "sh4/sh4core.h"
     9.6  #include "sh4/sh4trans.h"
     9.7 -#include "sh4/xltcache.h"
     9.8  #include "sh4/sh4mmio.h"
     9.9  #include "sh4/mmu.h"
    9.10 +#include "xlat/xltcache.h"
    9.11  
    9.12  /**
    9.13   * Execute a timeslice using translated code only (ie translate/execute loop)

    10.1 --- a/src/sh4/sh4trans.h	Wed Mar 04 23:04:54 2009 +0000
    10.2 +++ b/src/sh4/sh4trans.h	Wed Mar 04 23:12:21 2009 +0000
    10.3 @@ -19,7 +19,7 @@
    10.4  #ifndef lxdream_sh4trans_H
    10.5  #define lxdream_sh4trans_H 1
    10.6  
    10.7 -#include "sh4/xltcache.h"
    10.8 +#include "xlat/xltcache.h"
    10.9  #include "dream.h"
   10.10  #include "mem.h"
   10.11  

    11.1 --- a/src/sh4/sh4x86.in	Wed Mar 04 23:04:54 2009 +0000
    11.2 +++ b/src/sh4/sh4x86.in	Wed Mar 04 23:12:21 2009 +0000
    11.3 @@ -26,17 +26,39 @@
    11.4  #endif
    11.5  
    11.6  #include "lxdream.h"
    11.7 -#include "sh4/xltcache.h"
    11.8  #include "sh4/sh4core.h"
    11.9  #include "sh4/sh4trans.h"
   11.10  #include "sh4/sh4stat.h"
   11.11  #include "sh4/sh4mmio.h"
   11.12 -#include "sh4/x86op.h"
   11.13  #include "sh4/mmu.h"
   11.14 +#include "xlat/xltcache.h"
   11.15 +#include "xlat/x86/x86op.h"
   11.16  #include "clock.h"
   11.17  
   11.18  #define DEFAULT_BACKPATCH_SIZE 4096
   11.19  
   11.20 +/* Offset of a reg relative to the sh4r structure */
   11.21 +#define REG_OFFSET(reg)  (((char *)&sh4r.reg) - ((char *)&sh4r) - 128)
   11.22 +
   11.23 +#define R_T   REG_OFFSET(t)
   11.24 +#define R_Q   REG_OFFSET(q)
   11.25 +#define R_S   REG_OFFSET(s)
   11.26 +#define R_M   REG_OFFSET(m)
   11.27 +#define R_SR  REG_OFFSET(sr)
   11.28 +#define R_GBR REG_OFFSET(gbr)
   11.29 +#define R_SSR REG_OFFSET(ssr)
   11.30 +#define R_SPC REG_OFFSET(spc)
   11.31 +#define R_VBR REG_OFFSET(vbr)
   11.32 +#define R_MACH REG_OFFSET(mac)+4
   11.33 +#define R_MACL REG_OFFSET(mac)
   11.34 +#define R_PC REG_OFFSET(pc)
   11.35 +#define R_NEW_PC REG_OFFSET(new_pc)
   11.36 +#define R_PR REG_OFFSET(pr)
   11.37 +#define R_SGR REG_OFFSET(sgr)
   11.38 +#define R_FPUL REG_OFFSET(fpul)
   11.39 +#define R_FPSCR REG_OFFSET(fpscr)
   11.40 +#define R_DBR REG_OFFSET(dbr)
   11.41 +
   11.42  struct backpatch_record {
   11.43      uint32_t fixup_offset;
   11.44      uint32_t fixup_icount;
   11.45 @@ -72,32 +94,6 @@
   11.46      uint32_t backpatch_size;
   11.47  };
   11.48  
   11.49 -#define TSTATE_NONE -1
   11.50 -#define TSTATE_O    0
   11.51 -#define TSTATE_C    2
   11.52 -#define TSTATE_E    4
   11.53 -#define TSTATE_NE   5
   11.54 -#define TSTATE_G    0xF
   11.55 -#define TSTATE_GE   0xD
   11.56 -#define TSTATE_A    7
   11.57 -#define TSTATE_AE   3
   11.58 -
   11.59 -#ifdef ENABLE_SH4STATS
   11.60 -#define COUNT_INST(id) load_imm32(R_EAX,id); call_func1(sh4_stats_add, R_EAX); sh4_x86.tstate = TSTATE_NONE
   11.61 -#else
   11.62 -#define COUNT_INST(id)
   11.63 -#endif
   11.64 -
   11.65 -/** Branch if T is set (either in the current cflags, or in sh4r.t) */
   11.66 -#define JT_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
   11.67 -	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
   11.68 -    OP(0x70+sh4_x86.tstate); MARK_JMP8(label); OP(-1)
   11.69 -
   11.70 -/** Branch if T is clear (either in the current cflags or in sh4r.t) */
   11.71 -#define JF_rel8(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
   11.72 -	CMP_imm8s_sh4r( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
   11.73 -    OP(0x70+ (sh4_x86.tstate^1)); MARK_JMP8(label); OP(-1)
   11.74 -
   11.75  static struct sh4_x86_state sh4_x86;
   11.76  
   11.77  static uint32_t max_int = 0x7FFFFFFF;
   11.78 @@ -125,6 +121,12 @@
   11.79  
   11.80  static void sh4_x86_add_backpatch( uint8_t *fixup_addr, uint32_t fixup_pc, uint32_t exc_code )
   11.81  {
   11.82 +    int reloc_size = 4;
   11.83 +    
   11.84 +    if( exc_code == -2 ) {
   11.85 +        reloc_size = sizeof(void *);
   11.86 +    }
   11.87 +    
   11.88      if( sh4_x86.backpatch_posn == sh4_x86.backpatch_size ) {
   11.89  	sh4_x86.backpatch_size <<= 1;
   11.90  	sh4_x86.backpatch_list = realloc( sh4_x86.backpatch_list, 
   11.91 @@ -134,106 +136,107 @@
   11.92      if( sh4_x86.in_delay_slot ) {
   11.93  	fixup_pc -= 2;
   11.94      }
   11.95 +
   11.96      sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_offset = 
   11.97 -	((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code);
   11.98 +	(((uint8_t *)fixup_addr) - ((uint8_t *)xlat_current_block->code)) - reloc_size;
   11.99      sh4_x86.backpatch_list[sh4_x86.backpatch_posn].fixup_icount = (fixup_pc - sh4_x86.block_start_pc)>>1;
  11.100      sh4_x86.backpatch_list[sh4_x86.backpatch_posn].exc_code = exc_code;
  11.101      sh4_x86.backpatch_posn++;
  11.102  }
  11.103  
  11.104 -/**
  11.105 - * Emit an instruction to load an SH4 reg into a real register
  11.106 - */
  11.107 -static inline void load_reg( int x86reg, int sh4reg ) 
  11.108 -{
  11.109 -    /* mov [bp+n], reg */
  11.110 -    OP(0x8B);
  11.111 -    OP(0x45 + (x86reg<<3));
  11.112 -    OP(REG_OFFSET(r[sh4reg]));
  11.113 -}
  11.114 +#define TSTATE_NONE -1
  11.115 +#define TSTATE_O    0
  11.116 +#define TSTATE_C    2
  11.117 +#define TSTATE_E    4
  11.118 +#define TSTATE_NE   5
  11.119 +#define TSTATE_G    0xF
  11.120 +#define TSTATE_GE   0xD
  11.121 +#define TSTATE_A    7
  11.122 +#define TSTATE_AE   3
  11.123  
  11.124 -static inline void load_reg16s( int x86reg, int sh4reg )
  11.125 -{
  11.126 -    OP(0x0F);
  11.127 -    OP(0xBF);
  11.128 -    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
  11.129 -}
  11.130 +#define MARK_JMP8(x) uint8_t *_mark_jmp_##x = (xlat_output-1)
  11.131 +#define JMP_TARGET(x) *_mark_jmp_##x += (xlat_output - _mark_jmp_##x)
  11.132  
  11.133 -static inline void load_reg16u( int x86reg, int sh4reg )
  11.134 -{
  11.135 -    OP(0x0F);
  11.136 -    OP(0xB7);
  11.137 -    MODRM_r32_sh4r(x86reg, REG_OFFSET(r[sh4reg]));
  11.138 +/* Convenience instructions */
  11.139 +#define LDC_t()          CMPB_imms_rbpdisp(1,R_T); CMC()
  11.140 +#define SETE_t()         SETCCB_cc_rbpdisp(X86_COND_E,R_T)
  11.141 +#define SETA_t()         SETCCB_cc_rbpdisp(X86_COND_A,R_T)
  11.142 +#define SETAE_t()        SETCCB_cc_rbpdisp(X86_COND_AE,R_T)
  11.143 +#define SETG_t()         SETCCB_cc_rbpdisp(X86_COND_G,R_T)
  11.144 +#define SETGE_t()        SETCCB_cc_rbpdisp(X86_COND_GE,R_T)
  11.145 +#define SETC_t()         SETCCB_cc_rbpdisp(X86_COND_C,R_T)
  11.146 +#define SETO_t()         SETCCB_cc_rbpdisp(X86_COND_O,R_T)
  11.147 +#define SETNE_t()        SETCCB_cc_rbpdisp(X86_COND_NE,R_T)
  11.148 +#define SETC_r8(r1)      SETCCB_cc_r8(X86_COND_C, r1)
  11.149 +#define JAE_label(label) JCC_cc_rel8(X86_COND_AE,-1); MARK_JMP8(label)
  11.150 +#define JE_label(label)  JCC_cc_rel8(X86_COND_E,-1); MARK_JMP8(label)
  11.151 +#define JGE_label(label) JCC_cc_rel8(X86_COND_GE,-1); MARK_JMP8(label)
  11.152 +#define JNA_label(label) JCC_cc_rel8(X86_COND_NA,-1); MARK_JMP8(label)
  11.153 +#define JNE_label(label) JCC_cc_rel8(X86_COND_NE,-1); MARK_JMP8(label)
  11.154 +#define JNO_label(label) JCC_cc_rel8(X86_COND_NO,-1); MARK_JMP8(label)
  11.155 +#define JS_label(label)  JCC_cc_rel8(X86_COND_S,-1); MARK_JMP8(label)
  11.156 +#define JMP_label(label) JMP_rel8(-1); MARK_JMP8(label)
  11.157 +#define JNE_exc(exc)     JCC_cc_rel32(X86_COND_NE,0); sh4_x86_add_backpatch(xlat_output, pc, exc)
  11.158  
  11.159 -}
  11.160 +/** Branch if T is set (either in the current cflags, or in sh4r.t) */
  11.161 +#define JT_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
  11.162 +	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
  11.163 +    JCC_cc_rel8(sh4_x86.tstate,-1); MARK_JMP8(label)
  11.164  
  11.165 -#define load_spreg( x86reg, regoff ) MOV_sh4r_r32( regoff, x86reg )
  11.166 -#define store_spreg( x86reg, regoff ) MOV_r32_sh4r( x86reg, regoff )
  11.167 -/**
  11.168 - * Emit an instruction to load an immediate value into a register
  11.169 - */
  11.170 -static inline void load_imm32( int x86reg, uint32_t value ) {
  11.171 -    /* mov #value, reg */
  11.172 -    OP(0xB8 + x86reg);
  11.173 -    OP32(value);
  11.174 -}
  11.175 +/** Branch if T is clear (either in the current cflags or in sh4r.t) */
  11.176 +#define JF_label(label) if( sh4_x86.tstate == TSTATE_NONE ) { \
  11.177 +	CMPL_imms_rbpdisp( 1, R_T ); sh4_x86.tstate = TSTATE_E; } \
  11.178 +    JCC_cc_rel8(sh4_x86.tstate^1, -1); MARK_JMP8(label)
  11.179  
  11.180 -
  11.181 -/**
  11.182 - * Load an immediate 64-bit quantity (note: x86-64 only)
  11.183 - */
  11.184 -static inline void load_imm64( int x86reg, uint64_t value ) {
  11.185 -    /* mov #value, reg */
  11.186 -    REXW();
  11.187 -    OP(0xB8 + x86reg);
  11.188 -    OP64(value);
  11.189 -}
  11.190 -
  11.191 -/**
  11.192 - * Emit an instruction to store an SH4 reg (RN)
  11.193 - */
  11.194 -void static inline store_reg( int x86reg, int sh4reg ) {
  11.195 -    /* mov reg, [bp+n] */
  11.196 -    OP(0x89);
  11.197 -    OP(0x45 + (x86reg<<3));
  11.198 -    OP(REG_OFFSET(r[sh4reg]));
  11.199 -}
  11.200 +#define load_reg16s(x86reg,sh4reg)  MOVSXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )
  11.201 +#define load_reg16u(x86reg,sh4reg)  MOVZXL_rbpdisp16_r32( REG_OFFSET(r[sh4reg]), x86reg )
  11.202 +#define load_imm32(x86reg,value)    MOVL_imm32_r32(value,x86reg)
  11.203 +#define load_imm64(x86reg,value)    MOVQ_imm64_r64(value,x86reg)
  11.204 +#define load_reg(x86reg,sh4reg)     MOVL_rbpdisp_r32( REG_OFFSET(r[sh4reg]), x86reg )
  11.205 +#define store_reg(x86reg,sh4reg)    MOVL_r32_rbpdisp( x86reg, REG_OFFSET(r[sh4reg]) )
  11.206 +#define load_spreg(x86reg, regoff)  MOVL_rbpdisp_r32( regoff, x86reg )
  11.207 +#define store_spreg(x86reg, regoff) MOVL_r32_rbpdisp( x86reg, regoff )
  11.208  
  11.209  /**
  11.210   * Load an FR register (single-precision floating point) into an integer x86
  11.211   * register (eg for register-to-register moves)
  11.212   */
  11.213 -#define load_fr(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[0][(frm)^1]) )
  11.214 -#define load_xf(reg,frm)  OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[1][(frm)^1]) )
  11.215 +#define load_fr(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[0][(frm)^1]), reg )
  11.216 +#define load_xf(reg,frm)  MOVL_rbpdisp_r32( REG_OFFSET(fr[1][(frm)^1]), reg )
  11.217  
  11.218  /**
  11.219   * Load the low half of a DR register (DR or XD) into an integer x86 register 
  11.220   */
  11.221 -#define load_dr0(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
  11.222 -#define load_dr1(reg,frm) OP(0x8B); MODRM_r32_ebp32(reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
  11.223 +#define load_dr0(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm|0x01]), reg )
  11.224 +#define load_dr1(reg,frm) MOVL_rbpdisp_r32( REG_OFFSET(fr[frm&1][frm&0x0E]), reg )
  11.225  
  11.226  /**
  11.227   * Store an FR register (single-precision floating point) from an integer x86+
  11.228   * register (eg for register-to-register moves)
  11.229   */
  11.230 -#define store_fr(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[0][(frm)^1]) )
  11.231 -#define store_xf(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[1][(frm)^1]) )
  11.232 +#define store_fr(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[0][(frm)^1]) )
  11.233 +#define store_xf(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[1][(frm)^1]) )
  11.234  
  11.235 -#define store_dr0(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
  11.236 -#define store_dr1(reg,frm) OP(0x89); MODRM_r32_ebp32( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
  11.237 +#define store_dr0(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm|0x01]) )
  11.238 +#define store_dr1(reg,frm) MOVL_r32_rbpdisp( reg, REG_OFFSET(fr[frm&1][frm&0x0E]) )
  11.239  
  11.240  
  11.241 -#define push_fpul()  FLDF_sh4r(R_FPUL)
  11.242 -#define pop_fpul()   FSTPF_sh4r(R_FPUL)
  11.243 -#define push_fr(frm) FLDF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
  11.244 -#define pop_fr(frm)  FSTPF_sh4r( REG_OFFSET(fr[0][(frm)^1]) )
  11.245 -#define push_xf(frm) FLDF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
  11.246 -#define pop_xf(frm)  FSTPF_sh4r( REG_OFFSET(fr[1][(frm)^1]) )
  11.247 -#define push_dr(frm) FLDD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
  11.248 -#define pop_dr(frm)  FSTPD_sh4r( REG_OFFSET(fr[0][(frm)&0x0E]) )
  11.249 -#define push_xdr(frm) FLDD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
  11.250 -#define pop_xdr(frm)  FSTPD_sh4r( REG_OFFSET(fr[1][(frm)&0x0E]) )
  11.251 +#define push_fpul()  FLDF_rbpdisp(R_FPUL)
  11.252 +#define pop_fpul()   FSTPF_rbpdisp(R_FPUL)
  11.253 +#define push_fr(frm) FLDF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
  11.254 +#define pop_fr(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[0][(frm)^1]) )
  11.255 +#define push_xf(frm) FLDF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
  11.256 +#define pop_xf(frm)  FSTPF_rbpdisp( REG_OFFSET(fr[1][(frm)^1]) )
  11.257 +#define push_dr(frm) FLDD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
  11.258 +#define pop_dr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[0][(frm)&0x0E]) )
  11.259 +#define push_xdr(frm) FLDD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
  11.260 +#define pop_xdr(frm)  FSTPD_rbpdisp( REG_OFFSET(fr[1][(frm)&0x0E]) )
  11.261  
  11.262 +#ifdef ENABLE_SH4STATS
  11.263 +#define COUNT_INST(id) load_imm32(REG_EAX,id); call_func1(sh4_stats_add, REG_EAX); sh4_x86.tstate = TSTATE_NONE
  11.264 +#else
  11.265 +#define COUNT_INST(id)
  11.266 +#endif
  11.267  
  11.268  
  11.269  /* Exception checks - Note that all exception checks will clobber EAX */
  11.270 @@ -253,8 +256,8 @@
  11.271  #define check_fpuen( ) \
  11.272      if( !sh4_x86.fpuen_checked ) {\
  11.273  	sh4_x86.fpuen_checked = TRUE;\
  11.274 -	load_spreg( R_EAX, R_SR );\
  11.275 -	AND_imm32_r32( SR_FD, R_EAX );\
  11.276 +	load_spreg( REG_EAX, R_SR );\
  11.277 +	ANDL_imms_r32( SR_FD, REG_EAX );\
  11.278  	if( sh4_x86.in_delay_slot ) {\
  11.279  	    JNE_exc(EXC_SLOT_FPU_DISABLED);\
  11.280  	} else {\
  11.281 @@ -264,46 +267,46 @@
  11.282      }
  11.283  
  11.284  #define check_ralign16( x86reg ) \
  11.285 -    TEST_imm32_r32( 0x00000001, x86reg ); \
  11.286 +    TESTL_imms_r32( 0x00000001, x86reg ); \
  11.287      JNE_exc(EXC_DATA_ADDR_READ)
  11.288  
  11.289  #define check_walign16( x86reg ) \
  11.290 -    TEST_imm32_r32( 0x00000001, x86reg ); \
  11.291 +    TESTL_imms_r32( 0x00000001, x86reg ); \
  11.292      JNE_exc(EXC_DATA_ADDR_WRITE);
  11.293  
  11.294  #define check_ralign32( x86reg ) \
  11.295 -    TEST_imm32_r32( 0x00000003, x86reg ); \
  11.296 +    TESTL_imms_r32( 0x00000003, x86reg ); \
  11.297      JNE_exc(EXC_DATA_ADDR_READ)
  11.298  
  11.299  #define check_walign32( x86reg ) \
  11.300 -    TEST_imm32_r32( 0x00000003, x86reg ); \
  11.301 +    TESTL_imms_r32( 0x00000003, x86reg ); \
  11.302      JNE_exc(EXC_DATA_ADDR_WRITE);
  11.303  
  11.304  #define check_ralign64( x86reg ) \
  11.305 -    TEST_imm32_r32( 0x00000007, x86reg ); \
  11.306 +    TESTL_imms_r32( 0x00000007, x86reg ); \
  11.307      JNE_exc(EXC_DATA_ADDR_READ)
  11.308  
  11.309  #define check_walign64( x86reg ) \
  11.310 -    TEST_imm32_r32( 0x00000007, x86reg ); \
  11.311 +    TESTL_imms_r32( 0x00000007, x86reg ); \
  11.312      JNE_exc(EXC_DATA_ADDR_WRITE);
  11.313  
  11.314  #define UNDEF(ir)
  11.315  #define MEM_REGION_PTR(name) offsetof( struct mem_region_fn, name )
  11.316 -#define MEM_RESULT(value_reg) if(value_reg != R_EAX) { MOV_r32_r32(R_EAX,value_reg); }
  11.317 +#define MEM_RESULT(value_reg) if(value_reg != REG_EAX) { MOVL_r32_r32(REG_EAX,value_reg); }
  11.318  /* Note: For SR.MD == 1 && MMUCR.AT == 0, there are no memory exceptions, so 
  11.319   * don't waste the cycles expecting them. Otherwise we need to save the exception pointer.
  11.320   */
  11.321   
  11.322  #ifdef HAVE_FRAME_ADDRESS
  11.323  #define _CALL_READ(addr_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
  11.324 -        call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \
  11.325 -        call_func1_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } 
  11.326 +        call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg); } else { \
  11.327 +        call_func1_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, pc); } 
  11.328  #define _CALL_WRITE(addr_reg, val_reg, fn) if( !sh4_x86.tlb_on && (sh4r.xlat_sh4_mode & SR_MD) ) { \
  11.329 -        call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \
  11.330 -        call_func2_r32disp8_exc(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }
  11.331 +        call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg); } else { \
  11.332 +        call_func2_r32disp8_exc(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg, pc); }
  11.333  #else 
  11.334 -#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg)
  11.335 -#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(R_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)
  11.336 +#define _CALL_READ(addr_reg, fn) call_func1_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg)
  11.337 +#define _CALL_WRITE(addr_reg, val_reg, fn) call_func2_r32disp8(REG_ECX, MEM_REGION_PTR(fn), addr_reg, val_reg)
  11.338  #endif
  11.339                  
  11.340  #define MEM_READ_BYTE( addr_reg, value_reg ) decode_address(addr_reg); _CALL_READ(addr_reg, read_byte); MEM_RESULT(value_reg)
  11.341 @@ -354,8 +357,8 @@
  11.342   */
  11.343  void sh4_translate_emit_breakpoint( sh4vma_t pc )
  11.344  {
  11.345 -    load_imm32( R_EAX, pc );
  11.346 -    call_func1( sh4_translate_breakpoint_hit, R_EAX );
  11.347 +    load_imm32( REG_EAX, pc );
  11.348 +    call_func1( sh4_translate_breakpoint_hit, REG_EAX );
  11.349      sh4_x86.tstate = TSTATE_NONE;
  11.350  }
  11.351  
  11.352 @@ -376,20 +379,20 @@
  11.353   */
  11.354  void exit_block_emu( sh4vma_t endpc )
  11.355  {
  11.356 -    load_imm32( R_ECX, endpc - sh4_x86.block_start_pc );   // 5
  11.357 -    ADD_r32_sh4r( R_ECX, R_PC );
  11.358 +    load_imm32( REG_ECX, endpc - sh4_x86.block_start_pc );   // 5
  11.359 +    ADDL_r32_rbpdisp( REG_ECX, R_PC );
  11.360      
  11.361 -    load_imm32( R_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
  11.362 -    ADD_r32_sh4r( R_ECX, REG_OFFSET(slice_cycle) );     // 6
  11.363 -    load_imm32( R_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
  11.364 -    store_spreg( R_ECX, REG_OFFSET(in_delay_slot) );
  11.365 +    load_imm32( REG_ECX, (((endpc - sh4_x86.block_start_pc)>>1)+1)*sh4_cpu_period ); // 5
  11.366 +    ADDL_r32_rbpdisp( REG_ECX, REG_OFFSET(slice_cycle) );     // 6
  11.367 +    load_imm32( REG_ECX, sh4_x86.in_delay_slot ? 1 : 0 );
  11.368 +    store_spreg( REG_ECX, REG_OFFSET(in_delay_slot) );
  11.369  
  11.370      call_func0( sh4_execute_instruction );    
  11.371 -    load_spreg( R_EAX, R_PC );
  11.372 +    load_spreg( REG_EAX, R_PC );
  11.373      if( sh4_x86.tlb_on ) {
  11.374 -	call_func1(xlat_get_code_by_vma,R_EAX);
  11.375 +	call_func1(xlat_get_code_by_vma,REG_EAX);
  11.376      } else {
  11.377 -	call_func1(xlat_get_code,R_EAX);
  11.378 +	call_func1(xlat_get_code,REG_EAX);
  11.379      }
  11.380      exit_block();
  11.381  } 
  11.382 @@ -417,15 +420,15 @@
  11.383  /* ALU operations */
  11.384  ADD Rm, Rn {:
  11.385      COUNT_INST(I_ADD);
  11.386 -    load_reg( R_EAX, Rm );
  11.387 -    load_reg( R_ECX, Rn );
  11.388 -    ADD_r32_r32( R_EAX, R_ECX );
  11.389 -    store_reg( R_ECX, Rn );
  11.390 +    load_reg( REG_EAX, Rm );
  11.391 +    load_reg( REG_ECX, Rn );
  11.392 +    ADDL_r32_r32( REG_EAX, REG_ECX );
  11.393 +    store_reg( REG_ECX, Rn );
  11.394      sh4_x86.tstate = TSTATE_NONE;
  11.395  :}
  11.396  ADD #imm, Rn {:  
  11.397      COUNT_INST(I_ADDI);
  11.398 -    ADD_imm8s_sh4r( imm, REG_OFFSET(r[Rn]) );
  11.399 +    ADDL_imms_rbpdisp( imm, REG_OFFSET(r[Rn]) );
  11.400      sh4_x86.tstate = TSTATE_NONE;
  11.401  :}
  11.402  ADDC Rm, Rn {:
  11.403 @@ -433,122 +436,122 @@
  11.404      if( sh4_x86.tstate != TSTATE_C ) {
  11.405          LDC_t();
  11.406      }
  11.407 -    load_reg( R_EAX, Rm );
  11.408 -    load_reg( R_ECX, Rn );
  11.409 -    ADC_r32_r32( R_EAX, R_ECX );
  11.410 -    store_reg( R_ECX, Rn );
  11.411 +    load_reg( REG_EAX, Rm );
  11.412 +    load_reg( REG_ECX, Rn );
  11.413 +    ADCL_r32_r32( REG_EAX, REG_ECX );
  11.414 +    store_reg( REG_ECX, Rn );
  11.415      SETC_t();
  11.416      sh4_x86.tstate = TSTATE_C;
  11.417  :}
  11.418  ADDV Rm, Rn {:
  11.419      COUNT_INST(I_ADDV);
  11.420 -    load_reg( R_EAX, Rm );
  11.421 -    load_reg( R_ECX, Rn );
  11.422 -    ADD_r32_r32( R_EAX, R_ECX );
  11.423 -    store_reg( R_ECX, Rn );
  11.424 +    load_reg( REG_EAX, Rm );
  11.425 +    load_reg( REG_ECX, Rn );
  11.426 +    ADDL_r32_r32( REG_EAX, REG_ECX );
  11.427 +    store_reg( REG_ECX, Rn );
  11.428      SETO_t();
  11.429      sh4_x86.tstate = TSTATE_O;
  11.430  :}
  11.431  AND Rm, Rn {:
  11.432      COUNT_INST(I_AND);
  11.433 -    load_reg( R_EAX, Rm );
  11.434 -    load_reg( R_ECX, Rn );
  11.435 -    AND_r32_r32( R_EAX, R_ECX );
  11.436 -    store_reg( R_ECX, Rn );
  11.437 +    load_reg( REG_EAX, Rm );
  11.438 +    load_reg( REG_ECX, Rn );
  11.439 +    ANDL_r32_r32( REG_EAX, REG_ECX );
  11.440 +    store_reg( REG_ECX, Rn );
  11.441      sh4_x86.tstate = TSTATE_NONE;
  11.442  :}
  11.443  AND #imm, R0 {:  
  11.444      COUNT_INST(I_ANDI);
  11.445 -    load_reg( R_EAX, 0 );
  11.446 -    AND_imm32_r32(imm, R_EAX); 
  11.447 -    store_reg( R_EAX, 0 );
  11.448 +    load_reg( REG_EAX, 0 );
  11.449 +    ANDL_imms_r32(imm, REG_EAX); 
  11.450 +    store_reg( REG_EAX, 0 );
  11.451      sh4_x86.tstate = TSTATE_NONE;
  11.452  :}
  11.453  AND.B #imm, @(R0, GBR) {: 
  11.454      COUNT_INST(I_ANDB);
  11.455 -    load_reg( R_EAX, 0 );
  11.456 -    ADD_sh4r_r32( R_GBR, R_EAX );
  11.457 -    MOV_r32_esp8(R_EAX, 0);
  11.458 -    MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );
  11.459 -    MOV_esp8_r32(0, R_EAX);
  11.460 -    AND_imm32_r32(imm, R_EDX );
  11.461 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
  11.462 +    load_reg( REG_EAX, 0 );
  11.463 +    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
  11.464 +    MOVL_r32_rspdisp(REG_EAX, 0);
  11.465 +    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
  11.466 +    MOVL_rspdisp_r32(0, REG_EAX);
  11.467 +    ANDL_imms_r32(imm, REG_EDX );
  11.468 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  11.469      sh4_x86.tstate = TSTATE_NONE;
  11.470  :}
  11.471  CMP/EQ Rm, Rn {:  
  11.472      COUNT_INST(I_CMPEQ);
  11.473 -    load_reg( R_EAX, Rm );
  11.474 -    load_reg( R_ECX, Rn );
  11.475 -    CMP_r32_r32( R_EAX, R_ECX );
  11.476 +    load_reg( REG_EAX, Rm );
  11.477 +    load_reg( REG_ECX, Rn );
  11.478 +    CMPL_r32_r32( REG_EAX, REG_ECX );
  11.479      SETE_t();
  11.480      sh4_x86.tstate = TSTATE_E;
  11.481  :}
  11.482  CMP/EQ #imm, R0 {:  
  11.483      COUNT_INST(I_CMPEQI);
  11.484 -    load_reg( R_EAX, 0 );
  11.485 -    CMP_imm8s_r32(imm, R_EAX);
  11.486 +    load_reg( REG_EAX, 0 );
  11.487 +    CMPL_imms_r32(imm, REG_EAX);
  11.488      SETE_t();
  11.489      sh4_x86.tstate = TSTATE_E;
  11.490  :}
  11.491  CMP/GE Rm, Rn {:  
  11.492      COUNT_INST(I_CMPGE);
  11.493 -    load_reg( R_EAX, Rm );
  11.494 -    load_reg( R_ECX, Rn );
  11.495 -    CMP_r32_r32( R_EAX, R_ECX );
  11.496 +    load_reg( REG_EAX, Rm );
  11.497 +    load_reg( REG_ECX, Rn );
  11.498 +    CMPL_r32_r32( REG_EAX, REG_ECX );
  11.499      SETGE_t();
  11.500      sh4_x86.tstate = TSTATE_GE;
  11.501  :}
  11.502  CMP/GT Rm, Rn {: 
  11.503      COUNT_INST(I_CMPGT);
  11.504 -    load_reg( R_EAX, Rm );
  11.505 -    load_reg( R_ECX, Rn );
  11.506 -    CMP_r32_r32( R_EAX, R_ECX );
  11.507 +    load_reg( REG_EAX, Rm );
  11.508 +    load_reg( REG_ECX, Rn );
  11.509 +    CMPL_r32_r32( REG_EAX, REG_ECX );
  11.510      SETG_t();
  11.511      sh4_x86.tstate = TSTATE_G;
  11.512  :}
  11.513  CMP/HI Rm, Rn {:  
  11.514      COUNT_INST(I_CMPHI);
  11.515 -    load_reg( R_EAX, Rm );
  11.516 -    load_reg( R_ECX, Rn );
  11.517 -    CMP_r32_r32( R_EAX, R_ECX );
  11.518 +    load_reg( REG_EAX, Rm );
  11.519 +    load_reg( REG_ECX, Rn );
  11.520 +    CMPL_r32_r32( REG_EAX, REG_ECX );
  11.521      SETA_t();
  11.522      sh4_x86.tstate = TSTATE_A;
  11.523  :}
  11.524  CMP/HS Rm, Rn {: 
  11.525      COUNT_INST(I_CMPHS);
  11.526 -    load_reg( R_EAX, Rm );
  11.527 -    load_reg( R_ECX, Rn );
  11.528 -    CMP_r32_r32( R_EAX, R_ECX );
  11.529 +    load_reg( REG_EAX, Rm );
  11.530 +    load_reg( REG_ECX, Rn );
  11.531 +    CMPL_r32_r32( REG_EAX, REG_ECX );
  11.532      SETAE_t();
  11.533      sh4_x86.tstate = TSTATE_AE;
  11.534   :}
  11.535  CMP/PL Rn {: 
  11.536      COUNT_INST(I_CMPPL);
  11.537 -    load_reg( R_EAX, Rn );
  11.538 -    CMP_imm8s_r32( 0, R_EAX );
  11.539 +    load_reg( REG_EAX, Rn );
  11.540 +    CMPL_imms_r32( 0, REG_EAX );
  11.541      SETG_t();
  11.542      sh4_x86.tstate = TSTATE_G;
  11.543  :}
  11.544  CMP/PZ Rn {:  
  11.545      COUNT_INST(I_CMPPZ);
  11.546 -    load_reg( R_EAX, Rn );
  11.547 -    CMP_imm8s_r32( 0, R_EAX );
  11.548 +    load_reg( REG_EAX, Rn );
  11.549 +    CMPL_imms_r32( 0, REG_EAX );
  11.550      SETGE_t();
  11.551      sh4_x86.tstate = TSTATE_GE;
  11.552  :}
  11.553  CMP/STR Rm, Rn {:  
  11.554      COUNT_INST(I_CMPSTR);
  11.555 -    load_reg( R_EAX, Rm );
  11.556 -    load_reg( R_ECX, Rn );
  11.557 -    XOR_r32_r32( R_ECX, R_EAX );
  11.558 -    TEST_r8_r8( R_AL, R_AL );
  11.559 -    JE_rel8(target1);
  11.560 -    TEST_r8_r8( R_AH, R_AH );
  11.561 -    JE_rel8(target2);
  11.562 -    SHR_imm8_r32( 16, R_EAX );
  11.563 -    TEST_r8_r8( R_AL, R_AL );
  11.564 -    JE_rel8(target3);
  11.565 -    TEST_r8_r8( R_AH, R_AH );
  11.566 +    load_reg( REG_EAX, Rm );
  11.567 +    load_reg( REG_ECX, Rn );
  11.568 +    XORL_r32_r32( REG_ECX, REG_EAX );
  11.569 +    TESTB_r8_r8( REG_AL, REG_AL );
  11.570 +    JE_label(target1);
  11.571 +    TESTB_r8_r8( REG_AH, REG_AH );
  11.572 +    JE_label(target2);
  11.573 +    SHRL_imm_r32( 16, REG_EAX );
  11.574 +    TESTB_r8_r8( REG_AL, REG_AL );
  11.575 +    JE_label(target3);
  11.576 +    TESTB_r8_r8( REG_AH, REG_AH );
  11.577      JMP_TARGET(target1);
  11.578      JMP_TARGET(target2);
  11.579      JMP_TARGET(target3);
  11.580 @@ -557,130 +560,130 @@
  11.581  :}
  11.582  DIV0S Rm, Rn {:
  11.583      COUNT_INST(I_DIV0S);
  11.584 -    load_reg( R_EAX, Rm );
  11.585 -    load_reg( R_ECX, Rn );
  11.586 -    SHR_imm8_r32( 31, R_EAX );
  11.587 -    SHR_imm8_r32( 31, R_ECX );
  11.588 -    store_spreg( R_EAX, R_M );
  11.589 -    store_spreg( R_ECX, R_Q );
  11.590 -    CMP_r32_r32( R_EAX, R_ECX );
  11.591 +    load_reg( REG_EAX, Rm );
  11.592 +    load_reg( REG_ECX, Rn );
  11.593 +    SHRL_imm_r32( 31, REG_EAX );
  11.594 +    SHRL_imm_r32( 31, REG_ECX );
  11.595 +    store_spreg( REG_EAX, R_M );
  11.596 +    store_spreg( REG_ECX, R_Q );
  11.597 +    CMPL_r32_r32( REG_EAX, REG_ECX );
  11.598      SETNE_t();
  11.599      sh4_x86.tstate = TSTATE_NE;
  11.600  :}
  11.601  DIV0U {:  
  11.602      COUNT_INST(I_DIV0U);
  11.603 -    XOR_r32_r32( R_EAX, R_EAX );
  11.604 -    store_spreg( R_EAX, R_Q );
  11.605 -    store_spreg( R_EAX, R_M );
  11.606 -    store_spreg( R_EAX, R_T );
  11.607 +    XORL_r32_r32( REG_EAX, REG_EAX );
  11.608 +    store_spreg( REG_EAX, R_Q );
  11.609 +    store_spreg( REG_EAX, R_M );
  11.610 +    store_spreg( REG_EAX, R_T );
  11.611      sh4_x86.tstate = TSTATE_C; // works for DIV1
  11.612  :}
  11.613  DIV1 Rm, Rn {:
  11.614      COUNT_INST(I_DIV1);
  11.615 -    load_spreg( R_ECX, R_M );
  11.616 -    load_reg( R_EAX, Rn );
  11.617 +    load_spreg( REG_ECX, R_M );
  11.618 +    load_reg( REG_EAX, Rn );
  11.619      if( sh4_x86.tstate != TSTATE_C ) {
  11.620  	LDC_t();
  11.621      }
  11.622 -    RCL1_r32( R_EAX );
  11.623 -    SETC_r8( R_DL ); // Q'
  11.624 -    CMP_sh4r_r32( R_Q, R_ECX );
  11.625 -    JE_rel8(mqequal);
  11.626 -    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  11.627 -    JMP_rel8(end);
  11.628 +    RCLL_imm_r32( 1, REG_EAX );
  11.629 +    SETC_r8( REG_DL ); // Q'
  11.630 +    CMPL_rbpdisp_r32( R_Q, REG_ECX );
  11.631 +    JE_label(mqequal);
  11.632 +    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
  11.633 +    JMP_label(end);
  11.634      JMP_TARGET(mqequal);
  11.635 -    SUB_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
  11.636 +    SUBL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
  11.637      JMP_TARGET(end);
  11.638 -    store_reg( R_EAX, Rn ); // Done with Rn now
  11.639 -    SETC_r8(R_AL); // tmp1
  11.640 -    XOR_r8_r8( R_DL, R_AL ); // Q' = Q ^ tmp1
  11.641 -    XOR_r8_r8( R_AL, R_CL ); // Q'' = Q' ^ M
  11.642 -    store_spreg( R_ECX, R_Q );
  11.643 -    XOR_imm8s_r32( 1, R_AL );   // T = !Q'
  11.644 -    MOVZX_r8_r32( R_AL, R_EAX );
  11.645 -    store_spreg( R_EAX, R_T );
  11.646 +    store_reg( REG_EAX, Rn ); // Done with Rn now
  11.647 +    SETC_r8(REG_AL); // tmp1
  11.648 +    XORB_r8_r8( REG_DL, REG_AL ); // Q' = Q ^ tmp1
  11.649 +    XORB_r8_r8( REG_AL, REG_CL ); // Q'' = Q' ^ M
  11.650 +    store_spreg( REG_ECX, R_Q );
  11.651 +    XORL_imms_r32( 1, REG_AL );   // T = !Q'
  11.652 +    MOVZXL_r8_r32( REG_AL, REG_EAX );
  11.653 +    store_spreg( REG_EAX, R_T );
  11.654      sh4_x86.tstate = TSTATE_NONE;
  11.655  :}
  11.656  DMULS.L Rm, Rn {:  
  11.657      COUNT_INST(I_DMULS);
  11.658 -    load_reg( R_EAX, Rm );
  11.659 -    load_reg( R_ECX, Rn );
  11.660 -    IMUL_r32(R_ECX);
  11.661 -    store_spreg( R_EDX, R_MACH );
  11.662 -    store_spreg( R_EAX, R_MACL );
  11.663 +    load_reg( REG_EAX, Rm );
  11.664 +    load_reg( REG_ECX, Rn );
  11.665 +    IMULL_r32(REG_ECX);
  11.666 +    store_spreg( REG_EDX, R_MACH );
  11.667 +    store_spreg( REG_EAX, R_MACL );
  11.668      sh4_x86.tstate = TSTATE_NONE;
  11.669  :}
  11.670  DMULU.L Rm, Rn {:  
  11.671      COUNT_INST(I_DMULU);
  11.672 -    load_reg( R_EAX, Rm );
  11.673 -    load_reg( R_ECX, Rn );
  11.674 -    MUL_r32(R_ECX);
  11.675 -    store_spreg( R_EDX, R_MACH );
  11.676 -    store_spreg( R_EAX, R_MACL );    
  11.677 +    load_reg( REG_EAX, Rm );
  11.678 +    load_reg( REG_ECX, Rn );
  11.679 +    MULL_r32(REG_ECX);
  11.680 +    store_spreg( REG_EDX, R_MACH );
  11.681 +    store_spreg( REG_EAX, R_MACL );    
  11.682      sh4_x86.tstate = TSTATE_NONE;
  11.683  :}
  11.684  DT Rn {:  
  11.685      COUNT_INST(I_DT);
  11.686 -    load_reg( R_EAX, Rn );
  11.687 -    ADD_imm8s_r32( -1, R_EAX );
  11.688 -    store_reg( R_EAX, Rn );
  11.689 +    load_reg( REG_EAX, Rn );
  11.690 +    ADDL_imms_r32( -1, REG_EAX );
  11.691 +    store_reg( REG_EAX, Rn );
  11.692      SETE_t();
  11.693      sh4_x86.tstate = TSTATE_E;
  11.694  :}
  11.695  EXTS.B Rm, Rn {:  
  11.696      COUNT_INST(I_EXTSB);
  11.697 -    load_reg( R_EAX, Rm );
  11.698 -    MOVSX_r8_r32( R_EAX, R_EAX );
  11.699 -    store_reg( R_EAX, Rn );
  11.700 +    load_reg( REG_EAX, Rm );
  11.701 +    MOVSXL_r8_r32( REG_EAX, REG_EAX );
  11.702 +    store_reg( REG_EAX, Rn );
  11.703  :}
  11.704  EXTS.W Rm, Rn {:  
  11.705      COUNT_INST(I_EXTSW);
  11.706 -    load_reg( R_EAX, Rm );
  11.707 -    MOVSX_r16_r32( R_EAX, R_EAX );
  11.708 -    store_reg( R_EAX, Rn );
  11.709 +    load_reg( REG_EAX, Rm );
  11.710 +    MOVSXL_r16_r32( REG_EAX, REG_EAX );
  11.711 +    store_reg( REG_EAX, Rn );
  11.712  :}
  11.713  EXTU.B Rm, Rn {:  
  11.714      COUNT_INST(I_EXTUB);
  11.715 -    load_reg( R_EAX, Rm );
  11.716 -    MOVZX_r8_r32( R_EAX, R_EAX );
  11.717 -    store_reg( R_EAX, Rn );
  11.718 +    load_reg( REG_EAX, Rm );
  11.719 +    MOVZXL_r8_r32( REG_EAX, REG_EAX );
  11.720 +    store_reg( REG_EAX, Rn );
  11.721  :}
  11.722  EXTU.W Rm, Rn {:  
  11.723      COUNT_INST(I_EXTUW);
  11.724 -    load_reg( R_EAX, Rm );
  11.725 -    MOVZX_r16_r32( R_EAX, R_EAX );
  11.726 -    store_reg( R_EAX, Rn );
  11.727 +    load_reg( REG_EAX, Rm );
  11.728 +    MOVZXL_r16_r32( REG_EAX, REG_EAX );
  11.729 +    store_reg( REG_EAX, Rn );
  11.730  :}
  11.731  MAC.L @Rm+, @Rn+ {:
  11.732      COUNT_INST(I_MACL);
  11.733      if( Rm == Rn ) {
  11.734 -	load_reg( R_EAX, Rm );
  11.735 -	check_ralign32( R_EAX );
  11.736 -	MEM_READ_LONG( R_EAX, R_EAX );
  11.737 -	MOV_r32_esp8(R_EAX, 0);
  11.738 -	load_reg( R_EAX, Rm );
  11.739 -	LEA_r32disp8_r32( R_EAX, 4, R_EAX );
  11.740 -	MEM_READ_LONG( R_EAX, R_EAX );
  11.741 -        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rn]) );
  11.742 +	load_reg( REG_EAX, Rm );
  11.743 +	check_ralign32( REG_EAX );
  11.744 +	MEM_READ_LONG( REG_EAX, REG_EAX );
  11.745 +	MOVL_r32_rspdisp(REG_EAX, 0);
  11.746 +	load_reg( REG_EAX, Rm );
  11.747 +	LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
  11.748 +	MEM_READ_LONG( REG_EAX, REG_EAX );
  11.749 +        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rn]) );
  11.750      } else {
  11.751 -	load_reg( R_EAX, Rm );
  11.752 -	check_ralign32( R_EAX );
  11.753 -	MEM_READ_LONG( R_EAX, R_EAX );
  11.754 -	MOV_r32_esp8( R_EAX, 0 );
  11.755 -	load_reg( R_EAX, Rn );
  11.756 -	check_ralign32( R_EAX );
  11.757 -	MEM_READ_LONG( R_EAX, R_EAX );
  11.758 -	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
  11.759 -	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
  11.760 +	load_reg( REG_EAX, Rm );
  11.761 +	check_ralign32( REG_EAX );
  11.762 +	MEM_READ_LONG( REG_EAX, REG_EAX );
  11.763 +	MOVL_r32_rspdisp( REG_EAX, 0 );
  11.764 +	load_reg( REG_EAX, Rn );
  11.765 +	check_ralign32( REG_EAX );
  11.766 +	MEM_READ_LONG( REG_EAX, REG_EAX );
  11.767 +	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
  11.768 +	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
  11.769      }
  11.770      
  11.771 -    IMUL_esp8( 0 );
  11.772 -    ADD_r32_sh4r( R_EAX, R_MACL );
  11.773 -    ADC_r32_sh4r( R_EDX, R_MACH );
  11.774 +    IMULL_rspdisp( 0 );
  11.775 +    ADDL_r32_rbpdisp( REG_EAX, R_MACL );
  11.776 +    ADCL_r32_rbpdisp( REG_EDX, R_MACH );
  11.777  
  11.778 -    load_spreg( R_ECX, R_S );
  11.779 -    TEST_r32_r32(R_ECX, R_ECX);
  11.780 -    JE_rel8( nosat );
  11.781 +    load_spreg( REG_ECX, R_S );
  11.782 +    TESTL_r32_r32(REG_ECX, REG_ECX);
  11.783 +    JE_label( nosat );
  11.784      call_func0( signsat48 );
  11.785      JMP_TARGET( nosat );
  11.786      sh4_x86.tstate = TSTATE_NONE;
  11.787 @@ -688,49 +691,49 @@
  11.788  MAC.W @Rm+, @Rn+ {:  
  11.789      COUNT_INST(I_MACW);
  11.790      if( Rm == Rn ) {
  11.791 -	load_reg( R_EAX, Rm );
  11.792 -	check_ralign16( R_EAX );
  11.793 -	MEM_READ_WORD( R_EAX, R_EAX );
  11.794 -        MOV_r32_esp8( R_EAX, 0 );
  11.795 -	load_reg( R_EAX, Rm );
  11.796 -	LEA_r32disp8_r32( R_EAX, 2, R_EAX );
  11.797 -	MEM_READ_WORD( R_EAX, R_EAX );
  11.798 -	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rn]) );
  11.799 +	load_reg( REG_EAX, Rm );
  11.800 +	check_ralign16( REG_EAX );
  11.801 +	MEM_READ_WORD( REG_EAX, REG_EAX );
  11.802 +        MOVL_r32_rspdisp( REG_EAX, 0 );
  11.803 +	load_reg( REG_EAX, Rm );
  11.804 +	LEAL_r32disp_r32( REG_EAX, 2, REG_EAX );
  11.805 +	MEM_READ_WORD( REG_EAX, REG_EAX );
  11.806 +	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rn]) );
  11.807  	// Note translate twice in case of page boundaries. Maybe worth
  11.808  	// adding a page-boundary check to skip the second translation
  11.809      } else {
  11.810 -	load_reg( R_EAX, Rm );
  11.811 -	check_ralign16( R_EAX );
  11.812 -	MEM_READ_WORD( R_EAX, R_EAX );
  11.813 -        MOV_r32_esp8( R_EAX, 0 );
  11.814 -	load_reg( R_EAX, Rn );
  11.815 -	check_ralign16( R_EAX );
  11.816 -	MEM_READ_WORD( R_EAX, R_EAX );
  11.817 -	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rn]) );
  11.818 -	ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
  11.819 +	load_reg( REG_EAX, Rm );
  11.820 +	check_ralign16( REG_EAX );
  11.821 +	MEM_READ_WORD( REG_EAX, REG_EAX );
  11.822 +        MOVL_r32_rspdisp( REG_EAX, 0 );
  11.823 +	load_reg( REG_EAX, Rn );
  11.824 +	check_ralign16( REG_EAX );
  11.825 +	MEM_READ_WORD( REG_EAX, REG_EAX );
  11.826 +	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rn]) );
  11.827 +	ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
  11.828      }
  11.829 -    IMUL_esp8( 0 );
  11.830 -    load_spreg( R_ECX, R_S );
  11.831 -    TEST_r32_r32( R_ECX, R_ECX );
  11.832 -    JE_rel8( nosat );
  11.833 +    IMULL_rspdisp( 0 );
  11.834 +    load_spreg( REG_ECX, R_S );
  11.835 +    TESTL_r32_r32( REG_ECX, REG_ECX );
  11.836 +    JE_label( nosat );
  11.837  
  11.838 -    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  11.839 -    JNO_rel8( end );            // 2
  11.840 -    load_imm32( R_EDX, 1 );         // 5
  11.841 -    store_spreg( R_EDX, R_MACH );   // 6
  11.842 -    JS_rel8( positive );        // 2
  11.843 -    load_imm32( R_EAX, 0x80000000 );// 5
  11.844 -    store_spreg( R_EAX, R_MACL );   // 6
  11.845 -    JMP_rel8(end2);           // 2
  11.846 +    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
  11.847 +    JNO_label( end );            // 2
  11.848 +    load_imm32( REG_EDX, 1 );         // 5
  11.849 +    store_spreg( REG_EDX, R_MACH );   // 6
  11.850 +    JS_label( positive );        // 2
  11.851 +    load_imm32( REG_EAX, 0x80000000 );// 5
  11.852 +    store_spreg( REG_EAX, R_MACL );   // 6
  11.853 +    JMP_label(end2);           // 2
  11.854  
  11.855      JMP_TARGET(positive);
  11.856 -    load_imm32( R_EAX, 0x7FFFFFFF );// 5
  11.857 -    store_spreg( R_EAX, R_MACL );   // 6
  11.858 -    JMP_rel8(end3);            // 2
  11.859 +    load_imm32( REG_EAX, 0x7FFFFFFF );// 5
  11.860 +    store_spreg( REG_EAX, R_MACL );   // 6
  11.861 +    JMP_label(end3);            // 2
  11.862  
  11.863      JMP_TARGET(nosat);
  11.864 -    ADD_r32_sh4r( R_EAX, R_MACL );  // 6
  11.865 -    ADC_r32_sh4r( R_EDX, R_MACH );  // 6
  11.866 +    ADDL_r32_rbpdisp( REG_EAX, R_MACL );  // 6
  11.867 +    ADCL_r32_rbpdisp( REG_EDX, R_MACH );  // 6
  11.868      JMP_TARGET(end);
  11.869      JMP_TARGET(end2);
  11.870      JMP_TARGET(end3);
  11.871 @@ -738,556 +741,556 @@
  11.872  :}
  11.873  MOVT Rn {:  
  11.874      COUNT_INST(I_MOVT);
  11.875 -    load_spreg( R_EAX, R_T );
  11.876 -    store_reg( R_EAX, Rn );
  11.877 +    load_spreg( REG_EAX, R_T );
  11.878 +    store_reg( REG_EAX, Rn );
  11.879  :}
  11.880  MUL.L Rm, Rn {:  
  11.881      COUNT_INST(I_MULL);
  11.882 -    load_reg( R_EAX, Rm );
  11.883 -    load_reg( R_ECX, Rn );
  11.884 -    MUL_r32( R_ECX );
  11.885 -    store_spreg( R_EAX, R_MACL );
  11.886 +    load_reg( REG_EAX, Rm );
  11.887 +    load_reg( REG_ECX, Rn );
  11.888 +    MULL_r32( REG_ECX );
  11.889 +    store_spreg( REG_EAX, R_MACL );
  11.890      sh4_x86.tstate = TSTATE_NONE;
  11.891  :}
  11.892  MULS.W Rm, Rn {:
  11.893      COUNT_INST(I_MULSW);
  11.894 -    load_reg16s( R_EAX, Rm );
  11.895 -    load_reg16s( R_ECX, Rn );
  11.896 -    MUL_r32( R_ECX );
  11.897 -    store_spreg( R_EAX, R_MACL );
  11.898 +    load_reg16s( REG_EAX, Rm );
  11.899 +    load_reg16s( REG_ECX, Rn );
  11.900 +    MULL_r32( REG_ECX );
  11.901 +    store_spreg( REG_EAX, R_MACL );
  11.902      sh4_x86.tstate = TSTATE_NONE;
  11.903  :}
  11.904  MULU.W Rm, Rn {:  
  11.905      COUNT_INST(I_MULUW);
  11.906 -    load_reg16u( R_EAX, Rm );
  11.907 -    load_reg16u( R_ECX, Rn );
  11.908 -    MUL_r32( R_ECX );
  11.909 -    store_spreg( R_EAX, R_MACL );
  11.910 +    load_reg16u( REG_EAX, Rm );
  11.911 +    load_reg16u( REG_ECX, Rn );
  11.912 +    MULL_r32( REG_ECX );
  11.913 +    store_spreg( REG_EAX, R_MACL );
  11.914      sh4_x86.tstate = TSTATE_NONE;
  11.915  :}
  11.916  NEG Rm, Rn {:
  11.917      COUNT_INST(I_NEG);
  11.918 -    load_reg( R_EAX, Rm );
  11.919 -    NEG_r32( R_EAX );
  11.920 -    store_reg( R_EAX, Rn );
  11.921 +    load_reg( REG_EAX, Rm );
  11.922 +    NEGL_r32( REG_EAX );
  11.923 +    store_reg( REG_EAX, Rn );
  11.924      sh4_x86.tstate = TSTATE_NONE;
  11.925  :}
  11.926  NEGC Rm, Rn {:  
  11.927      COUNT_INST(I_NEGC);
  11.928 -    load_reg( R_EAX, Rm );
  11.929 -    XOR_r32_r32( R_ECX, R_ECX );
  11.930 +    load_reg( REG_EAX, Rm );
  11.931 +    XORL_r32_r32( REG_ECX, REG_ECX );
  11.932      LDC_t();
  11.933 -    SBB_r32_r32( R_EAX, R_ECX );
  11.934 -    store_reg( R_ECX, Rn );
  11.935 +    SBBL_r32_r32( REG_EAX, REG_ECX );
  11.936 +    store_reg( REG_ECX, Rn );
  11.937      SETC_t();
  11.938      sh4_x86.tstate = TSTATE_C;
  11.939  :}
  11.940  NOT Rm, Rn {:  
  11.941      COUNT_INST(I_NOT);
  11.942 -    load_reg( R_EAX, Rm );
  11.943 -    NOT_r32( R_EAX );
  11.944 -    store_reg( R_EAX, Rn );
  11.945 +    load_reg( REG_EAX, Rm );
  11.946 +    NOTL_r32( REG_EAX );
  11.947 +    store_reg( REG_EAX, Rn );
  11.948      sh4_x86.tstate = TSTATE_NONE;
  11.949  :}
  11.950  OR Rm, Rn {:  
  11.951      COUNT_INST(I_OR);
  11.952 -    load_reg( R_EAX, Rm );
  11.953 -    load_reg( R_ECX, Rn );
  11.954 -    OR_r32_r32( R_EAX, R_ECX );
  11.955 -    store_reg( R_ECX, Rn );
  11.956 +    load_reg( REG_EAX, Rm );
  11.957 +    load_reg( REG_ECX, Rn );
  11.958 +    ORL_r32_r32( REG_EAX, REG_ECX );
  11.959 +    store_reg( REG_ECX, Rn );
  11.960      sh4_x86.tstate = TSTATE_NONE;
  11.961  :}
  11.962  OR #imm, R0 {:
  11.963      COUNT_INST(I_ORI);
  11.964 -    load_reg( R_EAX, 0 );
  11.965 -    OR_imm32_r32(imm, R_EAX);
  11.966 -    store_reg( R_EAX, 0 );
  11.967 +    load_reg( REG_EAX, 0 );
  11.968 +    ORL_imms_r32(imm, REG_EAX);
  11.969 +    store_reg( REG_EAX, 0 );
  11.970      sh4_x86.tstate = TSTATE_NONE;
  11.971  :}
  11.972  OR.B #imm, @(R0, GBR) {:  
  11.973      COUNT_INST(I_ORB);
  11.974 -    load_reg( R_EAX, 0 );
  11.975 -    ADD_sh4r_r32( R_GBR, R_EAX );
  11.976 -    MOV_r32_esp8( R_EAX, 0 );
  11.977 -    MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );
  11.978 -    MOV_esp8_r32( 0, R_EAX );
  11.979 -    OR_imm32_r32(imm, R_EDX );
  11.980 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
  11.981 +    load_reg( REG_EAX, 0 );
  11.982 +    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
  11.983 +    MOVL_r32_rspdisp( REG_EAX, 0 );
  11.984 +    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
  11.985 +    MOVL_rspdisp_r32( 0, REG_EAX );
  11.986 +    ORL_imms_r32(imm, REG_EDX );
  11.987 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
  11.988      sh4_x86.tstate = TSTATE_NONE;
  11.989  :}
  11.990  ROTCL Rn {:
  11.991      COUNT_INST(I_ROTCL);
  11.992 -    load_reg( R_EAX, Rn );
  11.993 +    load_reg( REG_EAX, Rn );
  11.994      if( sh4_x86.tstate != TSTATE_C ) {
  11.995  	LDC_t();
  11.996      }
  11.997 -    RCL1_r32( R_EAX );
  11.998 -    store_reg( R_EAX, Rn );
  11.999 +    RCLL_imm_r32( 1, REG_EAX );
 11.1000 +    store_reg( REG_EAX, Rn );
 11.1001      SETC_t();
 11.1002      sh4_x86.tstate = TSTATE_C;
 11.1003  :}
 11.1004  ROTCR Rn {:  
 11.1005      COUNT_INST(I_ROTCR);
 11.1006 -    load_reg( R_EAX, Rn );
 11.1007 +    load_reg( REG_EAX, Rn );
 11.1008      if( sh4_x86.tstate != TSTATE_C ) {
 11.1009  	LDC_t();
 11.1010      }
 11.1011 -    RCR1_r32( R_EAX );
 11.1012 -    store_reg( R_EAX, Rn );
 11.1013 +    RCRL_imm_r32( 1, REG_EAX );
 11.1014 +    store_reg( REG_EAX, Rn );
 11.1015      SETC_t();
 11.1016      sh4_x86.tstate = TSTATE_C;
 11.1017  :}
 11.1018  ROTL Rn {:  
 11.1019      COUNT_INST(I_ROTL);
 11.1020 -    load_reg( R_EAX, Rn );
 11.1021 -    ROL1_r32( R_EAX );
 11.1022 -    store_reg( R_EAX, Rn );
 11.1023 +    load_reg( REG_EAX, Rn );
 11.1024 +    ROLL_imm_r32( 1, REG_EAX );
 11.1025 +    store_reg( REG_EAX, Rn );
 11.1026      SETC_t();
 11.1027      sh4_x86.tstate = TSTATE_C;
 11.1028  :}
 11.1029  ROTR Rn {:  
 11.1030      COUNT_INST(I_ROTR);
 11.1031 -    load_reg( R_EAX, Rn );
 11.1032 -    ROR1_r32( R_EAX );
 11.1033 -    store_reg( R_EAX, Rn );
 11.1034 +    load_reg( REG_EAX, Rn );
 11.1035 +    RORL_imm_r32( 1, REG_EAX );
 11.1036 +    store_reg( REG_EAX, Rn );
 11.1037      SETC_t();
 11.1038      sh4_x86.tstate = TSTATE_C;
 11.1039  :}
 11.1040  SHAD Rm, Rn {:
 11.1041      COUNT_INST(I_SHAD);
 11.1042      /* Annoyingly enough, not directly convertible */
 11.1043 -    load_reg( R_EAX, Rn );
 11.1044 -    load_reg( R_ECX, Rm );
 11.1045 -    CMP_imm32_r32( 0, R_ECX );
 11.1046 -    JGE_rel8(doshl);
 11.1047 +    load_reg( REG_EAX, Rn );
 11.1048 +    load_reg( REG_ECX, Rm );
 11.1049 +    CMPL_imms_r32( 0, REG_ECX );
 11.1050 +    JGE_label(doshl);
 11.1051                      
 11.1052 -    NEG_r32( R_ECX );      // 2
 11.1053 -    AND_imm8_r8( 0x1F, R_CL ); // 3
 11.1054 -    JE_rel8(emptysar);     // 2
 11.1055 -    SAR_r32_CL( R_EAX );       // 2
 11.1056 -    JMP_rel8(end);          // 2
 11.1057 +    NEGL_r32( REG_ECX );      // 2
 11.1058 +    ANDB_imms_r8( 0x1F, REG_CL ); // 3
 11.1059 +    JE_label(emptysar);     // 2
 11.1060 +    SARL_cl_r32( REG_EAX );       // 2
 11.1061 +    JMP_label(end);          // 2
 11.1062  
 11.1063      JMP_TARGET(emptysar);
 11.1064 -    SAR_imm8_r32(31, R_EAX );  // 3
 11.1065 -    JMP_rel8(end2);
 11.1066 +    SARL_imm_r32(31, REG_EAX );  // 3
 11.1067 +    JMP_label(end2);
 11.1068  
 11.1069      JMP_TARGET(doshl);
 11.1070 -    AND_imm8_r8( 0x1F, R_CL ); // 3
 11.1071 -    SHL_r32_CL( R_EAX );       // 2
 11.1072 +    ANDB_imms_r8( 0x1F, REG_CL ); // 3
 11.1073 +    SHLL_cl_r32( REG_EAX );       // 2
 11.1074      JMP_TARGET(end);
 11.1075      JMP_TARGET(end2);
 11.1076 -    store_reg( R_EAX, Rn );
 11.1077 +    store_reg( REG_EAX, Rn );
 11.1078      sh4_x86.tstate = TSTATE_NONE;
 11.1079  :}
 11.1080  SHLD Rm, Rn {:  
 11.1081      COUNT_INST(I_SHLD);
 11.1082 -    load_reg( R_EAX, Rn );
 11.1083 -    load_reg( R_ECX, Rm );
 11.1084 -    CMP_imm32_r32( 0, R_ECX );
 11.1085 -    JGE_rel8(doshl);
 11.1086 +    load_reg( REG_EAX, Rn );
 11.1087 +    load_reg( REG_ECX, Rm );
 11.1088 +    CMPL_imms_r32( 0, REG_ECX );
 11.1089 +    JGE_label(doshl);
 11.1090  
 11.1091 -    NEG_r32( R_ECX );      // 2
 11.1092 -    AND_imm8_r8( 0x1F, R_CL ); // 3
 11.1093 -    JE_rel8(emptyshr );
 11.1094 -    SHR_r32_CL( R_EAX );       // 2
 11.1095 -    JMP_rel8(end);          // 2
 11.1096 +    NEGL_r32( REG_ECX );      // 2
 11.1097 +    ANDB_imms_r8( 0x1F, REG_CL ); // 3
 11.1098 +    JE_label(emptyshr );
 11.1099 +    SHRL_cl_r32( REG_EAX );       // 2
 11.1100 +    JMP_label(end);          // 2
 11.1101  
 11.1102      JMP_TARGET(emptyshr);
 11.1103 -    XOR_r32_r32( R_EAX, R_EAX );
 11.1104 -    JMP_rel8(end2);
 11.1105 +    XORL_r32_r32( REG_EAX, REG_EAX );
 11.1106 +    JMP_label(end2);
 11.1107  
 11.1108      JMP_TARGET(doshl);
 11.1109 -    AND_imm8_r8( 0x1F, R_CL ); // 3
 11.1110 -    SHL_r32_CL( R_EAX );       // 2
 11.1111 +    ANDB_imms_r8( 0x1F, REG_CL ); // 3
 11.1112 +    SHLL_cl_r32( REG_EAX );       // 2
 11.1113      JMP_TARGET(end);
 11.1114      JMP_TARGET(end2);
 11.1115 -    store_reg( R_EAX, Rn );
 11.1116 +    store_reg( REG_EAX, Rn );
 11.1117      sh4_x86.tstate = TSTATE_NONE;
 11.1118  :}
 11.1119  SHAL Rn {: 
 11.1120      COUNT_INST(I_SHAL);
 11.1121 -    load_reg( R_EAX, Rn );
 11.1122 -    SHL1_r32( R_EAX );
 11.1123 +    load_reg( REG_EAX, Rn );
 11.1124 +    SHLL_imm_r32( 1, REG_EAX );
 11.1125      SETC_t();
 11.1126 -    store_reg( R_EAX, Rn );
 11.1127 +    store_reg( REG_EAX, Rn );
 11.1128      sh4_x86.tstate = TSTATE_C;
 11.1129  :}
 11.1130  SHAR Rn {:  
 11.1131      COUNT_INST(I_SHAR);
 11.1132 -    load_reg( R_EAX, Rn );
 11.1133 -    SAR1_r32( R_EAX );
 11.1134 +    load_reg( REG_EAX, Rn );
 11.1135 +    SARL_imm_r32( 1, REG_EAX );
 11.1136      SETC_t();
 11.1137 -    store_reg( R_EAX, Rn );
 11.1138 +    store_reg( REG_EAX, Rn );
 11.1139      sh4_x86.tstate = TSTATE_C;
 11.1140  :}
 11.1141  SHLL Rn {:  
 11.1142      COUNT_INST(I_SHLL);
 11.1143 -    load_reg( R_EAX, Rn );
 11.1144 -    SHL1_r32( R_EAX );
 11.1145 +    load_reg( REG_EAX, Rn );
 11.1146 +    SHLL_imm_r32( 1, REG_EAX );
 11.1147      SETC_t();
 11.1148 -    store_reg( R_EAX, Rn );
 11.1149 +    store_reg( REG_EAX, Rn );
 11.1150      sh4_x86.tstate = TSTATE_C;
 11.1151  :}
 11.1152  SHLL2 Rn {:
 11.1153      COUNT_INST(I_SHLL);
 11.1154 -    load_reg( R_EAX, Rn );
 11.1155 -    SHL_imm8_r32( 2, R_EAX );
 11.1156 -    store_reg( R_EAX, Rn );
 11.1157 +    load_reg( REG_EAX, Rn );
 11.1158 +    SHLL_imm_r32( 2, REG_EAX );
 11.1159 +    store_reg( REG_EAX, Rn );
 11.1160      sh4_x86.tstate = TSTATE_NONE;
 11.1161  :}
 11.1162  SHLL8 Rn {:  
 11.1163      COUNT_INST(I_SHLL);
 11.1164 -    load_reg( R_EAX, Rn );
 11.1165 -    SHL_imm8_r32( 8, R_EAX );
 11.1166 -    store_reg( R_EAX, Rn );
 11.1167 +    load_reg( REG_EAX, Rn );
 11.1168 +    SHLL_imm_r32( 8, REG_EAX );
 11.1169 +    store_reg( REG_EAX, Rn );
 11.1170      sh4_x86.tstate = TSTATE_NONE;
 11.1171  :}
 11.1172  SHLL16 Rn {:  
 11.1173      COUNT_INST(I_SHLL);
 11.1174 -    load_reg( R_EAX, Rn );
 11.1175 -    SHL_imm8_r32( 16, R_EAX );
 11.1176 -    store_reg( R_EAX, Rn );
 11.1177 +    load_reg( REG_EAX, Rn );
 11.1178 +    SHLL_imm_r32( 16, REG_EAX );
 11.1179 +    store_reg( REG_EAX, Rn );
 11.1180      sh4_x86.tstate = TSTATE_NONE;
 11.1181  :}
 11.1182  SHLR Rn {:  
 11.1183      COUNT_INST(I_SHLR);
 11.1184 -    load_reg( R_EAX, Rn );
 11.1185 -    SHR1_r32( R_EAX );
 11.1186 +    load_reg( REG_EAX, Rn );
 11.1187 +    SHRL_imm_r32( 1, REG_EAX );
 11.1188      SETC_t();
 11.1189 -    store_reg( R_EAX, Rn );
 11.1190 +    store_reg( REG_EAX, Rn );
 11.1191      sh4_x86.tstate = TSTATE_C;
 11.1192  :}
 11.1193  SHLR2 Rn {:  
 11.1194      COUNT_INST(I_SHLR);
 11.1195 -    load_reg( R_EAX, Rn );
 11.1196 -    SHR_imm8_r32( 2, R_EAX );
 11.1197 -    store_reg( R_EAX, Rn );
 11.1198 +    load_reg( REG_EAX, Rn );
 11.1199 +    SHRL_imm_r32( 2, REG_EAX );
 11.1200 +    store_reg( REG_EAX, Rn );
 11.1201      sh4_x86.tstate = TSTATE_NONE;
 11.1202  :}
 11.1203  SHLR8 Rn {:  
 11.1204      COUNT_INST(I_SHLR);
 11.1205 -    load_reg( R_EAX, Rn );
 11.1206 -    SHR_imm8_r32( 8, R_EAX );
 11.1207 -    store_reg( R_EAX, Rn );
 11.1208 +    load_reg( REG_EAX, Rn );
 11.1209 +    SHRL_imm_r32( 8, REG_EAX );
 11.1210 +    store_reg( REG_EAX, Rn );
 11.1211      sh4_x86.tstate = TSTATE_NONE;
 11.1212  :}
 11.1213  SHLR16 Rn {:  
 11.1214      COUNT_INST(I_SHLR);
 11.1215 -    load_reg( R_EAX, Rn );
 11.1216 -    SHR_imm8_r32( 16, R_EAX );
 11.1217 -    store_reg( R_EAX, Rn );
 11.1218 +    load_reg( REG_EAX, Rn );
 11.1219 +    SHRL_imm_r32( 16, REG_EAX );
 11.1220 +    store_reg( REG_EAX, Rn );
 11.1221      sh4_x86.tstate = TSTATE_NONE;
 11.1222  :}
 11.1223  SUB Rm, Rn {:  
 11.1224      COUNT_INST(I_SUB);
 11.1225 -    load_reg( R_EAX, Rm );
 11.1226 -    load_reg( R_ECX, Rn );
 11.1227 -    SUB_r32_r32( R_EAX, R_ECX );
 11.1228 -    store_reg( R_ECX, Rn );
 11.1229 +    load_reg( REG_EAX, Rm );
 11.1230 +    load_reg( REG_ECX, Rn );
 11.1231 +    SUBL_r32_r32( REG_EAX, REG_ECX );
 11.1232 +    store_reg( REG_ECX, Rn );
 11.1233      sh4_x86.tstate = TSTATE_NONE;
 11.1234  :}
 11.1235  SUBC Rm, Rn {:  
 11.1236      COUNT_INST(I_SUBC);
 11.1237 -    load_reg( R_EAX, Rm );
 11.1238 -    load_reg( R_ECX, Rn );
 11.1239 +    load_reg( REG_EAX, Rm );
 11.1240 +    load_reg( REG_ECX, Rn );
 11.1241      if( sh4_x86.tstate != TSTATE_C ) {
 11.1242  	LDC_t();
 11.1243      }
 11.1244 -    SBB_r32_r32( R_EAX, R_ECX );
 11.1245 -    store_reg( R_ECX, Rn );
 11.1246 +    SBBL_r32_r32( REG_EAX, REG_ECX );
 11.1247 +    store_reg( REG_ECX, Rn );
 11.1248      SETC_t();
 11.1249      sh4_x86.tstate = TSTATE_C;
 11.1250  :}
 11.1251  SUBV Rm, Rn {:  
 11.1252      COUNT_INST(I_SUBV);
 11.1253 -    load_reg( R_EAX, Rm );
 11.1254 -    load_reg( R_ECX, Rn );
 11.1255 -    SUB_r32_r32( R_EAX, R_ECX );
 11.1256 -    store_reg( R_ECX, Rn );
 11.1257 +    load_reg( REG_EAX, Rm );
 11.1258 +    load_reg( REG_ECX, Rn );
 11.1259 +    SUBL_r32_r32( REG_EAX, REG_ECX );
 11.1260 +    store_reg( REG_ECX, Rn );
 11.1261      SETO_t();
 11.1262      sh4_x86.tstate = TSTATE_O;
 11.1263  :}
 11.1264  SWAP.B Rm, Rn {:  
 11.1265      COUNT_INST(I_SWAPB);
 11.1266 -    load_reg( R_EAX, Rm );
 11.1267 -    XCHG_r8_r8( R_AL, R_AH ); // NB: does not touch EFLAGS
 11.1268 -    store_reg( R_EAX, Rn );
 11.1269 +    load_reg( REG_EAX, Rm );
 11.1270 +    XCHGB_r8_r8( REG_AL, REG_AH ); // NB: does not touch EFLAGS
 11.1271 +    store_reg( REG_EAX, Rn );
 11.1272  :}
 11.1273  SWAP.W Rm, Rn {:  
 11.1274      COUNT_INST(I_SWAPB);
 11.1275 -    load_reg( R_EAX, Rm );
 11.1276 -    MOV_r32_r32( R_EAX, R_ECX );
 11.1277 -    SHL_imm8_r32( 16, R_ECX );
 11.1278 -    SHR_imm8_r32( 16, R_EAX );
 11.1279 -    OR_r32_r32( R_EAX, R_ECX );
 11.1280 -    store_reg( R_ECX, Rn );
 11.1281 +    load_reg( REG_EAX, Rm );
 11.1282 +    MOVL_r32_r32( REG_EAX, REG_ECX );
 11.1283 +    SHLL_imm_r32( 16, REG_ECX );
 11.1284 +    SHRL_imm_r32( 16, REG_EAX );
 11.1285 +    ORL_r32_r32( REG_EAX, REG_ECX );
 11.1286 +    store_reg( REG_ECX, Rn );
 11.1287      sh4_x86.tstate = TSTATE_NONE;
 11.1288  :}
 11.1289  TAS.B @Rn {:  
 11.1290      COUNT_INST(I_TASB);
 11.1291 -    load_reg( R_EAX, Rn );
 11.1292 -    MOV_r32_esp8( R_EAX, 0 );
 11.1293 -    MEM_READ_BYTE_FOR_WRITE( R_EAX, R_EDX );
 11.1294 -    TEST_r8_r8( R_DL, R_DL );
 11.1295 +    load_reg( REG_EAX, Rn );
 11.1296 +    MOVL_r32_rspdisp( REG_EAX, 0 );
 11.1297 +    MEM_READ_BYTE_FOR_WRITE( REG_EAX, REG_EDX );
 11.1298 +    TESTB_r8_r8( REG_DL, REG_DL );
 11.1299      SETE_t();
 11.1300 -    OR_imm8_r8( 0x80, R_DL );
 11.1301 -    MOV_esp8_r32( 0, R_EAX );
 11.1302 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
 11.1303 +    ORB_imms_r8( 0x80, REG_DL );
 11.1304 +    MOVL_rspdisp_r32( 0, REG_EAX );
 11.1305 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
 11.1306      sh4_x86.tstate = TSTATE_NONE;
 11.1307  :}
 11.1308  TST Rm, Rn {:  
 11.1309      COUNT_INST(I_TST);
 11.1310 -    load_reg( R_EAX, Rm );
 11.1311 -    load_reg( R_ECX, Rn );
 11.1312 -    TEST_r32_r32( R_EAX, R_ECX );
 11.1313 +    load_reg( REG_EAX, Rm );
 11.1314 +    load_reg( REG_ECX, Rn );
 11.1315 +    TESTL_r32_r32( REG_EAX, REG_ECX );
 11.1316      SETE_t();
 11.1317      sh4_x86.tstate = TSTATE_E;
 11.1318  :}
 11.1319  TST #imm, R0 {:  
 11.1320      COUNT_INST(I_TSTI);
 11.1321 -    load_reg( R_EAX, 0 );
 11.1322 -    TEST_imm32_r32( imm, R_EAX );
 11.1323 +    load_reg( REG_EAX, 0 );
 11.1324 +    TESTL_imms_r32( imm, REG_EAX );
 11.1325      SETE_t();
 11.1326      sh4_x86.tstate = TSTATE_E;
 11.1327  :}
 11.1328  TST.B #imm, @(R0, GBR) {:  
 11.1329      COUNT_INST(I_TSTB);
 11.1330 -    load_reg( R_EAX, 0);
 11.1331 -    ADD_sh4r_r32( R_GBR, R_EAX );
 11.1332 -    MEM_READ_BYTE( R_EAX, R_EAX );
 11.1333 -    TEST_imm8_r8( imm, R_AL );
 11.1334 +    load_reg( REG_EAX, 0);
 11.1335 +    ADDL_rbpdisp_r32( R_GBR, REG_EAX );
 11.1336 +    MEM_READ_BYTE( REG_EAX, REG_EAX );
 11.1337 +    TESTB_imms_r8( imm, REG_AL );
 11.1338      SETE_t();
 11.1339      sh4_x86.tstate = TSTATE_E;
 11.1340  :}
 11.1341  XOR Rm, Rn {:  
 11.1342      COUNT_INST(I_XOR);
 11.1343 -    load_reg( R_EAX, Rm );
 11.1344 -    load_reg( R_ECX, Rn );
 11.1345 -    XOR_r32_r32( R_EAX, R_ECX );
 11.1346 -    store_reg( R_ECX, Rn );
 11.1347 +    load_reg( REG_EAX, Rm );
 11.1348 +    load_reg( REG_ECX, Rn );
 11.1349 +    XORL_r32_r32( REG_EAX, REG_ECX );
 11.1350 +    store_reg( REG_ECX, Rn );
 11.1351      sh4_x86.tstate = TSTATE_NONE;
 11.1352  :}
 11.1353  XOR #imm, R0 {:  
 11.1354      COUNT_INST(I_XORI);
 11.1355 -    load_reg( R_EAX, 0 );
 11.1356 -    XOR_imm32_r32( imm, R_EAX );
 11.1357 -    store_reg( R_EAX, 0 );
 11.1358 +    load_reg( REG_EAX, 0 );
 11.1359 +    XORL_imms_r32( imm, REG_EAX );
 11.1360 +    store_reg( REG_EAX, 0 );
 11.1361      sh4_x86.tstate = TSTATE_NONE;
 11.1362  :}
 11.1363  XOR.B #imm, @(R0, GBR) {:  
 11.1364      COUNT_INST(I_XORB);
 11.1365 -    load_reg( R_EAX, 0 );
 11.1366 -    ADD_sh4r_r32( R_GBR, R_EAX ); 
 11.1367 -    MOV_r32_esp8( R_EAX, 0 );
 11.1368 -    MEM_READ_BYTE_FOR_WRITE(R_EAX, R_EDX);
 11.1369 -    MOV_esp8_r32( 0, R_EAX );
 11.1370 -    XOR_imm32_r32( imm, R_EDX );
 11.1371 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
 11.1372 +    load_reg( REG_EAX, 0 );
 11.1373 +    ADDL_rbpdisp_r32( R_GBR, REG_EAX ); 
 11.1374 +    MOVL_r32_rspdisp( REG_EAX, 0 );
 11.1375 +    MEM_READ_BYTE_FOR_WRITE(REG_EAX, REG_EDX);
 11.1376 +    MOVL_rspdisp_r32( 0, REG_EAX );
 11.1377 +    XORL_imms_r32( imm, REG_EDX );
 11.1378 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
 11.1379      sh4_x86.tstate = TSTATE_NONE;
 11.1380  :}
 11.1381  XTRCT Rm, Rn {:
 11.1382      COUNT_INST(I_XTRCT);
 11.1383 -    load_reg( R_EAX, Rm );
 11.1384 -    load_reg( R_ECX, Rn );
 11.1385 -    SHL_imm8_r32( 16, R_EAX );
 11.1386 -    SHR_imm8_r32( 16, R_ECX );
 11.1387 -    OR_r32_r32( R_EAX, R_ECX );
 11.1388 -    store_reg( R_ECX, Rn );
 11.1389 +    load_reg( REG_EAX, Rm );
 11.1390 +    load_reg( REG_ECX, Rn );
 11.1391 +    SHLL_imm_r32( 16, REG_EAX );
 11.1392 +    SHRL_imm_r32( 16, REG_ECX );
 11.1393 +    ORL_r32_r32( REG_EAX, REG_ECX );
 11.1394 +    store_reg( REG_ECX, Rn );
 11.1395      sh4_x86.tstate = TSTATE_NONE;
 11.1396  :}
 11.1397  
 11.1398  /* Data move instructions */
 11.1399  MOV Rm, Rn {:  
 11.1400      COUNT_INST(I_MOV);
 11.1401 -    load_reg( R_EAX, Rm );
 11.1402 -    store_reg( R_EAX, Rn );
 11.1403 +    load_reg( REG_EAX, Rm );
 11.1404 +    store_reg( REG_EAX, Rn );
 11.1405  :}
 11.1406  MOV #imm, Rn {:  
 11.1407      COUNT_INST(I_MOVI);
 11.1408 -    load_imm32( R_EAX, imm );
 11.1409 -    store_reg( R_EAX, Rn );
 11.1410 +    load_imm32( REG_EAX, imm );
 11.1411 +    store_reg( REG_EAX, Rn );
 11.1412  :}
 11.1413  MOV.B Rm, @Rn {:  
 11.1414      COUNT_INST(I_MOVB);
 11.1415 -    load_reg( R_EAX, Rn );
 11.1416 -    load_reg( R_EDX, Rm );
 11.1417 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
 11.1418 +    load_reg( REG_EAX, Rn );
 11.1419 +    load_reg( REG_EDX, Rm );
 11.1420 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
 11.1421      sh4_x86.tstate = TSTATE_NONE;
 11.1422  :}
 11.1423  MOV.B Rm, @-Rn {:  
 11.1424      COUNT_INST(I_MOVB);
 11.1425 -    load_reg( R_EAX, Rn );
 11.1426 -    LEA_r32disp8_r32( R_EAX, -1, R_EAX );
 11.1427 -    load_reg( R_EDX, Rm );
 11.1428 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
 11.1429 -    ADD_imm8s_sh4r( -1, REG_OFFSET(r[Rn]) );
 11.1430 +    load_reg( REG_EAX, Rn );
 11.1431 +    LEAL_r32disp_r32( REG_EAX, -1, REG_EAX );
 11.1432 +    load_reg( REG_EDX, Rm );
 11.1433 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
 11.1434 +    ADDL_imms_rbpdisp( -1, REG_OFFSET(r[Rn]) );
 11.1435      sh4_x86.tstate = TSTATE_NONE;
 11.1436  :}
 11.1437  MOV.B Rm, @(R0, Rn) {:  
 11.1438      COUNT_INST(I_MOVB);
 11.1439 -    load_reg( R_EAX, 0 );
 11.1440 -    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
 11.1441 -    load_reg( R_EDX, Rm );
 11.1442 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
 11.1443 +    load_reg( REG_EAX, 0 );
 11.1444 +    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
 11.1445 +    load_reg( REG_EDX, Rm );
 11.1446 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
 11.1447      sh4_x86.tstate = TSTATE_NONE;
 11.1448  :}
 11.1449  MOV.B R0, @(disp, GBR) {:  
 11.1450      COUNT_INST(I_MOVB);
 11.1451 -    load_spreg( R_EAX, R_GBR );
 11.1452 -    ADD_imm32_r32( disp, R_EAX );
 11.1453 -    load_reg( R_EDX, 0 );
 11.1454 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
 11.1455 +    load_spreg( REG_EAX, R_GBR );
 11.1456 +    ADDL_imms_r32( disp, REG_EAX );
 11.1457 +    load_reg( REG_EDX, 0 );
 11.1458 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
 11.1459      sh4_x86.tstate = TSTATE_NONE;
 11.1460  :}
 11.1461  MOV.B R0, @(disp, Rn) {:  
 11.1462      COUNT_INST(I_MOVB);
 11.1463 -    load_reg( R_EAX, Rn );
 11.1464 -    ADD_imm32_r32( disp, R_EAX );
 11.1465 -    load_reg( R_EDX, 0 );
 11.1466 -    MEM_WRITE_BYTE( R_EAX, R_EDX );
 11.1467 +    load_reg( REG_EAX, Rn );
 11.1468 +    ADDL_imms_r32( disp, REG_EAX );
 11.1469 +    load_reg( REG_EDX, 0 );
 11.1470 +    MEM_WRITE_BYTE( REG_EAX, REG_EDX );
 11.1471      sh4_x86.tstate = TSTATE_NONE;
 11.1472  :}
 11.1473  MOV.B @Rm, Rn {:  
 11.1474      COUNT_INST(I_MOVB);
 11.1475 -    load_reg( R_EAX, Rm );
 11.1476 -    MEM_READ_BYTE( R_EAX, R_EAX );
 11.1477 -    store_reg( R_EAX, Rn );
 11.1478 +    load_reg( REG_EAX, Rm );
 11.1479 +    MEM_READ_BYTE( REG_EAX, REG_EAX );
 11.1480 +    store_reg( REG_EAX, Rn );
 11.1481      sh4_x86.tstate = TSTATE_NONE;
 11.1482  :}
 11.1483  MOV.B @Rm+, Rn {:  
 11.1484      COUNT_INST(I_MOVB);
 11.1485 -    load_reg( R_EAX, Rm );
 11.1486 -    MEM_READ_BYTE( R_EAX, R_EAX );
 11.1487 +    load_reg( REG_EAX, Rm );
 11.1488 +    MEM_READ_BYTE( REG_EAX, REG_EAX );
 11.1489      if( Rm != Rn ) {
 11.1490 -    	ADD_imm8s_sh4r( 1, REG_OFFSET(r[Rm]) );
 11.1491 +    	ADDL_imms_rbpdisp( 1, REG_OFFSET(r[Rm]) );
 11.1492      }
 11.1493 -    store_reg( R_EAX, Rn );
 11.1494 +    store_reg( REG_EAX, Rn );
 11.1495      sh4_x86.tstate = TSTATE_NONE;
 11.1496  :}
 11.1497  MOV.B @(R0, Rm), Rn {:  
 11.1498      COUNT_INST(I_MOVB);
 11.1499 -    load_reg( R_EAX, 0 );
 11.1500 -    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
 11.1501 -    MEM_READ_BYTE( R_EAX, R_EAX );
 11.1502 -    store_reg( R_EAX, Rn );
 11.1503 +    load_reg( REG_EAX, 0 );
 11.1504 +    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
 11.1505 +    MEM_READ_BYTE( REG_EAX, REG_EAX );
 11.1506 +    store_reg( REG_EAX, Rn );
 11.1507      sh4_x86.tstate = TSTATE_NONE;
 11.1508  :}
 11.1509  MOV.B @(disp, GBR), R0 {:  
 11.1510      COUNT_INST(I_MOVB);
 11.1511 -    load_spreg( R_EAX, R_GBR );
 11.1512 -    ADD_imm32_r32( disp, R_EAX );
 11.1513 -    MEM_READ_BYTE( R_EAX, R_EAX );
 11.1514 -    store_reg( R_EAX, 0 );
 11.1515 +    load_spreg( REG_EAX, R_GBR );
 11.1516 +    ADDL_imms_r32( disp, REG_EAX );
 11.1517 +    MEM_READ_BYTE( REG_EAX, REG_EAX );
 11.1518 +    store_reg( REG_EAX, 0 );
 11.1519      sh4_x86.tstate = TSTATE_NONE;
 11.1520  :}
 11.1521  MOV.B @(disp, Rm), R0 {:  
 11.1522      COUNT_INST(I_MOVB);
 11.1523 -    load_reg( R_EAX, Rm );
 11.1524 -    ADD_imm32_r32( disp, R_EAX );
 11.1525 -    MEM_READ_BYTE( R_EAX, R_EAX );
 11.1526 -    store_reg( R_EAX, 0 );
 11.1527 +    load_reg( REG_EAX, Rm );
 11.1528 +    ADDL_imms_r32( disp, REG_EAX );
 11.1529 +    MEM_READ_BYTE( REG_EAX, REG_EAX );
 11.1530 +    store_reg( REG_EAX, 0 );
 11.1531      sh4_x86.tstate = TSTATE_NONE;
 11.1532  :}
 11.1533  MOV.L Rm, @Rn {:
 11.1534      COUNT_INST(I_MOVL);
 11.1535 -    load_reg( R_EAX, Rn );
 11.1536 -    check_walign32(R_EAX);
 11.1537 -    MOV_r32_r32( R_EAX, R_ECX );
 11.1538 -    AND_imm32_r32( 0xFC000000, R_ECX );
 11.1539 -    CMP_imm32_r32( 0xE0000000, R_ECX );
 11.1540 -    JNE_rel8( notsq );
 11.1541 -    AND_imm8s_r32( 0x3C, R_EAX );
 11.1542 -    load_reg( R_EDX, Rm );
 11.1543 -    MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
 11.1544 -    JMP_rel8(end);
 11.1545 +    load_reg( REG_EAX, Rn );
 11.1546 +    check_walign32(REG_EAX);
 11.1547 +    MOVL_r32_r32( REG_EAX, REG_ECX );
 11.1548 +    ANDL_imms_r32( 0xFC000000, REG_ECX );
 11.1549 +    CMPL_imms_r32( 0xE0000000, REG_ECX );
 11.1550 +    JNE_label( notsq );
 11.1551 +    ANDL_imms_r32( 0x3C, REG_EAX );
 11.1552 +    load_reg( REG_EDX, Rm );
 11.1553 +    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
 11.1554 +    JMP_label(end);
 11.1555      JMP_TARGET(notsq);
 11.1556 -    load_reg( R_EDX, Rm );
 11.1557 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.1558 +    load_reg( REG_EDX, Rm );
 11.1559 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.1560      JMP_TARGET(end);
 11.1561      sh4_x86.tstate = TSTATE_NONE;
 11.1562  :}
 11.1563  MOV.L Rm, @-Rn {:  
 11.1564      COUNT_INST(I_MOVL);
 11.1565 -    load_reg( R_EAX, Rn );
 11.1566 -    ADD_imm8s_r32( -4, R_EAX );
 11.1567 -    check_walign32( R_EAX );
 11.1568 -    load_reg( R_EDX, Rm );
 11.1569 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.1570 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.1571 +    load_reg( REG_EAX, Rn );
 11.1572 +    ADDL_imms_r32( -4, REG_EAX );
 11.1573 +    check_walign32( REG_EAX );
 11.1574 +    load_reg( REG_EDX, Rm );
 11.1575 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.1576 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.1577      sh4_x86.tstate = TSTATE_NONE;
 11.1578  :}
 11.1579  MOV.L Rm, @(R0, Rn) {:  
 11.1580      COUNT_INST(I_MOVL);
 11.1581 -    load_reg( R_EAX, 0 );
 11.1582 -    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
 11.1583 -    check_walign32( R_EAX );
 11.1584 -    load_reg( R_EDX, Rm );
 11.1585 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.1586 +    load_reg( REG_EAX, 0 );
 11.1587 +    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
 11.1588 +    check_walign32( REG_EAX );
 11.1589 +    load_reg( REG_EDX, Rm );
 11.1590 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.1591      sh4_x86.tstate = TSTATE_NONE;
 11.1592  :}
 11.1593  MOV.L R0, @(disp, GBR) {:  
 11.1594      COUNT_INST(I_MOVL);
 11.1595 -    load_spreg( R_EAX, R_GBR );
 11.1596 -    ADD_imm32_r32( disp, R_EAX );
 11.1597 -    check_walign32( R_EAX );
 11.1598 -    load_reg( R_EDX, 0 );
 11.1599 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.1600 +    load_spreg( REG_EAX, R_GBR );
 11.1601 +    ADDL_imms_r32( disp, REG_EAX );
 11.1602 +    check_walign32( REG_EAX );
 11.1603 +    load_reg( REG_EDX, 0 );
 11.1604 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.1605      sh4_x86.tstate = TSTATE_NONE;
 11.1606  :}
 11.1607  MOV.L Rm, @(disp, Rn) {:  
 11.1608      COUNT_INST(I_MOVL);
 11.1609 -    load_reg( R_EAX, Rn );
 11.1610 -    ADD_imm32_r32( disp, R_EAX );
 11.1611 -    check_walign32( R_EAX );
 11.1612 -    MOV_r32_r32( R_EAX, R_ECX );
 11.1613 -    AND_imm32_r32( 0xFC000000, R_ECX );
 11.1614 -    CMP_imm32_r32( 0xE0000000, R_ECX );
 11.1615 -    JNE_rel8( notsq );
 11.1616 -    AND_imm8s_r32( 0x3C, R_EAX );
 11.1617 -    load_reg( R_EDX, Rm );
 11.1618 -    MOV_r32_ebpr32disp32( R_EDX, R_EAX, REG_OFFSET(store_queue) );
 11.1619 -    JMP_rel8(end);
 11.1620 +    load_reg( REG_EAX, Rn );
 11.1621 +    ADDL_imms_r32( disp, REG_EAX );
 11.1622 +    check_walign32( REG_EAX );
 11.1623 +    MOVL_r32_r32( REG_EAX, REG_ECX );
 11.1624 +    ANDL_imms_r32( 0xFC000000, REG_ECX );
 11.1625 +    CMPL_imms_r32( 0xE0000000, REG_ECX );
 11.1626 +    JNE_label( notsq );
 11.1627 +    ANDL_imms_r32( 0x3C, REG_EAX );
 11.1628 +    load_reg( REG_EDX, Rm );
 11.1629 +    MOVL_r32_sib( REG_EDX, 0, REG_EBP, REG_EAX, REG_OFFSET(store_queue) );
 11.1630 +    JMP_label(end);
 11.1631      JMP_TARGET(notsq);
 11.1632 -    load_reg( R_EDX, Rm );
 11.1633 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.1634 +    load_reg( REG_EDX, Rm );
 11.1635 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.1636      JMP_TARGET(end);
 11.1637      sh4_x86.tstate = TSTATE_NONE;
 11.1638  :}
 11.1639  MOV.L @Rm, Rn {:  
 11.1640      COUNT_INST(I_MOVL);
 11.1641 -    load_reg( R_EAX, Rm );
 11.1642 -    check_ralign32( R_EAX );
 11.1643 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.1644 -    store_reg( R_EAX, Rn );
 11.1645 +    load_reg( REG_EAX, Rm );
 11.1646 +    check_ralign32( REG_EAX );
 11.1647 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.1648 +    store_reg( REG_EAX, Rn );
 11.1649      sh4_x86.tstate = TSTATE_NONE;
 11.1650  :}
 11.1651  MOV.L @Rm+, Rn {:  
 11.1652      COUNT_INST(I_MOVL);
 11.1653 -    load_reg( R_EAX, Rm );
 11.1654 -    check_ralign32( R_EAX );
 11.1655 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.1656 +    load_reg( REG_EAX, Rm );
 11.1657 +    check_ralign32( REG_EAX );
 11.1658 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.1659      if( Rm != Rn ) {
 11.1660 -    	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.1661 +    	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.1662      }
 11.1663 -    store_reg( R_EAX, Rn );
 11.1664 +    store_reg( REG_EAX, Rn );
 11.1665      sh4_x86.tstate = TSTATE_NONE;
 11.1666  :}
 11.1667  MOV.L @(R0, Rm), Rn {:  
 11.1668      COUNT_INST(I_MOVL);
 11.1669 -    load_reg( R_EAX, 0 );
 11.1670 -    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
 11.1671 -    check_ralign32( R_EAX );
 11.1672 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.1673 -    store_reg( R_EAX, Rn );
 11.1674 +    load_reg( REG_EAX, 0 );
 11.1675 +    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
 11.1676 +    check_ralign32( REG_EAX );
 11.1677 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.1678 +    store_reg( REG_EAX, Rn );
 11.1679      sh4_x86.tstate = TSTATE_NONE;
 11.1680  :}
 11.1681  MOV.L @(disp, GBR), R0 {:
 11.1682      COUNT_INST(I_MOVL);
 11.1683 -    load_spreg( R_EAX, R_GBR );
 11.1684 -    ADD_imm32_r32( disp, R_EAX );
 11.1685 -    check_ralign32( R_EAX );
 11.1686 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.1687 -    store_reg( R_EAX, 0 );
 11.1688 +    load_spreg( REG_EAX, R_GBR );
 11.1689 +    ADDL_imms_r32( disp, REG_EAX );
 11.1690 +    check_ralign32( REG_EAX );
 11.1691 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.1692 +    store_reg( REG_EAX, 0 );
 11.1693      sh4_x86.tstate = TSTATE_NONE;
 11.1694  :}
 11.1695  MOV.L @(disp, PC), Rn {:  
 11.1696 @@ -1307,108 +1310,108 @@
 11.1697  	    // behaviour to confirm) Unlikely to be anyone depending on this
 11.1698  	    // behaviour though.
 11.1699  	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
 11.1700 -	    MOV_moff32_EAX( ptr );
 11.1701 +	    MOVL_moffptr_eax( ptr );
 11.1702  	} else {
 11.1703  	    // Note: we use sh4r.pc for the calc as we could be running at a
 11.1704  	    // different virtual address than the translation was done with,
 11.1705  	    // but we can safely assume that the low bits are the same.
 11.1706 -	    load_imm32( R_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
 11.1707 -	    ADD_sh4r_r32( R_PC, R_EAX );
 11.1708 -	    MEM_READ_LONG( R_EAX, R_EAX );
 11.1709 +	    load_imm32( REG_EAX, (pc-sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
 11.1710 +	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
 11.1711 +	    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.1712  	    sh4_x86.tstate = TSTATE_NONE;
 11.1713  	}
 11.1714 -	store_reg( R_EAX, Rn );
 11.1715 +	store_reg( REG_EAX, Rn );
 11.1716      }
 11.1717  :}
 11.1718  MOV.L @(disp, Rm), Rn {:  
 11.1719      COUNT_INST(I_MOVL);
 11.1720 -    load_reg( R_EAX, Rm );
 11.1721 -    ADD_imm8s_r32( disp, R_EAX );
 11.1722 -    check_ralign32( R_EAX );
 11.1723 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.1724 -    store_reg( R_EAX, Rn );
 11.1725 +    load_reg( REG_EAX, Rm );
 11.1726 +    ADDL_imms_r32( disp, REG_EAX );
 11.1727 +    check_ralign32( REG_EAX );
 11.1728 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.1729 +    store_reg( REG_EAX, Rn );
 11.1730      sh4_x86.tstate = TSTATE_NONE;
 11.1731  :}
 11.1732  MOV.W Rm, @Rn {:  
 11.1733      COUNT_INST(I_MOVW);
 11.1734 -    load_reg( R_EAX, Rn );
 11.1735 -    check_walign16( R_EAX );
 11.1736 -    load_reg( R_EDX, Rm );
 11.1737 -    MEM_WRITE_WORD( R_EAX, R_EDX );
 11.1738 +    load_reg( REG_EAX, Rn );
 11.1739 +    check_walign16( REG_EAX );
 11.1740 +    load_reg( REG_EDX, Rm );
 11.1741 +    MEM_WRITE_WORD( REG_EAX, REG_EDX );
 11.1742      sh4_x86.tstate = TSTATE_NONE;
 11.1743  :}
 11.1744  MOV.W Rm, @-Rn {:  
 11.1745      COUNT_INST(I_MOVW);
 11.1746 -    load_reg( R_EAX, Rn );
 11.1747 -    check_walign16( R_EAX );
 11.1748 -    LEA_r32disp8_r32( R_EAX, -2, R_EAX );
 11.1749 -    load_reg( R_EDX, Rm );
 11.1750 -    MEM_WRITE_WORD( R_EAX, R_EDX );
 11.1751 -    ADD_imm8s_sh4r( -2, REG_OFFSET(r[Rn]) );
 11.1752 +    load_reg( REG_EAX, Rn );
 11.1753 +    check_walign16( REG_EAX );
 11.1754 +    LEAL_r32disp_r32( REG_EAX, -2, REG_EAX );
 11.1755 +    load_reg( REG_EDX, Rm );
 11.1756 +    MEM_WRITE_WORD( REG_EAX, REG_EDX );
 11.1757 +    ADDL_imms_rbpdisp( -2, REG_OFFSET(r[Rn]) );
 11.1758      sh4_x86.tstate = TSTATE_NONE;
 11.1759  :}
 11.1760  MOV.W Rm, @(R0, Rn) {:  
 11.1761      COUNT_INST(I_MOVW);
 11.1762 -    load_reg( R_EAX, 0 );
 11.1763 -    ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
 11.1764 -    check_walign16( R_EAX );
 11.1765 -    load_reg( R_EDX, Rm );
 11.1766 -    MEM_WRITE_WORD( R_EAX, R_EDX );
 11.1767 +    load_reg( REG_EAX, 0 );
 11.1768 +    ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
 11.1769 +    check_walign16( REG_EAX );
 11.1770 +    load_reg( REG_EDX, Rm );
 11.1771 +    MEM_WRITE_WORD( REG_EAX, REG_EDX );
 11.1772      sh4_x86.tstate = TSTATE_NONE;
 11.1773  :}
 11.1774  MOV.W R0, @(disp, GBR) {:  
 11.1775      COUNT_INST(I_MOVW);
 11.1776 -    load_spreg( R_EAX, R_GBR );
 11.1777 -    ADD_imm32_r32( disp, R_EAX );
 11.1778 -    check_walign16( R_EAX );
 11.1779 -    load_reg( R_EDX, 0 );
 11.1780 -    MEM_WRITE_WORD( R_EAX, R_EDX );
 11.1781 +    load_spreg( REG_EAX, R_GBR );
 11.1782 +    ADDL_imms_r32( disp, REG_EAX );
 11.1783 +    check_walign16( REG_EAX );
 11.1784 +    load_reg( REG_EDX, 0 );
 11.1785 +    MEM_WRITE_WORD( REG_EAX, REG_EDX );
 11.1786      sh4_x86.tstate = TSTATE_NONE;
 11.1787  :}
 11.1788  MOV.W R0, @(disp, Rn) {:  
 11.1789      COUNT_INST(I_MOVW);
 11.1790 -    load_reg( R_EAX, Rn );
 11.1791 -    ADD_imm32_r32( disp, R_EAX );
 11.1792 -    check_walign16( R_EAX );
 11.1793 -    load_reg( R_EDX, 0 );
 11.1794 -    MEM_WRITE_WORD( R_EAX, R_EDX );
 11.1795 +    load_reg( REG_EAX, Rn );
 11.1796 +    ADDL_imms_r32( disp, REG_EAX );
 11.1797 +    check_walign16( REG_EAX );
 11.1798 +    load_reg( REG_EDX, 0 );
 11.1799 +    MEM_WRITE_WORD( REG_EAX, REG_EDX );
 11.1800      sh4_x86.tstate = TSTATE_NONE;
 11.1801  :}
 11.1802  MOV.W @Rm, Rn {:  
 11.1803      COUNT_INST(I_MOVW);
 11.1804 -    load_reg( R_EAX, Rm );
 11.1805 -    check_ralign16( R_EAX );
 11.1806 -    MEM_READ_WORD( R_EAX, R_EAX );
 11.1807 -    store_reg( R_EAX, Rn );
 11.1808 +    load_reg( REG_EAX, Rm );
 11.1809 +    check_ralign16( REG_EAX );
 11.1810 +    MEM_READ_WORD( REG_EAX, REG_EAX );
 11.1811 +    store_reg( REG_EAX, Rn );
 11.1812      sh4_x86.tstate = TSTATE_NONE;
 11.1813  :}
 11.1814  MOV.W @Rm+, Rn {:  
 11.1815      COUNT_INST(I_MOVW);
 11.1816 -    load_reg( R_EAX, Rm );
 11.1817 -    check_ralign16( R_EAX );
 11.1818 -    MEM_READ_WORD( R_EAX, R_EAX );
 11.1819 +    load_reg( REG_EAX, Rm );
 11.1820 +    check_ralign16( REG_EAX );
 11.1821 +    MEM_READ_WORD( REG_EAX, REG_EAX );
 11.1822      if( Rm != Rn ) {
 11.1823 -        ADD_imm8s_sh4r( 2, REG_OFFSET(r[Rm]) );
 11.1824 +        ADDL_imms_rbpdisp( 2, REG_OFFSET(r[Rm]) );
 11.1825      }
 11.1826 -    store_reg( R_EAX, Rn );
 11.1827 +    store_reg( REG_EAX, Rn );
 11.1828      sh4_x86.tstate = TSTATE_NONE;
 11.1829  :}
 11.1830  MOV.W @(R0, Rm), Rn {:  
 11.1831      COUNT_INST(I_MOVW);
 11.1832 -    load_reg( R_EAX, 0 );
 11.1833 -    ADD_sh4r_r32( REG_OFFSET(r[Rm]), R_EAX );
 11.1834 -    check_ralign16( R_EAX );
 11.1835 -    MEM_READ_WORD( R_EAX, R_EAX );
 11.1836 -    store_reg( R_EAX, Rn );
 11.1837 +    load_reg( REG_EAX, 0 );
 11.1838 +    ADDL_rbpdisp_r32( REG_OFFSET(r[Rm]), REG_EAX );
 11.1839 +    check_ralign16( REG_EAX );
 11.1840 +    MEM_READ_WORD( REG_EAX, REG_EAX );
 11.1841 +    store_reg( REG_EAX, Rn );
 11.1842      sh4_x86.tstate = TSTATE_NONE;
 11.1843  :}
 11.1844  MOV.W @(disp, GBR), R0 {:  
 11.1845      COUNT_INST(I_MOVW);
 11.1846 -    load_spreg( R_EAX, R_GBR );
 11.1847 -    ADD_imm32_r32( disp, R_EAX );
 11.1848 -    check_ralign16( R_EAX );
 11.1849 -    MEM_READ_WORD( R_EAX, R_EAX );
 11.1850 -    store_reg( R_EAX, 0 );
 11.1851 +    load_spreg( REG_EAX, R_GBR );
 11.1852 +    ADDL_imms_r32( disp, REG_EAX );
 11.1853 +    check_ralign16( REG_EAX );
 11.1854 +    MEM_READ_WORD( REG_EAX, REG_EAX );
 11.1855 +    store_reg( REG_EAX, 0 );
 11.1856      sh4_x86.tstate = TSTATE_NONE;
 11.1857  :}
 11.1858  MOV.W @(disp, PC), Rn {:  
 11.1859 @@ -1420,24 +1423,24 @@
 11.1860  	uint32_t target = pc + disp + 4;
 11.1861  	if( IS_IN_ICACHE(target) ) {
 11.1862  	    sh4ptr_t ptr = GET_ICACHE_PTR(target);
 11.1863 -	    MOV_moff32_EAX( ptr );
 11.1864 -	    MOVSX_r16_r32( R_EAX, R_EAX );
 11.1865 +	    MOVL_moffptr_eax( ptr );
 11.1866 +	    MOVSXL_r16_r32( REG_EAX, REG_EAX );
 11.1867  	} else {
 11.1868 -	    load_imm32( R_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
 11.1869 -	    ADD_sh4r_r32( R_PC, R_EAX );
 11.1870 -	    MEM_READ_WORD( R_EAX, R_EAX );
 11.1871 +	    load_imm32( REG_EAX, (pc - sh4_x86.block_start_pc) + disp + 4 );
 11.1872 +	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
 11.1873 +	    MEM_READ_WORD( REG_EAX, REG_EAX );
 11.1874  	    sh4_x86.tstate = TSTATE_NONE;
 11.1875  	}
 11.1876 -	store_reg( R_EAX, Rn );
 11.1877 +	store_reg( REG_EAX, Rn );
 11.1878      }
 11.1879  :}
 11.1880  MOV.W @(disp, Rm), R0 {:  
 11.1881      COUNT_INST(I_MOVW);
 11.1882 -    load_reg( R_EAX, Rm );
 11.1883 -    ADD_imm32_r32( disp, R_EAX );
 11.1884 -    check_ralign16( R_EAX );
 11.1885 -    MEM_READ_WORD( R_EAX, R_EAX );
 11.1886 -    store_reg( R_EAX, 0 );
 11.1887 +    load_reg( REG_EAX, Rm );
 11.1888 +    ADDL_imms_r32( disp, REG_EAX );
 11.1889 +    check_ralign16( REG_EAX );
 11.1890 +    MEM_READ_WORD( REG_EAX, REG_EAX );
 11.1891 +    store_reg( REG_EAX, 0 );
 11.1892      sh4_x86.tstate = TSTATE_NONE;
 11.1893  :}
 11.1894  MOVA @(disp, PC), R0 {:  
 11.1895 @@ -1445,18 +1448,18 @@
 11.1896      if( sh4_x86.in_delay_slot ) {
 11.1897  	SLOTILLEGAL();
 11.1898      } else {
 11.1899 -	load_imm32( R_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
 11.1900 -	ADD_sh4r_r32( R_PC, R_ECX );
 11.1901 -	store_reg( R_ECX, 0 );
 11.1902 +	load_imm32( REG_ECX, (pc - sh4_x86.block_start_pc) + disp + 4 - (pc&0x03) );
 11.1903 +	ADDL_rbpdisp_r32( R_PC, REG_ECX );
 11.1904 +	store_reg( REG_ECX, 0 );
 11.1905  	sh4_x86.tstate = TSTATE_NONE;
 11.1906      }
 11.1907  :}
 11.1908  MOVCA.L R0, @Rn {:  
 11.1909      COUNT_INST(I_MOVCA);
 11.1910 -    load_reg( R_EAX, Rn );
 11.1911 -    check_walign32( R_EAX );
 11.1912 -    load_reg( R_EDX, 0 );
 11.1913 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.1914 +    load_reg( REG_EAX, Rn );
 11.1915 +    check_walign32( REG_EAX );
 11.1916 +    load_reg( REG_EDX, 0 );
 11.1917 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.1918      sh4_x86.tstate = TSTATE_NONE;
 11.1919  :}
 11.1920  
 11.1921 @@ -1467,7 +1470,7 @@
 11.1922  	SLOTILLEGAL();
 11.1923      } else {
 11.1924  	sh4vma_t target = disp + pc + 4;
 11.1925 -	JT_rel8( nottaken );
 11.1926 +	JT_label( nottaken );
 11.1927  	exit_block_rel(target, pc+2 );
 11.1928  	JMP_TARGET(nottaken);
 11.1929  	return 2;
 11.1930 @@ -1480,22 +1483,23 @@
 11.1931      } else {
 11.1932  	sh4_x86.in_delay_slot = DELAY_PC;
 11.1933  	if( UNTRANSLATABLE(pc+2) ) {
 11.1934 -	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
 11.1935 -	    JT_rel8(nottaken);
 11.1936 -	    ADD_imm32_r32( disp, R_EAX );
 11.1937 +	    load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc );
 11.1938 +	    JT_label(nottaken);
 11.1939 +	    ADDL_imms_r32( disp, REG_EAX );
 11.1940  	    JMP_TARGET(nottaken);
 11.1941 -	    ADD_sh4r_r32( R_PC, R_EAX );
 11.1942 -	    store_spreg( R_EAX, R_NEW_PC );
 11.1943 +	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
 11.1944 +	    store_spreg( REG_EAX, R_NEW_PC );
 11.1945  	    exit_block_emu(pc+2);
 11.1946  	    sh4_x86.branch_taken = TRUE;
 11.1947  	    return 2;
 11.1948  	} else {
 11.1949  	    if( sh4_x86.tstate == TSTATE_NONE ) {
 11.1950 -		CMP_imm8s_sh4r( 1, R_T );
 11.1951 +		CMPL_imms_rbpdisp( 1, R_T );
 11.1952  		sh4_x86.tstate = TSTATE_E;
 11.1953  	    }
 11.1954  	    sh4vma_t target = disp + pc + 4;
 11.1955 -	    OP(0x0F); OP(0x80+sh4_x86.tstate); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JT rel32
 11.1956 +	    JCC_cc_rel32(sh4_x86.tstate,0);
 11.1957 +	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
 11.1958  	    int save_tstate = sh4_x86.tstate;
 11.1959  	    sh4_translate_instruction(pc+2);
 11.1960  	    exit_block_rel( target, pc+4 );
 11.1961 @@ -1516,9 +1520,9 @@
 11.1962  	sh4_x86.in_delay_slot = DELAY_PC;
 11.1963  	sh4_x86.branch_taken = TRUE;
 11.1964  	if( UNTRANSLATABLE(pc+2) ) {
 11.1965 -	    load_spreg( R_EAX, R_PC );
 11.1966 -	    ADD_imm32_r32( pc + disp + 4 - sh4_x86.block_start_pc, R_EAX );
 11.1967 -	    store_spreg( R_EAX, R_NEW_PC );
 11.1968 +	    load_spreg( REG_EAX, R_PC );
 11.1969 +	    ADDL_imms_r32( pc + disp + 4 - sh4_x86.block_start_pc, REG_EAX );
 11.1970 +	    store_spreg( REG_EAX, R_NEW_PC );
 11.1971  	    exit_block_emu(pc+2);
 11.1972  	    return 2;
 11.1973  	} else {
 11.1974 @@ -1533,10 +1537,10 @@
 11.1975      if( sh4_x86.in_delay_slot ) {
 11.1976  	SLOTILLEGAL();
 11.1977      } else {
 11.1978 -	load_spreg( R_EAX, R_PC );
 11.1979 -	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
 11.1980 -	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
 11.1981 -	store_spreg( R_EAX, R_NEW_PC );
 11.1982 +	load_spreg( REG_EAX, R_PC );
 11.1983 +	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
 11.1984 +	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
 11.1985 +	store_spreg( REG_EAX, R_NEW_PC );
 11.1986  	sh4_x86.in_delay_slot = DELAY_PC;
 11.1987  	sh4_x86.tstate = TSTATE_NONE;
 11.1988  	sh4_x86.branch_taken = TRUE;
 11.1989 @@ -1555,15 +1559,15 @@
 11.1990      if( sh4_x86.in_delay_slot ) {
 11.1991  	SLOTILLEGAL();
 11.1992      } else {
 11.1993 -	load_spreg( R_EAX, R_PC );
 11.1994 -	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
 11.1995 -	store_spreg( R_EAX, R_PR );
 11.1996 +	load_spreg( REG_EAX, R_PC );
 11.1997 +	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
 11.1998 +	store_spreg( REG_EAX, R_PR );
 11.1999  	sh4_x86.in_delay_slot = DELAY_PC;
 11.2000  	sh4_x86.branch_taken = TRUE;
 11.2001  	sh4_x86.tstate = TSTATE_NONE;
 11.2002  	if( UNTRANSLATABLE(pc+2) ) {
 11.2003 -	    ADD_imm32_r32( disp, R_EAX );
 11.2004 -	    store_spreg( R_EAX, R_NEW_PC );
 11.2005 +	    ADDL_imms_r32( disp, REG_EAX );
 11.2006 +	    store_spreg( REG_EAX, R_NEW_PC );
 11.2007  	    exit_block_emu(pc+2);
 11.2008  	    return 2;
 11.2009  	} else {
 11.2010 @@ -1578,11 +1582,11 @@
 11.2011      if( sh4_x86.in_delay_slot ) {
 11.2012  	SLOTILLEGAL();
 11.2013      } else {
 11.2014 -	load_spreg( R_EAX, R_PC );
 11.2015 -	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
 11.2016 -	store_spreg( R_EAX, R_PR );
 11.2017 -	ADD_sh4r_r32( REG_OFFSET(r[Rn]), R_EAX );
 11.2018 -	store_spreg( R_EAX, R_NEW_PC );
 11.2019 +	load_spreg( REG_EAX, R_PC );
 11.2020 +	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
 11.2021 +	store_spreg( REG_EAX, R_PR );
 11.2022 +	ADDL_rbpdisp_r32( REG_OFFSET(r[Rn]), REG_EAX );
 11.2023 +	store_spreg( REG_EAX, R_NEW_PC );
 11.2024  
 11.2025  	sh4_x86.in_delay_slot = DELAY_PC;
 11.2026  	sh4_x86.tstate = TSTATE_NONE;
 11.2027 @@ -1603,7 +1607,7 @@
 11.2028  	SLOTILLEGAL();
 11.2029      } else {
 11.2030  	sh4vma_t target = disp + pc + 4;
 11.2031 -	JF_rel8( nottaken );
 11.2032 +	JF_label( nottaken );
 11.2033  	exit_block_rel(target, pc+2 );
 11.2034  	JMP_TARGET(nottaken);
 11.2035  	return 2;
 11.2036 @@ -1616,21 +1620,23 @@
 11.2037      } else {
 11.2038  	sh4_x86.in_delay_slot = DELAY_PC;
 11.2039  	if( UNTRANSLATABLE(pc+2) ) {
 11.2040 -	    load_imm32( R_EAX, pc + 4 - sh4_x86.block_start_pc );
 11.2041 -	    JF_rel8(nottaken);
 11.2042 -	    ADD_imm32_r32( disp, R_EAX );
 11.2043 +	    load_imm32( REG_EAX, pc + 4 - sh4_x86.block_start_pc );
 11.2044 +	    JF_label(nottaken);
 11.2045 +	    ADDL_imms_r32( disp, REG_EAX );
 11.2046  	    JMP_TARGET(nottaken);
 11.2047 -	    ADD_sh4r_r32( R_PC, R_EAX );
 11.2048 -	    store_spreg( R_EAX, R_NEW_PC );
 11.2049 +	    ADDL_rbpdisp_r32( R_PC, REG_EAX );
 11.2050 +	    store_spreg( REG_EAX, R_NEW_PC );
 11.2051  	    exit_block_emu(pc+2);
 11.2052  	    sh4_x86.branch_taken = TRUE;
 11.2053  	    return 2;
 11.2054  	} else {
 11.2055  	    if( sh4_x86.tstate == TSTATE_NONE ) {
 11.2056 -		CMP_imm8s_sh4r( 1, R_T );
 11.2057 +		CMPL_imms_rbpdisp( 1, R_T );
 11.2058  		sh4_x86.tstate = TSTATE_E;
 11.2059  	    }
 11.2060 -	    OP(0x0F); OP(0x80+(sh4_x86.tstate^1)); uint32_t *patch = (uint32_t *)xlat_output; OP32(0); // JF rel32
 11.2061 +	    JCC_cc_rel32(sh4_x86.tstate^1,0);
 11.2062 +	    uint32_t *patch = ((uint32_t *)xlat_output)-1;
 11.2063 +
 11.2064  	    int save_tstate = sh4_x86.tstate;
 11.2065  	    sh4_translate_instruction(pc+2);
 11.2066  	    exit_block_rel( disp + pc + 4, pc+4 );
 11.2067 @@ -1647,8 +1653,8 @@
 11.2068      if( sh4_x86.in_delay_slot ) {
 11.2069  	SLOTILLEGAL();
 11.2070      } else {
 11.2071 -	load_reg( R_ECX, Rn );
 11.2072 -	store_spreg( R_ECX, R_NEW_PC );
 11.2073 +	load_reg( REG_ECX, Rn );
 11.2074 +	store_spreg( REG_ECX, R_NEW_PC );
 11.2075  	sh4_x86.in_delay_slot = DELAY_PC;
 11.2076  	sh4_x86.branch_taken = TRUE;
 11.2077  	if( UNTRANSLATABLE(pc+2) ) {
 11.2078 @@ -1666,11 +1672,11 @@
 11.2079      if( sh4_x86.in_delay_slot ) {
 11.2080  	SLOTILLEGAL();
 11.2081      } else {
 11.2082 -	load_spreg( R_EAX, R_PC );
 11.2083 -	ADD_imm32_r32( pc + 4 - sh4_x86.block_start_pc, R_EAX );
 11.2084 -	store_spreg( R_EAX, R_PR );
 11.2085 -	load_reg( R_ECX, Rn );
 11.2086 -	store_spreg( R_ECX, R_NEW_PC );
 11.2087 +	load_spreg( REG_EAX, R_PC );
 11.2088 +	ADDL_imms_r32( pc + 4 - sh4_x86.block_start_pc, REG_EAX );
 11.2089 +	store_spreg( REG_EAX, R_PR );
 11.2090 +	load_reg( REG_ECX, Rn );
 11.2091 +	store_spreg( REG_ECX, R_NEW_PC );
 11.2092  	sh4_x86.in_delay_slot = DELAY_PC;
 11.2093  	sh4_x86.branch_taken = TRUE;
 11.2094  	sh4_x86.tstate = TSTATE_NONE;
 11.2095 @@ -1690,10 +1696,10 @@
 11.2096  	SLOTILLEGAL();
 11.2097      } else {
 11.2098  	check_priv();
 11.2099 -	load_spreg( R_ECX, R_SPC );
 11.2100 -	store_spreg( R_ECX, R_NEW_PC );
 11.2101 -	load_spreg( R_EAX, R_SSR );
 11.2102 -	call_func1( sh4_write_sr, R_EAX );
 11.2103 +	load_spreg( REG_ECX, R_SPC );
 11.2104 +	store_spreg( REG_ECX, R_NEW_PC );
 11.2105 +	load_spreg( REG_EAX, R_SSR );
 11.2106 +	call_func1( sh4_write_sr, REG_EAX );
 11.2107  	sh4_x86.in_delay_slot = DELAY_PC;
 11.2108  	sh4_x86.fpuen_checked = FALSE;
 11.2109  	sh4_x86.tstate = TSTATE_NONE;
 11.2110 @@ -1713,8 +1719,8 @@
 11.2111      if( sh4_x86.in_delay_slot ) {
 11.2112  	SLOTILLEGAL();
 11.2113      } else {
 11.2114 -	load_spreg( R_ECX, R_PR );
 11.2115 -	store_spreg( R_ECX, R_NEW_PC );
 11.2116 +	load_spreg( REG_ECX, R_PR );
 11.2117 +	store_spreg( REG_ECX, R_NEW_PC );
 11.2118  	sh4_x86.in_delay_slot = DELAY_PC;
 11.2119  	sh4_x86.branch_taken = TRUE;
 11.2120  	if( UNTRANSLATABLE(pc+2) ) {
 11.2121 @@ -1732,10 +1738,10 @@
 11.2122      if( sh4_x86.in_delay_slot ) {
 11.2123  	SLOTILLEGAL();
 11.2124      } else {
 11.2125 -	load_imm32( R_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
 11.2126 -	ADD_r32_sh4r( R_ECX, R_PC );
 11.2127 -	load_imm32( R_EAX, imm );
 11.2128 -	call_func1( sh4_raise_trap, R_EAX );
 11.2129 +	load_imm32( REG_ECX, pc+2 - sh4_x86.block_start_pc );   // 5
 11.2130 +	ADDL_r32_rbpdisp( REG_ECX, R_PC );
 11.2131 +	load_imm32( REG_EAX, imm );
 11.2132 +	call_func1( sh4_raise_trap, REG_EAX );
 11.2133  	sh4_x86.tstate = TSTATE_NONE;
 11.2134  	exit_block_pcset(pc+2);
 11.2135  	sh4_x86.branch_taken = TRUE;
 11.2136 @@ -1754,15 +1760,15 @@
 11.2137  
 11.2138  CLRMAC {:  
 11.2139      COUNT_INST(I_CLRMAC);
 11.2140 -    XOR_r32_r32(R_EAX, R_EAX);
 11.2141 -    store_spreg( R_EAX, R_MACL );
 11.2142 -    store_spreg( R_EAX, R_MACH );
 11.2143 +    XORL_r32_r32(REG_EAX, REG_EAX);
 11.2144 +    store_spreg( REG_EAX, R_MACL );
 11.2145 +    store_spreg( REG_EAX, R_MACH );
 11.2146      sh4_x86.tstate = TSTATE_NONE;
 11.2147  :}
 11.2148  CLRS {:
 11.2149      COUNT_INST(I_CLRS);
 11.2150      CLC();
 11.2151 -    SETC_sh4r(R_S);
 11.2152 +    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
 11.2153      sh4_x86.tstate = TSTATE_NONE;
 11.2154  :}
 11.2155  CLRT {:  
 11.2156 @@ -1774,7 +1780,7 @@
 11.2157  SETS {:  
 11.2158      COUNT_INST(I_SETS);
 11.2159      STC();
 11.2160 -    SETC_sh4r(R_S);
 11.2161 +    SETCCB_cc_rbpdisp(X86_COND_C, R_S);
 11.2162      sh4_x86.tstate = TSTATE_NONE;
 11.2163  :}
 11.2164  SETT {:  
 11.2165 @@ -1789,136 +1795,136 @@
 11.2166      COUNT_INST(I_FMOV1);
 11.2167      check_fpuen();
 11.2168      if( sh4_x86.double_size ) {
 11.2169 -        load_dr0( R_EAX, FRm );
 11.2170 -        load_dr1( R_ECX, FRm );
 11.2171 -        store_dr0( R_EAX, FRn );
 11.2172 -        store_dr1( R_ECX, FRn );
 11.2173 +        load_dr0( REG_EAX, FRm );
 11.2174 +        load_dr1( REG_ECX, FRm );
 11.2175 +        store_dr0( REG_EAX, FRn );
 11.2176 +        store_dr1( REG_ECX, FRn );
 11.2177      } else {
 11.2178 -        load_fr( R_EAX, FRm ); // SZ=0 branch
 11.2179 -        store_fr( R_EAX, FRn );
 11.2180 +        load_fr( REG_EAX, FRm ); // SZ=0 branch
 11.2181 +        store_fr( REG_EAX, FRn );
 11.2182      }
 11.2183  :}
 11.2184  FMOV FRm, @Rn {: 
 11.2185      COUNT_INST(I_FMOV2);
 11.2186      check_fpuen();
 11.2187 -    load_reg( R_EAX, Rn );
 11.2188 +    load_reg( REG_EAX, Rn );
 11.2189      if( sh4_x86.double_size ) {
 11.2190 -        check_walign64( R_EAX );
 11.2191 -        load_dr0( R_EDX, FRm );
 11.2192 -        MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2193 -        load_reg( R_EAX, Rn );
 11.2194 -        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
 11.2195 -        load_dr1( R_EDX, FRm );
 11.2196 -        MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2197 +        check_walign64( REG_EAX );
 11.2198 +        load_dr0( REG_EDX, FRm );
 11.2199 +        MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2200 +        load_reg( REG_EAX, Rn );
 11.2201 +        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
 11.2202 +        load_dr1( REG_EDX, FRm );
 11.2203 +        MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2204      } else {
 11.2205 -        check_walign32( R_EAX );
 11.2206 -        load_fr( R_EDX, FRm );
 11.2207 -        MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2208 +        check_walign32( REG_EAX );
 11.2209 +        load_fr( REG_EDX, FRm );
 11.2210 +        MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2211      }
 11.2212      sh4_x86.tstate = TSTATE_NONE;
 11.2213  :}
 11.2214  FMOV @Rm, FRn {:  
 11.2215      COUNT_INST(I_FMOV5);
 11.2216      check_fpuen();
 11.2217 -    load_reg( R_EAX, Rm );
 11.2218 +    load_reg( REG_EAX, Rm );
 11.2219      if( sh4_x86.double_size ) {
 11.2220 -        check_ralign64( R_EAX );
 11.2221 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2222 -        store_dr0( R_EAX, FRn );
 11.2223 -        load_reg( R_EAX, Rm );
 11.2224 -        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
 11.2225 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2226 -        store_dr1( R_EAX, FRn );
 11.2227 +        check_ralign64( REG_EAX );
 11.2228 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2229 +        store_dr0( REG_EAX, FRn );
 11.2230 +        load_reg( REG_EAX, Rm );
 11.2231 +        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
 11.2232 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2233 +        store_dr1( REG_EAX, FRn );
 11.2234      } else {
 11.2235 -        check_ralign32( R_EAX );
 11.2236 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2237 -        store_fr( R_EAX, FRn );
 11.2238 +        check_ralign32( REG_EAX );
 11.2239 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2240 +        store_fr( REG_EAX, FRn );
 11.2241      }
 11.2242      sh4_x86.tstate = TSTATE_NONE;
 11.2243  :}
 11.2244  FMOV FRm, @-Rn {:  
 11.2245      COUNT_INST(I_FMOV3);
 11.2246      check_fpuen();
 11.2247 -    load_reg( R_EAX, Rn );
 11.2248 +    load_reg( REG_EAX, Rn );
 11.2249      if( sh4_x86.double_size ) {
 11.2250 -        check_walign64( R_EAX );
 11.2251 -        LEA_r32disp8_r32( R_EAX, -8, R_EAX );
 11.2252 -        load_dr0( R_EDX, FRm );
 11.2253 -        MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2254 -        load_reg( R_EAX, Rn );
 11.2255 -        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
 11.2256 -        load_dr1( R_EDX, FRm );
 11.2257 -        MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2258 -        ADD_imm8s_sh4r(-8,REG_OFFSET(r[Rn]));
 11.2259 +        check_walign64( REG_EAX );
 11.2260 +        LEAL_r32disp_r32( REG_EAX, -8, REG_EAX );
 11.2261 +        load_dr0( REG_EDX, FRm );
 11.2262 +        MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2263 +        load_reg( REG_EAX, Rn );
 11.2264 +        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
 11.2265 +        load_dr1( REG_EDX, FRm );
 11.2266 +        MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2267 +        ADDL_imms_rbpdisp(-8,REG_OFFSET(r[Rn]));
 11.2268      } else {
 11.2269 -        check_walign32( R_EAX );
 11.2270 -        LEA_r32disp8_r32( R_EAX, -4, R_EAX );
 11.2271 -        load_fr( R_EDX, FRm );
 11.2272 -        MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2273 -        ADD_imm8s_sh4r(-4,REG_OFFSET(r[Rn]));
 11.2274 +        check_walign32( REG_EAX );
 11.2275 +        LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
 11.2276 +        load_fr( REG_EDX, FRm );
 11.2277 +        MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2278 +        ADDL_imms_rbpdisp(-4,REG_OFFSET(r[Rn]));
 11.2279      }
 11.2280      sh4_x86.tstate = TSTATE_NONE;
 11.2281  :}
 11.2282  FMOV @Rm+, FRn {:
 11.2283      COUNT_INST(I_FMOV6);
 11.2284      check_fpuen();
 11.2285 -    load_reg( R_EAX, Rm );
 11.2286 +    load_reg( REG_EAX, Rm );
 11.2287      if( sh4_x86.double_size ) {
 11.2288 -        check_ralign64( R_EAX );
 11.2289 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2290 -        store_dr0( R_EAX, FRn );
 11.2291 -        load_reg( R_EAX, Rm );
 11.2292 -        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
 11.2293 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2294 -        store_dr1( R_EAX, FRn );
 11.2295 -        ADD_imm8s_sh4r( 8, REG_OFFSET(r[Rm]) );
 11.2296 +        check_ralign64( REG_EAX );
 11.2297 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2298 +        store_dr0( REG_EAX, FRn );
 11.2299 +        load_reg( REG_EAX, Rm );
 11.2300 +        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
 11.2301 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2302 +        store_dr1( REG_EAX, FRn );
 11.2303 +        ADDL_imms_rbpdisp( 8, REG_OFFSET(r[Rm]) );
 11.2304      } else {
 11.2305 -        check_ralign32( R_EAX );
 11.2306 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2307 -        store_fr( R_EAX, FRn );
 11.2308 -        ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2309 +        check_ralign32( REG_EAX );
 11.2310 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2311 +        store_fr( REG_EAX, FRn );
 11.2312 +        ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2313      }
 11.2314      sh4_x86.tstate = TSTATE_NONE;
 11.2315  :}
 11.2316  FMOV FRm, @(R0, Rn) {:  
 11.2317      COUNT_INST(I_FMOV4);
 11.2318      check_fpuen();
 11.2319 -    load_reg( R_EAX, Rn );
 11.2320 -    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
 11.2321 +    load_reg( REG_EAX, Rn );
 11.2322 +    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
 11.2323      if( sh4_x86.double_size ) {
 11.2324 -        check_walign64( R_EAX );
 11.2325 -        load_dr0( R_EDX, FRm );
 11.2326 -        MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2327 -        load_reg( R_EAX, Rn );
 11.2328 -        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
 11.2329 -        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
 11.2330 -        load_dr1( R_EDX, FRm );
 11.2331 -        MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2332 +        check_walign64( REG_EAX );
 11.2333 +        load_dr0( REG_EDX, FRm );
 11.2334 +        MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2335 +        load_reg( REG_EAX, Rn );
 11.2336 +        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
 11.2337 +        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
 11.2338 +        load_dr1( REG_EDX, FRm );
 11.2339 +        MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2340      } else {
 11.2341 -        check_walign32( R_EAX );
 11.2342 -        load_fr( R_EDX, FRm );
 11.2343 -        MEM_WRITE_LONG( R_EAX, R_EDX ); // 12
 11.2344 +        check_walign32( REG_EAX );
 11.2345 +        load_fr( REG_EDX, FRm );
 11.2346 +        MEM_WRITE_LONG( REG_EAX, REG_EDX ); // 12
 11.2347      }
 11.2348      sh4_x86.tstate = TSTATE_NONE;
 11.2349  :}
 11.2350  FMOV @(R0, Rm), FRn {:  
 11.2351      COUNT_INST(I_FMOV7);
 11.2352      check_fpuen();
 11.2353 -    load_reg( R_EAX, Rm );
 11.2354 -    ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
 11.2355 +    load_reg( REG_EAX, Rm );
 11.2356 +    ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
 11.2357      if( sh4_x86.double_size ) {
 11.2358 -        check_ralign64( R_EAX );
 11.2359 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2360 -        store_dr0( R_EAX, FRn );
 11.2361 -        load_reg( R_EAX, Rm );
 11.2362 -        ADD_sh4r_r32( REG_OFFSET(r[0]), R_EAX );
 11.2363 -        LEA_r32disp8_r32( R_EAX, 4, R_EAX );
 11.2364 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2365 -        store_dr1( R_EAX, FRn );
 11.2366 +        check_ralign64( REG_EAX );
 11.2367 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2368 +        store_dr0( REG_EAX, FRn );
 11.2369 +        load_reg( REG_EAX, Rm );
 11.2370 +        ADDL_rbpdisp_r32( REG_OFFSET(r[0]), REG_EAX );
 11.2371 +        LEAL_r32disp_r32( REG_EAX, 4, REG_EAX );
 11.2372 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2373 +        store_dr1( REG_EAX, FRn );
 11.2374      } else {
 11.2375 -        check_ralign32( R_EAX );
 11.2376 -        MEM_READ_LONG( R_EAX, R_EAX );
 11.2377 -        store_fr( R_EAX, FRn );
 11.2378 +        check_ralign32( REG_EAX );
 11.2379 +        MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2380 +        store_fr( REG_EAX, FRn );
 11.2381      }
 11.2382      sh4_x86.tstate = TSTATE_NONE;
 11.2383  :}
 11.2384 @@ -1926,8 +1932,8 @@
 11.2385      COUNT_INST(I_FLDI0);
 11.2386      check_fpuen();
 11.2387      if( sh4_x86.double_prec == 0 ) {
 11.2388 -        XOR_r32_r32( R_EAX, R_EAX );
 11.2389 -        store_fr( R_EAX, FRn );
 11.2390 +        XORL_r32_r32( REG_EAX, REG_EAX );
 11.2391 +        store_fr( REG_EAX, FRn );
 11.2392      }
 11.2393      sh4_x86.tstate = TSTATE_NONE;
 11.2394  :}
 11.2395 @@ -1935,15 +1941,15 @@
 11.2396      COUNT_INST(I_FLDI1);
 11.2397      check_fpuen();
 11.2398      if( sh4_x86.double_prec == 0 ) {
 11.2399 -        load_imm32(R_EAX, 0x3F800000);
 11.2400 -        store_fr( R_EAX, FRn );
 11.2401 +        load_imm32(REG_EAX, 0x3F800000);
 11.2402 +        store_fr( REG_EAX, FRn );
 11.2403      }
 11.2404  :}
 11.2405  
 11.2406  FLOAT FPUL, FRn {:  
 11.2407      COUNT_INST(I_FLOAT);
 11.2408      check_fpuen();
 11.2409 -    FILD_sh4r(R_FPUL);
 11.2410 +    FILD_rbpdisp(R_FPUL);
 11.2411      if( sh4_x86.double_prec ) {
 11.2412          pop_dr( FRn );
 11.2413      } else {
 11.2414 @@ -1958,26 +1964,26 @@
 11.2415      } else {
 11.2416          push_fr( FRm );
 11.2417      }
 11.2418 -    load_ptr( R_ECX, &max_int );
 11.2419 -    FILD_r32ind( R_ECX );
 11.2420 +    load_ptr( REG_ECX, &max_int );
 11.2421 +    FILD_r32disp( REG_ECX, 0 );
 11.2422      FCOMIP_st(1);
 11.2423 -    JNA_rel8( sat );
 11.2424 -    load_ptr( R_ECX, &min_int );  // 5
 11.2425 -    FILD_r32ind( R_ECX );           // 2
 11.2426 +    JNA_label( sat );
 11.2427 +    load_ptr( REG_ECX, &min_int );  // 5
 11.2428 +    FILD_r32disp( REG_ECX, 0 );           // 2
 11.2429      FCOMIP_st(1);                   // 2
 11.2430 -    JAE_rel8( sat2 );            // 2
 11.2431 -    load_ptr( R_EAX, &save_fcw );
 11.2432 -    FNSTCW_r32ind( R_EAX );
 11.2433 -    load_ptr( R_EDX, &trunc_fcw );
 11.2434 -    FLDCW_r32ind( R_EDX );
 11.2435 -    FISTP_sh4r(R_FPUL);             // 3
 11.2436 -    FLDCW_r32ind( R_EAX );
 11.2437 -    JMP_rel8(end);             // 2
 11.2438 +    JAE_label( sat2 );            // 2
 11.2439 +    load_ptr( REG_EAX, &save_fcw );
 11.2440 +    FNSTCW_r32disp( REG_EAX, 0 );
 11.2441 +    load_ptr( REG_EDX, &trunc_fcw );
 11.2442 +    FLDCW_r32disp( REG_EDX, 0 );
 11.2443 +    FISTP_rbpdisp(R_FPUL);             // 3
 11.2444 +    FLDCW_r32disp( REG_EAX, 0 );
 11.2445 +    JMP_label(end);             // 2
 11.2446  
 11.2447      JMP_TARGET(sat);
 11.2448      JMP_TARGET(sat2);
 11.2449 -    MOV_r32ind_r32( R_ECX, R_ECX ); // 2
 11.2450 -    store_spreg( R_ECX, R_FPUL );
 11.2451 +    MOVL_r32disp_r32( REG_ECX, 0, REG_ECX ); // 2
 11.2452 +    store_spreg( REG_ECX, R_FPUL );
 11.2453      FPOP_st();
 11.2454      JMP_TARGET(end);
 11.2455      sh4_x86.tstate = TSTATE_NONE;
 11.2456 @@ -1985,14 +1991,14 @@
 11.2457  FLDS FRm, FPUL {:  
 11.2458      COUNT_INST(I_FLDS);
 11.2459      check_fpuen();
 11.2460 -    load_fr( R_EAX, FRm );
 11.2461 -    store_spreg( R_EAX, R_FPUL );
 11.2462 +    load_fr( REG_EAX, FRm );
 11.2463 +    store_spreg( REG_EAX, R_FPUL );
 11.2464  :}
 11.2465  FSTS FPUL, FRn {:  
 11.2466      COUNT_INST(I_FSTS);
 11.2467      check_fpuen();
 11.2468 -    load_spreg( R_EAX, R_FPUL );
 11.2469 -    store_fr( R_EAX, FRn );
 11.2470 +    load_spreg( REG_EAX, R_FPUL );
 11.2471 +    store_fr( REG_EAX, FRn );
 11.2472  :}
 11.2473  FCNVDS FRm, FPUL {:  
 11.2474      COUNT_INST(I_FCNVDS);
 11.2475 @@ -2178,9 +2184,9 @@
 11.2476      COUNT_INST(I_FSCA);
 11.2477      check_fpuen();
 11.2478      if( sh4_x86.double_prec == 0 ) {
 11.2479 -        LEA_sh4r_rptr( REG_OFFSET(fr[0][FRn&0x0E]), R_EDX );
 11.2480 -        load_spreg( R_EAX, R_FPUL );
 11.2481 -        call_func2( sh4_fsca, R_EAX, R_EDX );
 11.2482 +        LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FRn&0x0E]), REG_EDX );
 11.2483 +        load_spreg( REG_EAX, R_FPUL );
 11.2484 +        call_func2( sh4_fsca, REG_EAX, REG_EDX );
 11.2485      }
 11.2486      sh4_x86.tstate = TSTATE_NONE;
 11.2487  :}
 11.2488 @@ -2189,11 +2195,11 @@
 11.2489      check_fpuen();
 11.2490      if( sh4_x86.double_prec == 0 ) {
 11.2491          if( sh4_x86.sse3_enabled ) {
 11.2492 -            MOVAPS_sh4r_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
 11.2493 -            MULPS_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
 11.2494 +            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVm<<2]), 4 );
 11.2495 +            MULPS_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 );
 11.2496              HADDPS_xmm_xmm( 4, 4 ); 
 11.2497              HADDPS_xmm_xmm( 4, 4 );
 11.2498 -            MOVSS_xmm_sh4r( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
 11.2499 +            MOVSS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][(FVn<<2)+2]) );
 11.2500          } else {
 11.2501              push_fr( FVm<<2 );
 11.2502              push_fr( FVn<<2 );
 11.2503 @@ -2219,15 +2225,15 @@
 11.2504      check_fpuen();
 11.2505      if( sh4_x86.double_prec == 0 ) {
 11.2506          if( sh4_x86.sse3_enabled ) {
 11.2507 -            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
 11.2508 -            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
 11.2509 -            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
 11.2510 -            MOVAPS_sh4r_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
 11.2511 +            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][0]), 1 ); // M1  M0  M3  M2
 11.2512 +            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][4]), 0 ); // M5  M4  M7  M6
 11.2513 +            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][8]), 3 ); // M9  M8  M11 M10
 11.2514 +            MOVAPS_rbpdisp_xmm( REG_OFFSET(fr[1][12]), 2 );// M13 M12 M15 M14
 11.2515  
 11.2516 -            MOVSLDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
 11.2517 -            MOVSHDUP_sh4r_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
 11.2518 -            MOVAPS_xmm_xmm( 4, 6 );
 11.2519 -            MOVAPS_xmm_xmm( 5, 7 );
 11.2520 +            MOVSLDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 4 ); // V1 V1 V3 V3
 11.2521 +            MOVSHDUP_rbpdisp_xmm( REG_OFFSET(fr[0][FVn<<2]), 5 ); // V0 V0 V2 V2
 11.2522 +            MOV_xmm_xmm( 4, 6 );
 11.2523 +            MOV_xmm_xmm( 5, 7 );
 11.2524              MOVLHPS_xmm_xmm( 4, 4 );  // V1 V1 V1 V1
 11.2525              MOVHLPS_xmm_xmm( 6, 6 );  // V3 V3 V3 V3
 11.2526              MOVLHPS_xmm_xmm( 5, 5 );  // V0 V0 V0 V0
 11.2527 @@ -2239,10 +2245,10 @@
 11.2528              ADDPS_xmm_xmm( 5, 4 );
 11.2529              ADDPS_xmm_xmm( 7, 6 );
 11.2530              ADDPS_xmm_xmm( 6, 4 );
 11.2531 -            MOVAPS_xmm_sh4r( 4, REG_OFFSET(fr[0][FVn<<2]) );
 11.2532 +            MOVAPS_xmm_rbpdisp( 4, REG_OFFSET(fr[0][FVn<<2]) );
 11.2533          } else {
 11.2534 -            LEA_sh4r_rptr( REG_OFFSET(fr[0][FVn<<2]), R_EAX );
 11.2535 -            call_func1( sh4_ftrv, R_EAX );
 11.2536 +            LEAP_rbpdisp_rptr( REG_OFFSET(fr[0][FVn<<2]), REG_EAX );
 11.2537 +            call_func1( sh4_ftrv, REG_EAX );
 11.2538          }
 11.2539      }
 11.2540      sh4_x86.tstate = TSTATE_NONE;
 11.2541 @@ -2251,15 +2257,15 @@
 11.2542  FRCHG {:  
 11.2543      COUNT_INST(I_FRCHG);
 11.2544      check_fpuen();
 11.2545 -    XOR_imm32_sh4r( FPSCR_FR, R_FPSCR );
 11.2546 +    XORL_imms_rbpdisp( FPSCR_FR, R_FPSCR );
 11.2547      call_func0( sh4_switch_fr_banks );
 11.2548      sh4_x86.tstate = TSTATE_NONE;
 11.2549  :}
 11.2550  FSCHG {:  
 11.2551      COUNT_INST(I_FSCHG);
 11.2552      check_fpuen();
 11.2553 -    XOR_imm32_sh4r( FPSCR_SZ, R_FPSCR);
 11.2554 -    XOR_imm32_sh4r( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
 11.2555 +    XORL_imms_rbpdisp( FPSCR_SZ, R_FPSCR);
 11.2556 +    XORL_imms_rbpdisp( FPSCR_SZ, REG_OFFSET(xlat_sh4_mode) );
 11.2557      sh4_x86.tstate = TSTATE_NONE;
 11.2558      sh4_x86.double_size = !sh4_x86.double_size;
 11.2559  :}
 11.2560 @@ -2271,8 +2277,8 @@
 11.2561  	SLOTILLEGAL();
 11.2562      } else {
 11.2563  	check_priv();
 11.2564 -	load_reg( R_EAX, Rm );
 11.2565 -	call_func1( sh4_write_sr, R_EAX );
 11.2566 +	load_reg( REG_EAX, Rm );
 11.2567 +	call_func1( sh4_write_sr, REG_EAX );
 11.2568  	sh4_x86.fpuen_checked = FALSE;
 11.2569  	sh4_x86.tstate = TSTATE_NONE;
 11.2570  	return 2;
 11.2571 @@ -2280,58 +2286,58 @@
 11.2572  :}
 11.2573  LDC Rm, GBR {: 
 11.2574      COUNT_INST(I_LDC);
 11.2575 -    load_reg( R_EAX, Rm );
 11.2576 -    store_spreg( R_EAX, R_GBR );
 11.2577 +    load_reg( REG_EAX, Rm );
 11.2578 +    store_spreg( REG_EAX, R_GBR );
 11.2579  :}
 11.2580  LDC Rm, VBR {:  
 11.2581      COUNT_INST(I_LDC);
 11.2582      check_priv();
 11.2583 -    load_reg( R_EAX, Rm );
 11.2584 -    store_spreg( R_EAX, R_VBR );
 11.2585 +    load_reg( REG_EAX, Rm );
 11.2586 +    store_spreg( REG_EAX, R_VBR );
 11.2587      sh4_x86.tstate = TSTATE_NONE;
 11.2588  :}
 11.2589  LDC Rm, SSR {:  
 11.2590      COUNT_INST(I_LDC);
 11.2591      check_priv();
 11.2592 -    load_reg( R_EAX, Rm );
 11.2593 -    store_spreg( R_EAX, R_SSR );
 11.2594 +    load_reg( REG_EAX, Rm );
 11.2595 +    store_spreg( REG_EAX, R_SSR );
 11.2596      sh4_x86.tstate = TSTATE_NONE;
 11.2597  :}
 11.2598  LDC Rm, SGR {:  
 11.2599      COUNT_INST(I_LDC);
 11.2600      check_priv();
 11.2601 -    load_reg( R_EAX, Rm );
 11.2602 -    store_spreg( R_EAX, R_SGR );
 11.2603 +    load_reg( REG_EAX, Rm );
 11.2604 +    store_spreg( REG_EAX, R_SGR );
 11.2605      sh4_x86.tstate = TSTATE_NONE;
 11.2606  :}
 11.2607  LDC Rm, SPC {:  
 11.2608      COUNT_INST(I_LDC);
 11.2609      check_priv();
 11.2610 -    load_reg( R_EAX, Rm );
 11.2611 -    store_spreg( R_EAX, R_SPC );
 11.2612 +    load_reg( REG_EAX, Rm );
 11.2613 +    store_spreg( REG_EAX, R_SPC );
 11.2614      sh4_x86.tstate = TSTATE_NONE;
 11.2615  :}
 11.2616  LDC Rm, DBR {:  
 11.2617      COUNT_INST(I_LDC);
 11.2618      check_priv();
 11.2619 -    load_reg( R_EAX, Rm );
 11.2620 -    store_spreg( R_EAX, R_DBR );
 11.2621 +    load_reg( REG_EAX, Rm );
 11.2622 +    store_spreg( REG_EAX, R_DBR );
 11.2623      sh4_x86.tstate = TSTATE_NONE;
 11.2624  :}
 11.2625  LDC Rm, Rn_BANK {:  
 11.2626      COUNT_INST(I_LDC);
 11.2627      check_priv();
 11.2628 -    load_reg( R_EAX, Rm );
 11.2629 -    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
 11.2630 +    load_reg( REG_EAX, Rm );
 11.2631 +    store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
 11.2632      sh4_x86.tstate = TSTATE_NONE;
 11.2633  :}
 11.2634  LDC.L @Rm+, GBR {:  
 11.2635      COUNT_INST(I_LDCM);
 11.2636 -    load_reg( R_EAX, Rm );
 11.2637 -    check_ralign32( R_EAX );
 11.2638 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2639 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2640 -    store_spreg( R_EAX, R_GBR );
 11.2641 +    load_reg( REG_EAX, Rm );
 11.2642 +    check_ralign32( REG_EAX );
 11.2643 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2644 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2645 +    store_spreg( REG_EAX, R_GBR );
 11.2646      sh4_x86.tstate = TSTATE_NONE;
 11.2647  :}
 11.2648  LDC.L @Rm+, SR {:
 11.2649 @@ -2340,11 +2346,11 @@
 11.2650  	SLOTILLEGAL();
 11.2651      } else {
 11.2652  	check_priv();
 11.2653 -	load_reg( R_EAX, Rm );
 11.2654 -	check_ralign32( R_EAX );
 11.2655 -	MEM_READ_LONG( R_EAX, R_EAX );
 11.2656 -	ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2657 -	call_func1( sh4_write_sr, R_EAX );
 11.2658 +	load_reg( REG_EAX, Rm );
 11.2659 +	check_ralign32( REG_EAX );
 11.2660 +	MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2661 +	ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2662 +	call_func1( sh4_write_sr, REG_EAX );
 11.2663  	sh4_x86.fpuen_checked = FALSE;
 11.2664  	sh4_x86.tstate = TSTATE_NONE;
 11.2665  	return 2;
 11.2666 @@ -2353,138 +2359,138 @@
 11.2667  LDC.L @Rm+, VBR {:  
 11.2668      COUNT_INST(I_LDCM);
 11.2669      check_priv();
 11.2670 -    load_reg( R_EAX, Rm );
 11.2671 -    check_ralign32( R_EAX );
 11.2672 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2673 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2674 -    store_spreg( R_EAX, R_VBR );
 11.2675 +    load_reg( REG_EAX, Rm );
 11.2676 +    check_ralign32( REG_EAX );
 11.2677 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2678 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2679 +    store_spreg( REG_EAX, R_VBR );
 11.2680      sh4_x86.tstate = TSTATE_NONE;
 11.2681  :}
 11.2682  LDC.L @Rm+, SSR {:
 11.2683      COUNT_INST(I_LDCM);
 11.2684      check_priv();
 11.2685 -    load_reg( R_EAX, Rm );
 11.2686 -    check_ralign32( R_EAX );
 11.2687 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2688 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2689 -    store_spreg( R_EAX, R_SSR );
 11.2690 +    load_reg( REG_EAX, Rm );
 11.2691 +    check_ralign32( REG_EAX );
 11.2692 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2693 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2694 +    store_spreg( REG_EAX, R_SSR );
 11.2695      sh4_x86.tstate = TSTATE_NONE;
 11.2696  :}
 11.2697  LDC.L @Rm+, SGR {:  
 11.2698      COUNT_INST(I_LDCM);
 11.2699      check_priv();
 11.2700 -    load_reg( R_EAX, Rm );
 11.2701 -    check_ralign32( R_EAX );
 11.2702 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2703 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2704 -    store_spreg( R_EAX, R_SGR );
 11.2705 +    load_reg( REG_EAX, Rm );
 11.2706 +    check_ralign32( REG_EAX );
 11.2707 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2708 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2709 +    store_spreg( REG_EAX, R_SGR );
 11.2710      sh4_x86.tstate = TSTATE_NONE;
 11.2711  :}
 11.2712  LDC.L @Rm+, SPC {:  
 11.2713      COUNT_INST(I_LDCM);
 11.2714      check_priv();
 11.2715 -    load_reg( R_EAX, Rm );
 11.2716 -    check_ralign32( R_EAX );
 11.2717 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2718 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2719 -    store_spreg( R_EAX, R_SPC );
 11.2720 +    load_reg( REG_EAX, Rm );
 11.2721 +    check_ralign32( REG_EAX );
 11.2722 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2723 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2724 +    store_spreg( REG_EAX, R_SPC );
 11.2725      sh4_x86.tstate = TSTATE_NONE;
 11.2726  :}
 11.2727  LDC.L @Rm+, DBR {:  
 11.2728      COUNT_INST(I_LDCM);
 11.2729      check_priv();
 11.2730 -    load_reg( R_EAX, Rm );
 11.2731 -    check_ralign32( R_EAX );
 11.2732 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2733 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2734 -    store_spreg( R_EAX, R_DBR );
 11.2735 +    load_reg( REG_EAX, Rm );
 11.2736 +    check_ralign32( REG_EAX );
 11.2737 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2738 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2739 +    store_spreg( REG_EAX, R_DBR );
 11.2740      sh4_x86.tstate = TSTATE_NONE;
 11.2741  :}
 11.2742  LDC.L @Rm+, Rn_BANK {:  
 11.2743      COUNT_INST(I_LDCM);
 11.2744      check_priv();
 11.2745 -    load_reg( R_EAX, Rm );
 11.2746 -    check_ralign32( R_EAX );
 11.2747 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2748 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2749 -    store_spreg( R_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
 11.2750 +    load_reg( REG_EAX, Rm );
 11.2751 +    check_ralign32( REG_EAX );
 11.2752 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2753 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2754 +    store_spreg( REG_EAX, REG_OFFSET(r_bank[Rn_BANK]) );
 11.2755      sh4_x86.tstate = TSTATE_NONE;
 11.2756  :}
 11.2757  LDS Rm, FPSCR {:
 11.2758      COUNT_INST(I_LDSFPSCR);
 11.2759      check_fpuen();
 11.2760 -    load_reg( R_EAX, Rm );
 11.2761 -    call_func1( sh4_write_fpscr, R_EAX );
 11.2762 +    load_reg( REG_EAX, Rm );
 11.2763 +    call_func1( sh4_write_fpscr, REG_EAX );
 11.2764      sh4_x86.tstate = TSTATE_NONE;
 11.2765      return 2;
 11.2766  :}
 11.2767  LDS.L @Rm+, FPSCR {:  
 11.2768      COUNT_INST(I_LDSFPSCRM);
 11.2769      check_fpuen();
 11.2770 -    load_reg( R_EAX, Rm );
 11.2771 -    check_ralign32( R_EAX );
 11.2772 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2773 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2774 -    call_func1( sh4_write_fpscr, R_EAX );
 11.2775 +    load_reg( REG_EAX, Rm );
 11.2776 +    check_ralign32( REG_EAX );
 11.2777 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2778 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2779 +    call_func1( sh4_write_fpscr, REG_EAX );
 11.2780      sh4_x86.tstate = TSTATE_NONE;
 11.2781      return 2;
 11.2782  :}
 11.2783  LDS Rm, FPUL {:  
 11.2784      COUNT_INST(I_LDS);
 11.2785      check_fpuen();
 11.2786 -    load_reg( R_EAX, Rm );
 11.2787 -    store_spreg( R_EAX, R_FPUL );
 11.2788 +    load_reg( REG_EAX, Rm );
 11.2789 +    store_spreg( REG_EAX, R_FPUL );
 11.2790  :}
 11.2791  LDS.L @Rm+, FPUL {:  
 11.2792      COUNT_INST(I_LDSM);
 11.2793      check_fpuen();
 11.2794 -    load_reg( R_EAX, Rm );
 11.2795 -    check_ralign32( R_EAX );
 11.2796 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2797 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2798 -    store_spreg( R_EAX, R_FPUL );
 11.2799 +    load_reg( REG_EAX, Rm );
 11.2800 +    check_ralign32( REG_EAX );
 11.2801 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2802 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2803 +    store_spreg( REG_EAX, R_FPUL );
 11.2804      sh4_x86.tstate = TSTATE_NONE;
 11.2805  :}
 11.2806  LDS Rm, MACH {: 
 11.2807      COUNT_INST(I_LDS);
 11.2808 -    load_reg( R_EAX, Rm );
 11.2809 -    store_spreg( R_EAX, R_MACH );
 11.2810 +    load_reg( REG_EAX, Rm );
 11.2811 +    store_spreg( REG_EAX, R_MACH );
 11.2812  :}
 11.2813  LDS.L @Rm+, MACH {:  
 11.2814      COUNT_INST(I_LDSM);
 11.2815 -    load_reg( R_EAX, Rm );
 11.2816 -    check_ralign32( R_EAX );
 11.2817 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2818 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2819 -    store_spreg( R_EAX, R_MACH );
 11.2820 +    load_reg( REG_EAX, Rm );
 11.2821 +    check_ralign32( REG_EAX );
 11.2822 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2823 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2824 +    store_spreg( REG_EAX, R_MACH );
 11.2825      sh4_x86.tstate = TSTATE_NONE;
 11.2826  :}
 11.2827  LDS Rm, MACL {:  
 11.2828      COUNT_INST(I_LDS);
 11.2829 -    load_reg( R_EAX, Rm );
 11.2830 -    store_spreg( R_EAX, R_MACL );
 11.2831 +    load_reg( REG_EAX, Rm );
 11.2832 +    store_spreg( REG_EAX, R_MACL );
 11.2833  :}
 11.2834  LDS.L @Rm+, MACL {:  
 11.2835      COUNT_INST(I_LDSM);
 11.2836 -    load_reg( R_EAX, Rm );
 11.2837 -    check_ralign32( R_EAX );
 11.2838 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2839 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2840 -    store_spreg( R_EAX, R_MACL );
 11.2841 +    load_reg( REG_EAX, Rm );
 11.2842 +    check_ralign32( REG_EAX );
 11.2843 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2844 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2845 +    store_spreg( REG_EAX, R_MACL );
 11.2846      sh4_x86.tstate = TSTATE_NONE;
 11.2847  :}
 11.2848  LDS Rm, PR {:  
 11.2849      COUNT_INST(I_LDS);
 11.2850 -    load_reg( R_EAX, Rm );
 11.2851 -    store_spreg( R_EAX, R_PR );
 11.2852 +    load_reg( REG_EAX, Rm );
 11.2853 +    store_spreg( REG_EAX, R_PR );
 11.2854  :}
 11.2855  LDS.L @Rm+, PR {:  
 11.2856      COUNT_INST(I_LDSM);
 11.2857 -    load_reg( R_EAX, Rm );
 11.2858 -    check_ralign32( R_EAX );
 11.2859 -    MEM_READ_LONG( R_EAX, R_EAX );
 11.2860 -    ADD_imm8s_sh4r( 4, REG_OFFSET(r[Rm]) );
 11.2861 -    store_spreg( R_EAX, R_PR );
 11.2862 +    load_reg( REG_EAX, Rm );
 11.2863 +    check_ralign32( REG_EAX );
 11.2864 +    MEM_READ_LONG( REG_EAX, REG_EAX );
 11.2865 +    ADDL_imms_rbpdisp( 4, REG_OFFSET(r[Rm]) );
 11.2866 +    store_spreg( REG_EAX, R_PR );
 11.2867      sh4_x86.tstate = TSTATE_NONE;
 11.2868  :}
 11.2869  LDTLB {:  
 11.2870 @@ -2503,8 +2509,8 @@
 11.2871  :}
 11.2872  PREF @Rn {:
 11.2873      COUNT_INST(I_PREF);
 11.2874 -    load_reg( R_EAX, Rn );
 11.2875 -    MEM_PREFETCH( R_EAX );
 11.2876 +    load_reg( REG_EAX, Rn );
 11.2877 +    MEM_PREFETCH( REG_EAX );
 11.2878      sh4_x86.tstate = TSTATE_NONE;
 11.2879  :}
 11.2880  SLEEP {: 
 11.2881 @@ -2519,221 +2525,221 @@
 11.2882      COUNT_INST(I_STCSR);
 11.2883      check_priv();
 11.2884      call_func0(sh4_read_sr);
 11.2885 -    store_reg( R_EAX, Rn );
 11.2886 +    store_reg( REG_EAX, Rn );
 11.2887      sh4_x86.tstate = TSTATE_NONE;
 11.2888  :}
 11.2889  STC GBR, Rn {:  
 11.2890      COUNT_INST(I_STC);
 11.2891 -    load_spreg( R_EAX, R_GBR );
 11.2892 -    store_reg( R_EAX, Rn );
 11.2893 +    load_spreg( REG_EAX, R_GBR );
 11.2894 +    store_reg( REG_EAX, Rn );
 11.2895  :}
 11.2896  STC VBR, Rn {:  
 11.2897      COUNT_INST(I_STC);
 11.2898      check_priv();
 11.2899 -    load_spreg( R_EAX, R_VBR );
 11.2900 -    store_reg( R_EAX, Rn );
 11.2901 +    load_spreg( REG_EAX, R_VBR );
 11.2902 +    store_reg( REG_EAX, Rn );
 11.2903      sh4_x86.tstate = TSTATE_NONE;
 11.2904  :}
 11.2905  STC SSR, Rn {:  
 11.2906      COUNT_INST(I_STC);
 11.2907      check_priv();
 11.2908 -    load_spreg( R_EAX, R_SSR );
 11.2909 -    store_reg( R_EAX, Rn );
 11.2910 +    load_spreg( REG_EAX, R_SSR );
 11.2911 +    store_reg( REG_EAX, Rn );
 11.2912      sh4_x86.tstate = TSTATE_NONE;
 11.2913  :}
 11.2914  STC SPC, Rn {:  
 11.2915      COUNT_INST(I_STC);
 11.2916      check_priv();
 11.2917 -    load_spreg( R_EAX, R_SPC );
 11.2918 -    store_reg( R_EAX, Rn );
 11.2919 +    load_spreg( REG_EAX, R_SPC );
 11.2920 +    store_reg( REG_EAX, Rn );
 11.2921      sh4_x86.tstate = TSTATE_NONE;
 11.2922  :}
 11.2923  STC SGR, Rn {:  
 11.2924      COUNT_INST(I_STC);
 11.2925      check_priv();
 11.2926 -    load_spreg( R_EAX, R_SGR );
 11.2927 -    store_reg( R_EAX, Rn );
 11.2928 +    load_spreg( REG_EAX, R_SGR );
 11.2929 +    store_reg( REG_EAX, Rn );
 11.2930      sh4_x86.tstate = TSTATE_NONE;
 11.2931  :}
 11.2932  STC DBR, Rn {:  
 11.2933      COUNT_INST(I_STC);
 11.2934      check_priv();
 11.2935 -    load_spreg( R_EAX, R_DBR );
 11.2936 -    store_reg( R_EAX, Rn );
 11.2937 +    load_spreg( REG_EAX, R_DBR );
 11.2938 +    store_reg( REG_EAX, Rn );
 11.2939      sh4_x86.tstate = TSTATE_NONE;
 11.2940  :}
 11.2941  STC Rm_BANK, Rn {:
 11.2942      COUNT_INST(I_STC);
 11.2943      check_priv();
 11.2944 -    load_spreg( R_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
 11.2945 -    store_reg( R_EAX, Rn );
 11.2946 +    load_spreg( REG_EAX, REG_OFFSET(r_bank[Rm_BANK]) );
 11.2947 +    store_reg( REG_EAX, Rn );
 11.2948      sh4_x86.tstate = TSTATE_NONE;
 11.2949  :}
 11.2950  STC.L SR, @-Rn {:
 11.2951      COUNT_INST(I_STCSRM);
 11.2952      check_priv();
 11.2953      call_func0( sh4_read_sr );
 11.2954 -    MOV_r32_r32( R_EAX, R_EDX );
 11.2955 -    load_reg( R_EAX, Rn );
 11.2956 -    check_walign32( R_EAX );
 11.2957 -    LEA_r32disp8_r32( R_EAX, -4, R_EAX );
 11.2958 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2959 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.2960 +    MOVL_r32_r32( REG_EAX, REG_EDX );
 11.2961 +    load_reg( REG_EAX, Rn );
 11.2962 +    check_walign32( REG_EAX );
 11.2963 +    LEAL_r32disp_r32( REG_EAX, -4, REG_EAX );
 11.2964 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2965 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.2966      sh4_x86.tstate = TSTATE_NONE;
 11.2967  :}
 11.2968  STC.L VBR, @-Rn {:  
 11.2969      COUNT_INST(I_STCM);
 11.2970      check_priv();
 11.2971 -    load_reg( R_EAX, Rn );
 11.2972 -    check_walign32( R_EAX );
 11.2973 -    ADD_imm8s_r32( -4, R_EAX );
 11.2974 -    load_spreg( R_EDX, R_VBR );
 11.2975 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2976 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.2977 +    load_reg( REG_EAX, Rn );
 11.2978 +    check_walign32( REG_EAX );
 11.2979 +    ADDL_imms_r32( -4, REG_EAX );
 11.2980 +    load_spreg( REG_EDX, R_VBR );
 11.2981 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2982 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.2983      sh4_x86.tstate = TSTATE_NONE;
 11.2984  :}
 11.2985  STC.L SSR, @-Rn {:  
 11.2986      COUNT_INST(I_STCM);
 11.2987      check_priv();
 11.2988 -    load_reg( R_EAX, Rn );
 11.2989 -    check_walign32( R_EAX );
 11.2990 -    ADD_imm8s_r32( -4, R_EAX );
 11.2991 -    load_spreg( R_EDX, R_SSR );
 11.2992 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.2993 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.2994 +    load_reg( REG_EAX, Rn );
 11.2995 +    check_walign32( REG_EAX );
 11.2996 +    ADDL_imms_r32( -4, REG_EAX );
 11.2997 +    load_spreg( REG_EDX, R_SSR );
 11.2998 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.2999 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3000      sh4_x86.tstate = TSTATE_NONE;
 11.3001  :}
 11.3002  STC.L SPC, @-Rn {:
 11.3003      COUNT_INST(I_STCM);
 11.3004      check_priv();
 11.3005 -    load_reg( R_EAX, Rn );
 11.3006 -    check_walign32( R_EAX );
 11.3007 -    ADD_imm8s_r32( -4, R_EAX );
 11.3008 -    load_spreg( R_EDX, R_SPC );
 11.3009 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3010 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3011 +    load_reg( REG_EAX, Rn );
 11.3012 +    check_walign32( REG_EAX );
 11.3013 +    ADDL_imms_r32( -4, REG_EAX );
 11.3014 +    load_spreg( REG_EDX, R_SPC );
 11.3015 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3016 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3017      sh4_x86.tstate = TSTATE_NONE;
 11.3018  :}
 11.3019  STC.L SGR, @-Rn {:  
 11.3020      COUNT_INST(I_STCM);
 11.3021      check_priv();
 11.3022 -    load_reg( R_EAX, Rn );
 11.3023 -    check_walign32( R_EAX );
 11.3024 -    ADD_imm8s_r32( -4, R_EAX );
 11.3025 -    load_spreg( R_EDX, R_SGR );
 11.3026 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3027 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3028 +    load_reg( REG_EAX, Rn );
 11.3029 +    check_walign32( REG_EAX );
 11.3030 +    ADDL_imms_r32( -4, REG_EAX );
 11.3031 +    load_spreg( REG_EDX, R_SGR );
 11.3032 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3033 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3034      sh4_x86.tstate = TSTATE_NONE;
 11.3035  :}
 11.3036  STC.L DBR, @-Rn {:  
 11.3037      COUNT_INST(I_STCM);
 11.3038      check_priv();
 11.3039 -    load_reg( R_EAX, Rn );
 11.3040 -    check_walign32( R_EAX );
 11.3041 -    ADD_imm8s_r32( -4, R_EAX );
 11.3042 -    load_spreg( R_EDX, R_DBR );
 11.3043 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3044 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3045 +    load_reg( REG_EAX, Rn );
 11.3046 +    check_walign32( REG_EAX );
 11.3047 +    ADDL_imms_r32( -4, REG_EAX );
 11.3048 +    load_spreg( REG_EDX, R_DBR );
 11.3049 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3050 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3051      sh4_x86.tstate = TSTATE_NONE;
 11.3052  :}
 11.3053  STC.L Rm_BANK, @-Rn {:  
 11.3054      COUNT_INST(I_STCM);
 11.3055      check_priv();
 11.3056 -    load_reg( R_EAX, Rn );
 11.3057 -    check_walign32( R_EAX );
 11.3058 -    ADD_imm8s_r32( -4, R_EAX );
 11.3059 -    load_spreg( R_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
 11.3060 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3061 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3062 +    load_reg( REG_EAX, Rn );
 11.3063 +    check_walign32( REG_EAX );
 11.3064 +    ADDL_imms_r32( -4, REG_EAX );
 11.3065 +    load_spreg( REG_EDX, REG_OFFSET(r_bank[Rm_BANK]) );
 11.3066 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3067 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3068      sh4_x86.tstate = TSTATE_NONE;
 11.3069  :}
 11.3070  STC.L GBR, @-Rn {:  
 11.3071      COUNT_INST(I_STCM);
 11.3072 -    load_reg( R_EAX, Rn );
 11.3073 -    check_walign32( R_EAX );
 11.3074 -    ADD_imm8s_r32( -4, R_EAX );
 11.3075 -    load_spreg( R_EDX, R_GBR );
 11.3076 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3077 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3078 +    load_reg( REG_EAX, Rn );
 11.3079 +    check_walign32( REG_EAX );
 11.3080 +    ADDL_imms_r32( -4, REG_EAX );
 11.3081 +    load_spreg( REG_EDX, R_GBR );
 11.3082 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3083 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3084      sh4_x86.tstate = TSTATE_NONE;
 11.3085  :}
 11.3086  STS FPSCR, Rn {:  
 11.3087      COUNT_INST(I_STSFPSCR);
 11.3088      check_fpuen();
 11.3089 -    load_spreg( R_EAX, R_FPSCR );
 11.3090 -    store_reg( R_EAX, Rn );
 11.3091 +    load_spreg( REG_EAX, R_FPSCR );
 11.3092 +    store_reg( REG_EAX, Rn );
 11.3093  :}
 11.3094  STS.L FPSCR, @-Rn {:  
 11.3095      COUNT_INST(I_STSFPSCRM);
 11.3096      check_fpuen();
 11.3097 -    load_reg( R_EAX, Rn );
 11.3098 -    check_walign32( R_EAX );
 11.3099 -    ADD_imm8s_r32( -4, R_EAX );
 11.3100 -    load_spreg( R_EDX, R_FPSCR );
 11.3101 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3102 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3103 +    load_reg( REG_EAX, Rn );
 11.3104 +    check_walign32( REG_EAX );
 11.3105 +    ADDL_imms_r32( -4, REG_EAX );
 11.3106 +    load_spreg( REG_EDX, R_FPSCR );
 11.3107 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3108 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3109      sh4_x86.tstate = TSTATE_NONE;
 11.3110  :}
 11.3111  STS FPUL, Rn {:  
 11.3112      COUNT_INST(I_STS);
 11.3113      check_fpuen();
 11.3114 -    load_spreg( R_EAX, R_FPUL );
 11.3115 -    store_reg( R_EAX, Rn );
 11.3116 +    load_spreg( REG_EAX, R_FPUL );
 11.3117 +    store_reg( REG_EAX, Rn );
 11.3118  :}
 11.3119  STS.L FPUL, @-Rn {:  
 11.3120      COUNT_INST(I_STSM);
 11.3121      check_fpuen();
 11.3122 -    load_reg( R_EAX, Rn );
 11.3123 -    check_walign32( R_EAX );
 11.3124 -    ADD_imm8s_r32( -4, R_EAX );
 11.3125 -    load_spreg( R_EDX, R_FPUL );
 11.3126 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3127 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3128 +    load_reg( REG_EAX, Rn );
 11.3129 +    check_walign32( REG_EAX );
 11.3130 +    ADDL_imms_r32( -4, REG_EAX );
 11.3131 +    load_spreg( REG_EDX, R_FPUL );
 11.3132 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3133 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3134      sh4_x86.tstate = TSTATE_NONE;
 11.3135  :}
 11.3136  STS MACH, Rn {:  
 11.3137      COUNT_INST(I_STS);
 11.3138 -    load_spreg( R_EAX, R_MACH );
 11.3139 -    store_reg( R_EAX, Rn );
 11.3140 +    load_spreg( REG_EAX, R_MACH );
 11.3141 +    store_reg( REG_EAX, Rn );
 11.3142  :}
 11.3143  STS.L MACH, @-Rn {:  
 11.3144      COUNT_INST(I_STSM);
 11.3145 -    load_reg( R_EAX, Rn );
 11.3146 -    check_walign32( R_EAX );
 11.3147 -    ADD_imm8s_r32( -4, R_EAX );
 11.3148 -    load_spreg( R_EDX, R_MACH );
 11.3149 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3150 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3151 +    load_reg( REG_EAX, Rn );
 11.3152 +    check_walign32( REG_EAX );
 11.3153 +    ADDL_imms_r32( -4, REG_EAX );
 11.3154 +    load_spreg( REG_EDX, R_MACH );
 11.3155 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3156 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3157      sh4_x86.tstate = TSTATE_NONE;
 11.3158  :}
 11.3159  STS MACL, Rn {:  
 11.3160      COUNT_INST(I_STS);
 11.3161 -    load_spreg( R_EAX, R_MACL );
 11.3162 -    store_reg( R_EAX, Rn );
 11.3163 +    load_spreg( REG_EAX, R_MACL );
 11.3164 +    store_reg( REG_EAX, Rn );
 11.3165  :}
 11.3166  STS.L MACL, @-Rn {:  
 11.3167      COUNT_INST(I_STSM);
 11.3168 -    load_reg( R_EAX, Rn );
 11.3169 -    check_walign32( R_EAX );
 11.3170 -    ADD_imm8s_r32( -4, R_EAX );
 11.3171 -    load_spreg( R_EDX, R_MACL );
 11.3172 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3173 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3174 +    load_reg( REG_EAX, Rn );
 11.3175 +    check_walign32( REG_EAX );
 11.3176 +    ADDL_imms_r32( -4, REG_EAX );
 11.3177 +    load_spreg( REG_EDX, R_MACL );
 11.3178 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3179 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3180      sh4_x86.tstate = TSTATE_NONE;
 11.3181  :}
 11.3182  STS PR, Rn {:  
 11.3183      COUNT_INST(I_STS);
 11.3184 -    load_spreg( R_EAX, R_PR );
 11.3185 -    store_reg( R_EAX, Rn );
 11.3186 +    load_spreg( REG_EAX, R_PR );
 11.3187 +    store_reg( REG_EAX, Rn );
 11.3188  :}
 11.3189  STS.L PR, @-Rn {:  
 11.3190      COUNT_INST(I_STSM);
 11.3191 -    load_reg( R_EAX, Rn );
 11.3192 -    check_walign32( R_EAX );
 11.3193 -    ADD_imm8s_r32( -4, R_EAX );
 11.3194 -    load_spreg( R_EDX, R_PR );
 11.3195 -    MEM_WRITE_LONG( R_EAX, R_EDX );
 11.3196 -    ADD_imm8s_sh4r( -4, REG_OFFSET(r[Rn]) );
 11.3197 +    load_reg( REG_EAX, Rn );
 11.3198 +    check_walign32( REG_EAX );
 11.3199 +    ADDL_imms_r32( -4, REG_EAX );
 11.3200 +    load_spreg( REG_EDX, R_PR );
 11.3201 +    MEM_WRITE_LONG( REG_EAX, REG_EDX );
 11.3202 +    ADDL_imms_rbpdisp( -4, REG_OFFSET(r[Rn]) );
 11.3203      sh4_x86.tstate = TSTATE_NONE;
 11.3204  :}
 11.3205