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lxdream.org :: lxdream :: r397:640324505325
lxdream 0.9.1
released Jun 29
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changeset397:640324505325
parent396:0738dbc01d95
child398:16b0856ea511
authornkeynes
dateWed Sep 19 11:30:30 2007 +0000 (13 years ago)
Fix SHLL/SHLR/SHAL/SHAR flag setting
src/sh4/sh4x86.c
src/sh4/sh4x86.in
1.1 --- a/src/sh4/sh4x86.c Wed Sep 19 11:22:43 2007 +0000
1.2 +++ b/src/sh4/sh4x86.c Wed Sep 19 11:30:30 2007 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: sh4x86.c,v 1.12 2007-09-19 10:04:16 nkeynes Exp $
1.6 + * $Id: sh4x86.c,v 1.13 2007-09-19 11:30:30 nkeynes Exp $
1.7 *
1.8 * SH4 => x86 translation. This version does no real optimization, it just
1.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
1.10 @@ -1266,6 +1266,7 @@
1.11 uint32_t Rn = ((ir>>8)&0xF);
1.12 load_reg( R_EAX, Rn );
1.13 SHL1_r32( R_EAX );
1.14 + SETC_t();
1.15 store_reg( R_EAX, Rn );
1.16 }
1.17 break;
1.18 @@ -1283,6 +1284,7 @@
1.19 uint32_t Rn = ((ir>>8)&0xF);
1.20 load_reg( R_EAX, Rn );
1.21 SHL1_r32( R_EAX );
1.22 + SETC_t();
1.23 store_reg( R_EAX, Rn );
1.24 }
1.25 break;
1.26 @@ -1298,6 +1300,7 @@
1.27 uint32_t Rn = ((ir>>8)&0xF);
1.28 load_reg( R_EAX, Rn );
1.29 SHR1_r32( R_EAX );
1.30 + SETC_t();
1.31 store_reg( R_EAX, Rn );
1.32 }
1.33 break;
1.34 @@ -1314,6 +1317,7 @@
1.35 uint32_t Rn = ((ir>>8)&0xF);
1.36 load_reg( R_EAX, Rn );
1.37 SAR1_r32( R_EAX );
1.38 + SETC_t();
1.39 store_reg( R_EAX, Rn );
1.40 }
1.41 break;
2.1 --- a/src/sh4/sh4x86.in Wed Sep 19 11:22:43 2007 +0000
2.2 +++ b/src/sh4/sh4x86.in Wed Sep 19 11:30:30 2007 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: sh4x86.in,v 1.13 2007-09-19 10:04:16 nkeynes Exp $
2.6 + * $Id: sh4x86.in,v 1.14 2007-09-19 11:30:30 nkeynes Exp $
2.7 *
2.8 * SH4 => x86 translation. This version does no real optimization, it just
2.9 * outputs straight-line x86 code - it mainly exists to provide a baseline
2.10 @@ -907,16 +907,19 @@
2.11 SHAL Rn {:
2.12 load_reg( R_EAX, Rn );
2.13 SHL1_r32( R_EAX );
2.14 + SETC_t();
2.15 store_reg( R_EAX, Rn );
2.16 :}
2.17 SHAR Rn {:
2.18 load_reg( R_EAX, Rn );
2.19 SAR1_r32( R_EAX );
2.20 + SETC_t();
2.21 store_reg( R_EAX, Rn );
2.22 :}
2.23 SHLL Rn {:
2.24 load_reg( R_EAX, Rn );
2.25 SHL1_r32( R_EAX );
2.26 + SETC_t();
2.27 store_reg( R_EAX, Rn );
2.28 :}
2.29 SHLL2 Rn {:
2.30 @@ -937,6 +940,7 @@
2.31 SHLR Rn {:
2.32 load_reg( R_EAX, Rn );
2.33 SHR1_r32( R_EAX );
2.34 + SETC_t();
2.35 store_reg( R_EAX, Rn );
2.36 :}
2.37 SHLR2 Rn {:
.