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lxdream.org :: lxdream :: r228:70adc8ffa8d1
lxdream 0.9.1
released Jun 29
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changeset228:70adc8ffa8d1
parent227:1b98af7fc601
child229:f27eb26ccdd2
authornkeynes
dateMon Sep 25 11:13:56 2006 +0000 (14 years ago)
Commit BF tests and initial exception handler
test/Makefile
test/interrupt.s
test/sh4/andi.s
test/sh4/bf.s
test/sh4/inc.s
test/sh4/testsh4.c
1.1 --- a/test/Makefile Sat Sep 23 11:38:41 2006 +0000
1.2 +++ b/test/Makefile Mon Sep 25 11:13:56 2006 +0000
1.3 @@ -71,8 +71,9 @@
1.4
1.5 build-tests: testsh4 testmath testide testta testregs
1.6
1.7 -testsh4: crt0.so sh4/testsh4.so sh4/timer.so \
1.8 - sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so
1.9 +testsh4: crt0.so sh4/testsh4.so sh4/timer.so sh4/interrupt.so \
1.10 + sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so \
1.11 + sh4/bf.so
1.12 $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
1.13
1.14 testide: crt0.so testide.so ide.so
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
2.2 +++ b/test/interrupt.s Mon Sep 25 11:13:56 2006 +0000
2.3 @@ -0,0 +1,247 @@
2.4 +.section .text
2.5 +.include "sh4/inc.s"
2.6 +
2.7 +! expect_interrupt( int intevt )
2.8 +.global _expect_interrupt
2.9 +_expect_interrupt:
2.10 + stc sr, r3 ! Mask off interrupts
2.11 + mov.l bl_mask, r0
2.12 + or r3, r0
2.13 + ldc r0, sr
2.14 + mova expected_intevt, r0
2.15 + mov.l r4, @r0
2.16 + xor r1, r1
2.17 + mova expected_expevt, r0
2.18 + mov.l r1, @r0
2.19 + mova _interrupt_count, r0
2.20 + mov.l r1, @r0
2.21 + mova _interrupt_pc, r0
2.22 + mov.l r1, @r0
2.23 + ldc r3, sr ! Restore old SR state
2.24 + rts
2.25 + nop
2.26 +
2.27 + .global _expect_exception
2.28 +_expect_exception:
2.29 + stc sr, r3 ! Mask off interrupts
2.30 + mov.l bl_mask, r0
2.31 + or r3, r0
2.32 + ldc r0, sr
2.33 + mova expected_expevt, r0
2.34 + mov.l r4, @r0
2.35 + xor r1, r1
2.36 + mova expected_intevt, r0
2.37 + mov.l r1, @r0
2.38 + mova _interrupt_count, r0
2.39 + mov.l r1, @r0
2.40 + mova _interrupt_pc, r0
2.41 + mov.l r1, @r0
2.42 + ldc r3, sr ! Restore old SR state
2.43 + rts
2.44 + nop
2.45 +
2.46 + .align 4
2.47 +.global _interrupt_count
2.48 +_interrupt_count:
2.49 + .long 0x00000000
2.50 +.global _interrupt_pc
2.51 +_interrupt_pc:
2.52 + .long 0x00000000
2.53 +bl_mask:
2.54 + .long 0x10000000
2.55 +
2.56 +.global _install_interrupt_handler
2.57 +_install_interrupt_handler:
2.58 + stc vbr, r1
2.59 + mova old_vbr, r0
2.60 + mov.l r1, @r0
2.61 + mova __interrupt_handler, r0
2.62 + ldc r0, vbr
2.63 + rts
2.64 + nop
2.65 +
2.66 +.global _remove_interrupt_handler
2.67 +_remove_interrupt_handler:
2.68 + mov.l old_vbr, r1
2.69 + ldc r1, vbr
2.70 + rts
2.71 + nop
2.72 +.align 4
2.73 +old_vbr:
2.74 + .long 0x00000000
2.75 +expected_intevt:
2.76 + .long 0x00000000
2.77 +expected_expevt:
2.78 + .long 0x00000000
2.79 +
2.80 +
2.81 +__interrupt_handler:
2.82 + .skip 0x100
2.83 +general_exception:
2.84 + mov.l handler_stack_ptr_k, r15
2.85 + mov.l @r15, r15
2.86 + mov.l r0, @-r15
2.87 + mov.l r1, @-r15
2.88 + mov.l r2, @-r15
2.89 +
2.90 + mov.l expevt_k, r0
2.91 + mov.l @r0, r1
2.92 + mov.l expected_expevt_k, r2
2.93 + mov.l @r2, r2
2.94 + cmp/eq r1, r2
2.95 + bf general_not_expected
2.96 + bra ex_expected
2.97 + nop
2.98 +general_not_expected:
2.99 + bra ex_dontcare
2.100 + nop
2.101 + nop
2.102 +expevt_k:
2.103 + .long 0xFF000024
2.104 +expected_expevt_k:
2.105 + .long expected_expevt
2.106 +handler_stack_ptr_k:
2.107 + .long handler_stack_ptr
2.108 + .skip 0x2D4 ! Pad up to 0x400
2.109 +
2.110 +tlb_exception:
2.111 + mov.l handler_stack_ptr, r15
2.112 + mov.l r0, @-r15
2.113 + mov.l r1, @-r15
2.114 + mov.l r2, @-r15
2.115 +
2.116 + mov.l expevt1_k, r0
2.117 + mov.l @r0, r1
2.118 + mov.l expected_expevt1_k, r2
2.119 + mov.l @r2, r2
2.120 + cmp/eq r1, r2
2.121 + bf tlb_not_expected
2.122 + bra ex_expected
2.123 + nop
2.124 +tlb_not_expected:
2.125 + bra ex_dontcare
2.126 + nop
2.127 +expevt1_k:
2.128 + .long 0xFF000024
2.129 +expected_expevt1_k:
2.130 + .long expected_expevt
2.131 +
2.132 + .skip 0x1DC ! Pad up to 0x600
2.133 +
2.134 +irq_raised:
2.135 + mov.l handler_stack_ptr, r15
2.136 + mov.l r0, @-r15
2.137 + mov.l r1, @-r15
2.138 + mov.l r2, @-r15
2.139 +
2.140 + mov.l intevt_k, r0
2.141 + mov.l @r0, r1
2.142 + mov.l expected_intevt_k, r2
2.143 + mov.l @r2, r2
2.144 + cmp/eq r1, r2
2.145 + bf ex_dontcare
2.146 +
2.147 +ex_expected:
2.148 + mov.l interrupt_count_k, r0
2.149 + mov.l @r0, r2
2.150 + add #1, r2
2.151 + mov.l r2, @r0
2.152 + stc spc, r2
2.153 + mov.l interrupt_pc_k, r0
2.154 + mov.l r2, @r0
2.155 +
2.156 +! For most instructions, spc = raising instruction, so add 2 to get the next
2.157 +! instruction. Exceptions are the slot illegals (need pc+4), and trapa/
2.158 +! user-break-after-instruction where the pc is already correct
2.159 + mov.l slot_illegal_k, r0
2.160 + cmp/eq r0, r1
2.161 + bt ex_slot_spc
2.162 + mov.l slot_fpu_disable_k, r0
2.163 + cmp/eq r0, r1
2.164 + bt ex_slot_spc
2.165 + mov.l trapa_exc_k, r0
2.166 + cmp/eq r0, r1
2.167 + bt ex_nochain
2.168 + mov.l break_after_k, r0
2.169 + cmp/eq r0, r1
2.170 + bt ex_nochain
2.171 +! For everything else, spc += 2
2.172 + add #2, r2
2.173 + ldc r2, spc
2.174 + bra ex_nochain
2.175 + nop
2.176 +ex_slot_spc:
2.177 + add #4, r2
2.178 + ldc r2, spc
2.179 + bra ex_nochain
2.180 + nop
2.181 +
2.182 +ex_dontcare: ! Not the event we were waiting for.
2.183 + mov.l old_vbr_k, r2
2.184 + mov.l @r2, r2
2.185 + xor r0, r0
2.186 + cmp/eq r0, r2
2.187 + bt ex_nochain
2.188 +
2.189 + stc ssr, r0
2.190 + mov.l r0, @-r15
2.191 + stc spc, r0
2.192 + mov.l r0, @-r15
2.193 + stc sgr, r0
2.194 + mov.l r0, @-r15
2.195 + mov.l ex_chainreturn, r0
2.196 + ldc r0, spc
2.197 + mova handler_stack_ptr, r0
2.198 + mov.l r15, @r0
2.199 + braf r2 ! Chain on
2.200 + nop
2.201 +
2.202 +ex_chainreturn:
2.203 + mov.l handler_stack_ptr, r15
2.204 + mov.l @r15+, r0
2.205 + ldc r0, sgr
2.206 + mov.l @r15+, r0
2.207 + ldc r0, spc
2.208 + mov.l @r15+, r0
2.209 + ldc r0, ssr
2.210 +
2.211 +ex_nochain: ! No previous vbr to chain to
2.212 + mova handler_stack_ptr, r0
2.213 + mov r15, r1
2.214 + add #12, r1
2.215 + mov.l r1, @r0
2.216 + mov.l @r15+, r2
2.217 + mov.l @r15+, r1
2.218 + mov.l @r15+, r0
2.219 + rte
2.220 + stc sgr, r15
2.221 +
2.222 +.align 4
2.223 +expected_intevt_k:
2.224 + .long expected_intevt
2.225 +interrupt_count_k:
2.226 + .long _interrupt_count
2.227 +interrupt_pc_k:
2.228 + .long _interrupt_pc
2.229 +old_vbr_k:
2.230 + .long old_vbr
2.231 +trapa_k:
2.232 + .long 0xFF000020
2.233 +intevt_k:
2.234 + .long 0xFF000028
2.235 +
2.236 +slot_illegal_k:
2.237 + .long 0x000001A0
2.238 +slot_fpu_disable_k:
2.239 + .long 0x00000820
2.240 +trapa_exc_k:
2.241 + .long 0x00000160
2.242 +break_after_k:
2.243 + .long 0x000001E0
2.244 +
2.245 +handler_stack_ptr:
2.246 + .long handler_stack_end
2.247 +
2.248 +handler_stack:
2.249 + .skip 0x200
2.250 +handler_stack_end:
3.1 --- a/test/sh4/andi.s Sat Sep 23 11:38:41 2006 +0000
3.2 +++ b/test/sh4/andi.s Mon Sep 25 11:13:56 2006 +0000
3.3 @@ -55,6 +55,10 @@
3.4 ldc r0, gbr
3.5 mov.l test_andi_4_op1, r0
3.6 and.b #254, @(r0,gbr)
3.7 + add #1, r0
3.8 + and.b #67, @(r0,gbr)
3.9 + add #2, r0
3.10 + and.b #227, @(r0,gbr)
3.11 ldc r4, gbr
3.12 mov.l test_andi_4_output, r1
3.13 mov.l test_andi_4_result, r2
3.14 @@ -70,7 +74,7 @@
3.15 test_andi_4_output:
3.16 .long 0x123456AB
3.17 test_andi_4_result:
3.18 - .long 0x123456AA
3.19 + .long 0x023442AA
3.20
3.21 test_andi_5:
3.22 test_andi_end:
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/test/sh4/bf.s Mon Sep 25 11:13:56 2006 +0000
4.3 @@ -0,0 +1,99 @@
4.4 +.section .text
4.5 +.include "sh4/inc.s"
4.6 +!
4.7 +! Test bf pcrel
4.8 +! Test bf/s pcrel
4.9 +
4.10 +.global _test_bf
4.11 +_test_bf:
4.12 + start_test
4.13 +
4.14 +test_bf_1: ! Test branch not taken
4.15 + add #1, r12
4.16 + setc
4.17 + bf test_bf_1_b
4.18 + bra test_bf_2
4.19 + nop
4.20 +test_bf_1_b:
4.21 + fail test_bf_str_k
4.22 +
4.23 +test_bf_2: ! Test branch taken
4.24 + add #1, r12
4.25 + clc
4.26 + bf test_bf_3
4.27 + fail test_bf_str_k
4.28 +
4.29 +test_bf_3: ! Test branch taken (backwards)
4.30 + add #1, r12
4.31 + clc
4.32 + bra test_bf_3_b
4.33 + nop
4.34 + fail test_bf_str_k
4.35 + bra test_bf_4
4.36 +test_bf_3_c:
4.37 + nop
4.38 + bra test_bf_4
4.39 + nop
4.40 + fail test_bf_str_k
4.41 + bra test_bf_4
4.42 +test_bf_3_b:
4.43 + nop
4.44 + bf test_bf_3_c
4.45 + fail test_bf_str_k
4.46 + bra test_bf_4
4.47 + nop
4.48 +test_bf_4: ! Test branch not taken w/ delay
4.49 + add #1, r12
4.50 + setc
4.51 + xor r0, r0
4.52 + bf/s test_bf_4_b
4.53 + add #1, r0
4.54 + bra test_bf_4_c
4.55 + nop
4.56 +test_bf_4_b:
4.57 + fail test_bf_str_k
4.58 + bra test_bf_5
4.59 + nop
4.60 +test_bf_4_c:
4.61 + xor r1,r1
4.62 + add #1, r1
4.63 + cmp/eq r0, r1
4.64 +
4.65 +test_bf_5: ! Test branch taken w/ delay
4.66 + add #1, r12
4.67 + clc
4.68 + xor r0,r0
4.69 + bf/s test_bf_5_b
4.70 + add #1, r0
4.71 + fail test_bf_str_k
4.72 + bra test_bf_6
4.73 +test_bf_5_b:
4.74 + xor r1,r1
4.75 + add #1, r1
4.76 + cmp/eq r0,r1
4.77 + bt test_bf_6
4.78 + fail test_bf_str_k
4.79 +
4.80 +test_bf_6:
4.81 + add #1, r12
4.82 + expect_exc 0x000001A0 ! BF is slot illegal
4.83 +test_bf_6_exc:
4.84 + bra test_bf_6_b
4.85 + bf test_bf_6_b
4.86 + assert_exc_caught test_bf_str_k test_bf_6_exc
4.87 + bra test_bf_end
4.88 + nop
4.89 +test_bf_6_b:
4.90 +test_bf_6_c:
4.91 + fail test_bf_str_k
4.92 +
4.93 +test_bf_end:
4.94 + end_test test_bf_str_k
4.95 +
4.96 +test_bf_str:
4.97 + .string "BF"
4.98 +
4.99 +.align 4
4.100 +test_bf_str_k:
4.101 + .long test_bf_str
4.102 +
4.103 \ No newline at end of file
5.1 --- a/test/sh4/inc.s Sat Sep 23 11:38:41 2006 +0000
5.2 +++ b/test/sh4/inc.s Mon Sep 25 11:13:56 2006 +0000
5.3 @@ -140,6 +140,67 @@
5.4 addc r0, r0
5.5 .endm
5.6
5.7 +.macro clearbl
5.8 +LOCAL L1
5.9 +LOCAL L2
5.10 + mov.l L1, r0
5.11 + stc sr, r1
5.12 + and r0, r1
5.13 + ldc r1, sr
5.14 + bra L2
5.15 + nop
5.16 +.align 4
5.17 +L1: .long 0xEFFFFFFF
5.18 +L2:
5.19 +.endm
5.20 +
5.21 +.macro setbl
5.22 +LOCAL L1
5.23 +LOCAL L2
5.24 + xor r0, r0
5.25 + add #1, r0
5.26 + shll r0, 28
5.27 + stc sr, r1
5.28 + or r0, r1
5.29 + ldc r1, sr
5.30 + bra L2
5.31 + nop
5.32 +.align 4
5.33 +L1: .long 0x10000000
5.34 +L2:
5.35 +.endm
5.36 +
5.37 +.macro expect_exc code
5.38 +LOCAL L1, L2, L3
5.39 + mov.l L1, r3
5.40 + mov.l L2, r4
5.41 + jsr @r3
5.42 + nop
5.43 + bra L3
5.44 + nop
5.45 +.align 4
5.46 +L1: .long _expect_exception
5.47 +L2: .long \code
5.48 +L3:
5.49 +
5.50 +.endm
5.51 +
5.52 +.macro assert_exc_caught testname, expectpc
5.53 +LOCAL L1, L2
5.54 + mov.l L1, r3
5.55 + mov.l \testname, r4
5.56 + mov r12, r5
5.57 + mov.l L2, r6
5.58 + jsr @r3
5.59 + nop
5.60 + add r0, r13
5.61 + bra L3
5.62 + nop
5.63 +.align 4
5.64 +L1: .long _assert_exception_caught
5.65 +L2: .long \expectpc
5.66 +L3:
5.67 +.endm
5.68
5.69 .align 2
5.70 assert_t_set_message:
6.1 --- a/test/sh4/testsh4.c Sat Sep 23 11:38:41 2006 +0000
6.2 +++ b/test/sh4/testsh4.c Mon Sep 25 11:13:56 2006 +0000
6.3 @@ -20,14 +20,38 @@
6.4 }
6.5 }
6.6
6.7 +extern unsigned int interrupt_pc;
6.8 +extern unsigned int interrupt_count;
6.9 +
6.10 +int assert_exception_caught( char *testname, int number, unsigned int expectedpc )
6.11 +{
6.12 + if( interrupt_count == 0 ) {
6.13 + fprintf( stderr, "%s: Test %d failed: Expected exception not delivered\n",
6.14 + testname, number );
6.15 + return 1;
6.16 + } else if( interrupt_count != 1 ) {
6.17 + fprintf( stderr, "%s: Test %d failed: Expected exception delivered %d times!\n",
6.18 + testname, number, interrupt_count );
6.19 + return 1;
6.20 + } else if( interrupt_pc != expectedpc ) {
6.21 + fprintf( stderr, "%s: Test %d failed: Expected exception at PC %08X, but was %08X\n",
6.22 + testname, number, expectedpc, interrupt_pc );
6.23 + return 1;
6.24 + } else {
6.25 + return 0;
6.26 + }
6.27 +}
6.28 +
6.29 int main()
6.30 {
6.31 -
6.32 + install_interrupt_handler();
6.33 test_add();
6.34 test_addc();
6.35 test_addv();
6.36 test_and();
6.37 test_andi();
6.38 + test_bf();
6.39 + remove_interrupt_handler();
6.40
6.41 fprintf( stderr, "Total: %d/%d tests passed (%d%%)\n", total_tests-total_fails,
6.42 total_tests, ((total_tests-total_fails)*100)/total_tests );
.