revision 228:70adc8ffa8d1
summary |
tree |
shortlog |
changelog |
graph |
changeset |
raw | bz2 | zip | gz changeset | 228:70adc8ffa8d1 |
parent | 227:1b98af7fc601 |
child | 229:f27eb26ccdd2 |
author | nkeynes |
date | Mon Sep 25 11:13:56 2006 +0000 (17 years ago) |
Commit BF tests and initial exception handler
test/Makefile | view | annotate | diff | log | ||
test/interrupt.s | view | annotate | diff | log | ||
test/sh4/andi.s | view | annotate | diff | log | ||
test/sh4/bf.s | view | annotate | diff | log | ||
test/sh4/inc.s | view | annotate | diff | log | ||
test/sh4/testsh4.c | view | annotate | diff | log |
1.1 --- a/test/Makefile Sat Sep 23 11:38:41 2006 +00001.2 +++ b/test/Makefile Mon Sep 25 11:13:56 2006 +00001.3 @@ -71,8 +71,9 @@1.5 build-tests: testsh4 testmath testide testta testregs1.7 -testsh4: crt0.so sh4/testsh4.so sh4/timer.so \1.8 - sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so1.9 +testsh4: crt0.so sh4/testsh4.so sh4/timer.so sh4/interrupt.so \1.10 + sh4/add.so sh4/addc.so sh4/addv.so sh4/and.so sh4/andi.so \1.11 + sh4/bf.so1.12 $(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)1.14 testide: crt0.so testide.so ide.so
2.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00002.2 +++ b/test/interrupt.s Mon Sep 25 11:13:56 2006 +00002.3 @@ -0,0 +1,247 @@2.4 +.section .text2.5 +.include "sh4/inc.s"2.6 +2.7 +! expect_interrupt( int intevt )2.8 +.global _expect_interrupt2.9 +_expect_interrupt:2.10 + stc sr, r3 ! Mask off interrupts2.11 + mov.l bl_mask, r02.12 + or r3, r02.13 + ldc r0, sr2.14 + mova expected_intevt, r02.15 + mov.l r4, @r02.16 + xor r1, r12.17 + mova expected_expevt, r02.18 + mov.l r1, @r02.19 + mova _interrupt_count, r02.20 + mov.l r1, @r02.21 + mova _interrupt_pc, r02.22 + mov.l r1, @r02.23 + ldc r3, sr ! Restore old SR state2.24 + rts2.25 + nop2.26 +2.27 + .global _expect_exception2.28 +_expect_exception:2.29 + stc sr, r3 ! Mask off interrupts2.30 + mov.l bl_mask, r02.31 + or r3, r02.32 + ldc r0, sr2.33 + mova expected_expevt, r02.34 + mov.l r4, @r02.35 + xor r1, r12.36 + mova expected_intevt, r02.37 + mov.l r1, @r02.38 + mova _interrupt_count, r02.39 + mov.l r1, @r02.40 + mova _interrupt_pc, r02.41 + mov.l r1, @r02.42 + ldc r3, sr ! Restore old SR state2.43 + rts2.44 + nop2.45 +2.46 + .align 42.47 +.global _interrupt_count2.48 +_interrupt_count:2.49 + .long 0x000000002.50 +.global _interrupt_pc2.51 +_interrupt_pc:2.52 + .long 0x000000002.53 +bl_mask:2.54 + .long 0x100000002.55 +2.56 +.global _install_interrupt_handler2.57 +_install_interrupt_handler:2.58 + stc vbr, r12.59 + mova old_vbr, r02.60 + mov.l r1, @r02.61 + mova __interrupt_handler, r02.62 + ldc r0, vbr2.63 + rts2.64 + nop2.65 +2.66 +.global _remove_interrupt_handler2.67 +_remove_interrupt_handler:2.68 + mov.l old_vbr, r12.69 + ldc r1, vbr2.70 + rts2.71 + nop2.72 +.align 42.73 +old_vbr:2.74 + .long 0x000000002.75 +expected_intevt:2.76 + .long 0x000000002.77 +expected_expevt:2.78 + .long 0x000000002.79 +2.80 +2.81 +__interrupt_handler:2.82 + .skip 0x1002.83 +general_exception:2.84 + mov.l handler_stack_ptr_k, r152.85 + mov.l @r15, r152.86 + mov.l r0, @-r152.87 + mov.l r1, @-r152.88 + mov.l r2, @-r152.89 +2.90 + mov.l expevt_k, r02.91 + mov.l @r0, r12.92 + mov.l expected_expevt_k, r22.93 + mov.l @r2, r22.94 + cmp/eq r1, r22.95 + bf general_not_expected2.96 + bra ex_expected2.97 + nop2.98 +general_not_expected:2.99 + bra ex_dontcare2.100 + nop2.101 + nop2.102 +expevt_k:2.103 + .long 0xFF0000242.104 +expected_expevt_k:2.105 + .long expected_expevt2.106 +handler_stack_ptr_k:2.107 + .long handler_stack_ptr2.108 + .skip 0x2D4 ! Pad up to 0x4002.109 +2.110 +tlb_exception:2.111 + mov.l handler_stack_ptr, r152.112 + mov.l r0, @-r152.113 + mov.l r1, @-r152.114 + mov.l r2, @-r152.115 +2.116 + mov.l expevt1_k, r02.117 + mov.l @r0, r12.118 + mov.l expected_expevt1_k, r22.119 + mov.l @r2, r22.120 + cmp/eq r1, r22.121 + bf tlb_not_expected2.122 + bra ex_expected2.123 + nop2.124 +tlb_not_expected:2.125 + bra ex_dontcare2.126 + nop2.127 +expevt1_k:2.128 + .long 0xFF0000242.129 +expected_expevt1_k:2.130 + .long expected_expevt2.131 +2.132 + .skip 0x1DC ! Pad up to 0x6002.133 +2.134 +irq_raised:2.135 + mov.l handler_stack_ptr, r152.136 + mov.l r0, @-r152.137 + mov.l r1, @-r152.138 + mov.l r2, @-r152.139 +2.140 + mov.l intevt_k, r02.141 + mov.l @r0, r12.142 + mov.l expected_intevt_k, r22.143 + mov.l @r2, r22.144 + cmp/eq r1, r22.145 + bf ex_dontcare2.146 +2.147 +ex_expected:2.148 + mov.l interrupt_count_k, r02.149 + mov.l @r0, r22.150 + add #1, r22.151 + mov.l r2, @r02.152 + stc spc, r22.153 + mov.l interrupt_pc_k, r02.154 + mov.l r2, @r02.155 +2.156 +! For most instructions, spc = raising instruction, so add 2 to get the next2.157 +! instruction. Exceptions are the slot illegals (need pc+4), and trapa/2.158 +! user-break-after-instruction where the pc is already correct2.159 + mov.l slot_illegal_k, r02.160 + cmp/eq r0, r12.161 + bt ex_slot_spc2.162 + mov.l slot_fpu_disable_k, r02.163 + cmp/eq r0, r12.164 + bt ex_slot_spc2.165 + mov.l trapa_exc_k, r02.166 + cmp/eq r0, r12.167 + bt ex_nochain2.168 + mov.l break_after_k, r02.169 + cmp/eq r0, r12.170 + bt ex_nochain2.171 +! For everything else, spc += 22.172 + add #2, r22.173 + ldc r2, spc2.174 + bra ex_nochain2.175 + nop2.176 +ex_slot_spc:2.177 + add #4, r22.178 + ldc r2, spc2.179 + bra ex_nochain2.180 + nop2.181 +2.182 +ex_dontcare: ! Not the event we were waiting for.2.183 + mov.l old_vbr_k, r22.184 + mov.l @r2, r22.185 + xor r0, r02.186 + cmp/eq r0, r22.187 + bt ex_nochain2.188 +2.189 + stc ssr, r02.190 + mov.l r0, @-r152.191 + stc spc, r02.192 + mov.l r0, @-r152.193 + stc sgr, r02.194 + mov.l r0, @-r152.195 + mov.l ex_chainreturn, r02.196 + ldc r0, spc2.197 + mova handler_stack_ptr, r02.198 + mov.l r15, @r02.199 + braf r2 ! Chain on2.200 + nop2.201 +2.202 +ex_chainreturn:2.203 + mov.l handler_stack_ptr, r152.204 + mov.l @r15+, r02.205 + ldc r0, sgr2.206 + mov.l @r15+, r02.207 + ldc r0, spc2.208 + mov.l @r15+, r02.209 + ldc r0, ssr2.210 +2.211 +ex_nochain: ! No previous vbr to chain to2.212 + mova handler_stack_ptr, r02.213 + mov r15, r12.214 + add #12, r12.215 + mov.l r1, @r02.216 + mov.l @r15+, r22.217 + mov.l @r15+, r12.218 + mov.l @r15+, r02.219 + rte2.220 + stc sgr, r152.221 +2.222 +.align 42.223 +expected_intevt_k:2.224 + .long expected_intevt2.225 +interrupt_count_k:2.226 + .long _interrupt_count2.227 +interrupt_pc_k:2.228 + .long _interrupt_pc2.229 +old_vbr_k:2.230 + .long old_vbr2.231 +trapa_k:2.232 + .long 0xFF0000202.233 +intevt_k:2.234 + .long 0xFF0000282.235 +2.236 +slot_illegal_k:2.237 + .long 0x000001A02.238 +slot_fpu_disable_k:2.239 + .long 0x000008202.240 +trapa_exc_k:2.241 + .long 0x000001602.242 +break_after_k:2.243 + .long 0x000001E02.244 +2.245 +handler_stack_ptr:2.246 + .long handler_stack_end2.247 +2.248 +handler_stack:2.249 + .skip 0x2002.250 +handler_stack_end:
3.1 --- a/test/sh4/andi.s Sat Sep 23 11:38:41 2006 +00003.2 +++ b/test/sh4/andi.s Mon Sep 25 11:13:56 2006 +00003.3 @@ -55,6 +55,10 @@3.4 ldc r0, gbr3.5 mov.l test_andi_4_op1, r03.6 and.b #254, @(r0,gbr)3.7 + add #1, r03.8 + and.b #67, @(r0,gbr)3.9 + add #2, r03.10 + and.b #227, @(r0,gbr)3.11 ldc r4, gbr3.12 mov.l test_andi_4_output, r13.13 mov.l test_andi_4_result, r23.14 @@ -70,7 +74,7 @@3.15 test_andi_4_output:3.16 .long 0x123456AB3.17 test_andi_4_result:3.18 - .long 0x123456AA3.19 + .long 0x023442AA3.21 test_andi_5:3.22 test_andi_end:
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +00004.2 +++ b/test/sh4/bf.s Mon Sep 25 11:13:56 2006 +00004.3 @@ -0,0 +1,99 @@4.4 +.section .text4.5 +.include "sh4/inc.s"4.6 +!4.7 +! Test bf pcrel4.8 +! Test bf/s pcrel4.9 +4.10 +.global _test_bf4.11 +_test_bf:4.12 + start_test4.13 +4.14 +test_bf_1: ! Test branch not taken4.15 + add #1, r124.16 + setc4.17 + bf test_bf_1_b4.18 + bra test_bf_24.19 + nop4.20 +test_bf_1_b:4.21 + fail test_bf_str_k4.22 +4.23 +test_bf_2: ! Test branch taken4.24 + add #1, r124.25 + clc4.26 + bf test_bf_34.27 + fail test_bf_str_k4.28 +4.29 +test_bf_3: ! Test branch taken (backwards)4.30 + add #1, r124.31 + clc4.32 + bra test_bf_3_b4.33 + nop4.34 + fail test_bf_str_k4.35 + bra test_bf_44.36 +test_bf_3_c:4.37 + nop4.38 + bra test_bf_44.39 + nop4.40 + fail test_bf_str_k4.41 + bra test_bf_44.42 +test_bf_3_b:4.43 + nop4.44 + bf test_bf_3_c4.45 + fail test_bf_str_k4.46 + bra test_bf_44.47 + nop4.48 +test_bf_4: ! Test branch not taken w/ delay4.49 + add #1, r124.50 + setc4.51 + xor r0, r04.52 + bf/s test_bf_4_b4.53 + add #1, r04.54 + bra test_bf_4_c4.55 + nop4.56 +test_bf_4_b:4.57 + fail test_bf_str_k4.58 + bra test_bf_54.59 + nop4.60 +test_bf_4_c:4.61 + xor r1,r14.62 + add #1, r14.63 + cmp/eq r0, r14.64 +4.65 +test_bf_5: ! Test branch taken w/ delay4.66 + add #1, r124.67 + clc4.68 + xor r0,r04.69 + bf/s test_bf_5_b4.70 + add #1, r04.71 + fail test_bf_str_k4.72 + bra test_bf_64.73 +test_bf_5_b:4.74 + xor r1,r14.75 + add #1, r14.76 + cmp/eq r0,r14.77 + bt test_bf_64.78 + fail test_bf_str_k4.79 +4.80 +test_bf_6:4.81 + add #1, r124.82 + expect_exc 0x000001A0 ! BF is slot illegal4.83 +test_bf_6_exc:4.84 + bra test_bf_6_b4.85 + bf test_bf_6_b4.86 + assert_exc_caught test_bf_str_k test_bf_6_exc4.87 + bra test_bf_end4.88 + nop4.89 +test_bf_6_b:4.90 +test_bf_6_c:4.91 + fail test_bf_str_k4.92 +4.93 +test_bf_end:4.94 + end_test test_bf_str_k4.95 +4.96 +test_bf_str:4.97 + .string "BF"4.98 +4.99 +.align 44.100 +test_bf_str_k:4.101 + .long test_bf_str4.102 +4.103 \ No newline at end of file
5.1 --- a/test/sh4/inc.s Sat Sep 23 11:38:41 2006 +00005.2 +++ b/test/sh4/inc.s Mon Sep 25 11:13:56 2006 +00005.3 @@ -140,6 +140,67 @@5.4 addc r0, r05.5 .endm5.7 +.macro clearbl5.8 +LOCAL L15.9 +LOCAL L25.10 + mov.l L1, r05.11 + stc sr, r15.12 + and r0, r15.13 + ldc r1, sr5.14 + bra L25.15 + nop5.16 +.align 45.17 +L1: .long 0xEFFFFFFF5.18 +L2:5.19 +.endm5.20 +5.21 +.macro setbl5.22 +LOCAL L15.23 +LOCAL L25.24 + xor r0, r05.25 + add #1, r05.26 + shll r0, 285.27 + stc sr, r15.28 + or r0, r15.29 + ldc r1, sr5.30 + bra L25.31 + nop5.32 +.align 45.33 +L1: .long 0x100000005.34 +L2:5.35 +.endm5.36 +5.37 +.macro expect_exc code5.38 +LOCAL L1, L2, L35.39 + mov.l L1, r35.40 + mov.l L2, r45.41 + jsr @r35.42 + nop5.43 + bra L35.44 + nop5.45 +.align 45.46 +L1: .long _expect_exception5.47 +L2: .long \code5.48 +L3:5.49 +5.50 +.endm5.51 +5.52 +.macro assert_exc_caught testname, expectpc5.53 +LOCAL L1, L25.54 + mov.l L1, r35.55 + mov.l \testname, r45.56 + mov r12, r55.57 + mov.l L2, r65.58 + jsr @r35.59 + nop5.60 + add r0, r135.61 + bra L35.62 + nop5.63 +.align 45.64 +L1: .long _assert_exception_caught5.65 +L2: .long \expectpc5.66 +L3:5.67 +.endm5.69 .align 25.70 assert_t_set_message:
6.1 --- a/test/sh4/testsh4.c Sat Sep 23 11:38:41 2006 +00006.2 +++ b/test/sh4/testsh4.c Mon Sep 25 11:13:56 2006 +00006.3 @@ -20,14 +20,38 @@6.4 }6.5 }6.7 +extern unsigned int interrupt_pc;6.8 +extern unsigned int interrupt_count;6.9 +6.10 +int assert_exception_caught( char *testname, int number, unsigned int expectedpc )6.11 +{6.12 + if( interrupt_count == 0 ) {6.13 + fprintf( stderr, "%s: Test %d failed: Expected exception not delivered\n",6.14 + testname, number );6.15 + return 1;6.16 + } else if( interrupt_count != 1 ) {6.17 + fprintf( stderr, "%s: Test %d failed: Expected exception delivered %d times!\n",6.18 + testname, number, interrupt_count );6.19 + return 1;6.20 + } else if( interrupt_pc != expectedpc ) {6.21 + fprintf( stderr, "%s: Test %d failed: Expected exception at PC %08X, but was %08X\n",6.22 + testname, number, expectedpc, interrupt_pc );6.23 + return 1;6.24 + } else {6.25 + return 0;6.26 + }6.27 +}6.28 +6.29 int main()6.30 {6.31 -6.32 + install_interrupt_handler();6.33 test_add();6.34 test_addc();6.35 test_addv();6.36 test_and();6.37 test_andi();6.38 + test_bf();6.39 + remove_interrupt_handler();6.41 fprintf( stderr, "Total: %d/%d tests passed (%d%%)\n", total_tests-total_fails,6.42 total_tests, ((total_tests-total_fails)*100)/total_tests );
.