revision 85:71e239d20c5d
summary |
tree |
shortlog |
changelog |
graph |
changeset |
raw | bz2 | zip | gz changeset | 85:71e239d20c5d |
parent | 84:b993a8d8fbf3 |
child | 86:f151e63f9754 |
author | nkeynes |
date | Sun Jan 22 22:38:51 2006 +0000 (18 years ago) |
Fix colour mode definitions
Add PVR2 palette region
Fix ta end-of-command when it's not in the same buffer
Add PVR2 palette region
Fix ta end-of-command when it's not in the same buffer
src/pvr2/pvr2.c | view | annotate | diff | log | ||
src/pvr2/pvr2.h | view | annotate | diff | log |
1.1 --- a/src/pvr2/pvr2.c Sat Jan 21 11:38:36 2006 +00001.2 +++ b/src/pvr2/pvr2.c Sun Jan 22 22:38:51 2006 +00001.3 @@ -1,5 +1,5 @@1.4 /**1.5 - * $Id: pvr2.c,v 1.12 2006-01-03 12:21:45 nkeynes Exp $1.6 + * $Id: pvr2.c,v 1.13 2006-01-22 22:38:51 nkeynes Exp $1.7 *1.8 * PVR2 (Video) MMIO and supporting functions.1.9 *1.10 @@ -39,6 +39,7 @@1.11 void pvr2_init( void )1.12 {1.13 register_io_region( &mmio_region_PVR2 );1.14 + register_io_region( &mmio_region_PVR2PAL );1.15 register_io_region( &mmio_region_PVR2TA );1.16 video_base = mem_get_region_by_name( MEM_REGION_VIDEO );1.17 }1.18 @@ -146,6 +147,8 @@1.19 }1.20 }1.22 +MMIO_REGION_DEFFNS( PVR2PAL )1.23 +1.24 void pvr2_set_base_address( uint32_t base )1.25 {1.26 mmio_region_PVR2_write( DISPADDR1, base );1.27 @@ -184,18 +187,19 @@1.28 DEBUG( "Direct write to TA %08X", val );1.29 }1.31 +unsigned int pvr2_last_poly_type = 0;1.32 +1.33 void pvr2ta_write( char *buf, uint32_t length )1.34 {1.35 int i;1.36 struct tacmd *cmd_list = (struct tacmd *)buf;1.37 int count = length >> 5;1.38 - unsigned int lasttype = 0;1.39 for( i=0; i<count; i++ ){1.40 unsigned int type = (cmd_list[i].command >> 24) & 0xFF;1.41 DEBUG( "PVR2 cmd: %08X %08X %08X", cmd_list[i].command, cmd_list[i].param1, cmd_list[i].param2 );1.42 if( type == 0 ) {1.43 /* End of list */1.44 - switch( lasttype ) {1.45 + switch( pvr2_last_poly_type ) {1.46 case 0x80: /* Opaque polys */1.47 asic_event( EVENT_PVR_OPAQUE_DONE );1.48 break;1.49 @@ -212,8 +216,9 @@1.50 asic_event( EVENT_PVR_PUNCHOUT_DONE );1.51 break;1.52 }1.53 - } else {1.54 - lasttype = type;1.55 + pvr2_last_poly_type = 0;1.56 + } else if( type >= 0x80 && type <= 0x84 ) {1.57 + pvr2_last_poly_type = type;1.58 }1.59 }1.60 }
2.1 --- a/src/pvr2/pvr2.h Sat Jan 21 11:38:36 2006 +00002.2 +++ b/src/pvr2/pvr2.h Sun Jan 22 22:38:51 2006 +00002.3 @@ -1,5 +1,5 @@2.4 /**2.5 - * $Id: pvr2.h,v 1.5 2006-01-03 12:21:45 nkeynes Exp $2.6 + * $Id: pvr2.h,v 1.6 2006-01-22 22:38:51 nkeynes Exp $2.7 *2.8 * PVR2 (video chip) MMIO registers and functions.2.9 *2.10 @@ -70,6 +70,10 @@2.11 LONG_PORT( 0x164, TAOPLST, PORT_MRW, 0, "TA Object Pointer List start" )2.12 MMIO_REGION_END2.14 +MMIO_REGION_BEGIN( 0x005F9000, PVR2PAL, "Power VR/2 CLUT Palettes" )2.15 + LONG_PORT( 0x000, PAL0_0, PORT_MRW, 0, "Pal0 colour 0" )2.16 +MMIO_REGION_END2.17 +2.18 MMIO_REGION_BEGIN( 0x10000000, PVR2TA, "Power VR/2 TA Command port" )2.19 LONG_PORT( 0x000, TACMD, PORT_MRW, 0, "TA Command port" )2.20 MMIO_REGION_END2.21 @@ -80,9 +84,9 @@2.22 #define DISPMODE_CD 0x08000000 /* Clock double */2.24 #define MODE_RGB15 0x000000002.25 -#define MODE_RGB16 0x000000402.26 -#define MODE_RGB24 0x000000802.27 -#define MODE_RGB32 0x000000C02.28 +#define MODE_RGB16 0x000000042.29 +#define MODE_RGB24 0x000000082.30 +#define MODE_RGB32 0x0000000C2.32 #define DISPSIZE_MODULO 0x3FF00000 /* line skip +1 (32-bit words)*/2.33 #define DISPSIZE_LPF 0x000FFC00 /* lines per field */
.