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lxdream.org :: lxdream :: r1265:7c6c5d26fd2e
lxdream 0.9.1
released Jun 29
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changeset1265:7c6c5d26fd2e
parent1264:74ad81710528
child1266:e6079b9c69ba
authornkeynes
dateTue Mar 06 12:42:33 2012 +1000 (8 years ago)
Merge ARM disassembler from binutils 2.22
src/Makefile.am
src/Makefile.in
src/xlat/disasm/arm-dis.c
src/xlat/disasm/arm.h
src/xlat/disasm/bfd.h
src/xlat/disasm/dis-asm.h
src/xlat/disasm/floatformat.c
src/xlat/disasm/floatformat.h
src/xlat/disasm/safe-ctype.c
src/xlat/disasm/safe-ctype.h
1.1 --- a/src/Makefile.am Tue Mar 06 12:19:08 2012 +1000
1.2 +++ b/src/Makefile.am Tue Mar 06 12:42:33 2012 +1000
1.3 @@ -90,13 +90,17 @@
1.4 sh4/sh4trans.c sh4/sh4trans.h sh4/mmux86.c sh4/shadow.c \
1.5 xlat/disasm/i386-dis.c xlat/disasm/dis-init.c xlat/disasm/dis-buf.c \
1.6 xlat/disasm/ansidecl.h xlat/disasm/bfd.h xlat/disasm/dis-asm.h \
1.7 - xlat/disasm/symcat.h xlat/disasm/sysdep.h
1.8 + xlat/disasm/symcat.h xlat/disasm/sysdep.h xlat/disasm/arm-dis.c \
1.9 + xlat/disasm/floatformat.c xlat/disasm/floatformat.h \
1.10 + xlat/disasm/arm.h xlat/disasm/safe-ctype.h xlat/disasm/safe-ctype.c
1.11
1.12 test_testsh4x86_LDADD = @LXDREAM_LIBS@ @GLIB_LIBS@ @GTK_LIBS@ @LIBPNG_LIBS@
1.13 test_testsh4x86_CPPFLAGS = @LXDREAMCPPFLAGS@
1.14 test_testsh4x86_SOURCES = test/testsh4x86.c xlat/xlatdasm.c \
1.15 xlat/xlatdasm.h xlat/disasm/i386-dis.c xlat/disasm/dis-init.c \
1.16 - xlat/disasm/dis-buf.c \
1.17 + xlat/disasm/dis-buf.c xlat/disasm/arm-dis.c \
1.18 + xlat/disasm/arm.h xlat/disasm/safe-ctype.h xlat/disasm/safe-ctype.c \
1.19 + xlat/disasm/floatformat.c xlat/disasm/floatformat.h \
1.20 sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c sh4/sh4dasm.c \
1.21 xlat/xltcache.h mem.c util.c cpu.c
1.22
2.1 --- a/src/Makefile.in Tue Mar 06 12:19:08 2012 +1000
2.2 +++ b/src/Makefile.in Tue Mar 06 12:42:33 2012 +1000
2.3 @@ -49,7 +49,9 @@
2.4 @BUILD_SH4X86_TRUE@ sh4/sh4trans.c sh4/sh4trans.h sh4/mmux86.c sh4/shadow.c \
2.5 @BUILD_SH4X86_TRUE@ xlat/disasm/i386-dis.c xlat/disasm/dis-init.c xlat/disasm/dis-buf.c \
2.6 @BUILD_SH4X86_TRUE@ xlat/disasm/ansidecl.h xlat/disasm/bfd.h xlat/disasm/dis-asm.h \
2.7 -@BUILD_SH4X86_TRUE@ xlat/disasm/symcat.h xlat/disasm/sysdep.h
2.8 +@BUILD_SH4X86_TRUE@ xlat/disasm/symcat.h xlat/disasm/sysdep.h xlat/disasm/arm-dis.c \
2.9 +@BUILD_SH4X86_TRUE@ xlat/disasm/floatformat.c xlat/disasm/floatformat.h \
2.10 +@BUILD_SH4X86_TRUE@ xlat/disasm/arm.h xlat/disasm/safe-ctype.h xlat/disasm/safe-ctype.c
2.11
2.12 @BUILD_SH4X86_TRUE@am__append_3 = test/testsh4x86
2.13 @GUI_GTK_TRUE@am__append_4 = gtkui/gtkui.c gtkui/gtkui.h \
2.14 @@ -149,7 +151,10 @@
2.15 sh4/shadow.c xlat/disasm/i386-dis.c xlat/disasm/dis-init.c \
2.16 xlat/disasm/dis-buf.c xlat/disasm/ansidecl.h xlat/disasm/bfd.h \
2.17 xlat/disasm/dis-asm.h xlat/disasm/symcat.h \
2.18 - xlat/disasm/sysdep.h cocoaui/paths_osx.m drivers/io_osx.m \
2.19 + xlat/disasm/sysdep.h xlat/disasm/arm-dis.c \
2.20 + xlat/disasm/floatformat.c xlat/disasm/floatformat.h \
2.21 + xlat/disasm/arm.h xlat/disasm/safe-ctype.h \
2.22 + xlat/disasm/safe-ctype.c cocoaui/paths_osx.m drivers/io_osx.m \
2.23 drivers/mac_keymap.h drivers/mac_keymap.txt paths_unix.c \
2.24 drivers/io_glib.c
2.25 @BUILD_SH4X86_TRUE@am__objects_1 = liblxdream_core_a-sh4x86.$(OBJEXT) \
2.26 @@ -159,7 +164,10 @@
2.27 @BUILD_SH4X86_TRUE@ liblxdream_core_a-shadow.$(OBJEXT) \
2.28 @BUILD_SH4X86_TRUE@ liblxdream_core_a-i386-dis.$(OBJEXT) \
2.29 @BUILD_SH4X86_TRUE@ liblxdream_core_a-dis-init.$(OBJEXT) \
2.30 -@BUILD_SH4X86_TRUE@ liblxdream_core_a-dis-buf.$(OBJEXT)
2.31 +@BUILD_SH4X86_TRUE@ liblxdream_core_a-dis-buf.$(OBJEXT) \
2.32 +@BUILD_SH4X86_TRUE@ liblxdream_core_a-arm-dis.$(OBJEXT) \
2.33 +@BUILD_SH4X86_TRUE@ liblxdream_core_a-floatformat.$(OBJEXT) \
2.34 +@BUILD_SH4X86_TRUE@ liblxdream_core_a-safe-ctype.$(OBJEXT)
2.35 @GUI_COCOA_TRUE@am__objects_2 = liblxdream_core_a-paths_osx.$(OBJEXT) \
2.36 @GUI_COCOA_TRUE@ liblxdream_core_a-io_osx.$(OBJEXT)
2.37 @GUI_COCOA_FALSE@am__objects_3 = \
2.38 @@ -355,15 +363,20 @@
2.39 am__dirstamp = $(am__leading_dot)dirstamp
2.40 am__test_testsh4x86_SOURCES_DIST = test/testsh4x86.c xlat/xlatdasm.c \
2.41 xlat/xlatdasm.h xlat/disasm/i386-dis.c xlat/disasm/dis-init.c \
2.42 - xlat/disasm/dis-buf.c sh4/sh4trans.c sh4/sh4x86.c \
2.43 - xlat/xltcache.c sh4/sh4dasm.c xlat/xltcache.h mem.c util.c \
2.44 - cpu.c
2.45 + xlat/disasm/dis-buf.c xlat/disasm/arm-dis.c xlat/disasm/arm.h \
2.46 + xlat/disasm/safe-ctype.h xlat/disasm/safe-ctype.c \
2.47 + xlat/disasm/floatformat.c xlat/disasm/floatformat.h \
2.48 + sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c sh4/sh4dasm.c \
2.49 + xlat/xltcache.h mem.c util.c cpu.c
2.50 @BUILD_SH4X86_TRUE@am_test_testsh4x86_OBJECTS = \
2.51 @BUILD_SH4X86_TRUE@ test_testsh4x86-testsh4x86.$(OBJEXT) \
2.52 @BUILD_SH4X86_TRUE@ test_testsh4x86-xlatdasm.$(OBJEXT) \
2.53 @BUILD_SH4X86_TRUE@ test_testsh4x86-i386-dis.$(OBJEXT) \
2.54 @BUILD_SH4X86_TRUE@ test_testsh4x86-dis-init.$(OBJEXT) \
2.55 @BUILD_SH4X86_TRUE@ test_testsh4x86-dis-buf.$(OBJEXT) \
2.56 +@BUILD_SH4X86_TRUE@ test_testsh4x86-arm-dis.$(OBJEXT) \
2.57 +@BUILD_SH4X86_TRUE@ test_testsh4x86-safe-ctype.$(OBJEXT) \
2.58 +@BUILD_SH4X86_TRUE@ test_testsh4x86-floatformat.$(OBJEXT) \
2.59 @BUILD_SH4X86_TRUE@ test_testsh4x86-sh4trans.$(OBJEXT) \
2.60 @BUILD_SH4X86_TRUE@ test_testsh4x86-sh4x86.$(OBJEXT) \
2.61 @BUILD_SH4X86_TRUE@ test_testsh4x86-xltcache.$(OBJEXT) \
2.62 @@ -698,7 +711,9 @@
2.63 @BUILD_SH4X86_TRUE@test_testsh4x86_CPPFLAGS = @LXDREAMCPPFLAGS@
2.64 @BUILD_SH4X86_TRUE@test_testsh4x86_SOURCES = test/testsh4x86.c xlat/xlatdasm.c \
2.65 @BUILD_SH4X86_TRUE@ xlat/xlatdasm.h xlat/disasm/i386-dis.c xlat/disasm/dis-init.c \
2.66 -@BUILD_SH4X86_TRUE@ xlat/disasm/dis-buf.c \
2.67 +@BUILD_SH4X86_TRUE@ xlat/disasm/dis-buf.c xlat/disasm/arm-dis.c \
2.68 +@BUILD_SH4X86_TRUE@ xlat/disasm/arm.h xlat/disasm/safe-ctype.h xlat/disasm/safe-ctype.c \
2.69 +@BUILD_SH4X86_TRUE@ xlat/disasm/floatformat.c xlat/disasm/floatformat.h \
2.70 @BUILD_SH4X86_TRUE@ sh4/sh4trans.c sh4/sh4x86.c xlat/xltcache.c sh4/sh4dasm.c \
2.71 @BUILD_SH4X86_TRUE@ xlat/xltcache.h mem.c util.c cpu.c
2.72
2.73 @@ -869,6 +884,7 @@
2.74 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/cd_none.Po@am__quote@
2.75 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/gui_android.Po@am__quote@
2.76 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-aica.Po@am__quote@
2.77 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-arm-dis.Po@am__quote@
2.78 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-armcore.Po@am__quote@
2.79 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-armdasm.Po@am__quote@
2.80 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-armmem.Po@am__quote@
2.81 @@ -895,6 +911,7 @@
2.82 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-drive.Po@am__quote@
2.83 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-edc_ecc.Po@am__quote@
2.84 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-eventq.Po@am__quote@
2.85 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-floatformat.Po@am__quote@
2.86 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-gdbserver.Po@am__quote@
2.87 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-gdlist.Po@am__quote@
2.88 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-gdrom.Po@am__quote@
2.89 @@ -928,6 +945,7 @@
2.90 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-pvr2mem.Po@am__quote@
2.91 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-rendsave.Po@am__quote@
2.92 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-rendsort.Po@am__quote@
2.93 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-safe-ctype.Po@am__quote@
2.94 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-scene.Po@am__quote@
2.95 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-scif.Po@am__quote@
2.96 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/liblxdream_core_a-sdram.Po@am__quote@
2.97 @@ -993,11 +1011,14 @@
2.98 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lxdream-video_nsgl.Po@am__quote@
2.99 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lxdream-video_osx.Po@am__quote@
2.100 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/lxpaths.Po@am__quote@
2.101 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-arm-dis.Po@am__quote@
2.102 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-cpu.Po@am__quote@
2.103 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-dis-buf.Po@am__quote@
2.104 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-dis-init.Po@am__quote@
2.105 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-floatformat.Po@am__quote@
2.106 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-i386-dis.Po@am__quote@
2.107 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-mem.Po@am__quote@
2.108 +@AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-safe-ctype.Po@am__quote@
2.109 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-sh4dasm.Po@am__quote@
2.110 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-sh4trans.Po@am__quote@
2.111 @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/test_testsh4x86-sh4x86.Po@am__quote@
2.112 @@ -2215,6 +2236,48 @@
2.113 @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.114 @am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o liblxdream_core_a-dis-buf.obj `if test -f 'xlat/disasm/dis-buf.c'; then $(CYGPATH_W) 'xlat/disasm/dis-buf.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/dis-buf.c'; fi`
2.115
2.116 +liblxdream_core_a-arm-dis.o: xlat/disasm/arm-dis.c
2.117 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT liblxdream_core_a-arm-dis.o -MD -MP -MF "$(DEPDIR)/liblxdream_core_a-arm-dis.Tpo" -c -o liblxdream_core_a-arm-dis.o `test -f 'xlat/disasm/arm-dis.c' || echo '$(srcdir)/'`xlat/disasm/arm-dis.c; \
2.118 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/liblxdream_core_a-arm-dis.Tpo" "$(DEPDIR)/liblxdream_core_a-arm-dis.Po"; else rm -f "$(DEPDIR)/liblxdream_core_a-arm-dis.Tpo"; exit 1; fi
2.119 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/arm-dis.c' object='liblxdream_core_a-arm-dis.o' libtool=no @AMDEPBACKSLASH@
2.120 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.121 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o liblxdream_core_a-arm-dis.o `test -f 'xlat/disasm/arm-dis.c' || echo '$(srcdir)/'`xlat/disasm/arm-dis.c
2.122 +
2.123 +liblxdream_core_a-arm-dis.obj: xlat/disasm/arm-dis.c
2.124 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT liblxdream_core_a-arm-dis.obj -MD -MP -MF "$(DEPDIR)/liblxdream_core_a-arm-dis.Tpo" -c -o liblxdream_core_a-arm-dis.obj `if test -f 'xlat/disasm/arm-dis.c'; then $(CYGPATH_W) 'xlat/disasm/arm-dis.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/arm-dis.c'; fi`; \
2.125 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/liblxdream_core_a-arm-dis.Tpo" "$(DEPDIR)/liblxdream_core_a-arm-dis.Po"; else rm -f "$(DEPDIR)/liblxdream_core_a-arm-dis.Tpo"; exit 1; fi
2.126 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/arm-dis.c' object='liblxdream_core_a-arm-dis.obj' libtool=no @AMDEPBACKSLASH@
2.127 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.128 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o liblxdream_core_a-arm-dis.obj `if test -f 'xlat/disasm/arm-dis.c'; then $(CYGPATH_W) 'xlat/disasm/arm-dis.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/arm-dis.c'; fi`
2.129 +
2.130 +liblxdream_core_a-floatformat.o: xlat/disasm/floatformat.c
2.131 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT liblxdream_core_a-floatformat.o -MD -MP -MF "$(DEPDIR)/liblxdream_core_a-floatformat.Tpo" -c -o liblxdream_core_a-floatformat.o `test -f 'xlat/disasm/floatformat.c' || echo '$(srcdir)/'`xlat/disasm/floatformat.c; \
2.132 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/liblxdream_core_a-floatformat.Tpo" "$(DEPDIR)/liblxdream_core_a-floatformat.Po"; else rm -f "$(DEPDIR)/liblxdream_core_a-floatformat.Tpo"; exit 1; fi
2.133 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/floatformat.c' object='liblxdream_core_a-floatformat.o' libtool=no @AMDEPBACKSLASH@
2.134 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.135 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o liblxdream_core_a-floatformat.o `test -f 'xlat/disasm/floatformat.c' || echo '$(srcdir)/'`xlat/disasm/floatformat.c
2.136 +
2.137 +liblxdream_core_a-floatformat.obj: xlat/disasm/floatformat.c
2.138 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT liblxdream_core_a-floatformat.obj -MD -MP -MF "$(DEPDIR)/liblxdream_core_a-floatformat.Tpo" -c -o liblxdream_core_a-floatformat.obj `if test -f 'xlat/disasm/floatformat.c'; then $(CYGPATH_W) 'xlat/disasm/floatformat.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/floatformat.c'; fi`; \
2.139 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/liblxdream_core_a-floatformat.Tpo" "$(DEPDIR)/liblxdream_core_a-floatformat.Po"; else rm -f "$(DEPDIR)/liblxdream_core_a-floatformat.Tpo"; exit 1; fi
2.140 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/floatformat.c' object='liblxdream_core_a-floatformat.obj' libtool=no @AMDEPBACKSLASH@
2.141 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.142 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o liblxdream_core_a-floatformat.obj `if test -f 'xlat/disasm/floatformat.c'; then $(CYGPATH_W) 'xlat/disasm/floatformat.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/floatformat.c'; fi`
2.143 +
2.144 +liblxdream_core_a-safe-ctype.o: xlat/disasm/safe-ctype.c
2.145 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT liblxdream_core_a-safe-ctype.o -MD -MP -MF "$(DEPDIR)/liblxdream_core_a-safe-ctype.Tpo" -c -o liblxdream_core_a-safe-ctype.o `test -f 'xlat/disasm/safe-ctype.c' || echo '$(srcdir)/'`xlat/disasm/safe-ctype.c; \
2.146 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/liblxdream_core_a-safe-ctype.Tpo" "$(DEPDIR)/liblxdream_core_a-safe-ctype.Po"; else rm -f "$(DEPDIR)/liblxdream_core_a-safe-ctype.Tpo"; exit 1; fi
2.147 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/safe-ctype.c' object='liblxdream_core_a-safe-ctype.o' libtool=no @AMDEPBACKSLASH@
2.148 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.149 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o liblxdream_core_a-safe-ctype.o `test -f 'xlat/disasm/safe-ctype.c' || echo '$(srcdir)/'`xlat/disasm/safe-ctype.c
2.150 +
2.151 +liblxdream_core_a-safe-ctype.obj: xlat/disasm/safe-ctype.c
2.152 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT liblxdream_core_a-safe-ctype.obj -MD -MP -MF "$(DEPDIR)/liblxdream_core_a-safe-ctype.Tpo" -c -o liblxdream_core_a-safe-ctype.obj `if test -f 'xlat/disasm/safe-ctype.c'; then $(CYGPATH_W) 'xlat/disasm/safe-ctype.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/safe-ctype.c'; fi`; \
2.153 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/liblxdream_core_a-safe-ctype.Tpo" "$(DEPDIR)/liblxdream_core_a-safe-ctype.Po"; else rm -f "$(DEPDIR)/liblxdream_core_a-safe-ctype.Tpo"; exit 1; fi
2.154 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/safe-ctype.c' object='liblxdream_core_a-safe-ctype.obj' libtool=no @AMDEPBACKSLASH@
2.155 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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2.157 +
2.158 liblxdream_core_a-paths_unix.o: paths_unix.c
2.159 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(liblxdream_core_a_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT liblxdream_core_a-paths_unix.o -MD -MP -MF "$(DEPDIR)/liblxdream_core_a-paths_unix.Tpo" -c -o liblxdream_core_a-paths_unix.o `test -f 'paths_unix.c' || echo '$(srcdir)/'`paths_unix.c; \
2.160 @am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/liblxdream_core_a-paths_unix.Tpo" "$(DEPDIR)/liblxdream_core_a-paths_unix.Po"; else rm -f "$(DEPDIR)/liblxdream_core_a-paths_unix.Tpo"; exit 1; fi
2.161 @@ -2705,6 +2768,48 @@
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2.164
2.165 +test_testsh4x86-arm-dis.o: xlat/disasm/arm-dis.c
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2.167 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/test_testsh4x86-arm-dis.Tpo" "$(DEPDIR)/test_testsh4x86-arm-dis.Po"; else rm -f "$(DEPDIR)/test_testsh4x86-arm-dis.Tpo"; exit 1; fi
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2.169 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
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2.171 +
2.172 +test_testsh4x86-arm-dis.obj: xlat/disasm/arm-dis.c
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2.174 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/test_testsh4x86-arm-dis.Tpo" "$(DEPDIR)/test_testsh4x86-arm-dis.Po"; else rm -f "$(DEPDIR)/test_testsh4x86-arm-dis.Tpo"; exit 1; fi
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2.176 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.177 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o test_testsh4x86-arm-dis.obj `if test -f 'xlat/disasm/arm-dis.c'; then $(CYGPATH_W) 'xlat/disasm/arm-dis.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/arm-dis.c'; fi`
2.178 +
2.179 +test_testsh4x86-safe-ctype.o: xlat/disasm/safe-ctype.c
2.180 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT test_testsh4x86-safe-ctype.o -MD -MP -MF "$(DEPDIR)/test_testsh4x86-safe-ctype.Tpo" -c -o test_testsh4x86-safe-ctype.o `test -f 'xlat/disasm/safe-ctype.c' || echo '$(srcdir)/'`xlat/disasm/safe-ctype.c; \
2.181 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/test_testsh4x86-safe-ctype.Tpo" "$(DEPDIR)/test_testsh4x86-safe-ctype.Po"; else rm -f "$(DEPDIR)/test_testsh4x86-safe-ctype.Tpo"; exit 1; fi
2.182 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/safe-ctype.c' object='test_testsh4x86-safe-ctype.o' libtool=no @AMDEPBACKSLASH@
2.183 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.184 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o test_testsh4x86-safe-ctype.o `test -f 'xlat/disasm/safe-ctype.c' || echo '$(srcdir)/'`xlat/disasm/safe-ctype.c
2.185 +
2.186 +test_testsh4x86-safe-ctype.obj: xlat/disasm/safe-ctype.c
2.187 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT test_testsh4x86-safe-ctype.obj -MD -MP -MF "$(DEPDIR)/test_testsh4x86-safe-ctype.Tpo" -c -o test_testsh4x86-safe-ctype.obj `if test -f 'xlat/disasm/safe-ctype.c'; then $(CYGPATH_W) 'xlat/disasm/safe-ctype.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/safe-ctype.c'; fi`; \
2.188 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/test_testsh4x86-safe-ctype.Tpo" "$(DEPDIR)/test_testsh4x86-safe-ctype.Po"; else rm -f "$(DEPDIR)/test_testsh4x86-safe-ctype.Tpo"; exit 1; fi
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2.190 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.191 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o test_testsh4x86-safe-ctype.obj `if test -f 'xlat/disasm/safe-ctype.c'; then $(CYGPATH_W) 'xlat/disasm/safe-ctype.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/safe-ctype.c'; fi`
2.192 +
2.193 +test_testsh4x86-floatformat.o: xlat/disasm/floatformat.c
2.194 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT test_testsh4x86-floatformat.o -MD -MP -MF "$(DEPDIR)/test_testsh4x86-floatformat.Tpo" -c -o test_testsh4x86-floatformat.o `test -f 'xlat/disasm/floatformat.c' || echo '$(srcdir)/'`xlat/disasm/floatformat.c; \
2.195 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/test_testsh4x86-floatformat.Tpo" "$(DEPDIR)/test_testsh4x86-floatformat.Po"; else rm -f "$(DEPDIR)/test_testsh4x86-floatformat.Tpo"; exit 1; fi
2.196 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/floatformat.c' object='test_testsh4x86-floatformat.o' libtool=no @AMDEPBACKSLASH@
2.197 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.198 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o test_testsh4x86-floatformat.o `test -f 'xlat/disasm/floatformat.c' || echo '$(srcdir)/'`xlat/disasm/floatformat.c
2.199 +
2.200 +test_testsh4x86-floatformat.obj: xlat/disasm/floatformat.c
2.201 +@am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT test_testsh4x86-floatformat.obj -MD -MP -MF "$(DEPDIR)/test_testsh4x86-floatformat.Tpo" -c -o test_testsh4x86-floatformat.obj `if test -f 'xlat/disasm/floatformat.c'; then $(CYGPATH_W) 'xlat/disasm/floatformat.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/floatformat.c'; fi`; \
2.202 +@am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/test_testsh4x86-floatformat.Tpo" "$(DEPDIR)/test_testsh4x86-floatformat.Po"; else rm -f "$(DEPDIR)/test_testsh4x86-floatformat.Tpo"; exit 1; fi
2.203 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ source='xlat/disasm/floatformat.c' object='test_testsh4x86-floatformat.obj' libtool=no @AMDEPBACKSLASH@
2.204 +@AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@
2.205 +@am__fastdepCC_FALSE@ $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -c -o test_testsh4x86-floatformat.obj `if test -f 'xlat/disasm/floatformat.c'; then $(CYGPATH_W) 'xlat/disasm/floatformat.c'; else $(CYGPATH_W) '$(srcdir)/xlat/disasm/floatformat.c'; fi`
2.206 +
2.207 test_testsh4x86-sh4trans.o: sh4/sh4trans.c
2.208 @am__fastdepCC_TRUE@ if $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(test_testsh4x86_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) -MT test_testsh4x86-sh4trans.o -MD -MP -MF "$(DEPDIR)/test_testsh4x86-sh4trans.Tpo" -c -o test_testsh4x86-sh4trans.o `test -f 'sh4/sh4trans.c' || echo '$(srcdir)/'`sh4/sh4trans.c; \
2.209 @am__fastdepCC_TRUE@ then mv -f "$(DEPDIR)/test_testsh4x86-sh4trans.Tpo" "$(DEPDIR)/test_testsh4x86-sh4trans.Po"; else rm -f "$(DEPDIR)/test_testsh4x86-sh4trans.Tpo"; exit 1; fi
3.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
3.2 +++ b/src/xlat/disasm/arm-dis.c Tue Mar 06 12:42:33 2012 +1000
3.3 @@ -0,0 +1,4995 @@
3.4 +/* Instruction printing code for the ARM
3.5 + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
3.6 + 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
3.7 + Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
3.8 + Modification by James G. Smith (jsmith@cygnus.co.uk)
3.9 +
3.10 + This file is part of libopcodes.
3.11 +
3.12 + This library is free software; you can redistribute it and/or modify
3.13 + it under the terms of the GNU General Public License as published by
3.14 + the Free Software Foundation; either version 3 of the License, or
3.15 + (at your option) any later version.
3.16 +
3.17 + It is distributed in the hope that it will be useful, but WITHOUT
3.18 + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
3.19 + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
3.20 + License for more details.
3.21 +
3.22 + You should have received a copy of the GNU General Public License
3.23 + along with this program; if not, write to the Free Software
3.24 + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
3.25 + MA 02110-1301, USA. */
3.26 +
3.27 +#include "sysdep.h"
3.28 +
3.29 +#include "dis-asm.h"
3.30 +#include "arm.h"
3.31 +#include "gettext.h"
3.32 +#include "safe-ctype.h"
3.33 +#include "floatformat.h"
3.34 +
3.35 +/* FIXME: Belongs in global header. */
3.36 +#ifndef strneq
3.37 +#define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
3.38 +#endif
3.39 +
3.40 +#define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
3.41 +
3.42 +#ifndef NUM_ELEM
3.43 +#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
3.44 +#endif
3.45 +
3.46 +/* Cached mapping symbol state. */
3.47 +enum map_type
3.48 +{
3.49 + MAP_ARM,
3.50 + MAP_THUMB,
3.51 + MAP_DATA
3.52 +};
3.53 +
3.54 +struct arm_private_data
3.55 +{
3.56 + /* The features to use when disassembling optional instructions. */
3.57 + arm_feature_set features;
3.58 +
3.59 + /* Whether any mapping symbols are present in the provided symbol
3.60 + table. -1 if we do not know yet, otherwise 0 or 1. */
3.61 + int has_mapping_symbols;
3.62 +
3.63 + /* Track the last type (although this doesn't seem to be useful) */
3.64 + enum map_type last_type;
3.65 +
3.66 + /* Tracking symbol table information */
3.67 + int last_mapping_sym;
3.68 + bfd_vma last_mapping_addr;
3.69 +};
3.70 +
3.71 +struct opcode32
3.72 +{
3.73 + unsigned long arch; /* Architecture defining this insn. */
3.74 + unsigned long value; /* If arch == 0 then value is a sentinel. */
3.75 + unsigned long mask; /* Recognise insn if (op & mask) == value. */
3.76 + const char * assembler; /* How to disassemble this insn. */
3.77 +};
3.78 +
3.79 +struct opcode16
3.80 +{
3.81 + unsigned long arch; /* Architecture defining this insn. */
3.82 + unsigned short value, mask; /* Recognise insn if (op & mask) == value. */
3.83 + const char *assembler; /* How to disassemble this insn. */
3.84 +};
3.85 +
3.86 +/* print_insn_coprocessor recognizes the following format control codes:
3.87 +
3.88 + %% %
3.89 +
3.90 + %c print condition code (always bits 28-31 in ARM mode)
3.91 + %q print shifter argument
3.92 + %u print condition code (unconditional in ARM mode)
3.93 + %A print address for ldc/stc/ldf/stf instruction
3.94 + %B print vstm/vldm register list
3.95 + %I print cirrus signed shift immediate: bits 0..3|4..6
3.96 + %F print the COUNT field of a LFM/SFM instruction.
3.97 + %P print floating point precision in arithmetic insn
3.98 + %Q print floating point precision in ldf/stf insn
3.99 + %R print floating point rounding mode
3.100 +
3.101 + %<bitfield>r print as an ARM register
3.102 + %<bitfield>R as %<>r but r15 is UNPREDICTABLE
3.103 + %<bitfield>ru as %<>r but each u register must be unique.
3.104 + %<bitfield>d print the bitfield in decimal
3.105 + %<bitfield>k print immediate for VFPv3 conversion instruction
3.106 + %<bitfield>x print the bitfield in hex
3.107 + %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3.108 + %<bitfield>f print a floating point constant if >7 else a
3.109 + floating point register
3.110 + %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
3.111 + %<bitfield>g print as an iWMMXt 64-bit register
3.112 + %<bitfield>G print as an iWMMXt general purpose or control register
3.113 + %<bitfield>D print as a NEON D register
3.114 + %<bitfield>Q print as a NEON Q register
3.115 +
3.116 + %y<code> print a single precision VFP reg.
3.117 + Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
3.118 + %z<code> print a double precision VFP reg
3.119 + Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
3.120 +
3.121 + %<bitfield>'c print specified char iff bitfield is all ones
3.122 + %<bitfield>`c print specified char iff bitfield is all zeroes
3.123 + %<bitfield>?ab... select from array of values in big endian order
3.124 +
3.125 + %L print as an iWMMXt N/M width field.
3.126 + %Z print the Immediate of a WSHUFH instruction.
3.127 + %l like 'A' except use byte offsets for 'B' & 'H'
3.128 + versions.
3.129 + %i print 5-bit immediate in bits 8,3..0
3.130 + (print "32" when 0)
3.131 + %r print register offset address for wldt/wstr instruction. */
3.132 +
3.133 +enum opcode_sentinel_enum
3.134 +{
3.135 + SENTINEL_IWMMXT_START = 1,
3.136 + SENTINEL_IWMMXT_END,
3.137 + SENTINEL_GENERIC_START
3.138 +} opcode_sentinels;
3.139 +
3.140 +#define UNDEFINED_INSTRUCTION "\t\t; <UNDEFINED> instruction: %0-31x"
3.141 +#define UNPREDICTABLE_INSTRUCTION "\t; <UNPREDICTABLE>"
3.142 +
3.143 +/* Common coprocessor opcodes shared between Arm and Thumb-2. */
3.144 +
3.145 +static const struct opcode32 coprocessor_opcodes[] =
3.146 +{
3.147 + /* XScale instructions. */
3.148 + {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"},
3.149 + {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"},
3.150 + {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"},
3.151 + {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"},
3.152 + {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"},
3.153 +
3.154 + /* Intel Wireless MMX technology instructions. */
3.155 + { 0, SENTINEL_IWMMXT_START, 0, "" },
3.156 + {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"},
3.157 + {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"},
3.158 + {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"},
3.159 + {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"},
3.160 + {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"},
3.161 + {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"},
3.162 + {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"},
3.163 + {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"},
3.164 + {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"},
3.165 + {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"},
3.166 + {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"},
3.167 + {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"},
3.168 + {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"},
3.169 + {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"},
3.170 + {ARM_CEXT_XSCALE, 0x0e120190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"},
3.171 + {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"},
3.172 + {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"},
3.173 + {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"},
3.174 + {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0fb00ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"},
3.175 + {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"},
3.176 + {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"},
3.177 + {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"},
3.178 + {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"},
3.179 + {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"},
3.180 + {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"},
3.181 + {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"},
3.182 + {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
3.183 + {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"},
3.184 + {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"},
3.185 + {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"},
3.186 + {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"},
3.187 + {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"},
3.188 + {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"},
3.189 + {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
3.190 + {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"},
3.191 + {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
3.192 + {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
3.193 + {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"},
3.194 + {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"},
3.195 + {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"},
3.196 + {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"},
3.197 + {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"},
3.198 + {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"},
3.199 + {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"},
3.200 + {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"},
3.201 + {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"},
3.202 + {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"},
3.203 + {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"},
3.204 + {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"},
3.205 + {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"},
3.206 + {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"},
3.207 + {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"},
3.208 + {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"},
3.209 + {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"},
3.210 + {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
3.211 + {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
3.212 + {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"},
3.213 + {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
3.214 + {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
3.215 + {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"},
3.216 + {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"},
3.217 + {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"},
3.218 + {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"},
3.219 + {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"},
3.220 + {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"},
3.221 + {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"},
3.222 + {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"},
3.223 + {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"},
3.224 + {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"},
3.225 + {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"},
3.226 + {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"},
3.227 + {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"},
3.228 + {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"},
3.229 + {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"},
3.230 + {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"},
3.231 + { 0, SENTINEL_IWMMXT_END, 0, "" },
3.232 +
3.233 + /* Floating point coprocessor (FPA) instructions. */
3.234 + {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.235 + {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.236 + {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.237 + {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.238 + {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.239 + {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.240 + {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.241 + {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.242 + {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.243 + {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.244 + {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.245 + {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.246 + {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"},
3.247 + {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"},
3.248 + {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"},
3.249 + {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"},
3.250 + {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"},
3.251 + {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"},
3.252 + {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"},
3.253 + {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"},
3.254 + {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"},
3.255 + {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"},
3.256 + {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"},
3.257 + {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"},
3.258 + {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"},
3.259 + {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"},
3.260 + {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"},
3.261 + {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"},
3.262 + {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"},
3.263 + {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"},
3.264 + {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"},
3.265 + {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"},
3.266 + {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"},
3.267 + {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"},
3.268 + {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"},
3.269 + {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"},
3.270 + {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"},
3.271 + {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"},
3.272 + {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"},
3.273 + {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"},
3.274 + {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"},
3.275 + {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"},
3.276 + {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"},
3.277 +
3.278 + /* Register load/store. */
3.279 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d2d0b00, 0x0fbf0f01, "vpush%c\t%B"},
3.280 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r!, %B"},
3.281 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r!, %B"},
3.282 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"},
3.283 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0cbd0b00, 0x0fbf0f01, "vpop%c\t%B"},
3.284 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"},
3.285 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %A"},
3.286 + {FPU_VFP_EXT_V1xD | FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %A"},
3.287 + {FPU_VFP_EXT_V1xD, 0x0d2d0a00, 0x0fbf0f00, "vpush%c\t%y3"},
3.288 + {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "vstmdb%c\t%16-19r!, %y3"},
3.289 + {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "vldmdb%c\t%16-19r!, %y3"},
3.290 + {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "vstmia%c\t%16-19r%21'!, %y3"},
3.291 + {FPU_VFP_EXT_V1xD, 0x0cbd0a00, 0x0fbf0f00, "vpop%c\t%y3"},
3.292 + {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "vldmia%c\t%16-19r%21'!, %y3"},
3.293 + {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "vstr%c\t%y1, %A"},
3.294 + {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "vldr%c\t%y1, %A"},
3.295 +
3.296 + {FPU_VFP_EXT_V1xD, 0x0d200b01, 0x0fb00f01, "fstmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
3.297 + {FPU_VFP_EXT_V1xD, 0x0d300b01, 0x0fb00f01, "fldmdbx%c\t%16-19r!, %z3\t;@ Deprecated"},
3.298 + {FPU_VFP_EXT_V1xD, 0x0c800b01, 0x0f900f01, "fstmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
3.299 + {FPU_VFP_EXT_V1xD, 0x0c900b01, 0x0f900f01, "fldmiax%c\t%16-19r%21'!, %z3\t;@ Deprecated"},
3.300 +
3.301 + /* Data transfer between ARM and NEON registers. */
3.302 + {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"},
3.303 + {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"},
3.304 + {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"},
3.305 + {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"},
3.306 + {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"},
3.307 + {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"},
3.308 + {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"},
3.309 + {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"},
3.310 + {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"},
3.311 + {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"},
3.312 + {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"},
3.313 + {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"},
3.314 + {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"},
3.315 + {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"},
3.316 + /* Half-precision conversion instructions. */
3.317 + {FPU_VFP_EXT_FP16, 0x0eb20a40, 0x0fbf0f50, "vcvt%7?tb%c.f32.f16\t%y1, %y0"},
3.318 + {FPU_VFP_EXT_FP16, 0x0eb30a40, 0x0fbf0f50, "vcvt%7?tb%c.f16.f32\t%y1, %y0"},
3.319 +
3.320 + /* Floating point coprocessor (VFP) instructions. */
3.321 + {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "vmsr%c\tfpsid, %12-15r"},
3.322 + {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "vmsr%c\tfpscr, %12-15r"},
3.323 + {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
3.324 + {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
3.325 + {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
3.326 + {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "vmsr%c\tfpinst, %12-15r\t@ Impl def"},
3.327 + {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "vmsr%c\tfpinst2, %12-15r\t@ Impl def"},
3.328 + {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpsid"},
3.329 + {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
3.330 + {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
3.331 + {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
3.332 + {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr0"},
3.333 + {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpexc"},
3.334 + {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst\t@ Impl def"},
3.335 + {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpinst2\t@ Impl def"},
3.336 + {FPU_VFP_EXT_V1, 0x0e000b10, 0x0fd00fff, "vmov%c.32\t%z2[%21d], %12-15r"},
3.337 + {FPU_VFP_EXT_V1, 0x0e100b10, 0x0fd00fff, "vmov%c.32\t%12-15r, %z2[%21d]"},
3.338 + {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "vmsr%c\t<impl def %16-19x>, %12-15r"},
3.339 + {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "vmrs%c\t%12-15r, <impl def %16-19x>"},
3.340 + {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "vmov%c\t%y2, %12-15r"},
3.341 + {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "vmov%c\t%12-15r, %y2"},
3.342 + {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "vcmp%7'e%c.f32\t%y1, #0.0"},
3.343 + {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "vcmp%7'e%c.f64\t%z1, #0.0"},
3.344 + {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "vmov%c.f32\t%y1, %y0"},
3.345 + {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "vabs%c.f32\t%y1, %y0"},
3.346 + {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "vmov%c.f64\t%z1, %z0"},
3.347 + {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "vabs%c.f64\t%z1, %z0"},
3.348 + {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "vneg%c.f32\t%y1, %y0"},
3.349 + {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "vsqrt%c.f32\t%y1, %y0"},
3.350 + {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "vneg%c.f64\t%z1, %z0"},
3.351 + {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "vsqrt%c.f64\t%z1, %z0"},
3.352 + {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "vcvt%c.f64.f32\t%z1, %y0"},
3.353 + {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "vcvt%c.f32.f64\t%y1, %z0"},
3.354 + {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0f50, "vcvt%c.f32.%7?su32\t%y1, %y0"},
3.355 + {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0f50, "vcvt%c.f64.%7?su32\t%z1, %y0"},
3.356 + {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "vcmp%7'e%c.f32\t%y1, %y0"},
3.357 + {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "vcmp%7'e%c.f64\t%z1, %z0"},
3.358 + {FPU_VFP_EXT_V3xD, 0x0eba0a40, 0x0fbe0f50, "vcvt%c.f32.%16?us%7?31%7?26\t%y1, %y1, #%5,0-3k"},
3.359 + {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "vcvt%c.f64.%16?us%7?31%7?26\t%z1, %z1, #%5,0-3k"},
3.360 + {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f32\t%y1, %y0"},
3.361 + {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "vcvt%7`r%c.%16?su32.f64\t%y1, %z0"},
3.362 + {FPU_VFP_EXT_V3xD, 0x0ebe0a40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f32\t%y1, %y1, #%5,0-3k"},
3.363 + {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "vcvt%c.%16?us%7?31%7?26.f64\t%z1, %z1, #%5,0-3k"},
3.364 + {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "vmov%c\t%12-15r, %16-19r, %z0"},
3.365 + {FPU_VFP_EXT_V3xD, 0x0eb00a00, 0x0fb00ff0, "vmov%c.f32\t%y1, #%0-3,16-19d"},
3.366 + {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "vmov%c.f64\t%z1, #%0-3,16-19d"},
3.367 + {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "vmov%c\t%y4, %12-15r, %16-19r"},
3.368 + {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%z0, %12-15r, %16-19r"},
3.369 + {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %y4"},
3.370 + {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "vmla%c.f32\t%y1, %y2, %y0"},
3.371 + {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "vmls%c.f32\t%y1, %y2, %y0"},
3.372 + {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "vmla%c.f64\t%z1, %z2, %z0"},
3.373 + {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "vmls%c.f64\t%z1, %z2, %z0"},
3.374 + {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "vnmls%c.f32\t%y1, %y2, %y0"},
3.375 + {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "vnmla%c.f32\t%y1, %y2, %y0"},
3.376 + {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "vnmls%c.f64\t%z1, %z2, %z0"},
3.377 + {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "vnmla%c.f64\t%z1, %z2, %z0"},
3.378 + {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "vmul%c.f32\t%y1, %y2, %y0"},
3.379 + {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "vnmul%c.f32\t%y1, %y2, %y0"},
3.380 + {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "vmul%c.f64\t%z1, %z2, %z0"},
3.381 + {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "vnmul%c.f64\t%z1, %z2, %z0"},
3.382 + {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "vadd%c.f32\t%y1, %y2, %y0"},
3.383 + {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "vsub%c.f32\t%y1, %y2, %y0"},
3.384 + {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "vadd%c.f64\t%z1, %z2, %z0"},
3.385 + {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "vsub%c.f64\t%z1, %z2, %z0"},
3.386 + {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "vdiv%c.f32\t%y1, %y2, %y0"},
3.387 + {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
3.388 +
3.389 + /* Cirrus coprocessor instructions. */
3.390 + {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
3.391 + {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"},
3.392 + {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
3.393 + {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"},
3.394 + {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
3.395 + {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"},
3.396 + {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
3.397 + {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"},
3.398 + {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
3.399 + {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"},
3.400 + {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
3.401 + {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"},
3.402 + {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
3.403 + {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"},
3.404 + {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
3.405 + {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"},
3.406 + {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"},
3.407 + {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"},
3.408 + {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"},
3.409 + {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"},
3.410 + {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"},
3.411 + {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"},
3.412 + {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"},
3.413 + {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"},
3.414 + {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"},
3.415 + {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"},
3.416 + {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"},
3.417 + {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"},
3.418 + {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"},
3.419 + {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"},
3.420 + {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"},
3.421 + {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"},
3.422 + {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"},
3.423 + {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"},
3.424 + {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"},
3.425 + {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"},
3.426 + {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"},
3.427 + {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"},
3.428 + {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"},
3.429 + {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"},
3.430 + {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"},
3.431 + {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"},
3.432 + {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"},
3.433 + {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"},
3.434 + {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"},
3.435 + {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"},
3.436 + {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"},
3.437 + {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"},
3.438 + {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"},
3.439 + {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"},
3.440 + {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"},
3.441 + {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"},
3.442 + {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"},
3.443 + {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"},
3.444 + {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"},
3.445 + {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"},
3.446 + {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"},
3.447 + {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"},
3.448 + {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"},
3.449 + {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"},
3.450 + {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"},
3.451 + {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"},
3.452 + {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
3.453 + {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
3.454 + {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
3.455 + {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
3.456 + {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"},
3.457 + {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"},
3.458 + {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"},
3.459 + {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"},
3.460 + {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"},
3.461 + {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"},
3.462 + {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.463 + {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
3.464 + {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.465 + {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
3.466 + {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.467 + {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"},
3.468 + {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.469 + {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.470 + {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.471 + {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.472 + {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.473 + {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"},
3.474 +
3.475 + /* VFP Fused multiply add instructions. */
3.476 + {FPU_VFP_EXT_FMA, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
3.477 + {FPU_VFP_EXT_FMA, 0x0ea00b00, 0x0fb00f50, "vfma%c.f64\t%z1, %z2, %z0"},
3.478 + {FPU_VFP_EXT_FMA, 0x0ea00a40, 0x0fb00f50, "vfms%c.f32\t%y1, %y2, %y0"},
3.479 + {FPU_VFP_EXT_FMA, 0x0ea00b40, 0x0fb00f50, "vfms%c.f64\t%z1, %z2, %z0"},
3.480 + {FPU_VFP_EXT_FMA, 0x0e900a40, 0x0fb00f50, "vfnma%c.f32\t%y1, %y2, %y0"},
3.481 + {FPU_VFP_EXT_FMA, 0x0e900b40, 0x0fb00f50, "vfnma%c.f64\t%z1, %z2, %z0"},
3.482 + {FPU_VFP_EXT_FMA, 0x0e900a00, 0x0fb00f50, "vfnms%c.f32\t%y1, %y2, %y0"},
3.483 + {FPU_VFP_EXT_FMA, 0x0e900b00, 0x0fb00f50, "vfnms%c.f64\t%z1, %z2, %z0"},
3.484 +
3.485 + /* Generic coprocessor instructions. */
3.486 + { 0, SENTINEL_GENERIC_START, 0, "" },
3.487 + {ARM_EXT_V5E, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15R, %16-19r, cr%0-3d"},
3.488 + {ARM_EXT_V5E, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
3.489 + {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
3.490 + {ARM_EXT_V2, 0x0e10f010, 0x0f10f010, "mrc%c\t%8-11d, %21-23d, APSR_nzcv, cr%16-19d, cr%0-3d, {%5-7d}"},
3.491 + {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
3.492 + {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
3.493 + {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"},
3.494 + {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"},
3.495 +
3.496 + /* V6 coprocessor instructions. */
3.497 + {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15Ru, %16-19Ru, cr%0-3d"},
3.498 + {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
3.499 +
3.500 + /* V5 coprocessor instructions. */
3.501 + {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
3.502 + {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"},
3.503 + {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"},
3.504 + {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15R, cr%16-19d, cr%0-3d, {%5-7d}"},
3.505 + {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"},
3.506 +
3.507 + {0, 0, 0, 0}
3.508 +};
3.509 +
3.510 +/* Neon opcode table: This does not encode the top byte -- that is
3.511 + checked by the print_insn_neon routine, as it depends on whether we are
3.512 + doing thumb32 or arm32 disassembly. */
3.513 +
3.514 +/* print_insn_neon recognizes the following format control codes:
3.515 +
3.516 + %% %
3.517 +
3.518 + %c print condition code
3.519 + %A print v{st,ld}[1234] operands
3.520 + %B print v{st,ld}[1234] any one operands
3.521 + %C print v{st,ld}[1234] single->all operands
3.522 + %D print scalar
3.523 + %E print vmov, vmvn, vorr, vbic encoded constant
3.524 + %F print vtbl,vtbx register list
3.525 +
3.526 + %<bitfield>r print as an ARM register
3.527 + %<bitfield>d print the bitfield in decimal
3.528 + %<bitfield>e print the 2^N - bitfield in decimal
3.529 + %<bitfield>D print as a NEON D register
3.530 + %<bitfield>Q print as a NEON Q register
3.531 + %<bitfield>R print as a NEON D or Q register
3.532 + %<bitfield>Sn print byte scaled width limited by n
3.533 + %<bitfield>Tn print short scaled width limited by n
3.534 + %<bitfield>Un print long scaled width limited by n
3.535 +
3.536 + %<bitfield>'c print specified char iff bitfield is all ones
3.537 + %<bitfield>`c print specified char iff bitfield is all zeroes
3.538 + %<bitfield>?ab... select from array of values in big endian order. */
3.539 +
3.540 +static const struct opcode32 neon_opcodes[] =
3.541 +{
3.542 + /* Extract. */
3.543 + {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
3.544 + {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"},
3.545 +
3.546 + /* Move data element to all lanes. */
3.547 + {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"},
3.548 + {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"},
3.549 + {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"},
3.550 +
3.551 + /* Table lookup. */
3.552 + {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"},
3.553 + {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"},
3.554 +
3.555 + /* Half-precision conversions. */
3.556 + {FPU_VFP_EXT_FP16, 0xf3b60600, 0xffbf0fd0, "vcvt%c.f16.f32\t%12-15,22D, %0-3,5Q"},
3.557 + {FPU_VFP_EXT_FP16, 0xf3b60700, 0xffbf0fd0, "vcvt%c.f32.f16\t%12-15,22Q, %0-3,5D"},
3.558 +
3.559 + /* NEON fused multiply add instructions. */
3.560 + {FPU_NEON_EXT_FMA, 0xf2000c10, 0xffa00f10, "vfma%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.561 + {FPU_NEON_EXT_FMA, 0xf2200c10, 0xffa00f10, "vfms%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.562 +
3.563 + /* Two registers, miscellaneous. */
3.564 + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"},
3.565 + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"},
3.566 + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"},
3.567 + {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"},
3.568 + {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"},
3.569 + {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"},
3.570 + {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"},
3.571 + {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
3.572 + {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"},
3.573 + {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"},
3.574 + {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"},
3.575 + {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
3.576 + {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"},
3.577 + {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"},
3.578 + {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"},
3.579 + {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"},
3.580 + {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
3.581 + {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"},
3.582 + {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
3.583 + {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"},
3.584 + {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"},
3.585 + {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"},
3.586 + {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"},
3.587 + {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
3.588 + {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
3.589 + {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"},
3.590 + {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
3.591 + {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"},
3.592 + {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
3.593 + {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"},
3.594 + {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
3.595 + {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"},
3.596 + {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
3.597 +
3.598 + /* Three registers of the same length. */
3.599 + {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.600 + {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.601 + {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.602 + {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.603 + {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.604 + {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.605 + {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.606 + {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.607 + {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.608 + {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.609 + {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.610 + {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.611 + {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.612 + {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.613 + {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.614 + {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.615 + {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.616 + {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.617 + {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.618 + {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.619 + {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.620 + {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.621 + {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.622 + {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.623 + {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.624 + {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.625 + {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.626 + {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.627 + {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.628 + {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.629 + {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.630 + {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.631 + {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.632 + {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.633 + {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.634 + {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.635 + {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.636 + {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.637 + {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.638 + {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.639 + {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.640 + {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.641 + {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
3.642 + {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
3.643 + {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
3.644 + {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"},
3.645 + {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.646 + {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.647 + {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.648 + {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.649 + {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.650 + {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.651 + {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"},
3.652 +
3.653 + /* One register and an immediate value. */
3.654 + {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"},
3.655 + {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"},
3.656 + {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"},
3.657 + {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"},
3.658 + {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"},
3.659 + {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"},
3.660 + {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"},
3.661 + {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"},
3.662 + {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"},
3.663 + {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"},
3.664 + {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"},
3.665 + {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"},
3.666 + {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"},
3.667 +
3.668 + /* Two registers and a shift amount. */
3.669 + {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
3.670 + {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"},
3.671 + {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
3.672 + {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"},
3.673 + {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
3.674 + {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"},
3.675 + {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"},
3.676 + {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
3.677 + {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"},
3.678 + {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
3.679 + {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"},
3.680 + {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"},
3.681 + {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"},
3.682 + {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
3.683 + {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"},
3.684 + {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
3.685 + {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"},
3.686 + {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"},
3.687 + {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
3.688 + {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
3.689 + {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
3.690 + {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"},
3.691 + {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"},
3.692 + {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
3.693 + {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"},
3.694 + {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
3.695 + {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"},
3.696 + {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"},
3.697 + {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"},
3.698 + {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"},
3.699 + {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
3.700 + {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
3.701 + {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
3.702 + {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"},
3.703 + {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"},
3.704 + {FPU_NEON_EXT_V1, 0xf2a00810, 0xfea00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
3.705 + {FPU_NEON_EXT_V1, 0xf2a00850, 0xfea00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"},
3.706 + {FPU_NEON_EXT_V1, 0xf2a00910, 0xfea00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
3.707 + {FPU_NEON_EXT_V1, 0xf2a00950, 0xfea00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"},
3.708 + {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
3.709 + {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"},
3.710 + {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"},
3.711 + {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"},
3.712 + {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
3.713 + {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
3.714 + {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
3.715 + {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"},
3.716 + {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"},
3.717 + {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
3.718 + {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"},
3.719 + {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"},
3.720 + {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"},
3.721 + {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
3.722 + {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
3.723 + {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
3.724 + {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"},
3.725 + {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"},
3.726 + {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"},
3.727 +
3.728 + /* Three registers of different lengths. */
3.729 + {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.730 + {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
3.731 + {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
3.732 + {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.733 + {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.734 + {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.735 + {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
3.736 + {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"},
3.737 + {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.738 + {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
3.739 + {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.740 + {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"},
3.741 + {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.742 + {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.743 + {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.744 + {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.745 + {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"},
3.746 +
3.747 + /* Two registers and a scalar. */
3.748 + {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
3.749 + {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
3.750 + {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
3.751 + {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
3.752 + {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"},
3.753 + {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
3.754 + {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"},
3.755 + {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"},
3.756 + {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
3.757 + {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
3.758 + {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"},
3.759 + {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
3.760 + {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
3.761 + {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
3.762 + {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
3.763 + {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
3.764 + {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"},
3.765 + {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
3.766 + {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"},
3.767 + {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
3.768 + {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
3.769 + {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"},
3.770 +
3.771 + /* Element and structure load/store. */
3.772 + {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"},
3.773 + {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"},
3.774 + {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"},
3.775 + {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"},
3.776 + {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"},
3.777 + {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
3.778 + {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
3.779 + {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
3.780 + {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"},
3.781 + {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
3.782 + {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
3.783 + {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
3.784 + {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"},
3.785 + {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"},
3.786 + {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"},
3.787 + {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"},
3.788 + {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"},
3.789 + {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"},
3.790 + {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"},
3.791 +
3.792 + {0,0 ,0, 0}
3.793 +};
3.794 +
3.795 +/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
3.796 + ordered: they must be searched linearly from the top to obtain a correct
3.797 + match. */
3.798 +
3.799 +/* print_insn_arm recognizes the following format control codes:
3.800 +
3.801 + %% %
3.802 +
3.803 + %a print address for ldr/str instruction
3.804 + %s print address for ldr/str halfword/signextend instruction
3.805 + %S like %s but allow UNPREDICTABLE addressing
3.806 + %b print branch destination
3.807 + %c print condition code (always bits 28-31)
3.808 + %m print register mask for ldm/stm instruction
3.809 + %o print operand2 (immediate or register + shift)
3.810 + %p print 'p' iff bits 12-15 are 15
3.811 + %t print 't' iff bit 21 set and bit 24 clear
3.812 + %B print arm BLX(1) destination
3.813 + %C print the PSR sub type.
3.814 + %U print barrier type.
3.815 + %P print address for pli instruction.
3.816 +
3.817 + %<bitfield>r print as an ARM register
3.818 + %<bitfield>R as %r but r15 is UNPREDICTABLE
3.819 + %<bitfield>{r|R}u as %{r|R} but if matches the other %u field then is UNPREDICTABLE
3.820 + %<bitfield>{r|R}U as %{r|R} but if matches the other %U field then is UNPREDICTABLE
3.821 + %<bitfield>d print the bitfield in decimal
3.822 + %<bitfield>W print the bitfield plus one in decimal
3.823 + %<bitfield>x print the bitfield in hex
3.824 + %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
3.825 +
3.826 + %<bitfield>'c print specified char iff bitfield is all ones
3.827 + %<bitfield>`c print specified char iff bitfield is all zeroes
3.828 + %<bitfield>?ab... select from array of values in big endian order
3.829 +
3.830 + %e print arm SMI operand (bits 0..7,8..19).
3.831 + %E print the LSB and WIDTH fields of a BFI or BFC instruction.
3.832 + %V print the 16-bit immediate field of a MOVT or MOVW instruction.
3.833 + %R print the SPSR/CPSR or banked register of an MRS. */
3.834 +
3.835 +static const struct opcode32 arm_opcodes[] =
3.836 +{
3.837 + /* ARM instructions. */
3.838 + {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t; (mov r0, r0)"},
3.839 + {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"},
3.840 + {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19R, %0-3R, %8-11R"},
3.841 + {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.842 + {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15RU, %0-3Ru, [%16-19RuU]"},
3.843 + {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3.844 + {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3.845 +
3.846 + /* Virtualization Extension instructions. */
3.847 + {ARM_EXT_VIRT, 0x0160006e, 0x0fffffff, "eret%c"},
3.848 + {ARM_EXT_VIRT, 0x01400070, 0x0ff000f0, "hvc%c\t%e"},
3.849 +
3.850 + /* Integer Divide Extension instructions. */
3.851 + {ARM_EXT_ADIV, 0x0710f010, 0x0ff0f0f0, "sdiv%c\t%16-19r, %0-3r, %8-11r"},
3.852 + {ARM_EXT_ADIV, 0x0730f010, 0x0ff0f0f0, "udiv%c\t%16-19r, %0-3r, %8-11r"},
3.853 +
3.854 + /* MP Extension instructions. */
3.855 + {ARM_EXT_MP, 0xf410f000, 0xfc70f000, "pldw\t%a"},
3.856 +
3.857 + /* V7 instructions. */
3.858 + {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"},
3.859 + {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"},
3.860 + {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"},
3.861 + {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"},
3.862 + {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"},
3.863 +
3.864 + /* ARM V6T2 instructions. */
3.865 + {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15R, %E"},
3.866 + {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15R, %0-3r, %E"},
3.867 + {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.868 + {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15R, %S"},
3.869 +
3.870 + {ARM_EXT_V6T2, 0x00300090, 0x0f3000f0, UNDEFINED_INSTRUCTION },
3.871 + {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"},
3.872 +
3.873 + {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"},
3.874 + {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"},
3.875 + {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"},
3.876 + {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"},
3.877 +
3.878 + /* ARM Security extension instructions. */
3.879 + {ARM_EXT_SEC, 0x01600070, 0x0ff000f0, "smc%c\t%e"},
3.880 +
3.881 + /* ARM V6K instructions. */
3.882 + {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"},
3.883 + {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15R, [%16-19R]"},
3.884 + {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19R]"},
3.885 + {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15R, [%16-19R]"},
3.886 + {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15R, %0-3R, [%16-19R]"},
3.887 + {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15R, %0-3r, [%16-19R]"},
3.888 + {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15R, %0-3R, [%16-19R]"},
3.889 +
3.890 + /* ARM V6K NOP hints. */
3.891 + {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"},
3.892 + {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"},
3.893 + {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"},
3.894 + {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"},
3.895 + {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"},
3.896 +
3.897 + /* ARM V6 instructions. */
3.898 + {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"},
3.899 + {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"},
3.900 + {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"},
3.901 + {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"},
3.902 + {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"},
3.903 + {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15R, %16-19R, %0-3R"},
3.904 + {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15R, %16-19R, %0-3R, lsl #%7-11d"},
3.905 + {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #32"},
3.906 + {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15R, %16-19R, %0-3R, asr #%7-11d"},
3.907 + {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19R]"},
3.908 + {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15R, %16-19R, %0-3R"},
3.909 + {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15R, %16-19R, %0-3R"},
3.910 + {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qasx%c\t%12-15R, %16-19R, %0-3R"},
3.911 + {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15R, %16-19R, %0-3R"},
3.912 + {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15R, %16-19R, %0-3R"},
3.913 + {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsax%c\t%12-15R, %16-19R, %0-3R"},
3.914 + {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15R, %16-19R, %0-3R"},
3.915 + {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15R, %16-19R, %0-3R"},
3.916 + {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "sasx%c\t%12-15R, %16-19R, %0-3R"},
3.917 + {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15R, %16-19R, %0-3R"},
3.918 + {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15R, %16-19R, %0-3R"},
3.919 + {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shasx%c\t%12-15R, %16-19R, %0-3R"},
3.920 + {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15R, %16-19R, %0-3R"},
3.921 + {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15R, %16-19R, %0-3R"},
3.922 + {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsax%c\t%12-15R, %16-19R, %0-3R"},
3.923 + {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15R, %16-19R, %0-3R"},
3.924 + {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15R, %16-19R, %0-3R"},
3.925 + {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssax%c\t%12-15R, %16-19R, %0-3R"},
3.926 + {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15R, %16-19R, %0-3R"},
3.927 + {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15R, %16-19R, %0-3R"},
3.928 + {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uasx%c\t%12-15R, %16-19R, %0-3R"},
3.929 + {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15R, %16-19R, %0-3R"},
3.930 + {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15R, %16-19R, %0-3R"},
3.931 + {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhasx%c\t%12-15R, %16-19R, %0-3R"},
3.932 + {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15R, %16-19R, %0-3R"},
3.933 + {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15R, %16-19R, %0-3R"},
3.934 + {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsax%c\t%12-15R, %16-19R, %0-3R"},
3.935 + {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15R, %16-19R, %0-3R"},
3.936 + {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15R, %16-19R, %0-3R"},
3.937 + {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqasx%c\t%12-15R, %16-19R, %0-3R"},
3.938 + {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15R, %16-19R, %0-3R"},
3.939 + {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15R, %16-19R, %0-3R"},
3.940 + {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsax%c\t%12-15R, %16-19R, %0-3R"},
3.941 + {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15R, %16-19R, %0-3R"},
3.942 + {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15R, %16-19R, %0-3R"},
3.943 + {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usax%c\t%12-15R, %16-19R, %0-3R"},
3.944 + {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t%12-15R, %0-3R"},
3.945 + {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t%12-15R, %0-3R"},
3.946 + {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t%12-15R, %0-3R"},
3.947 + {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t%16-19r%21'!"},
3.948 + {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R"},
3.949 + {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #8"},
3.950 + {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #16"},
3.951 + {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15R, %0-3R, ror #24"},
3.952 + {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R"},
3.953 + {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #8"},
3.954 + {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #16"},
3.955 + {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15R, %0-3R, ror #24"},
3.956 + {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R"},
3.957 + {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #8"},
3.958 + {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #16"},
3.959 + {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15R, %0-3R, ror #24"},
3.960 + {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R"},
3.961 + {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #8"},
3.962 + {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #16"},
3.963 + {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15R, %0-3R, ror #24"},
3.964 + {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R"},
3.965 + {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #8"},
3.966 + {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #16"},
3.967 + {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15R, %0-3R, ror #24"},
3.968 + {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R"},
3.969 + {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #8"},
3.970 + {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #16"},
3.971 + {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15R, %0-3R, ror #24"},
3.972 + {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R"},
3.973 + {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3.974 + {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3.975 + {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3.976 + {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R"},
3.977 + {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3.978 + {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3.979 + {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3.980 + {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R"},
3.981 + {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3.982 + {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3.983 + {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3.984 + {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R"},
3.985 + {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3.986 + {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3.987 + {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3.988 + {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R"},
3.989 + {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3.990 + {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3.991 + {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15R, %16-19r, %0-3R, ROR #24"},
3.992 + {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R"},
3.993 + {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #8"},
3.994 + {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #16"},
3.995 + {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15R, %16-19r, %0-3R, ror #24"},
3.996 + {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15R, %16-19R, %0-3R"},
3.997 + {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"},
3.998 + {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19R, %0-3R, %8-11R"},
3.999 + {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19R, %0-3R, %8-11R"},
3.1000 + {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1001 + {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3.1002 + {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1003 + {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3.1004 + {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19R, %0-3R, %8-11R"},
3.1005 + {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1006 + {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1007 + {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"},
3.1008 + {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15R, #%16-20W, %0-3R"},
3.1009 + {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, lsl #%7-11d"},
3.1010 + {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15R, #%16-20W, %0-3R, asr #%7-11d"},
3.1011 + {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"},
3.1012 + {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15R, %0-3R, [%16-19R]"},
3.1013 + {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15R, %16-19R, %0-3R, %8-11R"},
3.1014 + {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19R, %0-3R, %8-11R"},
3.1015 + {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1016 + {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15R, #%16-20d, %0-3R"},
3.1017 + {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, lsl #%7-11d"},
3.1018 + {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15R, #%16-20d, %0-3R, asr #%7-11d"},
3.1019 + {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15R, #%16-19d, %0-3R"},
3.1020 +
3.1021 + /* V5J instruction. */
3.1022 + {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3R"},
3.1023 +
3.1024 + /* V5 Instructions. */
3.1025 + {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"},
3.1026 + {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"},
3.1027 + {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3R"},
3.1028 + {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15R, %0-3R"},
3.1029 +
3.1030 + /* V5E "El Segundo" Instructions. */
3.1031 + {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"},
3.1032 + {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"},
3.1033 + {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"},
3.1034 + {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1035 + {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1036 + {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1037 + {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11R, %12-15R"},
3.1038 +
3.1039 + {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19R, %0-3R, %8-11R, %12-15R"},
3.1040 + {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19R, %0-3r, %8-11R, %12-15R"},
3.1041 +
3.1042 + {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3.1043 + {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3.1044 + {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3.1045 + {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15Ru, %16-19Ru, %0-3R, %8-11R"},
3.1046 +
3.1047 + {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19R, %0-3R, %8-11R"},
3.1048 + {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19R, %0-3R, %8-11R"},
3.1049 + {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19R, %0-3R, %8-11R"},
3.1050 + {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19R, %0-3R, %8-11R"},
3.1051 +
3.1052 + {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19R, %0-3R, %8-11R"},
3.1053 + {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19R, %0-3R, %8-11R"},
3.1054 +
3.1055 + {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15R, %0-3R, %16-19R"},
3.1056 + {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15R, %0-3R, %16-19R"},
3.1057 + {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15R, %0-3R, %16-19R"},
3.1058 + {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15R, %0-3R, %16-19R"},
3.1059 +
3.1060 + /* ARM Instructions. */
3.1061 + {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"},
3.1062 +
3.1063 + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%t%c\t%12-15R, %a"},
3.1064 + {ARM_EXT_V1, 0x04000000, 0x0e500000, "str%t%c\t%12-15r, %a"},
3.1065 + {ARM_EXT_V1, 0x06400000, 0x0e500ff0, "strb%t%c\t%12-15R, %a"},
3.1066 + {ARM_EXT_V1, 0x06000000, 0x0e500ff0, "str%t%c\t%12-15r, %a"},
3.1067 + {ARM_EXT_V1, 0x04400000, 0x0c500010, "strb%t%c\t%12-15R, %a"},
3.1068 + {ARM_EXT_V1, 0x04000000, 0x0c500010, "str%t%c\t%12-15r, %a"},
3.1069 +
3.1070 + {ARM_EXT_V1, 0x04400000, 0x0e500000, "strb%c\t%12-15R, %a"},
3.1071 + {ARM_EXT_V1, 0x06400000, 0x0e500010, "strb%c\t%12-15R, %a"},
3.1072 + {ARM_EXT_V1, 0x004000b0, 0x0e5000f0, "strh%c\t%12-15R, %s"},
3.1073 + {ARM_EXT_V1, 0x000000b0, 0x0e500ff0, "strh%c\t%12-15R, %s"},
3.1074 +
3.1075 + {ARM_EXT_V1, 0x00500090, 0x0e5000f0, UNDEFINED_INSTRUCTION},
3.1076 + {ARM_EXT_V1, 0x00500090, 0x0e500090, "ldr%6's%5?hb%c\t%12-15R, %s"},
3.1077 + {ARM_EXT_V1, 0x00100090, 0x0e500ff0, UNDEFINED_INSTRUCTION},
3.1078 + {ARM_EXT_V1, 0x00100090, 0x0e500f90, "ldr%6's%5?hb%c\t%12-15R, %s"},
3.1079 +
3.1080 + {ARM_EXT_V1, 0x02000000, 0x0fe00000, "and%20's%c\t%12-15r, %16-19r, %o"},
3.1081 + {ARM_EXT_V1, 0x00000000, 0x0fe00010, "and%20's%c\t%12-15r, %16-19r, %o"},
3.1082 + {ARM_EXT_V1, 0x00000010, 0x0fe00090, "and%20's%c\t%12-15R, %16-19R, %o"},
3.1083 +
3.1084 + {ARM_EXT_V1, 0x02200000, 0x0fe00000, "eor%20's%c\t%12-15r, %16-19r, %o"},
3.1085 + {ARM_EXT_V1, 0x00200000, 0x0fe00010, "eor%20's%c\t%12-15r, %16-19r, %o"},
3.1086 + {ARM_EXT_V1, 0x00200010, 0x0fe00090, "eor%20's%c\t%12-15R, %16-19R, %o"},
3.1087 +
3.1088 + {ARM_EXT_V1, 0x02400000, 0x0fe00000, "sub%20's%c\t%12-15r, %16-19r, %o"},
3.1089 + {ARM_EXT_V1, 0x00400000, 0x0fe00010, "sub%20's%c\t%12-15r, %16-19r, %o"},
3.1090 + {ARM_EXT_V1, 0x00400010, 0x0fe00090, "sub%20's%c\t%12-15R, %16-19R, %o"},
3.1091 +
3.1092 + {ARM_EXT_V1, 0x02600000, 0x0fe00000, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3.1093 + {ARM_EXT_V1, 0x00600000, 0x0fe00010, "rsb%20's%c\t%12-15r, %16-19r, %o"},
3.1094 + {ARM_EXT_V1, 0x00600010, 0x0fe00090, "rsb%20's%c\t%12-15R, %16-19R, %o"},
3.1095 +
3.1096 + {ARM_EXT_V1, 0x02800000, 0x0fe00000, "add%20's%c\t%12-15r, %16-19r, %o"},
3.1097 + {ARM_EXT_V1, 0x00800000, 0x0fe00010, "add%20's%c\t%12-15r, %16-19r, %o"},
3.1098 + {ARM_EXT_V1, 0x00800010, 0x0fe00090, "add%20's%c\t%12-15R, %16-19R, %o"},
3.1099 +
3.1100 + {ARM_EXT_V1, 0x02a00000, 0x0fe00000, "adc%20's%c\t%12-15r, %16-19r, %o"},
3.1101 + {ARM_EXT_V1, 0x00a00000, 0x0fe00010, "adc%20's%c\t%12-15r, %16-19r, %o"},
3.1102 + {ARM_EXT_V1, 0x00a00010, 0x0fe00090, "adc%20's%c\t%12-15R, %16-19R, %o"},
3.1103 +
3.1104 + {ARM_EXT_V1, 0x02c00000, 0x0fe00000, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3.1105 + {ARM_EXT_V1, 0x00c00000, 0x0fe00010, "sbc%20's%c\t%12-15r, %16-19r, %o"},
3.1106 + {ARM_EXT_V1, 0x00c00010, 0x0fe00090, "sbc%20's%c\t%12-15R, %16-19R, %o"},
3.1107 +
3.1108 + {ARM_EXT_V1, 0x02e00000, 0x0fe00000, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3.1109 + {ARM_EXT_V1, 0x00e00000, 0x0fe00010, "rsc%20's%c\t%12-15r, %16-19r, %o"},
3.1110 + {ARM_EXT_V1, 0x00e00010, 0x0fe00090, "rsc%20's%c\t%12-15R, %16-19R, %o"},
3.1111 +
3.1112 + {ARM_EXT_VIRT, 0x0120f200, 0x0fb0f200, "msr%c\t%C, %0-3r"},
3.1113 + {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%C, %o"},
3.1114 + {ARM_EXT_V3, 0x01000000, 0x0fb00cff, "mrs%c\t%12-15R, %R"},
3.1115 +
3.1116 + {ARM_EXT_V1, 0x03000000, 0x0fe00000, "tst%p%c\t%16-19r, %o"},
3.1117 + {ARM_EXT_V1, 0x01000000, 0x0fe00010, "tst%p%c\t%16-19r, %o"},
3.1118 + {ARM_EXT_V1, 0x01000010, 0x0fe00090, "tst%p%c\t%16-19R, %o"},
3.1119 +
3.1120 + {ARM_EXT_V1, 0x03200000, 0x0fe00000, "teq%p%c\t%16-19r, %o"},
3.1121 + {ARM_EXT_V1, 0x01200000, 0x0fe00010, "teq%p%c\t%16-19r, %o"},
3.1122 + {ARM_EXT_V1, 0x01200010, 0x0fe00090, "teq%p%c\t%16-19R, %o"},
3.1123 +
3.1124 + {ARM_EXT_V1, 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
3.1125 + {ARM_EXT_V1, 0x01400000, 0x0fe00010, "cmp%p%c\t%16-19r, %o"},
3.1126 + {ARM_EXT_V1, 0x01400010, 0x0fe00090, "cmp%p%c\t%16-19R, %o"},
3.1127 +
3.1128 + {ARM_EXT_V1, 0x03600000, 0x0fe00000, "cmn%p%c\t%16-19r, %o"},
3.1129 + {ARM_EXT_V1, 0x01600000, 0x0fe00010, "cmn%p%c\t%16-19r, %o"},
3.1130 + {ARM_EXT_V1, 0x01600010, 0x0fe00090, "cmn%p%c\t%16-19R, %o"},
3.1131 +
3.1132 + {ARM_EXT_V1, 0x03800000, 0x0fe00000, "orr%20's%c\t%12-15r, %16-19r, %o"},
3.1133 + {ARM_EXT_V1, 0x01800000, 0x0fe00010, "orr%20's%c\t%12-15r, %16-19r, %o"},
3.1134 + {ARM_EXT_V1, 0x01800010, 0x0fe00090, "orr%20's%c\t%12-15R, %16-19R, %o"},
3.1135 +
3.1136 + {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"},
3.1137 + {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"},
3.1138 + {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15R, %q"},
3.1139 + {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15R, %q"},
3.1140 + {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15R, %q"},
3.1141 + {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"},
3.1142 + {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15R, %q"},
3.1143 +
3.1144 + {ARM_EXT_V1, 0x03c00000, 0x0fe00000, "bic%20's%c\t%12-15r, %16-19r, %o"},
3.1145 + {ARM_EXT_V1, 0x01c00000, 0x0fe00010, "bic%20's%c\t%12-15r, %16-19r, %o"},
3.1146 + {ARM_EXT_V1, 0x01c00010, 0x0fe00090, "bic%20's%c\t%12-15R, %16-19R, %o"},
3.1147 +
3.1148 + {ARM_EXT_V1, 0x03e00000, 0x0fe00000, "mvn%20's%c\t%12-15r, %o"},
3.1149 + {ARM_EXT_V1, 0x01e00000, 0x0fe00010, "mvn%20's%c\t%12-15r, %o"},
3.1150 + {ARM_EXT_V1, 0x01e00010, 0x0fe00090, "mvn%20's%c\t%12-15R, %o"},
3.1151 +
3.1152 + {ARM_EXT_V1, 0x06000010, 0x0e000010, UNDEFINED_INSTRUCTION},
3.1153 + {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"},
3.1154 +
3.1155 + {ARM_EXT_V1, 0x04500000, 0x0c500000, "ldrb%t%c\t%12-15R, %a"},
3.1156 +
3.1157 + {ARM_EXT_V1, 0x04300000, 0x0d700000, "ldrt%c\t%12-15R, %a"},
3.1158 + {ARM_EXT_V1, 0x04100000, 0x0c500000, "ldr%c\t%12-15r, %a"},
3.1159 +
3.1160 + {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"},
3.1161 + {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19R%21'!, %m%22'^"},
3.1162 + {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3.1163 + {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"},
3.1164 + {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19R%21'!, %m%22'^"},
3.1165 + {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19R%21'!, %m%22'^"},
3.1166 + {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"},
3.1167 + {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"},
3.1168 +
3.1169 + /* The rest. */
3.1170 + {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3.1171 + {0, 0x00000000, 0x00000000, 0}
3.1172 +};
3.1173 +
3.1174 +/* print_insn_thumb16 recognizes the following format control codes:
3.1175 +
3.1176 + %S print Thumb register (bits 3..5 as high number if bit 6 set)
3.1177 + %D print Thumb register (bits 0..2 as high number if bit 7 set)
3.1178 + %<bitfield>I print bitfield as a signed decimal
3.1179 + (top bit of range being the sign bit)
3.1180 + %N print Thumb register mask (with LR)
3.1181 + %O print Thumb register mask (with PC)
3.1182 + %M print Thumb register mask
3.1183 + %b print CZB's 6-bit unsigned branch destination
3.1184 + %s print Thumb right-shift immediate (6..10; 0 == 32).
3.1185 + %c print the condition code
3.1186 + %C print the condition code, or "s" if not conditional
3.1187 + %x print warning if conditional an not at end of IT block"
3.1188 + %X print "\t; unpredictable <IT:code>" if conditional
3.1189 + %I print IT instruction suffix and operands
3.1190 + %W print Thumb Writeback indicator for LDMIA
3.1191 + %<bitfield>r print bitfield as an ARM register
3.1192 + %<bitfield>d print bitfield as a decimal
3.1193 + %<bitfield>H print (bitfield * 2) as a decimal
3.1194 + %<bitfield>W print (bitfield * 4) as a decimal
3.1195 + %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
3.1196 + %<bitfield>B print Thumb branch destination (signed displacement)
3.1197 + %<bitfield>c print bitfield as a condition code
3.1198 + %<bitnum>'c print specified char iff bit is one
3.1199 + %<bitnum>?ab print a if bit is one else print b. */
3.1200 +
3.1201 +static const struct opcode16 thumb_opcodes[] =
3.1202 +{
3.1203 + /* Thumb instructions. */
3.1204 +
3.1205 + /* ARM V6K no-argument instructions. */
3.1206 + {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"},
3.1207 + {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"},
3.1208 + {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"},
3.1209 + {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"},
3.1210 + {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"},
3.1211 + {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"},
3.1212 +
3.1213 + /* ARM V6T2 instructions. */
3.1214 + {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"},
3.1215 + {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"},
3.1216 + {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"},
3.1217 +
3.1218 + /* ARM V6. */
3.1219 + {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"},
3.1220 + {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"},
3.1221 + {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"},
3.1222 + {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"},
3.1223 + {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"},
3.1224 + {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"},
3.1225 + {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"},
3.1226 + {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"},
3.1227 + {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"},
3.1228 + {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"},
3.1229 + {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"},
3.1230 +
3.1231 + /* ARM V5 ISA extends Thumb. */
3.1232 + {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */
3.1233 + /* This is BLX(2). BLX(1) is a 32-bit instruction. */
3.1234 + {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */
3.1235 + /* ARM V4T ISA (Thumb v1). */
3.1236 + {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t; (mov r8, r8)"},
3.1237 + /* Format 4. */
3.1238 + {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"},
3.1239 + {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"},
3.1240 + {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"},
3.1241 + {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"},
3.1242 + {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"},
3.1243 + {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"},
3.1244 + {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"},
3.1245 + {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"},
3.1246 + {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"},
3.1247 + {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"},
3.1248 + {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"},
3.1249 + {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"},
3.1250 + {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"},
3.1251 + {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"},
3.1252 + {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"},
3.1253 + {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"},
3.1254 + /* format 13 */
3.1255 + {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"},
3.1256 + {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"},
3.1257 + /* format 5 */
3.1258 + {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"},
3.1259 + {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"},
3.1260 + {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"},
3.1261 + {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"},
3.1262 + /* format 14 */
3.1263 + {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"},
3.1264 + {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"},
3.1265 + /* format 2 */
3.1266 + {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"},
3.1267 + {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"},
3.1268 + {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"},
3.1269 + {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"},
3.1270 + /* format 8 */
3.1271 + {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"},
3.1272 + {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"},
3.1273 + {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"},
3.1274 + /* format 7 */
3.1275 + {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3.1276 + {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"},
3.1277 + /* format 1 */
3.1278 + {ARM_EXT_V4T, 0x0000, 0xFFC0, "mov%C\t%0-2r, %3-5r"},
3.1279 + {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"},
3.1280 + {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"},
3.1281 + {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"},
3.1282 + /* format 3 */
3.1283 + {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"},
3.1284 + {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"},
3.1285 + {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"},
3.1286 + {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"},
3.1287 + /* format 6 */
3.1288 + {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t; (%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */
3.1289 + /* format 9 */
3.1290 + {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"},
3.1291 + {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"},
3.1292 + {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"},
3.1293 + {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"},
3.1294 + /* format 10 */
3.1295 + {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"},
3.1296 + {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"},
3.1297 + /* format 11 */
3.1298 + {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"},
3.1299 + {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"},
3.1300 + /* format 12 */
3.1301 + {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t; (adr %8-10r, %0-7a)"},
3.1302 + {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"},
3.1303 + /* format 15 */
3.1304 + {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"},
3.1305 + {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r%W, %M"},
3.1306 + /* format 17 */
3.1307 + {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"},
3.1308 + /* format 16 */
3.1309 + {ARM_EXT_V4T, 0xDE00, 0xFE00, UNDEFINED_INSTRUCTION},
3.1310 + {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"},
3.1311 + /* format 18 */
3.1312 + {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"},
3.1313 +
3.1314 + /* The E800 .. FFFF range is unconditionally redirected to the
3.1315 + 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
3.1316 + are processed via that table. Thus, we can never encounter a
3.1317 + bare "second half of BL/BLX(1)" instruction here. */
3.1318 + {ARM_EXT_V1, 0x0000, 0x0000, UNDEFINED_INSTRUCTION},
3.1319 + {0, 0, 0, 0}
3.1320 +};
3.1321 +
3.1322 +/* Thumb32 opcodes use the same table structure as the ARM opcodes.
3.1323 + We adopt the convention that hw1 is the high 16 bits of .value and
3.1324 + .mask, hw2 the low 16 bits.
3.1325 +
3.1326 + print_insn_thumb32 recognizes the following format control codes:
3.1327 +
3.1328 + %% %
3.1329 +
3.1330 + %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
3.1331 + %M print a modified 12-bit immediate (same location)
3.1332 + %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
3.1333 + %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
3.1334 + %H print a 16-bit immediate from hw2[3:0],hw1[11:0]
3.1335 + %S print a possibly-shifted Rm
3.1336 +
3.1337 + %L print address for a ldrd/strd instruction
3.1338 + %a print the address of a plain load/store
3.1339 + %w print the width and signedness of a core load/store
3.1340 + %m print register mask for ldm/stm
3.1341 +
3.1342 + %E print the lsb and width fields of a bfc/bfi instruction
3.1343 + %F print the lsb and width fields of a sbfx/ubfx instruction
3.1344 + %b print a conditional branch offset
3.1345 + %B print an unconditional branch offset
3.1346 + %s print the shift field of an SSAT instruction
3.1347 + %R print the rotation field of an SXT instruction
3.1348 + %U print barrier type.
3.1349 + %P print address for pli instruction.
3.1350 + %c print the condition code
3.1351 + %x print warning if conditional an not at end of IT block"
3.1352 + %X print "\t; unpredictable <IT:code>" if conditional
3.1353 +
3.1354 + %<bitfield>d print bitfield in decimal
3.1355 + %<bitfield>W print bitfield*4 in decimal
3.1356 + %<bitfield>r print bitfield as an ARM register
3.1357 + %<bitfield>R as %<>r bit r15 is UNPREDICTABLE
3.1358 + %<bitfield>c print bitfield as a condition code
3.1359 +
3.1360 + %<bitfield>'c print specified char iff bitfield is all ones
3.1361 + %<bitfield>`c print specified char iff bitfield is all zeroes
3.1362 + %<bitfield>?ab... select from array of values in big endian order
3.1363 +
3.1364 + With one exception at the bottom (done because BL and BLX(1) need
3.1365 + to come dead last), this table was machine-sorted first in
3.1366 + decreasing order of number of bits set in the mask, then in
3.1367 + increasing numeric order of mask, then in increasing numeric order
3.1368 + of opcode. This order is not the clearest for a human reader, but
3.1369 + is guaranteed never to catch a special-case bit pattern with a more
3.1370 + general mask, which is important, because this instruction encoding
3.1371 + makes heavy use of special-case bit patterns. */
3.1372 +static const struct opcode32 thumb32_opcodes[] =
3.1373 +{
3.1374 + /* V7 instructions. */
3.1375 + {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"},
3.1376 + {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"},
3.1377 + {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"},
3.1378 + {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"},
3.1379 + {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"},
3.1380 + {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"},
3.1381 + {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"},
3.1382 +
3.1383 + /* Virtualization Extension instructions. */
3.1384 + {ARM_EXT_VIRT, 0xf7e08000, 0xfff0f000, "hvc%c\t%V"},
3.1385 + /* We skip ERET as that is SUBS pc, lr, #0. */
3.1386 +
3.1387 + /* MP Extension instructions. */
3.1388 + {ARM_EXT_MP, 0xf830f000, 0xff70f000, "pldw%c\t%a"},
3.1389 +
3.1390 + /* Security extension instructions. */
3.1391 + {ARM_EXT_SEC, 0xf7f08000, 0xfff0f000, "smc%c\t%K"},
3.1392 +
3.1393 + /* Instructions defined in the basic V6T2 set. */
3.1394 + {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"},
3.1395 + {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"},
3.1396 + {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"},
3.1397 + {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"},
3.1398 + {ARM_EXT_V6T2, 0xf3af8004, 0xffffffff, "sev%c.w"},
3.1399 + {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"},
3.1400 +
3.1401 + {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"},
3.1402 + {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"},
3.1403 + {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"},
3.1404 + {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"},
3.1405 + {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"},
3.1406 + {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"},
3.1407 + {ARM_EXT_V6T2, 0xf3e08000, 0xffe0f000, "mrs%c\t%8-11r, %D"},
3.1408 + {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"},
3.1409 + {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"},
3.1410 + {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"},
3.1411 + {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"},
3.1412 + {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"},
3.1413 + {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"},
3.1414 + {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"},
3.1415 + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"},
3.1416 + {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"},
3.1417 + {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"},
3.1418 + {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"},
3.1419 + {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"},
3.1420 + {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"},
3.1421 + {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"},
3.1422 + {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"},
3.1423 + {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"},
3.1424 + {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"},
3.1425 + {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"},
3.1426 + {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"},
3.1427 + {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"},
3.1428 + {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"},
3.1429 + {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"},
3.1430 + {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"},
3.1431 + {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"},
3.1432 + {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"},
3.1433 + {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"},
3.1434 + {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"},
3.1435 + {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"},
3.1436 + {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"},
3.1437 + {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"},
3.1438 + {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"},
3.1439 + {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"},
3.1440 + {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"},
3.1441 + {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"},
3.1442 + {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"},
3.1443 + {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"},
3.1444 + {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"},
3.1445 + {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"},
3.1446 + {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"},
3.1447 + {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "sasx%c\t%8-11r, %16-19r, %0-3r"},
3.1448 + {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qasx%c\t%8-11r, %16-19r, %0-3r"},
3.1449 + {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shasx%c\t%8-11r, %16-19r, %0-3r"},
3.1450 + {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uasx%c\t%8-11r, %16-19r, %0-3r"},
3.1451 + {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqasx%c\t%8-11r, %16-19r, %0-3r"},
3.1452 + {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhasx%c\t%8-11r, %16-19r, %0-3r"},
3.1453 + {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"},
3.1454 + {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"},
3.1455 + {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"},
3.1456 + {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"},
3.1457 + {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"},
3.1458 + {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"},
3.1459 + {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"},
3.1460 + {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"},
3.1461 + {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"},
3.1462 + {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"},
3.1463 + {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"},
3.1464 + {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"},
3.1465 + {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"},
3.1466 + {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"},
3.1467 + {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssax%c\t%8-11r, %16-19r, %0-3r"},
3.1468 + {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsax%c\t%8-11r, %16-19r, %0-3r"},
3.1469 + {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsax%c\t%8-11r, %16-19r, %0-3r"},
3.1470 + {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usax%c\t%8-11r, %16-19r, %0-3r"},
3.1471 + {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsax%c\t%8-11r, %16-19r, %0-3r"},
3.1472 + {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsax%c\t%8-11r, %16-19r, %0-3r"},
3.1473 + {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"},
3.1474 + {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"},
3.1475 + {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3.1476 + {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3.1477 + {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"},
3.1478 + {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"},
3.1479 + {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"},
3.1480 + {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"},
3.1481 + {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"},
3.1482 + {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"},
3.1483 + {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3.1484 + {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"},
3.1485 + {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"},
3.1486 + {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3.1487 + {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"},
3.1488 + {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3.1489 + {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"},
3.1490 + {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3.1491 + {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"},
3.1492 + {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"},
3.1493 + {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"},
3.1494 + {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"},
3.1495 + {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"},
3.1496 + {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"},
3.1497 + {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"},
3.1498 + {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"},
3.1499 + {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"},
3.1500 + {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"},
3.1501 + {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"},
3.1502 + {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"},
3.1503 + {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"},
3.1504 + {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"},
3.1505 + {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3.1506 + {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3.1507 + {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3.1508 + {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3.1509 + {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3.1510 + {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3.1511 + {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3.1512 + {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3.1513 + {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"},
3.1514 + {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"},
3.1515 + {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"},
3.1516 + {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"},
3.1517 + {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3.1518 + {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3.1519 + {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3.1520 + {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3.1521 + {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11R, %16-19R, %0-3R, %12-15R"},
3.1522 + {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3.1523 + {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15R, %8-11R, %16-19R, %0-3R"},
3.1524 + {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"},
3.1525 + {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"},
3.1526 + {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"},
3.1527 + {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"},
3.1528 + {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"},
3.1529 + {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"},
3.1530 + {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"},
3.1531 + {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"},
3.1532 + {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"},
3.1533 + {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"},
3.1534 + {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"},
3.1535 + {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"},
3.1536 + {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"},
3.1537 + {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"},
3.1538 + {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"},
3.1539 + {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"},
3.1540 + {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"},
3.1541 + {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"},
3.1542 + {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"},
3.1543 + {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"},
3.1544 + {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"},
3.1545 + {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"},
3.1546 + {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"},
3.1547 + {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"},
3.1548 + {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"},
3.1549 + {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"},
3.1550 + {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"},
3.1551 + {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"},
3.1552 + {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"},
3.1553 + {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"},
3.1554 + {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"},
3.1555 + {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"},
3.1556 + {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"},
3.1557 + {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"},
3.1558 + {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"},
3.1559 + {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"},
3.1560 + {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"},
3.1561 + {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"},
3.1562 + {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"},
3.1563 + {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"},
3.1564 + {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"},
3.1565 + {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"},
3.1566 + {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3.1567 + {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!%L"},
3.1568 + {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3.1569 + {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W%L"},
3.1570 + {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"},
3.1571 + {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"},
3.1572 +
3.1573 + /* Filter out Bcc with cond=E or F, which are used for other instructions. */
3.1574 + {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"},
3.1575 + {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"},
3.1576 + {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"},
3.1577 + {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"},
3.1578 +
3.1579 + /* These have been 32-bit since the invention of Thumb. */
3.1580 + {ARM_EXT_V4T, 0xf000c000, 0xf800d001, "blx%c\t%B%x"},
3.1581 + {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"},
3.1582 +
3.1583 + /* Fallback. */
3.1584 + {ARM_EXT_V1, 0x00000000, 0x00000000, UNDEFINED_INSTRUCTION},
3.1585 + {0, 0, 0, 0}
3.1586 +};
3.1587 +
3.1588 +static const char *const arm_conditional[] =
3.1589 +{"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc",
3.1590 + "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""};
3.1591 +
3.1592 +static const char *const arm_fp_const[] =
3.1593 +{"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"};
3.1594 +
3.1595 +static const char *const arm_shift[] =
3.1596 +{"lsl", "lsr", "asr", "ror"};
3.1597 +
3.1598 +typedef struct
3.1599 +{
3.1600 + const char *name;
3.1601 + const char *description;
3.1602 + const char *reg_names[16];
3.1603 +}
3.1604 +arm_regname;
3.1605 +
3.1606 +static const arm_regname regnames[] =
3.1607 +{
3.1608 + { "raw" , "Select raw register names",
3.1609 + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
3.1610 + { "gcc", "Select register names used by GCC",
3.1611 + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
3.1612 + { "std", "Select register names used in ARM's ISA documentation",
3.1613 + { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
3.1614 + { "apcs", "Select register names used in the APCS",
3.1615 + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
3.1616 + { "atpcs", "Select register names used in the ATPCS",
3.1617 + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
3.1618 + { "special-atpcs", "Select special register names used in the ATPCS",
3.1619 + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
3.1620 +};
3.1621 +
3.1622 +static const char *const iwmmxt_wwnames[] =
3.1623 +{"b", "h", "w", "d"};
3.1624 +
3.1625 +static const char *const iwmmxt_wwssnames[] =
3.1626 +{"b", "bus", "bc", "bss",
3.1627 + "h", "hus", "hc", "hss",
3.1628 + "w", "wus", "wc", "wss",
3.1629 + "d", "dus", "dc", "dss"
3.1630 +};
3.1631 +
3.1632 +static const char *const iwmmxt_regnames[] =
3.1633 +{ "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7",
3.1634 + "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"
3.1635 +};
3.1636 +
3.1637 +static const char *const iwmmxt_cregnames[] =
3.1638 +{ "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved",
3.1639 + "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"
3.1640 +};
3.1641 +
3.1642 +/* Default to GCC register name set. */
3.1643 +static unsigned int regname_selected = 1;
3.1644 +
3.1645 +#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
3.1646 +#define arm_regnames regnames[regname_selected].reg_names
3.1647 +
3.1648 +static bfd_boolean force_thumb = FALSE;
3.1649 +
3.1650 +/* Current IT instruction state. This contains the same state as the IT
3.1651 + bits in the CPSR. */
3.1652 +static unsigned int ifthen_state;
3.1653 +/* IT state for the next instruction. */
3.1654 +static unsigned int ifthen_next_state;
3.1655 +/* The address of the insn for which the IT state is valid. */
3.1656 +static bfd_vma ifthen_address;
3.1657 +#define IFTHEN_COND ((ifthen_state >> 4) & 0xf)
3.1658 +
3.1659 +
3.1660 +/* Functions. */
3.1661 +int
3.1662 +get_arm_regname_num_options (void)
3.1663 +{
3.1664 + return NUM_ARM_REGNAMES;
3.1665 +}
3.1666 +
3.1667 +int
3.1668 +set_arm_regname_option (int option)
3.1669 +{
3.1670 + int old = regname_selected;
3.1671 + regname_selected = option;
3.1672 + return old;
3.1673 +}
3.1674 +
3.1675 +int
3.1676 +get_arm_regnames (int option,
3.1677 + const char **setname,
3.1678 + const char **setdescription,
3.1679 + const char *const **register_names)
3.1680 +{
3.1681 + *setname = regnames[option].name;
3.1682 + *setdescription = regnames[option].description;
3.1683 + *register_names = regnames[option].reg_names;
3.1684 + return 16;
3.1685 +}
3.1686 +
3.1687 +/* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
3.1688 + Returns pointer to following character of the format string and
3.1689 + fills in *VALUEP and *WIDTHP with the extracted value and number of
3.1690 + bits extracted. WIDTHP can be NULL. */
3.1691 +
3.1692 +static const char *
3.1693 +arm_decode_bitfield (const char *ptr,
3.1694 + unsigned long insn,
3.1695 + unsigned long *valuep,
3.1696 + int *widthp)
3.1697 +{
3.1698 + unsigned long value = 0;
3.1699 + int width = 0;
3.1700 +
3.1701 + do
3.1702 + {
3.1703 + int start, end;
3.1704 + int bits;
3.1705 +
3.1706 + for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++)
3.1707 + start = start * 10 + *ptr - '0';
3.1708 + if (*ptr == '-')
3.1709 + for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++)
3.1710 + end = end * 10 + *ptr - '0';
3.1711 + else
3.1712 + end = start;
3.1713 + bits = end - start;
3.1714 + if (bits < 0)
3.1715 + abort ();
3.1716 + value |= ((insn >> start) & ((2ul << bits) - 1)) << width;
3.1717 + width += bits + 1;
3.1718 + }
3.1719 + while (*ptr++ == ',');
3.1720 + *valuep = value;
3.1721 + if (widthp)
3.1722 + *widthp = width;
3.1723 + return ptr - 1;
3.1724 +}
3.1725 +
3.1726 +static void
3.1727 +arm_decode_shift (long given, fprintf_ftype func, void *stream,
3.1728 + bfd_boolean print_shift)
3.1729 +{
3.1730 + func (stream, "%s", arm_regnames[given & 0xf]);
3.1731 +
3.1732 + if ((given & 0xff0) != 0)
3.1733 + {
3.1734 + if ((given & 0x10) == 0)
3.1735 + {
3.1736 + int amount = (given & 0xf80) >> 7;
3.1737 + int shift = (given & 0x60) >> 5;
3.1738 +
3.1739 + if (amount == 0)
3.1740 + {
3.1741 + if (shift == 3)
3.1742 + {
3.1743 + func (stream, ", rrx");
3.1744 + return;
3.1745 + }
3.1746 +
3.1747 + amount = 32;
3.1748 + }
3.1749 +
3.1750 + if (print_shift)
3.1751 + func (stream, ", %s #%d", arm_shift[shift], amount);
3.1752 + else
3.1753 + func (stream, ", #%d", amount);
3.1754 + }
3.1755 + else if ((given & 0x80) == 0x80)
3.1756 + func (stream, "\t; <illegal shifter operand>");
3.1757 + else if (print_shift)
3.1758 + func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5],
3.1759 + arm_regnames[(given & 0xf00) >> 8]);
3.1760 + else
3.1761 + func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]);
3.1762 + }
3.1763 +}
3.1764 +
3.1765 +#define W_BIT 21
3.1766 +#define I_BIT 22
3.1767 +#define U_BIT 23
3.1768 +#define P_BIT 24
3.1769 +
3.1770 +#define WRITEBACK_BIT_SET (given & (1 << W_BIT))
3.1771 +#define IMMEDIATE_BIT_SET (given & (1 << I_BIT))
3.1772 +#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
3.1773 +#define PRE_BIT_SET (given & (1 << P_BIT))
3.1774 +
3.1775 +/* Print one coprocessor instruction on INFO->STREAM.
3.1776 + Return TRUE if the instuction matched, FALSE if this is not a
3.1777 + recognised coprocessor instruction. */
3.1778 +
3.1779 +static bfd_boolean
3.1780 +print_insn_coprocessor (bfd_vma pc,
3.1781 + struct disassemble_info *info,
3.1782 + long given,
3.1783 + bfd_boolean thumb)
3.1784 +{
3.1785 + const struct opcode32 *insn;
3.1786 + void *stream = info->stream;
3.1787 + fprintf_ftype func = info->fprintf_func;
3.1788 + unsigned long mask;
3.1789 + unsigned long value = 0;
3.1790 + struct arm_private_data *private_data = info->private_data;
3.1791 + unsigned long allowed_arches = private_data->features.coproc;
3.1792 + int cond;
3.1793 +
3.1794 + for (insn = coprocessor_opcodes; insn->assembler; insn++)
3.1795 + {
3.1796 + unsigned long u_reg = 16;
3.1797 + bfd_boolean is_unpredictable = FALSE;
3.1798 + signed long value_in_comment = 0;
3.1799 + const char *c;
3.1800 +
3.1801 + if (insn->arch == 0)
3.1802 + switch (insn->value)
3.1803 + {
3.1804 + case SENTINEL_IWMMXT_START:
3.1805 + if (info->mach != bfd_mach_arm_XScale
3.1806 + && info->mach != bfd_mach_arm_iWMMXt
3.1807 + && info->mach != bfd_mach_arm_iWMMXt2)
3.1808 + do
3.1809 + insn++;
3.1810 + while (insn->arch != 0 && insn->value != SENTINEL_IWMMXT_END);
3.1811 + continue;
3.1812 +
3.1813 + case SENTINEL_IWMMXT_END:
3.1814 + continue;
3.1815 +
3.1816 + case SENTINEL_GENERIC_START:
3.1817 + allowed_arches = private_data->features.core;
3.1818 + continue;
3.1819 +
3.1820 + default:
3.1821 + abort ();
3.1822 + }
3.1823 +
3.1824 + mask = insn->mask;
3.1825 + value = insn->value;
3.1826 + if (thumb)
3.1827 + {
3.1828 + /* The high 4 bits are 0xe for Arm conditional instructions, and
3.1829 + 0xe for arm unconditional instructions. The rest of the
3.1830 + encoding is the same. */
3.1831 + mask |= 0xf0000000;
3.1832 + value |= 0xe0000000;
3.1833 + if (ifthen_state)
3.1834 + cond = IFTHEN_COND;
3.1835 + else
3.1836 + cond = 16;
3.1837 + }
3.1838 + else
3.1839 + {
3.1840 + /* Only match unconditional instuctions against unconditional
3.1841 + patterns. */
3.1842 + if ((given & 0xf0000000) == 0xf0000000)
3.1843 + {
3.1844 + mask |= 0xf0000000;
3.1845 + cond = 16;
3.1846 + }
3.1847 + else
3.1848 + {
3.1849 + cond = (given >> 28) & 0xf;
3.1850 + if (cond == 0xe)
3.1851 + cond = 16;
3.1852 + }
3.1853 + }
3.1854 +
3.1855 + if ((given & mask) != value)
3.1856 + continue;
3.1857 +
3.1858 + if ((insn->arch & allowed_arches) == 0)
3.1859 + continue;
3.1860 +
3.1861 + for (c = insn->assembler; *c; c++)
3.1862 + {
3.1863 + if (*c == '%')
3.1864 + {
3.1865 + switch (*++c)
3.1866 + {
3.1867 + case '%':
3.1868 + func (stream, "%%");
3.1869 + break;
3.1870 +
3.1871 + case 'A':
3.1872 + {
3.1873 + int rn = (given >> 16) & 0xf;
3.1874 + bfd_vma offset = given & 0xff;
3.1875 +
3.1876 + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3.1877 +
3.1878 + if (PRE_BIT_SET || WRITEBACK_BIT_SET)
3.1879 + {
3.1880 + /* Not unindexed. The offset is scaled. */
3.1881 + offset = offset * 4;
3.1882 + if (NEGATIVE_BIT_SET)
3.1883 + offset = - offset;
3.1884 + if (rn != 15)
3.1885 + value_in_comment = offset;
3.1886 + }
3.1887 +
3.1888 + if (PRE_BIT_SET)
3.1889 + {
3.1890 + if (offset)
3.1891 + func (stream, ", #%d]%s",
3.1892 + offset,
3.1893 + WRITEBACK_BIT_SET ? "!" : "");
3.1894 + else if (NEGATIVE_BIT_SET)
3.1895 + func (stream, ", #-0]");
3.1896 + else
3.1897 + func (stream, "]");
3.1898 + }
3.1899 + else
3.1900 + {
3.1901 + func (stream, "]");
3.1902 +
3.1903 + if (WRITEBACK_BIT_SET)
3.1904 + {
3.1905 + if (offset)
3.1906 + func (stream, ", #%d", offset);
3.1907 + else if (NEGATIVE_BIT_SET)
3.1908 + func (stream, ", #-0");
3.1909 + }
3.1910 + else
3.1911 + {
3.1912 + func (stream, ", {%s%d}",
3.1913 + (NEGATIVE_BIT_SET && !offset) ? "-" : "",
3.1914 + offset);
3.1915 + value_in_comment = offset;
3.1916 + }
3.1917 + }
3.1918 + if (rn == 15 && (PRE_BIT_SET || WRITEBACK_BIT_SET))
3.1919 + {
3.1920 + func (stream, "\t; ");
3.1921 + /* For unaligned PCs, apply off-by-alignment
3.1922 + correction. */
3.1923 + info->print_address_func (offset + pc
3.1924 + + info->bytes_per_chunk * 2
3.1925 + - (pc & 3),
3.1926 + info);
3.1927 + }
3.1928 + }
3.1929 + break;
3.1930 +
3.1931 + case 'B':
3.1932 + {
3.1933 + int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10);
3.1934 + int offset = (given >> 1) & 0x3f;
3.1935 +
3.1936 + if (offset == 1)
3.1937 + func (stream, "{d%d}", regno);
3.1938 + else if (regno + offset > 32)
3.1939 + func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1);
3.1940 + else
3.1941 + func (stream, "{d%d-d%d}", regno, regno + offset - 1);
3.1942 + }
3.1943 + break;
3.1944 +
3.1945 + case 'c':
3.1946 + func (stream, "%s", arm_conditional[cond]);
3.1947 + break;
3.1948 +
3.1949 + case 'I':
3.1950 + /* Print a Cirrus/DSP shift immediate. */
3.1951 + /* Immediates are 7bit signed ints with bits 0..3 in
3.1952 + bits 0..3 of opcode and bits 4..6 in bits 5..7
3.1953 + of opcode. */
3.1954 + {
3.1955 + int imm;
3.1956 +
3.1957 + imm = (given & 0xf) | ((given & 0xe0) >> 1);
3.1958 +
3.1959 + /* Is ``imm'' a negative number? */
3.1960 + if (imm & 0x40)
3.1961 + imm |= (-1 << 7);
3.1962 +
3.1963 + func (stream, "%d", imm);
3.1964 + }
3.1965 +
3.1966 + break;
3.1967 +
3.1968 + case 'F':
3.1969 + switch (given & 0x00408000)
3.1970 + {
3.1971 + case 0:
3.1972 + func (stream, "4");
3.1973 + break;
3.1974 + case 0x8000:
3.1975 + func (stream, "1");
3.1976 + break;
3.1977 + case 0x00400000:
3.1978 + func (stream, "2");
3.1979 + break;
3.1980 + default:
3.1981 + func (stream, "3");
3.1982 + }
3.1983 + break;
3.1984 +
3.1985 + case 'P':
3.1986 + switch (given & 0x00080080)
3.1987 + {
3.1988 + case 0:
3.1989 + func (stream, "s");
3.1990 + break;
3.1991 + case 0x80:
3.1992 + func (stream, "d");
3.1993 + break;
3.1994 + case 0x00080000:
3.1995 + func (stream, "e");
3.1996 + break;
3.1997 + default:
3.1998 + func (stream, _("<illegal precision>"));
3.1999 + break;
3.2000 + }
3.2001 + break;
3.2002 +
3.2003 + case 'Q':
3.2004 + switch (given & 0x00408000)
3.2005 + {
3.2006 + case 0:
3.2007 + func (stream, "s");
3.2008 + break;
3.2009 + case 0x8000:
3.2010 + func (stream, "d");
3.2011 + break;
3.2012 + case 0x00400000:
3.2013 + func (stream, "e");
3.2014 + break;
3.2015 + default:
3.2016 + func (stream, "p");
3.2017 + break;
3.2018 + }
3.2019 + break;
3.2020 +
3.2021 + case 'R':
3.2022 + switch (given & 0x60)
3.2023 + {
3.2024 + case 0:
3.2025 + break;
3.2026 + case 0x20:
3.2027 + func (stream, "p");
3.2028 + break;
3.2029 + case 0x40:
3.2030 + func (stream, "m");
3.2031 + break;
3.2032 + default:
3.2033 + func (stream, "z");
3.2034 + break;
3.2035 + }
3.2036 + break;
3.2037 +
3.2038 + case '0': case '1': case '2': case '3': case '4':
3.2039 + case '5': case '6': case '7': case '8': case '9':
3.2040 + {
3.2041 + int width;
3.2042 +
3.2043 + c = arm_decode_bitfield (c, given, &value, &width);
3.2044 +
3.2045 + switch (*c)
3.2046 + {
3.2047 + case 'R':
3.2048 + if (value == 15)
3.2049 + is_unpredictable = TRUE;
3.2050 + /* Fall through. */
3.2051 + case 'r':
3.2052 + if (c[1] == 'u')
3.2053 + {
3.2054 + /* Eat the 'u' character. */
3.2055 + ++ c;
3.2056 +
3.2057 + if (u_reg == value)
3.2058 + is_unpredictable = TRUE;
3.2059 + u_reg = value;
3.2060 + }
3.2061 + func (stream, "%s", arm_regnames[value]);
3.2062 + break;
3.2063 + case 'D':
3.2064 + func (stream, "d%ld", value);
3.2065 + break;
3.2066 + case 'Q':
3.2067 + if (value & 1)
3.2068 + func (stream, "<illegal reg q%ld.5>", value >> 1);
3.2069 + else
3.2070 + func (stream, "q%ld", value >> 1);
3.2071 + break;
3.2072 + case 'd':
3.2073 + func (stream, "%ld", value);
3.2074 + value_in_comment = value;
3.2075 + break;
3.2076 + case 'k':
3.2077 + {
3.2078 + int from = (given & (1 << 7)) ? 32 : 16;
3.2079 + func (stream, "%ld", from - value);
3.2080 + }
3.2081 + break;
3.2082 +
3.2083 + case 'f':
3.2084 + if (value > 7)
3.2085 + func (stream, "#%s", arm_fp_const[value & 7]);
3.2086 + else
3.2087 + func (stream, "f%ld", value);
3.2088 + break;
3.2089 +
3.2090 + case 'w':
3.2091 + if (width == 2)
3.2092 + func (stream, "%s", iwmmxt_wwnames[value]);
3.2093 + else
3.2094 + func (stream, "%s", iwmmxt_wwssnames[value]);
3.2095 + break;
3.2096 +
3.2097 + case 'g':
3.2098 + func (stream, "%s", iwmmxt_regnames[value]);
3.2099 + break;
3.2100 + case 'G':
3.2101 + func (stream, "%s", iwmmxt_cregnames[value]);
3.2102 + break;
3.2103 +
3.2104 + case 'x':
3.2105 + func (stream, "0x%lx", (value & 0xffffffffUL));
3.2106 + break;
3.2107 +
3.2108 + case '`':
3.2109 + c++;
3.2110 + if (value == 0)
3.2111 + func (stream, "%c", *c);
3.2112 + break;
3.2113 + case '\'':
3.2114 + c++;
3.2115 + if (value == ((1ul << width) - 1))
3.2116 + func (stream, "%c", *c);
3.2117 + break;
3.2118 + case '?':
3.2119 + func (stream, "%c", c[(1 << width) - (int) value]);
3.2120 + c += 1 << width;
3.2121 + break;
3.2122 + default:
3.2123 + abort ();
3.2124 + }
3.2125 + break;
3.2126 +
3.2127 + case 'y':
3.2128 + case 'z':
3.2129 + {
3.2130 + int single = *c++ == 'y';
3.2131 + int regno;
3.2132 +
3.2133 + switch (*c)
3.2134 + {
3.2135 + case '4': /* Sm pair */
3.2136 + case '0': /* Sm, Dm */
3.2137 + regno = given & 0x0000000f;
3.2138 + if (single)
3.2139 + {
3.2140 + regno <<= 1;
3.2141 + regno += (given >> 5) & 1;
3.2142 + }
3.2143 + else
3.2144 + regno += ((given >> 5) & 1) << 4;
3.2145 + break;
3.2146 +
3.2147 + case '1': /* Sd, Dd */
3.2148 + regno = (given >> 12) & 0x0000000f;
3.2149 + if (single)
3.2150 + {
3.2151 + regno <<= 1;
3.2152 + regno += (given >> 22) & 1;
3.2153 + }
3.2154 + else
3.2155 + regno += ((given >> 22) & 1) << 4;
3.2156 + break;
3.2157 +
3.2158 + case '2': /* Sn, Dn */
3.2159 + regno = (given >> 16) & 0x0000000f;
3.2160 + if (single)
3.2161 + {
3.2162 + regno <<= 1;
3.2163 + regno += (given >> 7) & 1;
3.2164 + }
3.2165 + else
3.2166 + regno += ((given >> 7) & 1) << 4;
3.2167 + break;
3.2168 +
3.2169 + case '3': /* List */
3.2170 + func (stream, "{");
3.2171 + regno = (given >> 12) & 0x0000000f;
3.2172 + if (single)
3.2173 + {
3.2174 + regno <<= 1;
3.2175 + regno += (given >> 22) & 1;
3.2176 + }
3.2177 + else
3.2178 + regno += ((given >> 22) & 1) << 4;
3.2179 + break;
3.2180 +
3.2181 + default:
3.2182 + abort ();
3.2183 + }
3.2184 +
3.2185 + func (stream, "%c%d", single ? 's' : 'd', regno);
3.2186 +
3.2187 + if (*c == '3')
3.2188 + {
3.2189 + int count = given & 0xff;
3.2190 +
3.2191 + if (single == 0)
3.2192 + count >>= 1;
3.2193 +
3.2194 + if (--count)
3.2195 + {
3.2196 + func (stream, "-%c%d",
3.2197 + single ? 's' : 'd',
3.2198 + regno + count);
3.2199 + }
3.2200 +
3.2201 + func (stream, "}");
3.2202 + }
3.2203 + else if (*c == '4')
3.2204 + func (stream, ", %c%d", single ? 's' : 'd',
3.2205 + regno + 1);
3.2206 + }
3.2207 + break;
3.2208 +
3.2209 + case 'L':
3.2210 + switch (given & 0x00400100)
3.2211 + {
3.2212 + case 0x00000000: func (stream, "b"); break;
3.2213 + case 0x00400000: func (stream, "h"); break;
3.2214 + case 0x00000100: func (stream, "w"); break;
3.2215 + case 0x00400100: func (stream, "d"); break;
3.2216 + default:
3.2217 + break;
3.2218 + }
3.2219 + break;
3.2220 +
3.2221 + case 'Z':
3.2222 + {
3.2223 + /* given (20, 23) | given (0, 3) */
3.2224 + value = ((given >> 16) & 0xf0) | (given & 0xf);
3.2225 + func (stream, "%d", value);
3.2226 + }
3.2227 + break;
3.2228 +
3.2229 + case 'l':
3.2230 + /* This is like the 'A' operator, except that if
3.2231 + the width field "M" is zero, then the offset is
3.2232 + *not* multiplied by four. */
3.2233 + {
3.2234 + int offset = given & 0xff;
3.2235 + int multiplier = (given & 0x00000100) ? 4 : 1;
3.2236 +
3.2237 + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3.2238 +
3.2239 + if (multiplier > 1)
3.2240 + {
3.2241 + value_in_comment = offset * multiplier;
3.2242 + if (NEGATIVE_BIT_SET)
3.2243 + value_in_comment = - value_in_comment;
3.2244 + }
3.2245 +
3.2246 + if (offset)
3.2247 + {
3.2248 + if (PRE_BIT_SET)
3.2249 + func (stream, ", #%s%d]%s",
3.2250 + NEGATIVE_BIT_SET ? "-" : "",
3.2251 + offset * multiplier,
3.2252 + WRITEBACK_BIT_SET ? "!" : "");
3.2253 + else
3.2254 + func (stream, "], #%s%d",
3.2255 + NEGATIVE_BIT_SET ? "-" : "",
3.2256 + offset * multiplier);
3.2257 + }
3.2258 + else
3.2259 + func (stream, "]");
3.2260 + }
3.2261 + break;
3.2262 +
3.2263 + case 'r':
3.2264 + {
3.2265 + int imm4 = (given >> 4) & 0xf;
3.2266 + int puw_bits = ((given >> 22) & 6) | ((given >> W_BIT) & 1);
3.2267 + int ubit = ! NEGATIVE_BIT_SET;
3.2268 + const char *rm = arm_regnames [given & 0xf];
3.2269 + const char *rn = arm_regnames [(given >> 16) & 0xf];
3.2270 +
3.2271 + switch (puw_bits)
3.2272 + {
3.2273 + case 1:
3.2274 + case 3:
3.2275 + func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm);
3.2276 + if (imm4)
3.2277 + func (stream, ", lsl #%d", imm4);
3.2278 + break;
3.2279 +
3.2280 + case 4:
3.2281 + case 5:
3.2282 + case 6:
3.2283 + case 7:
3.2284 + func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm);
3.2285 + if (imm4 > 0)
3.2286 + func (stream, ", lsl #%d", imm4);
3.2287 + func (stream, "]");
3.2288 + if (puw_bits == 5 || puw_bits == 7)
3.2289 + func (stream, "!");
3.2290 + break;
3.2291 +
3.2292 + default:
3.2293 + func (stream, "INVALID");
3.2294 + }
3.2295 + }
3.2296 + break;
3.2297 +
3.2298 + case 'i':
3.2299 + {
3.2300 + long imm5;
3.2301 + imm5 = ((given & 0x100) >> 4) | (given & 0xf);
3.2302 + func (stream, "%ld", (imm5 == 0) ? 32 : imm5);
3.2303 + }
3.2304 + break;
3.2305 +
3.2306 + default:
3.2307 + abort ();
3.2308 + }
3.2309 + }
3.2310 + }
3.2311 + else
3.2312 + func (stream, "%c", *c);
3.2313 + }
3.2314 +
3.2315 + if (value_in_comment > 32 || value_in_comment < -16)
3.2316 + func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3.2317 +
3.2318 + if (is_unpredictable)
3.2319 + func (stream, UNPREDICTABLE_INSTRUCTION);
3.2320 +
3.2321 + return TRUE;
3.2322 + }
3.2323 + return FALSE;
3.2324 +}
3.2325 +
3.2326 +/* Decodes and prints ARM addressing modes. Returns the offset
3.2327 + used in the address, if any, if it is worthwhile printing the
3.2328 + offset as a hexadecimal value in a comment at the end of the
3.2329 + line of disassembly. */
3.2330 +
3.2331 +static signed long
3.2332 +print_arm_address (bfd_vma pc, struct disassemble_info *info, long given)
3.2333 +{
3.2334 + void *stream = info->stream;
3.2335 + fprintf_ftype func = info->fprintf_func;
3.2336 + bfd_vma offset = 0;
3.2337 +
3.2338 + if (((given & 0x000f0000) == 0x000f0000)
3.2339 + && ((given & 0x02000000) == 0))
3.2340 + {
3.2341 + offset = given & 0xfff;
3.2342 +
3.2343 + func (stream, "[pc");
3.2344 +
3.2345 + if (PRE_BIT_SET)
3.2346 + {
3.2347 + /* Pre-indexed. Elide offset of positive zero when
3.2348 + non-writeback. */
3.2349 + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3.2350 + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", offset);
3.2351 +
3.2352 + if (NEGATIVE_BIT_SET)
3.2353 + offset = -offset;
3.2354 +
3.2355 + offset += pc + 8;
3.2356 +
3.2357 + /* Cope with the possibility of write-back
3.2358 + being used. Probably a very dangerous thing
3.2359 + for the programmer to do, but who are we to
3.2360 + argue ? */
3.2361 + func (stream, "]%s", WRITEBACK_BIT_SET ? "!" : "");
3.2362 + }
3.2363 + else /* Post indexed. */
3.2364 + {
3.2365 + func (stream, "], #%s%d", NEGATIVE_BIT_SET ? "-" : "", offset);
3.2366 +
3.2367 + /* Ie ignore the offset. */
3.2368 + offset = pc + 8;
3.2369 + }
3.2370 +
3.2371 + func (stream, "\t; ");
3.2372 + info->print_address_func (offset, info);
3.2373 + offset = 0;
3.2374 + }
3.2375 + else
3.2376 + {
3.2377 + func (stream, "[%s",
3.2378 + arm_regnames[(given >> 16) & 0xf]);
3.2379 +
3.2380 + if (PRE_BIT_SET)
3.2381 + {
3.2382 + if ((given & 0x02000000) == 0)
3.2383 + {
3.2384 + /* Elide offset of positive zero when non-writeback. */
3.2385 + offset = given & 0xfff;
3.2386 + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET || offset)
3.2387 + func (stream, ", #%s%d", NEGATIVE_BIT_SET ? "-" : "", offset);
3.2388 + }
3.2389 + else
3.2390 + {
3.2391 + func (stream, ", %s", NEGATIVE_BIT_SET ? "-" : "");
3.2392 + arm_decode_shift (given, func, stream, TRUE);
3.2393 + }
3.2394 +
3.2395 + func (stream, "]%s",
3.2396 + WRITEBACK_BIT_SET ? "!" : "");
3.2397 + }
3.2398 + else
3.2399 + {
3.2400 + if ((given & 0x02000000) == 0)
3.2401 + {
3.2402 + /* Always show offset. */
3.2403 + offset = given & 0xfff;
3.2404 + func (stream, "], #%s%d",
3.2405 + NEGATIVE_BIT_SET ? "-" : "", offset);
3.2406 + }
3.2407 + else
3.2408 + {
3.2409 + func (stream, "], %s",
3.2410 + NEGATIVE_BIT_SET ? "-" : "");
3.2411 + arm_decode_shift (given, func, stream, TRUE);
3.2412 + }
3.2413 + }
3.2414 + }
3.2415 +
3.2416 + return (signed long) offset;
3.2417 +}
3.2418 +
3.2419 +/* Print one neon instruction on INFO->STREAM.
3.2420 + Return TRUE if the instuction matched, FALSE if this is not a
3.2421 + recognised neon instruction. */
3.2422 +
3.2423 +static bfd_boolean
3.2424 +print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
3.2425 +{
3.2426 + const struct opcode32 *insn;
3.2427 + void *stream = info->stream;
3.2428 + fprintf_ftype func = info->fprintf_func;
3.2429 +
3.2430 + if (thumb)
3.2431 + {
3.2432 + if ((given & 0xef000000) == 0xef000000)
3.2433 + {
3.2434 + /* Move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
3.2435 + unsigned long bit28 = given & (1 << 28);
3.2436 +
3.2437 + given &= 0x00ffffff;
3.2438 + if (bit28)
3.2439 + given |= 0xf3000000;
3.2440 + else
3.2441 + given |= 0xf2000000;
3.2442 + }
3.2443 + else if ((given & 0xff000000) == 0xf9000000)
3.2444 + given ^= 0xf9000000 ^ 0xf4000000;
3.2445 + else
3.2446 + return FALSE;
3.2447 + }
3.2448 +
3.2449 + for (insn = neon_opcodes; insn->assembler; insn++)
3.2450 + {
3.2451 + if ((given & insn->mask) == insn->value)
3.2452 + {
3.2453 + signed long value_in_comment = 0;
3.2454 + const char *c;
3.2455 +
3.2456 + for (c = insn->assembler; *c; c++)
3.2457 + {
3.2458 + if (*c == '%')
3.2459 + {
3.2460 + switch (*++c)
3.2461 + {
3.2462 + case '%':
3.2463 + func (stream, "%%");
3.2464 + break;
3.2465 +
3.2466 + case 'c':
3.2467 + if (thumb && ifthen_state)
3.2468 + func (stream, "%s", arm_conditional[IFTHEN_COND]);
3.2469 + break;
3.2470 +
3.2471 + case 'A':
3.2472 + {
3.2473 + static const unsigned char enc[16] =
3.2474 + {
3.2475 + 0x4, 0x14, /* st4 0,1 */
3.2476 + 0x4, /* st1 2 */
3.2477 + 0x4, /* st2 3 */
3.2478 + 0x3, /* st3 4 */
3.2479 + 0x13, /* st3 5 */
3.2480 + 0x3, /* st1 6 */
3.2481 + 0x1, /* st1 7 */
3.2482 + 0x2, /* st2 8 */
3.2483 + 0x12, /* st2 9 */
3.2484 + 0x2, /* st1 10 */
3.2485 + 0, 0, 0, 0, 0
3.2486 + };
3.2487 + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3.2488 + int rn = ((given >> 16) & 0xf);
3.2489 + int rm = ((given >> 0) & 0xf);
3.2490 + int align = ((given >> 4) & 0x3);
3.2491 + int type = ((given >> 8) & 0xf);
3.2492 + int n = enc[type] & 0xf;
3.2493 + int stride = (enc[type] >> 4) + 1;
3.2494 + int ix;
3.2495 +
3.2496 + func (stream, "{");
3.2497 + if (stride > 1)
3.2498 + for (ix = 0; ix != n; ix++)
3.2499 + func (stream, "%sd%d", ix ? "," : "", rd + ix * stride);
3.2500 + else if (n == 1)
3.2501 + func (stream, "d%d", rd);
3.2502 + else
3.2503 + func (stream, "d%d-d%d", rd, rd + n - 1);
3.2504 + func (stream, "}, [%s", arm_regnames[rn]);
3.2505 + if (align)
3.2506 + func (stream, " :%d", 32 << align);
3.2507 + func (stream, "]");
3.2508 + if (rm == 0xd)
3.2509 + func (stream, "!");
3.2510 + else if (rm != 0xf)
3.2511 + func (stream, ", %s", arm_regnames[rm]);
3.2512 + }
3.2513 + break;
3.2514 +
3.2515 + case 'B':
3.2516 + {
3.2517 + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3.2518 + int rn = ((given >> 16) & 0xf);
3.2519 + int rm = ((given >> 0) & 0xf);
3.2520 + int idx_align = ((given >> 4) & 0xf);
3.2521 + int align = 0;
3.2522 + int size = ((given >> 10) & 0x3);
3.2523 + int idx = idx_align >> (size + 1);
3.2524 + int length = ((given >> 8) & 3) + 1;
3.2525 + int stride = 1;
3.2526 + int i;
3.2527 +
3.2528 + if (length > 1 && size > 0)
3.2529 + stride = (idx_align & (1 << size)) ? 2 : 1;
3.2530 +
3.2531 + switch (length)
3.2532 + {
3.2533 + case 1:
3.2534 + {
3.2535 + int amask = (1 << size) - 1;
3.2536 + if ((idx_align & (1 << size)) != 0)
3.2537 + return FALSE;
3.2538 + if (size > 0)
3.2539 + {
3.2540 + if ((idx_align & amask) == amask)
3.2541 + align = 8 << size;
3.2542 + else if ((idx_align & amask) != 0)
3.2543 + return FALSE;
3.2544 + }
3.2545 + }
3.2546 + break;
3.2547 +
3.2548 + case 2:
3.2549 + if (size == 2 && (idx_align & 2) != 0)
3.2550 + return FALSE;
3.2551 + align = (idx_align & 1) ? 16 << size : 0;
3.2552 + break;
3.2553 +
3.2554 + case 3:
3.2555 + if ((size == 2 && (idx_align & 3) != 0)
3.2556 + || (idx_align & 1) != 0)
3.2557 + return FALSE;
3.2558 + break;
3.2559 +
3.2560 + case 4:
3.2561 + if (size == 2)
3.2562 + {
3.2563 + if ((idx_align & 3) == 3)
3.2564 + return FALSE;
3.2565 + align = (idx_align & 3) * 64;
3.2566 + }
3.2567 + else
3.2568 + align = (idx_align & 1) ? 32 << size : 0;
3.2569 + break;
3.2570 +
3.2571 + default:
3.2572 + abort ();
3.2573 + }
3.2574 +
3.2575 + func (stream, "{");
3.2576 + for (i = 0; i < length; i++)
3.2577 + func (stream, "%sd%d[%d]", (i == 0) ? "" : ",",
3.2578 + rd + i * stride, idx);
3.2579 + func (stream, "}, [%s", arm_regnames[rn]);
3.2580 + if (align)
3.2581 + func (stream, " :%d", align);
3.2582 + func (stream, "]");
3.2583 + if (rm == 0xd)
3.2584 + func (stream, "!");
3.2585 + else if (rm != 0xf)
3.2586 + func (stream, ", %s", arm_regnames[rm]);
3.2587 + }
3.2588 + break;
3.2589 +
3.2590 + case 'C':
3.2591 + {
3.2592 + int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4);
3.2593 + int rn = ((given >> 16) & 0xf);
3.2594 + int rm = ((given >> 0) & 0xf);
3.2595 + int align = ((given >> 4) & 0x1);
3.2596 + int size = ((given >> 6) & 0x3);
3.2597 + int type = ((given >> 8) & 0x3);
3.2598 + int n = type + 1;
3.2599 + int stride = ((given >> 5) & 0x1);
3.2600 + int ix;
3.2601 +
3.2602 + if (stride && (n == 1))
3.2603 + n++;
3.2604 + else
3.2605 + stride++;
3.2606 +
3.2607 + func (stream, "{");
3.2608 + if (stride > 1)
3.2609 + for (ix = 0; ix != n; ix++)
3.2610 + func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride);
3.2611 + else if (n == 1)
3.2612 + func (stream, "d%d[]", rd);
3.2613 + else
3.2614 + func (stream, "d%d[]-d%d[]", rd, rd + n - 1);
3.2615 + func (stream, "}, [%s", arm_regnames[rn]);
3.2616 + if (align)
3.2617 + {
3.2618 + align = (8 * (type + 1)) << size;
3.2619 + if (type == 3)
3.2620 + align = (size > 1) ? align >> 1 : align;
3.2621 + if (type == 2 || (type == 0 && !size))
3.2622 + func (stream, " :<bad align %d>", align);
3.2623 + else
3.2624 + func (stream, " :%d", align);
3.2625 + }
3.2626 + func (stream, "]");
3.2627 + if (rm == 0xd)
3.2628 + func (stream, "!");
3.2629 + else if (rm != 0xf)
3.2630 + func (stream, ", %s", arm_regnames[rm]);
3.2631 + }
3.2632 + break;
3.2633 +
3.2634 + case 'D':
3.2635 + {
3.2636 + int raw_reg = (given & 0xf) | ((given >> 1) & 0x10);
3.2637 + int size = (given >> 20) & 3;
3.2638 + int reg = raw_reg & ((4 << size) - 1);
3.2639 + int ix = raw_reg >> size >> 2;
3.2640 +
3.2641 + func (stream, "d%d[%d]", reg, ix);
3.2642 + }
3.2643 + break;
3.2644 +
3.2645 + case 'E':
3.2646 + /* Neon encoded constant for mov, mvn, vorr, vbic. */
3.2647 + {
3.2648 + int bits = 0;
3.2649 + int cmode = (given >> 8) & 0xf;
3.2650 + int op = (given >> 5) & 0x1;
3.2651 + unsigned long value = 0, hival = 0;
3.2652 + unsigned shift;
3.2653 + int size = 0;
3.2654 + int isfloat = 0;
3.2655 +
3.2656 + bits |= ((given >> 24) & 1) << 7;
3.2657 + bits |= ((given >> 16) & 7) << 4;
3.2658 + bits |= ((given >> 0) & 15) << 0;
3.2659 +
3.2660 + if (cmode < 8)
3.2661 + {
3.2662 + shift = (cmode >> 1) & 3;
3.2663 + value = (unsigned long) bits << (8 * shift);
3.2664 + size = 32;
3.2665 + }
3.2666 + else if (cmode < 12)
3.2667 + {
3.2668 + shift = (cmode >> 1) & 1;
3.2669 + value = (unsigned long) bits << (8 * shift);
3.2670 + size = 16;
3.2671 + }
3.2672 + else if (cmode < 14)
3.2673 + {
3.2674 + shift = (cmode & 1) + 1;
3.2675 + value = (unsigned long) bits << (8 * shift);
3.2676 + value |= (1ul << (8 * shift)) - 1;
3.2677 + size = 32;
3.2678 + }
3.2679 + else if (cmode == 14)
3.2680 + {
3.2681 + if (op)
3.2682 + {
3.2683 + /* Bit replication into bytes. */
3.2684 + int ix;
3.2685 + unsigned long mask;
3.2686 +
3.2687 + value = 0;
3.2688 + hival = 0;
3.2689 + for (ix = 7; ix >= 0; ix--)
3.2690 + {
3.2691 + mask = ((bits >> ix) & 1) ? 0xff : 0;
3.2692 + if (ix <= 3)
3.2693 + value = (value << 8) | mask;
3.2694 + else
3.2695 + hival = (hival << 8) | mask;
3.2696 + }
3.2697 + size = 64;
3.2698 + }
3.2699 + else
3.2700 + {
3.2701 + /* Byte replication. */
3.2702 + value = (unsigned long) bits;
3.2703 + size = 8;
3.2704 + }
3.2705 + }
3.2706 + else if (!op)
3.2707 + {
3.2708 + /* Floating point encoding. */
3.2709 + int tmp;
3.2710 +
3.2711 + value = (unsigned long) (bits & 0x7f) << 19;
3.2712 + value |= (unsigned long) (bits & 0x80) << 24;
3.2713 + tmp = bits & 0x40 ? 0x3c : 0x40;
3.2714 + value |= (unsigned long) tmp << 24;
3.2715 + size = 32;
3.2716 + isfloat = 1;
3.2717 + }
3.2718 + else
3.2719 + {
3.2720 + func (stream, "<illegal constant %.8x:%x:%x>",
3.2721 + bits, cmode, op);
3.2722 + size = 32;
3.2723 + break;
3.2724 + }
3.2725 + switch (size)
3.2726 + {
3.2727 + case 8:
3.2728 + func (stream, "#%ld\t; 0x%.2lx", value, value);
3.2729 + break;
3.2730 +
3.2731 + case 16:
3.2732 + func (stream, "#%ld\t; 0x%.4lx", value, value);
3.2733 + break;
3.2734 +
3.2735 + case 32:
3.2736 + if (isfloat)
3.2737 + {
3.2738 + unsigned char valbytes[4];
3.2739 + double fvalue;
3.2740 +
3.2741 + /* Do this a byte at a time so we don't have to
3.2742 + worry about the host's endianness. */
3.2743 + valbytes[0] = value & 0xff;
3.2744 + valbytes[1] = (value >> 8) & 0xff;
3.2745 + valbytes[2] = (value >> 16) & 0xff;
3.2746 + valbytes[3] = (value >> 24) & 0xff;
3.2747 +
3.2748 + floatformat_to_double
3.2749 + (& floatformat_ieee_single_little, valbytes,
3.2750 + & fvalue);
3.2751 +
3.2752 + func (stream, "#%.7g\t; 0x%.8lx", fvalue,
3.2753 + value);
3.2754 + }
3.2755 + else
3.2756 + func (stream, "#%ld\t; 0x%.8lx",
3.2757 + (long) (((value & 0x80000000L) != 0)
3.2758 + ? value | ~0xffffffffL : value),
3.2759 + value);
3.2760 + break;
3.2761 +
3.2762 + case 64:
3.2763 + func (stream, "#0x%.8lx%.8lx", hival, value);
3.2764 + break;
3.2765 +
3.2766 + default:
3.2767 + abort ();
3.2768 + }
3.2769 + }
3.2770 + break;
3.2771 +
3.2772 + case 'F':
3.2773 + {
3.2774 + int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10);
3.2775 + int num = (given >> 8) & 0x3;
3.2776 +
3.2777 + if (!num)
3.2778 + func (stream, "{d%d}", regno);
3.2779 + else if (num + regno >= 32)
3.2780 + func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
3.2781 + else
3.2782 + func (stream, "{d%d-d%d}", regno, regno + num);
3.2783 + }
3.2784 + break;
3.2785 +
3.2786 +
3.2787 + case '0': case '1': case '2': case '3': case '4':
3.2788 + case '5': case '6': case '7': case '8': case '9':
3.2789 + {
3.2790 + int width;
3.2791 + unsigned long value;
3.2792 +
3.2793 + c = arm_decode_bitfield (c, given, &value, &width);
3.2794 +
3.2795 + switch (*c)
3.2796 + {
3.2797 + case 'r':
3.2798 + func (stream, "%s", arm_regnames[value]);
3.2799 + break;
3.2800 + case 'd':
3.2801 + func (stream, "%ld", value);
3.2802 + value_in_comment = value;
3.2803 + break;
3.2804 + case 'e':
3.2805 + func (stream, "%ld", (1ul << width) - value);
3.2806 + break;
3.2807 +
3.2808 + case 'S':
3.2809 + case 'T':
3.2810 + case 'U':
3.2811 + /* Various width encodings. */
3.2812 + {
3.2813 + int base = 8 << (*c - 'S'); /* 8,16 or 32 */
3.2814 + int limit;
3.2815 + unsigned low, high;
3.2816 +
3.2817 + c++;
3.2818 + if (*c >= '0' && *c <= '9')
3.2819 + limit = *c - '0';
3.2820 + else if (*c >= 'a' && *c <= 'f')
3.2821 + limit = *c - 'a' + 10;
3.2822 + else
3.2823 + abort ();
3.2824 + low = limit >> 2;
3.2825 + high = limit & 3;
3.2826 +
3.2827 + if (value < low || value > high)
3.2828 + func (stream, "<illegal width %d>", base << value);
3.2829 + else
3.2830 + func (stream, "%d", base << value);
3.2831 + }
3.2832 + break;
3.2833 + case 'R':
3.2834 + if (given & (1 << 6))
3.2835 + goto Q;
3.2836 + /* FALLTHROUGH */
3.2837 + case 'D':
3.2838 + func (stream, "d%ld", value);
3.2839 + break;
3.2840 + case 'Q':
3.2841 + Q:
3.2842 + if (value & 1)
3.2843 + func (stream, "<illegal reg q%ld.5>", value >> 1);
3.2844 + else
3.2845 + func (stream, "q%ld", value >> 1);
3.2846 + break;
3.2847 +
3.2848 + case '`':
3.2849 + c++;
3.2850 + if (value == 0)
3.2851 + func (stream, "%c", *c);
3.2852 + break;
3.2853 + case '\'':
3.2854 + c++;
3.2855 + if (value == ((1ul << width) - 1))
3.2856 + func (stream, "%c", *c);
3.2857 + break;
3.2858 + case '?':
3.2859 + func (stream, "%c", c[(1 << width) - (int) value]);
3.2860 + c += 1 << width;
3.2861 + break;
3.2862 + default:
3.2863 + abort ();
3.2864 + }
3.2865 + break;
3.2866 +
3.2867 + default:
3.2868 + abort ();
3.2869 + }
3.2870 + }
3.2871 + }
3.2872 + else
3.2873 + func (stream, "%c", *c);
3.2874 + }
3.2875 +
3.2876 + if (value_in_comment > 32 || value_in_comment < -16)
3.2877 + func (stream, "\t; 0x%lx", value_in_comment);
3.2878 +
3.2879 + return TRUE;
3.2880 + }
3.2881 + }
3.2882 + return FALSE;
3.2883 +}
3.2884 +
3.2885 +/* Return the name of a v7A special register. */
3.2886 +
3.2887 +static const char *
3.2888 +banked_regname (unsigned reg)
3.2889 +{
3.2890 + switch (reg)
3.2891 + {
3.2892 + case 15: return "CPSR";
3.2893 + case 32: return "R8_usr";
3.2894 + case 33: return "R9_usr";
3.2895 + case 34: return "R10_usr";
3.2896 + case 35: return "R11_usr";
3.2897 + case 36: return "R12_usr";
3.2898 + case 37: return "SP_usr";
3.2899 + case 38: return "LR_usr";
3.2900 + case 40: return "R8_fiq";
3.2901 + case 41: return "R9_fiq";
3.2902 + case 42: return "R10_fiq";
3.2903 + case 43: return "R11_fiq";
3.2904 + case 44: return "R12_fiq";
3.2905 + case 45: return "SP_fiq";
3.2906 + case 46: return "LR_fiq";
3.2907 + case 48: return "LR_irq";
3.2908 + case 49: return "SP_irq";
3.2909 + case 50: return "LR_svc";
3.2910 + case 51: return "SP_svc";
3.2911 + case 52: return "LR_abt";
3.2912 + case 53: return "SP_abt";
3.2913 + case 54: return "LR_und";
3.2914 + case 55: return "SP_und";
3.2915 + case 60: return "LR_mon";
3.2916 + case 61: return "SP_mon";
3.2917 + case 62: return "ELR_hyp";
3.2918 + case 63: return "SP_hyp";
3.2919 + case 79: return "SPSR";
3.2920 + case 110: return "SPSR_fiq";
3.2921 + case 112: return "SPSR_irq";
3.2922 + case 114: return "SPSR_svc";
3.2923 + case 116: return "SPSR_abt";
3.2924 + case 118: return "SPSR_und";
3.2925 + case 124: return "SPSR_mon";
3.2926 + case 126: return "SPSR_hyp";
3.2927 + default: return NULL;
3.2928 + }
3.2929 +}
3.2930 +
3.2931 +/* Print one ARM instruction from PC on INFO->STREAM. */
3.2932 +
3.2933 +static void
3.2934 +print_insn_arm (bfd_vma pc, struct disassemble_info *info, long given)
3.2935 +{
3.2936 + const struct opcode32 *insn;
3.2937 + void *stream = info->stream;
3.2938 + fprintf_ftype func = info->fprintf_func;
3.2939 + struct arm_private_data *private_data = info->private_data;
3.2940 +
3.2941 + if (print_insn_coprocessor (pc, info, given, FALSE))
3.2942 + return;
3.2943 +
3.2944 + if (print_insn_neon (info, given, FALSE))
3.2945 + return;
3.2946 +
3.2947 + for (insn = arm_opcodes; insn->assembler; insn++)
3.2948 + {
3.2949 + if ((given & insn->mask) != insn->value)
3.2950 + continue;
3.2951 +
3.2952 + if ((insn->arch & private_data->features.core) == 0)
3.2953 + continue;
3.2954 +
3.2955 + /* Special case: an instruction with all bits set in the condition field
3.2956 + (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
3.2957 + or by the catchall at the end of the table. */
3.2958 + if ((given & 0xF0000000) != 0xF0000000
3.2959 + || (insn->mask & 0xF0000000) == 0xF0000000
3.2960 + || (insn->mask == 0 && insn->value == 0))
3.2961 + {
3.2962 + unsigned long u_reg = 16;
3.2963 + unsigned long U_reg = 16;
3.2964 + bfd_boolean is_unpredictable = FALSE;
3.2965 + signed long value_in_comment = 0;
3.2966 + const char *c;
3.2967 +
3.2968 + for (c = insn->assembler; *c; c++)
3.2969 + {
3.2970 + if (*c == '%')
3.2971 + {
3.2972 + bfd_boolean allow_unpredictable = FALSE;
3.2973 +
3.2974 + switch (*++c)
3.2975 + {
3.2976 + case '%':
3.2977 + func (stream, "%%");
3.2978 + break;
3.2979 +
3.2980 + case 'a':
3.2981 + value_in_comment = print_arm_address (pc, info, given);
3.2982 + break;
3.2983 +
3.2984 + case 'P':
3.2985 + /* Set P address bit and use normal address
3.2986 + printing routine. */
3.2987 + value_in_comment = print_arm_address (pc, info, given | (1 << P_BIT));
3.2988 + break;
3.2989 +
3.2990 + case 'S':
3.2991 + allow_unpredictable = TRUE;
3.2992 + case 's':
3.2993 + if ((given & 0x004f0000) == 0x004f0000)
3.2994 + {
3.2995 + /* PC relative with immediate offset. */
3.2996 + bfd_vma offset = ((given & 0xf00) >> 4) | (given & 0xf);
3.2997 +
3.2998 + if (PRE_BIT_SET)
3.2999 + {
3.3000 + /* Elide positive zero offset. */
3.3001 + if (offset || NEGATIVE_BIT_SET)
3.3002 + func (stream, "[pc, #%s%d]\t; ",
3.3003 + NEGATIVE_BIT_SET ? "-" : "", offset);
3.3004 + else
3.3005 + func (stream, "[pc]\t; ");
3.3006 + if (NEGATIVE_BIT_SET)
3.3007 + offset = -offset;
3.3008 + info->print_address_func (offset + pc + 8, info);
3.3009 + }
3.3010 + else
3.3011 + {
3.3012 + /* Always show the offset. */
3.3013 + func (stream, "[pc], #%s%d",
3.3014 + NEGATIVE_BIT_SET ? "-" : "", offset);
3.3015 + if (! allow_unpredictable)
3.3016 + is_unpredictable = TRUE;
3.3017 + }
3.3018 + }
3.3019 + else
3.3020 + {
3.3021 + int offset = ((given & 0xf00) >> 4) | (given & 0xf);
3.3022 +
3.3023 + func (stream, "[%s",
3.3024 + arm_regnames[(given >> 16) & 0xf]);
3.3025 +
3.3026 + if (PRE_BIT_SET)
3.3027 + {
3.3028 + if (IMMEDIATE_BIT_SET)
3.3029 + {
3.3030 + /* Elide offset for non-writeback
3.3031 + positive zero. */
3.3032 + if (WRITEBACK_BIT_SET || NEGATIVE_BIT_SET
3.3033 + || offset)
3.3034 + func (stream, ", #%s%d",
3.3035 + NEGATIVE_BIT_SET ? "-" : "", offset);
3.3036 +
3.3037 + if (NEGATIVE_BIT_SET)
3.3038 + offset = -offset;
3.3039 +
3.3040 + value_in_comment = offset;
3.3041 + }
3.3042 + else
3.3043 + {
3.3044 + /* Register Offset or Register Pre-Indexed. */
3.3045 + func (stream, ", %s%s",
3.3046 + NEGATIVE_BIT_SET ? "-" : "",
3.3047 + arm_regnames[given & 0xf]);
3.3048 +
3.3049 + /* Writing back to the register that is the source/
3.3050 + destination of the load/store is unpredictable. */
3.3051 + if (! allow_unpredictable
3.3052 + && WRITEBACK_BIT_SET
3.3053 + && ((given & 0xf) == ((given >> 12) & 0xf)))
3.3054 + is_unpredictable = TRUE;
3.3055 + }
3.3056 +
3.3057 + func (stream, "]%s",
3.3058 + WRITEBACK_BIT_SET ? "!" : "");
3.3059 + }
3.3060 + else
3.3061 + {
3.3062 + if (IMMEDIATE_BIT_SET)
3.3063 + {
3.3064 + /* Immediate Post-indexed. */
3.3065 + /* PR 10924: Offset must be printed, even if it is zero. */
3.3066 + func (stream, "], #%s%d",
3.3067 + NEGATIVE_BIT_SET ? "-" : "", offset);
3.3068 + if (NEGATIVE_BIT_SET)
3.3069 + offset = -offset;
3.3070 + value_in_comment = offset;
3.3071 + }
3.3072 + else
3.3073 + {
3.3074 + /* Register Post-indexed. */
3.3075 + func (stream, "], %s%s",
3.3076 + NEGATIVE_BIT_SET ? "-" : "",
3.3077 + arm_regnames[given & 0xf]);
3.3078 +
3.3079 + /* Writing back to the register that is the source/
3.3080 + destination of the load/store is unpredictable. */
3.3081 + if (! allow_unpredictable
3.3082 + && (given & 0xf) == ((given >> 12) & 0xf))
3.3083 + is_unpredictable = TRUE;
3.3084 + }
3.3085 +
3.3086 + if (! allow_unpredictable)
3.3087 + {
3.3088 + /* Writeback is automatically implied by post- addressing.
3.3089 + Setting the W bit is unnecessary and ARM specify it as
3.3090 + being unpredictable. */
3.3091 + if (WRITEBACK_BIT_SET
3.3092 + /* Specifying the PC register as the post-indexed
3.3093 + registers is also unpredictable. */
3.3094 + || (! IMMEDIATE_BIT_SET && ((given & 0xf) == 0xf)))
3.3095 + is_unpredictable = TRUE;
3.3096 + }
3.3097 + }
3.3098 + }
3.3099 + break;
3.3100 +
3.3101 + case 'b':
3.3102 + {
3.3103 + bfd_vma disp = (((given & 0xffffff) ^ 0x800000) - 0x800000);
3.3104 + info->print_address_func (disp * 4 + pc + 8, info);
3.3105 + }
3.3106 + break;
3.3107 +
3.3108 + case 'c':
3.3109 + if (((given >> 28) & 0xf) != 0xe)
3.3110 + func (stream, "%s",
3.3111 + arm_conditional [(given >> 28) & 0xf]);
3.3112 + break;
3.3113 +
3.3114 + case 'm':
3.3115 + {
3.3116 + int started = 0;
3.3117 + int reg;
3.3118 +
3.3119 + func (stream, "{");
3.3120 + for (reg = 0; reg < 16; reg++)
3.3121 + if ((given & (1 << reg)) != 0)
3.3122 + {
3.3123 + if (started)
3.3124 + func (stream, ", ");
3.3125 + started = 1;
3.3126 + func (stream, "%s", arm_regnames[reg]);
3.3127 + }
3.3128 + func (stream, "}");
3.3129 + if (! started)
3.3130 + is_unpredictable = TRUE;
3.3131 + }
3.3132 + break;
3.3133 +
3.3134 + case 'q':
3.3135 + arm_decode_shift (given, func, stream, FALSE);
3.3136 + break;
3.3137 +
3.3138 + case 'o':
3.3139 + if ((given & 0x02000000) != 0)
3.3140 + {
3.3141 + int rotate = (given & 0xf00) >> 7;
3.3142 + int immed = (given & 0xff);
3.3143 +
3.3144 + immed = (((immed << (32 - rotate))
3.3145 + | (immed >> rotate)) & 0xffffffff);
3.3146 + func (stream, "#%d", immed);
3.3147 + value_in_comment = immed;
3.3148 + }
3.3149 + else
3.3150 + arm_decode_shift (given, func, stream, TRUE);
3.3151 + break;
3.3152 +
3.3153 + case 'p':
3.3154 + if ((given & 0x0000f000) == 0x0000f000)
3.3155 + {
3.3156 + /* The p-variants of tst/cmp/cmn/teq are the pre-V6
3.3157 + mechanism for setting PSR flag bits. They are
3.3158 + obsolete in V6 onwards. */
3.3159 + if ((private_data->features.core & ARM_EXT_V6) == 0)
3.3160 + func (stream, "p");
3.3161 + }
3.3162 + break;
3.3163 +
3.3164 + case 't':
3.3165 + if ((given & 0x01200000) == 0x00200000)
3.3166 + func (stream, "t");
3.3167 + break;
3.3168 +
3.3169 + case 'A':
3.3170 + {
3.3171 + int offset = given & 0xff;
3.3172 +
3.3173 + value_in_comment = offset * 4;
3.3174 + if (NEGATIVE_BIT_SET)
3.3175 + value_in_comment = - value_in_comment;
3.3176 +
3.3177 + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]);
3.3178 +
3.3179 + if (PRE_BIT_SET)
3.3180 + {
3.3181 + if (offset)
3.3182 + func (stream, ", #%d]%s",
3.3183 + value_in_comment,
3.3184 + WRITEBACK_BIT_SET ? "!" : "");
3.3185 + else
3.3186 + func (stream, "]");
3.3187 + }
3.3188 + else
3.3189 + {
3.3190 + func (stream, "]");
3.3191 +
3.3192 + if (WRITEBACK_BIT_SET)
3.3193 + {
3.3194 + if (offset)
3.3195 + func (stream, ", #%d", value_in_comment);
3.3196 + }
3.3197 + else
3.3198 + {
3.3199 + func (stream, ", {%d}", offset);
3.3200 + value_in_comment = offset;
3.3201 + }
3.3202 + }
3.3203 + }
3.3204 + break;
3.3205 +
3.3206 + case 'B':
3.3207 + /* Print ARM V5 BLX(1) address: pc+25 bits. */
3.3208 + {
3.3209 + bfd_vma address;
3.3210 + bfd_vma offset = 0;
3.3211 +
3.3212 + if (! NEGATIVE_BIT_SET)
3.3213 + /* Is signed, hi bits should be ones. */
3.3214 + offset = (-1) ^ 0x00ffffff;
3.3215 +
3.3216 + /* Offset is (SignExtend(offset field)<<2). */
3.3217 + offset += given & 0x00ffffff;
3.3218 + offset <<= 2;
3.3219 + address = offset + pc + 8;
3.3220 +
3.3221 + if (given & 0x01000000)
3.3222 + /* H bit allows addressing to 2-byte boundaries. */
3.3223 + address += 2;
3.3224 +
3.3225 + info->print_address_func (address, info);
3.3226 + }
3.3227 + break;
3.3228 +
3.3229 + case 'C':
3.3230 + if ((given & 0x02000200) == 0x200)
3.3231 + {
3.3232 + const char * name;
3.3233 + unsigned sysm = (given & 0x004f0000) >> 16;
3.3234 +
3.3235 + sysm |= (given & 0x300) >> 4;
3.3236 + name = banked_regname (sysm);
3.3237 +
3.3238 + if (name != NULL)
3.3239 + func (stream, "%s", name);
3.3240 + else
3.3241 + func (stream, "(UNDEF: %lu)", sysm);
3.3242 + }
3.3243 + else
3.3244 + {
3.3245 + func (stream, "%cPSR_",
3.3246 + (given & 0x00400000) ? 'S' : 'C');
3.3247 + if (given & 0x80000)
3.3248 + func (stream, "f");
3.3249 + if (given & 0x40000)
3.3250 + func (stream, "s");
3.3251 + if (given & 0x20000)
3.3252 + func (stream, "x");
3.3253 + if (given & 0x10000)
3.3254 + func (stream, "c");
3.3255 + }
3.3256 + break;
3.3257 +
3.3258 + case 'U':
3.3259 + if ((given & 0xf0) == 0x60)
3.3260 + {
3.3261 + switch (given & 0xf)
3.3262 + {
3.3263 + case 0xf: func (stream, "sy"); break;
3.3264 + default:
3.3265 + func (stream, "#%d", (int) given & 0xf);
3.3266 + break;
3.3267 + }
3.3268 + }
3.3269 + else
3.3270 + {
3.3271 + switch (given & 0xf)
3.3272 + {
3.3273 + case 0xf: func (stream, "sy"); break;
3.3274 + case 0x7: func (stream, "un"); break;
3.3275 + case 0xe: func (stream, "st"); break;
3.3276 + case 0x6: func (stream, "unst"); break;
3.3277 + case 0xb: func (stream, "ish"); break;
3.3278 + case 0xa: func (stream, "ishst"); break;
3.3279 + case 0x3: func (stream, "osh"); break;
3.3280 + case 0x2: func (stream, "oshst"); break;
3.3281 + default:
3.3282 + func (stream, "#%d", (int) given & 0xf);
3.3283 + break;
3.3284 + }
3.3285 + }
3.3286 + break;
3.3287 +
3.3288 + case '0': case '1': case '2': case '3': case '4':
3.3289 + case '5': case '6': case '7': case '8': case '9':
3.3290 + {
3.3291 + int width;
3.3292 + unsigned long value;
3.3293 +
3.3294 + c = arm_decode_bitfield (c, given, &value, &width);
3.3295 +
3.3296 + switch (*c)
3.3297 + {
3.3298 + case 'R':
3.3299 + if (value == 15)
3.3300 + is_unpredictable = TRUE;
3.3301 + /* Fall through. */
3.3302 + case 'r':
3.3303 + if (c[1] == 'u')
3.3304 + {
3.3305 + /* Eat the 'u' character. */
3.3306 + ++ c;
3.3307 +
3.3308 + if (u_reg == value)
3.3309 + is_unpredictable = TRUE;
3.3310 + u_reg = value;
3.3311 + }
3.3312 + if (c[1] == 'U')
3.3313 + {
3.3314 + /* Eat the 'U' character. */
3.3315 + ++ c;
3.3316 +
3.3317 + if (U_reg == value)
3.3318 + is_unpredictable = TRUE;
3.3319 + U_reg = value;
3.3320 + }
3.3321 + func (stream, "%s", arm_regnames[value]);
3.3322 + break;
3.3323 + case 'd':
3.3324 + func (stream, "%ld", value);
3.3325 + value_in_comment = value;
3.3326 + break;
3.3327 + case 'b':
3.3328 + func (stream, "%ld", value * 8);
3.3329 + value_in_comment = value * 8;
3.3330 + break;
3.3331 + case 'W':
3.3332 + func (stream, "%ld", value + 1);
3.3333 + value_in_comment = value + 1;
3.3334 + break;
3.3335 + case 'x':
3.3336 + func (stream, "0x%08lx", value);
3.3337 +
3.3338 + /* Some SWI instructions have special
3.3339 + meanings. */
3.3340 + if ((given & 0x0fffffff) == 0x0FF00000)
3.3341 + func (stream, "\t; IMB");
3.3342 + else if ((given & 0x0fffffff) == 0x0FF00001)
3.3343 + func (stream, "\t; IMBRange");
3.3344 + break;
3.3345 + case 'X':
3.3346 + func (stream, "%01lx", value & 0xf);
3.3347 + value_in_comment = value;
3.3348 + break;
3.3349 + case '`':
3.3350 + c++;
3.3351 + if (value == 0)
3.3352 + func (stream, "%c", *c);
3.3353 + break;
3.3354 + case '\'':
3.3355 + c++;
3.3356 + if (value == ((1ul << width) - 1))
3.3357 + func (stream, "%c", *c);
3.3358 + break;
3.3359 + case '?':
3.3360 + func (stream, "%c", c[(1 << width) - (int) value]);
3.3361 + c += 1 << width;
3.3362 + break;
3.3363 + default:
3.3364 + abort ();
3.3365 + }
3.3366 + break;
3.3367 +
3.3368 + case 'e':
3.3369 + {
3.3370 + int imm;
3.3371 +
3.3372 + imm = (given & 0xf) | ((given & 0xfff00) >> 4);
3.3373 + func (stream, "%d", imm);
3.3374 + value_in_comment = imm;
3.3375 + }
3.3376 + break;
3.3377 +
3.3378 + case 'E':
3.3379 + /* LSB and WIDTH fields of BFI or BFC. The machine-
3.3380 + language instruction encodes LSB and MSB. */
3.3381 + {
3.3382 + long msb = (given & 0x001f0000) >> 16;
3.3383 + long lsb = (given & 0x00000f80) >> 7;
3.3384 + long w = msb - lsb + 1;
3.3385 +
3.3386 + if (w > 0)
3.3387 + func (stream, "#%lu, #%lu", lsb, w);
3.3388 + else
3.3389 + func (stream, "(invalid: %lu:%lu)", lsb, msb);
3.3390 + }
3.3391 + break;
3.3392 +
3.3393 + case 'R':
3.3394 + /* Get the PSR/banked register name. */
3.3395 + {
3.3396 + const char * name;
3.3397 + unsigned sysm = (given & 0x004f0000) >> 16;
3.3398 +
3.3399 + sysm |= (given & 0x300) >> 4;
3.3400 + name = banked_regname (sysm);
3.3401 +
3.3402 + if (name != NULL)
3.3403 + func (stream, "%s", name);
3.3404 + else
3.3405 + func (stream, "(UNDEF: %lu)", sysm);
3.3406 + }
3.3407 + break;
3.3408 +
3.3409 + case 'V':
3.3410 + /* 16-bit unsigned immediate from a MOVT or MOVW
3.3411 + instruction, encoded in bits 0:11 and 15:19. */
3.3412 + {
3.3413 + long hi = (given & 0x000f0000) >> 4;
3.3414 + long lo = (given & 0x00000fff);
3.3415 + long imm16 = hi | lo;
3.3416 +
3.3417 + func (stream, "#%lu", imm16);
3.3418 + value_in_comment = imm16;
3.3419 + }
3.3420 + break;
3.3421 +
3.3422 + default:
3.3423 + abort ();
3.3424 + }
3.3425 + }
3.3426 + }
3.3427 + else
3.3428 + func (stream, "%c", *c);
3.3429 + }
3.3430 +
3.3431 + if (value_in_comment > 32 || value_in_comment < -16)
3.3432 + func (stream, "\t; 0x%lx", (value_in_comment & 0xffffffffUL));
3.3433 +
3.3434 + if (is_unpredictable)
3.3435 + func (stream, UNPREDICTABLE_INSTRUCTION);
3.3436 +
3.3437 + return;
3.3438 + }
3.3439 + }
3.3440 + abort ();
3.3441 +}
3.3442 +
3.3443 +/* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
3.3444 +
3.3445 +static void
3.3446 +print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given)
3.3447 +{
3.3448 + const struct opcode16 *insn;
3.3449 + void *stream = info->stream;
3.3450 + fprintf_ftype func = info->fprintf_func;
3.3451 +
3.3452 + for (insn = thumb_opcodes; insn->assembler; insn++)
3.3453 + if ((given & insn->mask) == insn->value)
3.3454 + {
3.3455 + signed long value_in_comment = 0;
3.3456 + const char *c = insn->assembler;
3.3457 +
3.3458 + for (; *c; c++)
3.3459 + {
3.3460 + int domaskpc = 0;
3.3461 + int domasklr = 0;
3.3462 +
3.3463 + if (*c != '%')
3.3464 + {
3.3465 + func (stream, "%c", *c);
3.3466 + continue;
3.3467 + }
3.3468 +
3.3469 + switch (*++c)
3.3470 + {
3.3471 + case '%':
3.3472 + func (stream, "%%");
3.3473 + break;
3.3474 +
3.3475 + case 'c':
3.3476 + if (ifthen_state)
3.3477 + func (stream, "%s", arm_conditional[IFTHEN_COND]);
3.3478 + break;
3.3479 +
3.3480 + case 'C':
3.3481 + if (ifthen_state)
3.3482 + func (stream, "%s", arm_conditional[IFTHEN_COND]);
3.3483 + else
3.3484 + func (stream, "s");
3.3485 + break;
3.3486 +
3.3487 + case 'I':
3.3488 + {
3.3489 + unsigned int tmp;
3.3490 +
3.3491 + ifthen_next_state = given & 0xff;
3.3492 + for (tmp = given << 1; tmp & 0xf; tmp <<= 1)
3.3493 + func (stream, ((given ^ tmp) & 0x10) ? "e" : "t");
3.3494 + func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]);
3.3495 + }
3.3496 + break;
3.3497 +
3.3498 + case 'x':
3.3499 + if (ifthen_next_state)
3.3500 + func (stream, "\t; unpredictable branch in IT block\n");
3.3501 + break;
3.3502 +
3.3503 + case 'X':
3.3504 + if (ifthen_state)
3.3505 + func (stream, "\t; unpredictable <IT:%s>",
3.3506 + arm_conditional[IFTHEN_COND]);
3.3507 + break;
3.3508 +
3.3509 + case 'S':
3.3510 + {
3.3511 + long reg;
3.3512 +
3.3513 + reg = (given >> 3) & 0x7;
3.3514 + if (given & (1 << 6))
3.3515 + reg += 8;
3.3516 +
3.3517 + func (stream, "%s", arm_regnames[reg]);
3.3518 + }
3.3519 + break;
3.3520 +
3.3521 + case 'D':
3.3522 + {
3.3523 + long reg;
3.3524 +
3.3525 + reg = given & 0x7;
3.3526 + if (given & (1 << 7))
3.3527 + reg += 8;
3.3528 +
3.3529 + func (stream, "%s", arm_regnames[reg]);
3.3530 + }
3.3531 + break;
3.3532 +
3.3533 + case 'N':
3.3534 + if (given & (1 << 8))
3.3535 + domasklr = 1;
3.3536 + /* Fall through. */
3.3537 + case 'O':
3.3538 + if (*c == 'O' && (given & (1 << 8)))
3.3539 + domaskpc = 1;
3.3540 + /* Fall through. */
3.3541 + case 'M':
3.3542 + {
3.3543 + int started = 0;
3.3544 + int reg;
3.3545 +
3.3546 + func (stream, "{");
3.3547 +
3.3548 + /* It would be nice if we could spot
3.3549 + ranges, and generate the rS-rE format: */
3.3550 + for (reg = 0; (reg < 8); reg++)
3.3551 + if ((given & (1 << reg)) != 0)
3.3552 + {
3.3553 + if (started)
3.3554 + func (stream, ", ");
3.3555 + started = 1;
3.3556 + func (stream, "%s", arm_regnames[reg]);
3.3557 + }
3.3558 +
3.3559 + if (domasklr)
3.3560 + {
3.3561 + if (started)
3.3562 + func (stream, ", ");
3.3563 + started = 1;
3.3564 + func (stream, arm_regnames[14] /* "lr" */);
3.3565 + }
3.3566 +
3.3567 + if (domaskpc)
3.3568 + {
3.3569 + if (started)
3.3570 + func (stream, ", ");
3.3571 + func (stream, arm_regnames[15] /* "pc" */);
3.3572 + }
3.3573 +
3.3574 + func (stream, "}");
3.3575 + }
3.3576 + break;
3.3577 +
3.3578 + case 'W':
3.3579 + /* Print writeback indicator for a LDMIA. We are doing a
3.3580 + writeback if the base register is not in the register
3.3581 + mask. */
3.3582 + if ((given & (1 << ((given & 0x0700) >> 8))) == 0)
3.3583 + func (stream, "!");
3.3584 + break;
3.3585 +
3.3586 + case 'b':
3.3587 + /* Print ARM V6T2 CZB address: pc+4+6 bits. */
3.3588 + {
3.3589 + bfd_vma address = (pc + 4
3.3590 + + ((given & 0x00f8) >> 2)
3.3591 + + ((given & 0x0200) >> 3));
3.3592 + info->print_address_func (address, info);
3.3593 + }
3.3594 + break;
3.3595 +
3.3596 + case 's':
3.3597 + /* Right shift immediate -- bits 6..10; 1-31 print
3.3598 + as themselves, 0 prints as 32. */
3.3599 + {
3.3600 + long imm = (given & 0x07c0) >> 6;
3.3601 + if (imm == 0)
3.3602 + imm = 32;
3.3603 + func (stream, "#%ld", imm);
3.3604 + }
3.3605 + break;
3.3606 +
3.3607 + case '0': case '1': case '2': case '3': case '4':
3.3608 + case '5': case '6': case '7': case '8': case '9':
3.3609 + {
3.3610 + int bitstart = *c++ - '0';
3.3611 + int bitend = 0;
3.3612 +
3.3613 + while (*c >= '0' && *c <= '9')
3.3614 + bitstart = (bitstart * 10) + *c++ - '0';
3.3615 +
3.3616 + switch (*c)
3.3617 + {
3.3618 + case '-':
3.3619 + {
3.3620 + bfd_vma reg;
3.3621 +
3.3622 + c++;
3.3623 + while (*c >= '0' && *c <= '9')
3.3624 + bitend = (bitend * 10) + *c++ - '0';
3.3625 + if (!bitend)
3.3626 + abort ();
3.3627 + reg = given >> bitstart;
3.3628 + reg &= (2 << (bitend - bitstart)) - 1;
3.3629 +
3.3630 + switch (*c)
3.3631 + {
3.3632 + case 'r':
3.3633 + func (stream, "%s", arm_regnames[reg]);
3.3634 + break;
3.3635 +
3.3636 + case 'd':
3.3637 + func (stream, "%ld", reg);
3.3638 + value_in_comment = reg;
3.3639 + break;
3.3640 +
3.3641 + case 'H':
3.3642 + func (stream, "%ld", reg << 1);
3.3643 + value_in_comment = reg << 1;
3.3644 + break;
3.3645 +
3.3646 + case 'W':
3.3647 + func (stream, "%ld", reg << 2);
3.3648 + value_in_comment = reg << 2;
3.3649 + break;
3.3650 +
3.3651 + case 'a':
3.3652 + /* PC-relative address -- the bottom two
3.3653 + bits of the address are dropped
3.3654 + before the calculation. */
3.3655 + info->print_address_func
3.3656 + (((pc + 4) & ~3) + (reg << 2), info);
3.3657 + value_in_comment = 0;
3.3658 + break;
3.3659 +
3.3660 + case 'x':
3.3661 + func (stream, "0x%04lx", reg);
3.3662 + break;
3.3663 +
3.3664 + case 'B':
3.3665 + reg = ((reg ^ (1 << bitend)) - (1 << bitend));
3.3666 + info->print_address_func (reg * 2 + pc + 4, info);
3.3667 + value_in_comment = 0;
3.3668 + break;
3.3669 +
3.3670 + case 'c':
3.3671 + func (stream, "%s", arm_conditional [reg]);
3.3672 + break;
3.3673 +
3.3674 + default:
3.3675 + abort ();
3.3676 + }
3.3677 + }
3.3678 + break;
3.3679 +
3.3680 + case '\'':
3.3681 + c++;
3.3682 + if ((given & (1 << bitstart)) != 0)
3.3683 + func (stream, "%c", *c);
3.3684 + break;
3.3685 +
3.3686 + case '?':
3.3687 + ++c;
3.3688 + if ((given & (1 << bitstart)) != 0)
3.3689 + func (stream, "%c", *c++);
3.3690 + else
3.3691 + func (stream, "%c", *++c);
3.3692 + break;
3.3693 +
3.3694 + default:
3.3695 + abort ();
3.3696 + }
3.3697 + }
3.3698 + break;
3.3699 +
3.3700 + default:
3.3701 + abort ();
3.3702 + }
3.3703 + }
3.3704 +
3.3705 + if (value_in_comment > 32 || value_in_comment < -16)
3.3706 + func (stream, "\t; 0x%lx", value_in_comment);
3.3707 + return;
3.3708 + }
3.3709 +
3.3710 + /* No match. */
3.3711 + abort ();
3.3712 +}
3.3713 +
3.3714 +/* Return the name of an V7M special register. */
3.3715 +
3.3716 +static const char *
3.3717 +psr_name (int regno)
3.3718 +{
3.3719 + switch (regno)
3.3720 + {
3.3721 + case 0: return "APSR";
3.3722 + case 1: return "IAPSR";
3.3723 + case 2: return "EAPSR";
3.3724 + case 3: return "PSR";
3.3725 + case 5: return "IPSR";
3.3726 + case 6: return "EPSR";
3.3727 + case 7: return "IEPSR";
3.3728 + case 8: return "MSP";
3.3729 + case 9: return "PSP";
3.3730 + case 16: return "PRIMASK";
3.3731 + case 17: return "BASEPRI";
3.3732 + case 18: return "BASEPRI_MAX";
3.3733 + case 19: return "FAULTMASK";
3.3734 + case 20: return "CONTROL";
3.3735 + default: return "<unknown>";
3.3736 + }
3.3737 +}
3.3738 +
3.3739 +/* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
3.3740 +
3.3741 +static void
3.3742 +print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
3.3743 +{
3.3744 + const struct opcode32 *insn;
3.3745 + void *stream = info->stream;
3.3746 + fprintf_ftype func = info->fprintf_func;
3.3747 +
3.3748 + if (print_insn_coprocessor (pc, info, given, TRUE))
3.3749 + return;
3.3750 +
3.3751 + if (print_insn_neon (info, given, TRUE))
3.3752 + return;
3.3753 +
3.3754 + for (insn = thumb32_opcodes; insn->assembler; insn++)
3.3755 + if ((given & insn->mask) == insn->value)
3.3756 + {
3.3757 + bfd_boolean is_unpredictable = FALSE;
3.3758 + signed long value_in_comment = 0;
3.3759 + const char *c = insn->assembler;
3.3760 +
3.3761 + for (; *c; c++)
3.3762 + {
3.3763 + if (*c != '%')
3.3764 + {
3.3765 + func (stream, "%c", *c);
3.3766 + continue;
3.3767 + }
3.3768 +
3.3769 + switch (*++c)
3.3770 + {
3.3771 + case '%':
3.3772 + func (stream, "%%");
3.3773 + break;
3.3774 +
3.3775 + case 'c':
3.3776 + if (ifthen_state)
3.3777 + func (stream, "%s", arm_conditional[IFTHEN_COND]);
3.3778 + break;
3.3779 +
3.3780 + case 'x':
3.3781 + if (ifthen_next_state)
3.3782 + func (stream, "\t; unpredictable branch in IT block\n");
3.3783 + break;
3.3784 +
3.3785 + case 'X':
3.3786 + if (ifthen_state)
3.3787 + func (stream, "\t; unpredictable <IT:%s>",
3.3788 + arm_conditional[IFTHEN_COND]);
3.3789 + break;
3.3790 +
3.3791 + case 'I':
3.3792 + {
3.3793 + unsigned int imm12 = 0;
3.3794 +
3.3795 + imm12 |= (given & 0x000000ffu);
3.3796 + imm12 |= (given & 0x00007000u) >> 4;
3.3797 + imm12 |= (given & 0x04000000u) >> 15;
3.3798 + func (stream, "#%u", imm12);
3.3799 + value_in_comment = imm12;
3.3800 + }
3.3801 + break;
3.3802 +
3.3803 + case 'M':
3.3804 + {
3.3805 + unsigned int bits = 0, imm, imm8, mod;
3.3806 +
3.3807 + bits |= (given & 0x000000ffu);
3.3808 + bits |= (given & 0x00007000u) >> 4;
3.3809 + bits |= (given & 0x04000000u) >> 15;
3.3810 + imm8 = (bits & 0x0ff);
3.3811 + mod = (bits & 0xf00) >> 8;
3.3812 + switch (mod)
3.3813 + {
3.3814 + case 0: imm = imm8; break;
3.3815 + case 1: imm = ((imm8 << 16) | imm8); break;
3.3816 + case 2: imm = ((imm8 << 24) | (imm8 << 8)); break;
3.3817 + case 3: imm = ((imm8 << 24) | (imm8 << 16) | (imm8 << 8) | imm8); break;
3.3818 + default:
3.3819 + mod = (bits & 0xf80) >> 7;
3.3820 + imm8 = (bits & 0x07f) | 0x80;
3.3821 + imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff);
3.3822 + }
3.3823 + func (stream, "#%u", imm);
3.3824 + value_in_comment = imm;
3.3825 + }
3.3826 + break;
3.3827 +
3.3828 + case 'J':
3.3829 + {
3.3830 + unsigned int imm = 0;
3.3831 +
3.3832 + imm |= (given & 0x000000ffu);
3.3833 + imm |= (given & 0x00007000u) >> 4;
3.3834 + imm |= (given & 0x04000000u) >> 15;
3.3835 + imm |= (given & 0x000f0000u) >> 4;
3.3836 + func (stream, "#%u", imm);
3.3837 + value_in_comment = imm;
3.3838 + }
3.3839 + break;
3.3840 +
3.3841 + case 'K':
3.3842 + {
3.3843 + unsigned int imm = 0;
3.3844 +
3.3845 + imm |= (given & 0x000f0000u) >> 16;
3.3846 + imm |= (given & 0x00000ff0u) >> 0;
3.3847 + imm |= (given & 0x0000000fu) << 12;
3.3848 + func (stream, "#%u", imm);
3.3849 + value_in_comment = imm;
3.3850 + }
3.3851 + break;
3.3852 +
3.3853 + case 'V':
3.3854 + {
3.3855 + unsigned int imm = 0;
3.3856 +
3.3857 + imm |= (given & 0x00000fffu);
3.3858 + imm |= (given & 0x000f0000u) >> 4;
3.3859 + func (stream, "#%u", imm);
3.3860 + value_in_comment = imm;
3.3861 + }
3.3862 + break;
3.3863 +
3.3864 + case 'S':
3.3865 + {
3.3866 + unsigned int reg = (given & 0x0000000fu);
3.3867 + unsigned int stp = (given & 0x00000030u) >> 4;
3.3868 + unsigned int imm = 0;
3.3869 + imm |= (given & 0x000000c0u) >> 6;
3.3870 + imm |= (given & 0x00007000u) >> 10;
3.3871 +
3.3872 + func (stream, "%s", arm_regnames[reg]);
3.3873 + switch (stp)
3.3874 + {
3.3875 + case 0:
3.3876 + if (imm > 0)
3.3877 + func (stream, ", lsl #%u", imm);
3.3878 + break;
3.3879 +
3.3880 + case 1:
3.3881 + if (imm == 0)
3.3882 + imm = 32;
3.3883 + func (stream, ", lsr #%u", imm);
3.3884 + break;
3.3885 +
3.3886 + case 2:
3.3887 + if (imm == 0)
3.3888 + imm = 32;
3.3889 + func (stream, ", asr #%u", imm);
3.3890 + break;
3.3891 +
3.3892 + case 3:
3.3893 + if (imm == 0)
3.3894 + func (stream, ", rrx");
3.3895 + else
3.3896 + func (stream, ", ror #%u", imm);
3.3897 + }
3.3898 + }
3.3899 + break;
3.3900 +
3.3901 + case 'a':
3.3902 + {
3.3903 + unsigned int Rn = (given & 0x000f0000) >> 16;
3.3904 + unsigned int U = ! NEGATIVE_BIT_SET;
3.3905 + unsigned int op = (given & 0x00000f00) >> 8;
3.3906 + unsigned int i12 = (given & 0x00000fff);
3.3907 + unsigned int i8 = (given & 0x000000ff);
3.3908 + bfd_boolean writeback = FALSE, postind = FALSE;
3.3909 + bfd_vma offset = 0;
3.3910 +
3.3911 + func (stream, "[%s", arm_regnames[Rn]);
3.3912 + if (U) /* 12-bit positive immediate offset. */
3.3913 + {
3.3914 + offset = i12;
3.3915 + if (Rn != 15)
3.3916 + value_in_comment = offset;
3.3917 + }
3.3918 + else if (Rn == 15) /* 12-bit negative immediate offset. */
3.3919 + offset = - (int) i12;
3.3920 + else if (op == 0x0) /* Shifted register offset. */
3.3921 + {
3.3922 + unsigned int Rm = (i8 & 0x0f);
3.3923 + unsigned int sh = (i8 & 0x30) >> 4;
3.3924 +
3.3925 + func (stream, ", %s", arm_regnames[Rm]);
3.3926 + if (sh)
3.3927 + func (stream, ", lsl #%u", sh);
3.3928 + func (stream, "]");
3.3929 + break;
3.3930 + }
3.3931 + else switch (op)
3.3932 + {
3.3933 + case 0xE: /* 8-bit positive immediate offset. */
3.3934 + offset = i8;
3.3935 + break;
3.3936 +
3.3937 + case 0xC: /* 8-bit negative immediate offset. */
3.3938 + offset = -i8;
3.3939 + break;
3.3940 +
3.3941 + case 0xF: /* 8-bit + preindex with wb. */
3.3942 + offset = i8;
3.3943 + writeback = TRUE;
3.3944 + break;
3.3945 +
3.3946 + case 0xD: /* 8-bit - preindex with wb. */
3.3947 + offset = -i8;
3.3948 + writeback = TRUE;
3.3949 + break;
3.3950 +
3.3951 + case 0xB: /* 8-bit + postindex. */
3.3952 + offset = i8;
3.3953 + postind = TRUE;
3.3954 + break;
3.3955 +
3.3956 + case 0x9: /* 8-bit - postindex. */
3.3957 + offset = -i8;
3.3958 + postind = TRUE;
3.3959 + break;
3.3960 +
3.3961 + default:
3.3962 + func (stream, ", <undefined>]");
3.3963 + goto skip;
3.3964 + }
3.3965 +
3.3966 + if (postind)
3.3967 + func (stream, "], #%d", offset);
3.3968 + else
3.3969 + {
3.3970 + if (offset)
3.3971 + func (stream, ", #%d", offset);
3.3972 + func (stream, writeback ? "]!" : "]");
3.3973 + }
3.3974 +
3.3975 + if (Rn == 15)
3.3976 + {
3.3977 + func (stream, "\t; ");
3.3978 + info->print_address_func (((pc + 4) & ~3) + offset, info);
3.3979 + }
3.3980 + }
3.3981 + skip:
3.3982 + break;
3.3983 +
3.3984 + case 'A':
3.3985 + {
3.3986 + unsigned int U = ! NEGATIVE_BIT_SET;
3.3987 + unsigned int W = WRITEBACK_BIT_SET;
3.3988 + unsigned int Rn = (given & 0x000f0000) >> 16;
3.3989 + unsigned int off = (given & 0x000000ff);
3.3990 +
3.3991 + func (stream, "[%s", arm_regnames[Rn]);
3.3992 +
3.3993 + if (PRE_BIT_SET)
3.3994 + {
3.3995 + if (off || !U)
3.3996 + {
3.3997 + func (stream, ", #%c%u", U ? '+' : '-', off * 4);
3.3998 + value_in_comment = off * 4 * U ? 1 : -1;
3.3999 + }
3.4000 + func (stream, "]");
3.4001 + if (W)
3.4002 + func (stream, "!");
3.4003 + }
3.4004 + else
3.4005 + {
3.4006 + func (stream, "], ");
3.4007 + if (W)
3.4008 + {
3.4009 + func (stream, "#%c%u", U ? '+' : '-', off * 4);
3.4010 + value_in_comment = off * 4 * U ? 1 : -1;
3.4011 + }
3.4012 + else
3.4013 + {
3.4014 + func (stream, "{%u}", off);
3.4015 + value_in_comment = off;
3.4016 + }
3.4017 + }
3.4018 + }
3.4019 + break;
3.4020 +
3.4021 + case 'w':
3.4022 + {
3.4023 + unsigned int Sbit = (given & 0x01000000) >> 24;
3.4024 + unsigned int type = (given & 0x00600000) >> 21;
3.4025 +
3.4026 + switch (type)
3.4027 + {
3.4028 + case 0: func (stream, Sbit ? "sb" : "b"); break;
3.4029 + case 1: func (stream, Sbit ? "sh" : "h"); break;
3.4030 + case 2:
3.4031 + if (Sbit)
3.4032 + func (stream, "??");
3.4033 + break;
3.4034 + case 3:
3.4035 + func (stream, "??");
3.4036 + break;
3.4037 + }
3.4038 + }
3.4039 + break;
3.4040 +
3.4041 + case 'm':
3.4042 + {
3.4043 + int started = 0;
3.4044 + int reg;
3.4045 +
3.4046 + func (stream, "{");
3.4047 + for (reg = 0; reg < 16; reg++)
3.4048 + if ((given & (1 << reg)) != 0)
3.4049 + {
3.4050 + if (started)
3.4051 + func (stream, ", ");
3.4052 + started = 1;
3.4053 + func (stream, "%s", arm_regnames[reg]);
3.4054 + }
3.4055 + func (stream, "}");
3.4056 + }
3.4057 + break;
3.4058 +
3.4059 + case 'E':
3.4060 + {
3.4061 + unsigned int msb = (given & 0x0000001f);
3.4062 + unsigned int lsb = 0;
3.4063 +
3.4064 + lsb |= (given & 0x000000c0u) >> 6;
3.4065 + lsb |= (given & 0x00007000u) >> 10;
3.4066 + func (stream, "#%u, #%u", lsb, msb - lsb + 1);
3.4067 + }
3.4068 + break;
3.4069 +
3.4070 + case 'F':
3.4071 + {
3.4072 + unsigned int width = (given & 0x0000001f) + 1;
3.4073 + unsigned int lsb = 0;
3.4074 +
3.4075 + lsb |= (given & 0x000000c0u) >> 6;
3.4076 + lsb |= (given & 0x00007000u) >> 10;
3.4077 + func (stream, "#%u, #%u", lsb, width);
3.4078 + }
3.4079 + break;
3.4080 +
3.4081 + case 'b':
3.4082 + {
3.4083 + unsigned int S = (given & 0x04000000u) >> 26;
3.4084 + unsigned int J1 = (given & 0x00002000u) >> 13;
3.4085 + unsigned int J2 = (given & 0x00000800u) >> 11;
3.4086 + bfd_vma offset = 0;
3.4087 +
3.4088 + offset |= !S << 20;
3.4089 + offset |= J2 << 19;
3.4090 + offset |= J1 << 18;
3.4091 + offset |= (given & 0x003f0000) >> 4;
3.4092 + offset |= (given & 0x000007ff) << 1;
3.4093 + offset -= (1 << 20);
3.4094 +
3.4095 + info->print_address_func (pc + 4 + offset, info);
3.4096 + }
3.4097 + break;
3.4098 +
3.4099 + case 'B':
3.4100 + {
3.4101 + unsigned int S = (given & 0x04000000u) >> 26;
3.4102 + unsigned int I1 = (given & 0x00002000u) >> 13;
3.4103 + unsigned int I2 = (given & 0x00000800u) >> 11;
3.4104 + bfd_vma offset = 0;
3.4105 +
3.4106 + offset |= !S << 24;
3.4107 + offset |= !(I1 ^ S) << 23;
3.4108 + offset |= !(I2 ^ S) << 22;
3.4109 + offset |= (given & 0x03ff0000u) >> 4;
3.4110 + offset |= (given & 0x000007ffu) << 1;
3.4111 + offset -= (1 << 24);
3.4112 + offset += pc + 4;
3.4113 +
3.4114 + /* BLX target addresses are always word aligned. */
3.4115 + if ((given & 0x00001000u) == 0)
3.4116 + offset &= ~2u;
3.4117 +
3.4118 + info->print_address_func (offset, info);
3.4119 + }
3.4120 + break;
3.4121 +
3.4122 + case 's':
3.4123 + {
3.4124 + unsigned int shift = 0;
3.4125 +
3.4126 + shift |= (given & 0x000000c0u) >> 6;
3.4127 + shift |= (given & 0x00007000u) >> 10;
3.4128 + if (WRITEBACK_BIT_SET)
3.4129 + func (stream, ", asr #%u", shift);
3.4130 + else if (shift)
3.4131 + func (stream, ", lsl #%u", shift);
3.4132 + /* else print nothing - lsl #0 */
3.4133 + }
3.4134 + break;
3.4135 +
3.4136 + case 'R':
3.4137 + {
3.4138 + unsigned int rot = (given & 0x00000030) >> 4;
3.4139 +
3.4140 + if (rot)
3.4141 + func (stream, ", ror #%u", rot * 8);
3.4142 + }
3.4143 + break;
3.4144 +
3.4145 + case 'U':
3.4146 + if ((given & 0xf0) == 0x60)
3.4147 + {
3.4148 + switch (given & 0xf)
3.4149 + {
3.4150 + case 0xf: func (stream, "sy"); break;
3.4151 + default:
3.4152 + func (stream, "#%d", (int) given & 0xf);
3.4153 + break;
3.4154 + }
3.4155 + }
3.4156 + else
3.4157 + {
3.4158 + switch (given & 0xf)
3.4159 + {
3.4160 + case 0xf: func (stream, "sy"); break;
3.4161 + case 0x7: func (stream, "un"); break;
3.4162 + case 0xe: func (stream, "st"); break;
3.4163 + case 0x6: func (stream, "unst"); break;
3.4164 + case 0xb: func (stream, "ish"); break;
3.4165 + case 0xa: func (stream, "ishst"); break;
3.4166 + case 0x3: func (stream, "osh"); break;
3.4167 + case 0x2: func (stream, "oshst"); break;
3.4168 + default:
3.4169 + func (stream, "#%d", (int) given & 0xf);
3.4170 + break;
3.4171 + }
3.4172 + }
3.4173 + break;
3.4174 +
3.4175 + case 'C':
3.4176 + if ((given & 0xff) == 0)
3.4177 + {
3.4178 + func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C');
3.4179 + if (given & 0x800)
3.4180 + func (stream, "f");
3.4181 + if (given & 0x400)
3.4182 + func (stream, "s");
3.4183 + if (given & 0x200)
3.4184 + func (stream, "x");
3.4185 + if (given & 0x100)
3.4186 + func (stream, "c");
3.4187 + }
3.4188 + else if ((given & 0x20) == 0x20)
3.4189 + {
3.4190 + char const* name;
3.4191 + unsigned sysm = (given & 0xf00) >> 8;
3.4192 +
3.4193 + sysm |= (given & 0x30);
3.4194 + sysm |= (given & 0x00100000) >> 14;
3.4195 + name = banked_regname (sysm);
3.4196 +
3.4197 + if (name != NULL)
3.4198 + func (stream, "%s", name);
3.4199 + else
3.4200 + func (stream, "(UNDEF: %lu)", sysm);
3.4201 + }
3.4202 + else
3.4203 + {
3.4204 + func (stream, psr_name (given & 0xff));
3.4205 + }
3.4206 + break;
3.4207 +
3.4208 + case 'D':
3.4209 + if (((given & 0xff) == 0)
3.4210 + || ((given & 0x20) == 0x20))
3.4211 + {
3.4212 + char const* name;
3.4213 + unsigned sm = (given & 0xf0000) >> 16;
3.4214 +
3.4215 + sm |= (given & 0x30);
3.4216 + sm |= (given & 0x00100000) >> 14;
3.4217 + name = banked_regname (sm);
3.4218 +
3.4219 + if (name != NULL)
3.4220 + func (stream, "%s", name);
3.4221 + else
3.4222 + func (stream, "(UNDEF: %lu)", sm);
3.4223 + }
3.4224 + else
3.4225 + func (stream, psr_name (given & 0xff));
3.4226 + break;
3.4227 +
3.4228 + case '0': case '1': case '2': case '3': case '4':
3.4229 + case '5': case '6': case '7': case '8': case '9':
3.4230 + {
3.4231 + int width;
3.4232 + unsigned long val;
3.4233 +
3.4234 + c = arm_decode_bitfield (c, given, &val, &width);
3.4235 +
3.4236 + switch (*c)
3.4237 + {
3.4238 + case 'd':
3.4239 + func (stream, "%lu", val);
3.4240 + value_in_comment = val;
3.4241 + break;
3.4242 +
3.4243 + case 'W':
3.4244 + func (stream, "%lu", val * 4);
3.4245 + value_in_comment = val * 4;
3.4246 + break;
3.4247 +
3.4248 + case 'R':
3.4249 + if (val == 15)
3.4250 + is_unpredictable = TRUE;
3.4251 + /* Fall through. */
3.4252 + case 'r':
3.4253 + func (stream, "%s", arm_regnames[val]);
3.4254 + break;
3.4255 +
3.4256 + case 'c':
3.4257 + func (stream, "%s", arm_conditional[val]);
3.4258 + break;
3.4259 +
3.4260 + case '\'':
3.4261 + c++;
3.4262 + if (val == ((1ul << width) - 1))
3.4263 + func (stream, "%c", *c);
3.4264 + break;
3.4265 +
3.4266 + case '`':
3.4267 + c++;
3.4268 + if (val == 0)
3.4269 + func (stream, "%c", *c);
3.4270 + break;
3.4271 +
3.4272 + case '?':
3.4273 + func (stream, "%c", c[(1 << width) - (int) val]);
3.4274 + c += 1 << width;
3.4275 + break;
3.4276 +
3.4277 + case 'x':
3.4278 + func (stream, "0x%lx", val & 0xffffffffUL);
3.4279 + break;
3.4280 +
3.4281 + default:
3.4282 + abort ();
3.4283 + }
3.4284 + }
3.4285 + break;
3.4286 +
3.4287 + case 'L':
3.4288 + /* PR binutils/12534
3.4289 + If we have a PC relative offset in an LDRD or STRD
3.4290 + instructions then display the decoded address. */
3.4291 + if (((given >> 16) & 0xf) == 0xf)
3.4292 + {
3.4293 + bfd_vma offset = (given & 0xff) * 4;
3.4294 +
3.4295 + if ((given & (1 << 23)) == 0)
3.4296 + offset = - offset;
3.4297 + func (stream, "\t; ");
3.4298 + info->print_address_func ((pc & ~3) + 4 + offset, info);
3.4299 + }
3.4300 + break;
3.4301 +
3.4302 + default:
3.4303 + abort ();
3.4304 + }
3.4305 + }
3.4306 +
3.4307 + if (value_in_comment > 32 || value_in_comment < -16)
3.4308 + func (stream, "\t; 0x%lx", value_in_comment);
3.4309 +
3.4310 + if (is_unpredictable)
3.4311 + func (stream, UNPREDICTABLE_INSTRUCTION);
3.4312 +
3.4313 + return;
3.4314 + }
3.4315 +
3.4316 + /* No match. */
3.4317 + abort ();
3.4318 +}
3.4319 +
3.4320 +/* Print data bytes on INFO->STREAM. */
3.4321 +
3.4322 +static void
3.4323 +print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
3.4324 + struct disassemble_info *info,
3.4325 + long given)
3.4326 +{
3.4327 + switch (info->bytes_per_chunk)
3.4328 + {
3.4329 + case 1:
3.4330 + info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
3.4331 + break;
3.4332 + case 2:
3.4333 + info->fprintf_func (info->stream, ".short\t0x%04lx", given);
3.4334 + break;
3.4335 + case 4:
3.4336 + info->fprintf_func (info->stream, ".word\t0x%08lx", given);
3.4337 + break;
3.4338 + default:
3.4339 + abort ();
3.4340 + }
3.4341 +}
3.4342 +
3.4343 +/* Disallow mapping symbols ($a, $b, $d, $t etc) from
3.4344 + being displayed in symbol relative addresses. */
3.4345 +
3.4346 +bfd_boolean
3.4347 +arm_symbol_is_valid (asymbol * sym,
3.4348 + struct disassemble_info * info ATTRIBUTE_UNUSED)
3.4349 +{
3.4350 + const char * name;
3.4351 +
3.4352 + if (sym == NULL)
3.4353 + return FALSE;
3.4354 +
3.4355 + name = bfd_asymbol_name (sym);
3.4356 +
3.4357 + return (name && *name != '$');
3.4358 +}
3.4359 +
3.4360 +/* Parse an individual disassembler option. */
3.4361 +
3.4362 +void
3.4363 +parse_arm_disassembler_option (char *option)
3.4364 +{
3.4365 + if (option == NULL)
3.4366 + return;
3.4367 +
3.4368 + if (CONST_STRNEQ (option, "reg-names-"))
3.4369 + {
3.4370 + int i;
3.4371 +
3.4372 + option += 10;
3.4373 +
3.4374 + for (i = NUM_ARM_REGNAMES; i--;)
3.4375 + if (strneq (option, regnames[i].name, strlen (regnames[i].name)))
3.4376 + {
3.4377 + regname_selected = i;
3.4378 + break;
3.4379 + }
3.4380 +
3.4381 + if (i < 0)
3.4382 + /* XXX - should break 'option' at following delimiter. */
3.4383 + fprintf (stderr, _("Unrecognised register name set: %s\n"), option);
3.4384 + }
3.4385 + else if (CONST_STRNEQ (option, "force-thumb"))
3.4386 + force_thumb = 1;
3.4387 + else if (CONST_STRNEQ (option, "no-force-thumb"))
3.4388 + force_thumb = 0;
3.4389 + else
3.4390 + /* XXX - should break 'option' at following delimiter. */
3.4391 + fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option);
3.4392 +
3.4393 + return;
3.4394 +}
3.4395 +
3.4396 +/* Parse the string of disassembler options, spliting it at whitespaces
3.4397 + or commas. (Whitespace separators supported for backwards compatibility). */
3.4398 +
3.4399 +static void
3.4400 +parse_disassembler_options (char *options)
3.4401 +{
3.4402 + if (options == NULL)
3.4403 + return;
3.4404 +
3.4405 + while (*options)
3.4406 + {
3.4407 + parse_arm_disassembler_option (options);
3.4408 +
3.4409 + /* Skip forward to next seperator. */
3.4410 + while ((*options) && (! ISSPACE (*options)) && (*options != ','))
3.4411 + ++ options;
3.4412 + /* Skip forward past seperators. */
3.4413 + while (ISSPACE (*options) || (*options == ','))
3.4414 + ++ options;
3.4415 + }
3.4416 +}
3.4417 +
3.4418 +/* Search back through the insn stream to determine if this instruction is
3.4419 + conditionally executed. */
3.4420 +
3.4421 +static void
3.4422 +find_ifthen_state (bfd_vma pc,
3.4423 + struct disassemble_info *info,
3.4424 + bfd_boolean little)
3.4425 +{
3.4426 + unsigned char b[2];
3.4427 + unsigned int insn;
3.4428 + int status;
3.4429 + /* COUNT is twice the number of instructions seen. It will be odd if we
3.4430 + just crossed an instruction boundary. */
3.4431 + int count;
3.4432 + int it_count;
3.4433 + unsigned int seen_it;
3.4434 + bfd_vma addr;
3.4435 +
3.4436 + ifthen_address = pc;
3.4437 + ifthen_state = 0;
3.4438 +
3.4439 + addr = pc;
3.4440 + count = 1;
3.4441 + it_count = 0;
3.4442 + seen_it = 0;
3.4443 + /* Scan backwards looking for IT instructions, keeping track of where
3.4444 + instruction boundaries are. We don't know if something is actually an
3.4445 + IT instruction until we find a definite instruction boundary. */
3.4446 + for (;;)
3.4447 + {
3.4448 + if (addr == 0 || info->symbol_at_address_func (addr, info))
3.4449 + {
3.4450 + /* A symbol must be on an instruction boundary, and will not
3.4451 + be within an IT block. */
3.4452 + if (seen_it && (count & 1))
3.4453 + break;
3.4454 +
3.4455 + return;
3.4456 + }
3.4457 + addr -= 2;
3.4458 + status = info->read_memory_func (addr, (bfd_byte *) b, 2, info);
3.4459 + if (status)
3.4460 + return;
3.4461 +
3.4462 + if (little)
3.4463 + insn = (b[0]) | (b[1] << 8);
3.4464 + else
3.4465 + insn = (b[1]) | (b[0] << 8);
3.4466 + if (seen_it)
3.4467 + {
3.4468 + if ((insn & 0xf800) < 0xe800)
3.4469 + {
3.4470 + /* Addr + 2 is an instruction boundary. See if this matches
3.4471 + the expected boundary based on the position of the last
3.4472 + IT candidate. */
3.4473 + if (count & 1)
3.4474 + break;
3.4475 + seen_it = 0;
3.4476 + }
3.4477 + }
3.4478 + if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0)
3.4479 + {
3.4480 + /* This could be an IT instruction. */
3.4481 + seen_it = insn;
3.4482 + it_count = count >> 1;
3.4483 + }
3.4484 + if ((insn & 0xf800) >= 0xe800)
3.4485 + count++;
3.4486 + else
3.4487 + count = (count + 2) | 1;
3.4488 + /* IT blocks contain at most 4 instructions. */
3.4489 + if (count >= 8 && !seen_it)
3.4490 + return;
3.4491 + }
3.4492 + /* We found an IT instruction. */
3.4493 + ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f);
3.4494 + if ((ifthen_state & 0xf) == 0)
3.4495 + ifthen_state = 0;
3.4496 +}
3.4497 +
3.4498 +/* Returns nonzero and sets *MAP_TYPE if the N'th symbol is a
3.4499 + mapping symbol. */
3.4500 +
3.4501 +static int
3.4502 +is_mapping_symbol (struct disassemble_info *info, int n,
3.4503 + enum map_type *map_type)
3.4504 +{
3.4505 + const char *name;
3.4506 +
3.4507 + name = bfd_asymbol_name (info->symtab[n]);
3.4508 + if (name[0] == '$' && (name[1] == 'a' || name[1] == 't' || name[1] == 'd')
3.4509 + && (name[2] == 0 || name[2] == '.'))
3.4510 + {
3.4511 + *map_type = ((name[1] == 'a') ? MAP_ARM
3.4512 + : (name[1] == 't') ? MAP_THUMB
3.4513 + : MAP_DATA);
3.4514 + return TRUE;
3.4515 + }
3.4516 +
3.4517 + return FALSE;
3.4518 +}
3.4519 +
3.4520 +/* Try to infer the code type (ARM or Thumb) from a mapping symbol.
3.4521 + Returns nonzero if *MAP_TYPE was set. */
3.4522 +
3.4523 +static int
3.4524 +get_map_sym_type (struct disassemble_info *info,
3.4525 + int n,
3.4526 + enum map_type *map_type)
3.4527 +{
3.4528 + /* If the symbol is in a different section, ignore it. */
3.4529 + if (info->section != NULL && info->section != info->symtab[n]->section)
3.4530 + return FALSE;
3.4531 +
3.4532 + return is_mapping_symbol (info, n, map_type);
3.4533 +}
3.4534 +
3.4535 +/* Try to infer the code type (ARM or Thumb) from a non-mapping symbol.
3.4536 + Returns nonzero if *MAP_TYPE was set. */
3.4537 +
3.4538 +static int
3.4539 +get_sym_code_type (struct disassemble_info *info,
3.4540 + int n,
3.4541 + enum map_type *map_type)
3.4542 +{
3.4543 +#if 0
3.4544 + elf_symbol_type *es;
3.4545 + unsigned int type;
3.4546 +
3.4547 + /* If the symbol is in a different section, ignore it. */
3.4548 + if (info->section != NULL && info->section != info->symtab[n]->section)
3.4549 + return FALSE;
3.4550 +
3.4551 + es = *(elf_symbol_type **)(info->symtab + n);
3.4552 + type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
3.4553 +
3.4554 + /* If the symbol has function type then use that. */
3.4555 + if (type == STT_FUNC || type == STT_GNU_IFUNC)
3.4556 + {
3.4557 + if (ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym) == ST_BRANCH_TO_THUMB)
3.4558 + *map_type = MAP_THUMB;
3.4559 + else
3.4560 + *map_type = MAP_ARM;
3.4561 + return TRUE;
3.4562 + }
3.4563 +#endif
3.4564 + return FALSE;
3.4565 +}
3.4566 +
3.4567 +/* Given a bfd_mach_arm_XXX value, this function fills in the fields
3.4568 + of the supplied arm_feature_set structure with bitmasks indicating
3.4569 + the support base architectures and coprocessor extensions.
3.4570 +
3.4571 + FIXME: This could more efficiently implemented as a constant array,
3.4572 + although it would also be less robust. */
3.4573 +
3.4574 +static void
3.4575 +select_arm_features (unsigned long mach,
3.4576 + arm_feature_set * features)
3.4577 +{
3.4578 +#undef ARM_FEATURE
3.4579 +#define ARM_FEATURE(ARCH,CEXT) \
3.4580 + features->core = (ARCH); \
3.4581 + features->coproc = (CEXT) | FPU_FPA; \
3.4582 + return
3.4583 +
3.4584 + switch (mach)
3.4585 + {
3.4586 + case bfd_mach_arm_2: ARM_ARCH_V2;
3.4587 + case bfd_mach_arm_2a: ARM_ARCH_V2S;
3.4588 + case bfd_mach_arm_3: ARM_ARCH_V3;
3.4589 + case bfd_mach_arm_3M: ARM_ARCH_V3M;
3.4590 + case bfd_mach_arm_4: ARM_ARCH_V4;
3.4591 + case bfd_mach_arm_4T: ARM_ARCH_V4T;
3.4592 + case bfd_mach_arm_5: ARM_ARCH_V5;
3.4593 + case bfd_mach_arm_5T: ARM_ARCH_V5T;
3.4594 + case bfd_mach_arm_5TE: ARM_ARCH_V5TE;
3.4595 + case bfd_mach_arm_XScale: ARM_ARCH_XSCALE;
3.4596 + case bfd_mach_arm_ep9312: ARM_FEATURE (ARM_AEXT_V4T, ARM_CEXT_MAVERICK | FPU_MAVERICK);
3.4597 + case bfd_mach_arm_iWMMXt: ARM_ARCH_IWMMXT;
3.4598 + case bfd_mach_arm_iWMMXt2: ARM_ARCH_IWMMXT2;
3.4599 + /* If the machine type is unknown allow all
3.4600 + architecture types and all extensions. */
3.4601 + case bfd_mach_arm_unknown: ARM_FEATURE (-1UL, -1UL);
3.4602 + default:
3.4603 + abort ();
3.4604 + }
3.4605 +}
3.4606 +
3.4607 +
3.4608 +/* NOTE: There are no checks in these routines that
3.4609 + the relevant number of data bytes exist. */
3.4610 +
3.4611 +static int
3.4612 +print_insn (bfd_vma pc, struct disassemble_info *info, bfd_boolean little)
3.4613 +{
3.4614 + unsigned char b[4];
3.4615 + long given;
3.4616 + int status;
3.4617 + int is_thumb = FALSE;
3.4618 + int is_data = FALSE;
3.4619 + int little_code;
3.4620 + unsigned int size = 4;
3.4621 + void (*printer) (bfd_vma, struct disassemble_info *, long);
3.4622 + bfd_boolean found = FALSE;
3.4623 + struct arm_private_data *private_data;
3.4624 +
3.4625 + if (info->disassembler_options)
3.4626 + {
3.4627 + parse_disassembler_options (info->disassembler_options);
3.4628 +
3.4629 + /* To avoid repeated parsing of these options, we remove them here. */
3.4630 + info->disassembler_options = NULL;
3.4631 + }
3.4632 +
3.4633 + /* PR 10288: Control which instructions will be disassembled. */
3.4634 + if (info->private_data == NULL)
3.4635 + {
3.4636 + static struct arm_private_data private;
3.4637 +
3.4638 + if ((info->flags & USER_SPECIFIED_MACHINE_TYPE) == 0)
3.4639 + /* If the user did not use the -m command line switch then default to
3.4640 + disassembling all types of ARM instruction.
3.4641 +
3.4642 + The info->mach value has to be ignored as this will be based on
3.4643 + the default archictecture for the target and/or hints in the notes
3.4644 + section, but it will never be greater than the current largest arm
3.4645 + machine value (iWMMXt2), which is only equivalent to the V5TE
3.4646 + architecture. ARM architectures have advanced beyond the machine
3.4647 + value encoding, and these newer architectures would be ignored if
3.4648 + the machine value was used.
3.4649 +
3.4650 + Ie the -m switch is used to restrict which instructions will be
3.4651 + disassembled. If it is necessary to use the -m switch to tell
3.4652 + objdump that an ARM binary is being disassembled, eg because the
3.4653 + input is a raw binary file, but it is also desired to disassemble
3.4654 + all ARM instructions then use "-marm". This will select the
3.4655 + "unknown" arm architecture which is compatible with any ARM
3.4656 + instruction. */
3.4657 + info->mach = bfd_mach_arm_unknown;
3.4658 +
3.4659 + /* Compute the architecture bitmask from the machine number.
3.4660 + Note: This assumes that the machine number will not change
3.4661 + during disassembly.... */
3.4662 + select_arm_features (info->mach, & private.features);
3.4663 +
3.4664 + private.has_mapping_symbols = -1;
3.4665 + private.last_mapping_sym = -1;
3.4666 + private.last_mapping_addr = 0;
3.4667 +
3.4668 + info->private_data = & private;
3.4669 + }
3.4670 +
3.4671 + private_data = info->private_data;
3.4672 +
3.4673 + /* Decide if our code is going to be little-endian, despite what the
3.4674 + function argument might say. */
3.4675 + little_code = ((info->endian_code == BFD_ENDIAN_LITTLE) || little);
3.4676 +
3.4677 + /* For ELF, consult the symbol table to determine what kind of code
3.4678 + or data we have. */
3.4679 + if (info->symtab_size != 0
3.4680 + && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
3.4681 + {
3.4682 + bfd_vma addr;
3.4683 + int n, start;
3.4684 + int last_sym = -1;
3.4685 + enum map_type type = MAP_ARM;
3.4686 +
3.4687 + /* Start scanning at the start of the function, or wherever
3.4688 + we finished last time. */
3.4689 + start = info->symtab_pos + 1;
3.4690 + if (start < private_data->last_mapping_sym)
3.4691 + start = private_data->last_mapping_sym;
3.4692 + found = FALSE;
3.4693 +
3.4694 + /* First, look for mapping symbols. */
3.4695 + if (private_data->has_mapping_symbols != 0)
3.4696 + {
3.4697 + /* Scan up to the location being disassembled. */
3.4698 + for (n = start; n < info->symtab_size; n++)
3.4699 + {
3.4700 + addr = bfd_asymbol_value (info->symtab[n]);
3.4701 + if (addr > pc)
3.4702 + break;
3.4703 + if (get_map_sym_type (info, n, &type))
3.4704 + {
3.4705 + last_sym = n;
3.4706 + found = TRUE;
3.4707 + }
3.4708 + }
3.4709 +
3.4710 + if (!found)
3.4711 + {
3.4712 + /* No mapping symbol found at this address. Look backwards
3.4713 + for a preceding one. */
3.4714 + for (n = start - 1; n >= 0; n--)
3.4715 + {
3.4716 + if (get_map_sym_type (info, n, &type))
3.4717 + {
3.4718 + last_sym = n;
3.4719 + found = TRUE;
3.4720 + break;
3.4721 + }
3.4722 + }
3.4723 + }
3.4724 +
3.4725 + if (found)
3.4726 + private_data->has_mapping_symbols = 1;
3.4727 +
3.4728 + /* No mapping symbols were found. A leading $d may be
3.4729 + omitted for sections which start with data; but for
3.4730 + compatibility with legacy and stripped binaries, only
3.4731 + assume the leading $d if there is at least one mapping
3.4732 + symbol in the file. */
3.4733 + if (!found && private_data->has_mapping_symbols == -1)
3.4734 + {
3.4735 + /* Look for mapping symbols, in any section. */
3.4736 + for (n = 0; n < info->symtab_size; n++)
3.4737 + if (is_mapping_symbol (info, n, &type))
3.4738 + {
3.4739 + private_data->has_mapping_symbols = 1;
3.4740 + break;
3.4741 + }
3.4742 + if (private_data->has_mapping_symbols == -1)
3.4743 + private_data->has_mapping_symbols = 0;
3.4744 + }
3.4745 +
3.4746 + if (!found && private_data->has_mapping_symbols == 1)
3.4747 + {
3.4748 + type = MAP_DATA;
3.4749 + found = TRUE;
3.4750 + }
3.4751 + }
3.4752 +
3.4753 + /* Next search for function symbols to separate ARM from Thumb
3.4754 + in binaries without mapping symbols. */
3.4755 + if (!found)
3.4756 + {
3.4757 + /* Scan up to the location being disassembled. */
3.4758 + for (n = start; n < info->symtab_size; n++)
3.4759 + {
3.4760 + addr = bfd_asymbol_value (info->symtab[n]);
3.4761 + if (addr > pc)
3.4762 + break;
3.4763 + if (get_sym_code_type (info, n, &type))
3.4764 + {
3.4765 + last_sym = n;
3.4766 + found = TRUE;
3.4767 + }
3.4768 + }
3.4769 +
3.4770 + if (!found)
3.4771 + {
3.4772 + /* No mapping symbol found at this address. Look backwards
3.4773 + for a preceding one. */
3.4774 + for (n = start - 1; n >= 0; n--)
3.4775 + {
3.4776 + if (get_sym_code_type (info, n, &type))
3.4777 + {
3.4778 + last_sym = n;
3.4779 + found = TRUE;
3.4780 + break;
3.4781 + }
3.4782 + }
3.4783 + }
3.4784 + }
3.4785 +
3.4786 + private_data->last_mapping_sym = last_sym;
3.4787 + private_data->last_type = type;
3.4788 + is_thumb = (private_data->last_type == MAP_THUMB);
3.4789 + is_data = (private_data->last_type == MAP_DATA);
3.4790 +
3.4791 + /* Look a little bit ahead to see if we should print out
3.4792 + two or four bytes of data. If there's a symbol,
3.4793 + mapping or otherwise, after two bytes then don't
3.4794 + print more. */
3.4795 + if (is_data)
3.4796 + {
3.4797 + size = 4 - (pc & 3);
3.4798 + for (n = last_sym + 1; n < info->symtab_size; n++)
3.4799 + {
3.4800 + addr = bfd_asymbol_value (info->symtab[n]);
3.4801 + if (addr > pc
3.4802 + && (info->section == NULL
3.4803 + || info->section == info->symtab[n]->section))
3.4804 + {
3.4805 + if (addr - pc < size)
3.4806 + size = addr - pc;
3.4807 + break;
3.4808 + }
3.4809 + }
3.4810 + /* If the next symbol is after three bytes, we need to
3.4811 + print only part of the data, so that we can use either
3.4812 + .byte or .short. */
3.4813 + if (size == 3)
3.4814 + size = (pc & 1) ? 1 : 2;
3.4815 + }
3.4816 + }
3.4817 +
3.4818 +#if 0
3.4819 + if (info->symbols != NULL)
3.4820 + {
3.4821 + if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
3.4822 + {
3.4823 + coff_symbol_type * cs;
3.4824 +
3.4825 + cs = coffsymbol (*info->symbols);
3.4826 + is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
3.4827 + || cs->native->u.syment.n_sclass == C_THUMBSTAT
3.4828 + || cs->native->u.syment.n_sclass == C_THUMBLABEL
3.4829 + || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
3.4830 + || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
3.4831 + }
3.4832 + else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
3.4833 + && !found)
3.4834 + {
3.4835 + /* If no mapping symbol has been found then fall back to the type
3.4836 + of the function symbol. */
3.4837 + elf_symbol_type * es;
3.4838 + unsigned int type;
3.4839 +
3.4840 + es = *(elf_symbol_type **)(info->symbols);
3.4841 + type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
3.4842 +
3.4843 + is_thumb = ((ARM_SYM_BRANCH_TYPE (&es->internal_elf_sym)
3.4844 + == ST_BRANCH_TO_THUMB)
3.4845 + || type == STT_ARM_16BIT);
3.4846 + }
3.4847 + }
3.4848 +#endif
3.4849 + if (force_thumb)
3.4850 + is_thumb = TRUE;
3.4851 +
3.4852 + if (is_data)
3.4853 + info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
3.4854 + else
3.4855 + info->display_endian = little_code ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG;
3.4856 +
3.4857 + info->bytes_per_line = 4;
3.4858 +
3.4859 + /* PR 10263: Disassemble data if requested to do so by the user. */
3.4860 + if (is_data && ((info->flags & DISASSEMBLE_DATA) == 0))
3.4861 + {
3.4862 + int i;
3.4863 +
3.4864 + /* Size was already set above. */
3.4865 + info->bytes_per_chunk = size;
3.4866 + printer = print_insn_data;
3.4867 +
3.4868 + status = info->read_memory_func (pc, (bfd_byte *) b, size, info);
3.4869 + given = 0;
3.4870 + if (little)
3.4871 + for (i = size - 1; i >= 0; i--)
3.4872 + given = b[i] | (given << 8);
3.4873 + else
3.4874 + for (i = 0; i < (int) size; i++)
3.4875 + given = b[i] | (given << 8);
3.4876 + }
3.4877 + else if (!is_thumb)
3.4878 + {
3.4879 + /* In ARM mode endianness is a straightforward issue: the instruction
3.4880 + is four bytes long and is either ordered 0123 or 3210. */
3.4881 + printer = print_insn_arm;
3.4882 + info->bytes_per_chunk = 4;
3.4883 + size = 4;
3.4884 +
3.4885 + status = info->read_memory_func (pc, (bfd_byte *) b, 4, info);
3.4886 + if (little_code)
3.4887 + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24);
3.4888 + else
3.4889 + given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24);
3.4890 + }
3.4891 + else
3.4892 + {
3.4893 + /* In Thumb mode we have the additional wrinkle of two
3.4894 + instruction lengths. Fortunately, the bits that determine
3.4895 + the length of the current instruction are always to be found
3.4896 + in the first two bytes. */
3.4897 + printer = print_insn_thumb16;
3.4898 + info->bytes_per_chunk = 2;
3.4899 + size = 2;
3.4900 +
3.4901 + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info);
3.4902 + if (little_code)
3.4903 + given = (b[0]) | (b[1] << 8);
3.4904 + else
3.4905 + given = (b[1]) | (b[0] << 8);
3.4906 +
3.4907 + if (!status)
3.4908 + {
3.4909 + /* These bit patterns signal a four-byte Thumb
3.4910 + instruction. */
3.4911 + if ((given & 0xF800) == 0xF800
3.4912 + || (given & 0xF800) == 0xF000
3.4913 + || (given & 0xF800) == 0xE800)
3.4914 + {
3.4915 + status = info->read_memory_func (pc + 2, (bfd_byte *) b, 2, info);
3.4916 + if (little_code)
3.4917 + given = (b[0]) | (b[1] << 8) | (given << 16);
3.4918 + else
3.4919 + given = (b[1]) | (b[0] << 8) | (given << 16);
3.4920 +
3.4921 + printer = print_insn_thumb32;
3.4922 + size = 4;
3.4923 + }
3.4924 + }
3.4925 +
3.4926 + if (ifthen_address != pc)
3.4927 + find_ifthen_state (pc, info, little_code);
3.4928 +
3.4929 + if (ifthen_state)
3.4930 + {
3.4931 + if ((ifthen_state & 0xf) == 0x8)
3.4932 + ifthen_next_state = 0;
3.4933 + else
3.4934 + ifthen_next_state = (ifthen_state & 0xe0)
3.4935 + | ((ifthen_state & 0xf) << 1);
3.4936 + }
3.4937 + }
3.4938 +
3.4939 + if (status)
3.4940 + {
3.4941 + info->memory_error_func (status, pc, info);
3.4942 + return -1;
3.4943 + }
3.4944 + if (info->flags & INSN_HAS_RELOC)
3.4945 + /* If the instruction has a reloc associated with it, then
3.4946 + the offset field in the instruction will actually be the
3.4947 + addend for the reloc. (We are using REL type relocs).
3.4948 + In such cases, we can ignore the pc when computing
3.4949 + addresses, since the addend is not currently pc-relative. */
3.4950 + pc = 0;
3.4951 +
3.4952 + printer (pc, info, given);
3.4953 +
3.4954 + if (is_thumb)
3.4955 + {
3.4956 + ifthen_state = ifthen_next_state;
3.4957 + ifthen_address += size;
3.4958 + }
3.4959 + return size;
3.4960 +}
3.4961 +
3.4962 +int
3.4963 +print_insn_big_arm (bfd_vma pc, struct disassemble_info *info)
3.4964 +{
3.4965 + /* Detect BE8-ness and record it in the disassembler info. */
3.4966 +#if 0
3.4967 + if (info->flavour == bfd_target_elf_flavour
3.4968 + && info->section != NULL
3.4969 + && (elf_elfheader (info->section->owner)->e_flags & EF_ARM_BE8))
3.4970 + info->endian_code = BFD_ENDIAN_LITTLE;
3.4971 +#endif
3.4972 + return print_insn (pc, info, FALSE);
3.4973 +}
3.4974 +
3.4975 +int
3.4976 +print_insn_little_arm (bfd_vma pc, struct disassemble_info *info)
3.4977 +{
3.4978 + return print_insn (pc, info, TRUE);
3.4979 +}
3.4980 +
3.4981 +void
3.4982 +print_arm_disassembler_options (FILE *stream)
3.4983 +{
3.4984 + int i;
3.4985 +
3.4986 + fprintf (stream, _("\n\
3.4987 +The following ARM specific disassembler options are supported for use with\n\
3.4988 +the -M switch:\n"));
3.4989 +
3.4990 + for (i = NUM_ARM_REGNAMES; i--;)
3.4991 + fprintf (stream, " reg-names-%s %*c%s\n",
3.4992 + regnames[i].name,
3.4993 + (int)(14 - strlen (regnames[i].name)), ' ',
3.4994 + regnames[i].description);
3.4995 +
3.4996 + fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
3.4997 + fprintf (stream, " no-force-thumb Examine preceding label to determine an insn's type\n\n");
3.4998 +}
4.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
4.2 +++ b/src/xlat/disasm/arm.h Tue Mar 06 12:42:33 2012 +1000
4.3 @@ -0,0 +1,261 @@
4.4 +/* ARM assembler/disassembler support.
4.5 + Copyright 2004, 2010, 2011 Free Software Foundation, Inc.
4.6 +
4.7 + This file is part of GDB and GAS.
4.8 +
4.9 + GDB and GAS are free software; you can redistribute it and/or
4.10 + modify it under the terms of the GNU General Public License as
4.11 + published by the Free Software Foundation; either version 3, or (at
4.12 + your option) any later version.
4.13 +
4.14 + GDB and GAS are distributed in the hope that it will be useful, but
4.15 + WITHOUT ANY WARRANTY; without even the implied warranty of
4.16 + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
4.17 + General Public License for more details.
4.18 +
4.19 + You should have received a copy of the GNU General Public License
4.20 + along with GDB or GAS; see the file COPYING3. If not, write to the
4.21 + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
4.22 + MA 02110-1301, USA. */
4.23 +
4.24 +/* The following bitmasks control CPU extensions: */
4.25 +#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
4.26 +#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
4.27 +#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
4.28 +#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
4.29 +#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
4.30 +#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
4.31 +#define ARM_EXT_V4T 0x00000040 /* Thumb. */
4.32 +#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
4.33 +#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
4.34 +#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
4.35 +#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
4.36 +#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
4.37 +#define ARM_EXT_V6 0x00001000 /* ARM V6. */
4.38 +#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
4.39 +/* 0x00004000 Was ARM V6Z. */
4.40 +#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
4.41 +#define ARM_EXT_DIV 0x00010000 /* Integer division. */
4.42 +/* The 'M' in Arm V7M stands for Microcontroller.
4.43 + On earlier architecture variants it stands for Multiply. */
4.44 +#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
4.45 +#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
4.46 +#define ARM_EXT_V7 0x00080000 /* Arm V7. */
4.47 +#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
4.48 +#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
4.49 +#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
4.50 +#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
4.51 +#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
4.52 +#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
4.53 +#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
4.54 + not in v7-M. */
4.55 +#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
4.56 +#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
4.57 +#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
4.58 +#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
4.59 + state. */
4.60 +#define ARM_EXT_VIRT 0x80000000 /* Virtualization extensions. */
4.61 +
4.62 +/* Co-processor space extensions. */
4.63 +#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
4.64 +#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
4.65 +#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
4.66 +#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */
4.67 +
4.68 +#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
4.69 +#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
4.70 +#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
4.71 +#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
4.72 +#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
4.73 +#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
4.74 +#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
4.75 +#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
4.76 +#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */
4.77 +#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */
4.78 +#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */
4.79 +#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */
4.80 +#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
4.81 +#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */
4.82 +#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */
4.83 +
4.84 +/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
4.85 + defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
4.86 + ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
4.87 + three more to cover cores prior to ARM6. Finally, there are cores which
4.88 + implement further extensions in the co-processor space. */
4.89 +#define ARM_AEXT_V1 ARM_EXT_V1
4.90 +#define ARM_AEXT_V2 (ARM_AEXT_V1 | ARM_EXT_V2)
4.91 +#define ARM_AEXT_V2S (ARM_AEXT_V2 | ARM_EXT_V2S)
4.92 +#define ARM_AEXT_V3 (ARM_AEXT_V2S | ARM_EXT_V3)
4.93 +#define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M)
4.94 +#define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4)
4.95 +#define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4)
4.96 +#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T)
4.97 +#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T)
4.98 +#define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5)
4.99 +#define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5)
4.100 +#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
4.101 +#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
4.102 +#define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP)
4.103 +#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E)
4.104 +#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
4.105 +#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ | ARM_EXT_V6)
4.106 +#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
4.107 +#define ARM_AEXT_V6Z (ARM_AEXT_V6K | ARM_EXT_SEC)
4.108 +#define ARM_AEXT_V6ZK (ARM_AEXT_V6K | ARM_EXT_SEC)
4.109 +#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
4.110 + | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
4.111 + | ARM_EXT_V6_DSP )
4.112 +#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
4.113 +#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_SEC)
4.114 +#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
4.115 +#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
4.116 +#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
4.117 +#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
4.118 +#define ARM_AEXT_NOTM \
4.119 + (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
4.120 + | ARM_EXT_V6_DSP )
4.121 +#define ARM_AEXT_V6M_ONLY \
4.122 + ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
4.123 +#define ARM_AEXT_V6M \
4.124 + ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
4.125 +#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
4.126 +#define ARM_AEXT_V7M \
4.127 + ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
4.128 + & ~(ARM_AEXT_NOTM))
4.129 +#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
4.130 +#define ARM_AEXT_V7EM \
4.131 + (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)
4.132 +
4.133 +/* Processors with specific extensions in the co-processor space. */
4.134 +#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
4.135 +#define ARM_ARCH_IWMMXT \
4.136 + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
4.137 +#define ARM_ARCH_IWMMXT2 \
4.138 + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)
4.139 +
4.140 +#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
4.141 +#define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1)
4.142 +#define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2)
4.143 +#define FPU_VFP_V3D16 (FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
4.144 +#define FPU_VFP_V3 (FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
4.145 +#define FPU_VFP_V3xD (FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
4.146 +#define FPU_VFP_V4D16 (FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
4.147 +#define FPU_VFP_V4 (FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
4.148 +#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
4.149 +#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
4.150 + | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
4.151 + | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
4.152 +#define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)
4.153 +
4.154 +/* Deprecated. */
4.155 +#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE)
4.156 +
4.157 +#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1)
4.158 +#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA)
4.159 +
4.160 +#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
4.161 +#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
4.162 +#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
4.163 +#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16)
4.164 +#define FPU_ARCH_VFP_V3D16_FP16 \
4.165 + ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
4.166 +#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
4.167 +#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16)
4.168 +#define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD)
4.169 +#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16)
4.170 +#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
4.171 +#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
4.172 + ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
4.173 +#define FPU_ARCH_NEON_FP16 \
4.174 + ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
4.175 +#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
4.176 +#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4)
4.177 +#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16)
4.178 +#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16)
4.179 +#define FPU_ARCH_NEON_VFP_V4 \
4.180 + ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)
4.181 +
4.182 +#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
4.183 +
4.184 +#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
4.185 +
4.186 +#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0)
4.187 +#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0)
4.188 +#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0)
4.189 +#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0)
4.190 +#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0)
4.191 +#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0)
4.192 +#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0)
4.193 +#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0)
4.194 +#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0)
4.195 +#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0)
4.196 +#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0)
4.197 +#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0)
4.198 +#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0)
4.199 +#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0)
4.200 +#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0)
4.201 +#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
4.202 +#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0)
4.203 +#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0)
4.204 +#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0)
4.205 +#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0)
4.206 +#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0)
4.207 +#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
4.208 +#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
4.209 +#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
4.210 +#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
4.211 +#define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0)
4.212 +#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
4.213 +#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
4.214 +#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
4.215 +#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
4.216 +#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0)
4.217 +
4.218 +/* Some useful combinations: */
4.219 +#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
4.220 +#define FPU_NONE ARM_FEATURE (0, 0)
4.221 +#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
4.222 +#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
4.223 +#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
4.224 +/* v7-a+sec. */
4.225 +#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0)
4.226 +/* v7-a+mp+sec. */
4.227 +#define ARM_ARCH_V7A_MP_SEC \
4.228 + ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
4.229 + 0)
4.230 +/* v7-a+idiv+mp+sec+virt. */
4.231 +#define ARM_ARCH_V7A_IDIV_MP_SEC_VIRT \
4.232 + ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \
4.233 + | ARM_EXT_DIV | ARM_EXT_ADIV \
4.234 + | ARM_EXT_VIRT, 0)
4.235 +/* v7-r+idiv. */
4.236 +#define ARM_ARCH_V7R_IDIV ARM_FEATURE (ARM_AEXT_V7R | ARM_EXT_ADIV, 0)
4.237 +/* Features that are present in v6M and v6S-M but not other v6 cores. */
4.238 +#define ARM_ARCH_V6M_ONLY ARM_FEATURE (ARM_AEXT_V6M_ONLY, 0)
4.239 +
4.240 +/* There are too many feature bits to fit in a single word, so use a
4.241 + structure. For simplicity we put all core features in one word and
4.242 + everything else in the other. */
4.243 +typedef struct
4.244 +{
4.245 + unsigned long core;
4.246 + unsigned long coproc;
4.247 +} arm_feature_set;
4.248 +
4.249 +#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
4.250 + (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)
4.251 +
4.252 +#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
4.253 + do { \
4.254 + (TARG).core = (F1).core | (F2).core; \
4.255 + (TARG).coproc = (F1).coproc | (F2).coproc; \
4.256 + } while (0)
4.257 +
4.258 +#define ARM_CLEAR_FEATURE(TARG,F1,F2) \
4.259 + do { \
4.260 + (TARG).core = (F1).core &~ (F2).core; \
4.261 + (TARG).coproc = (F1).coproc &~ (F2).coproc; \
4.262 + } while (0)
4.263 +
4.264 +#define ARM_FEATURE(core, coproc) {(core), (coproc)}
5.1 --- a/src/xlat/disasm/bfd.h Tue Mar 06 12:19:08 2012 +1000
5.2 +++ b/src/xlat/disasm/bfd.h Tue Mar 06 12:42:33 2012 +1000
5.3 @@ -1714,6 +1714,7 @@
5.4 #define bfd_mach_arm_XScale 10
5.5 #define bfd_mach_arm_ep9312 11
5.6 #define bfd_mach_arm_iWMMXt 12
5.7 +#define bfd_mach_arm_iWMMXt2 13
5.8 bfd_arch_ns32k, /* National Semiconductors ns32000 */
5.9 bfd_arch_w65, /* WDC 65816 */
5.10 bfd_arch_tic30, /* Texas Instruments TMS320C30 */
6.1 --- a/src/xlat/disasm/dis-asm.h Tue Mar 06 12:19:08 2012 +1000
6.2 +++ b/src/xlat/disasm/dis-asm.h Tue Mar 06 12:42:33 2012 +1000
6.3 @@ -1,11 +1,11 @@
6.4 /* Interface between the opcode library and its callers.
6.5
6.6 - Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005
6.7 - Free Software Foundation, Inc.
6.8 -
6.9 + Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010,
6.10 + 2011 Free Software Foundation, Inc.
6.11 +
6.12 This program is free software; you can redistribute it and/or modify
6.13 it under the terms of the GNU General Public License as published by
6.14 - the Free Software Foundation; either version 2, or (at your option)
6.15 + the Free Software Foundation; either version 3, or (at your option)
6.16 any later version.
6.17
6.18 This program is distributed in the hope that it will be useful,
6.19 @@ -15,9 +15,9 @@
6.20
6.21 You should have received a copy of the GNU General Public License
6.22 along with this program; if not, write to the Free Software
6.23 - Foundation, Inc., 59 Temple Place - Suite 330,
6.24 - Boston, MA 02111-1307, USA.
6.25 -
6.26 + Foundation, Inc., 51 Franklin Street - Fifth Floor,
6.27 + Boston, MA 02110-1301, USA.
6.28 +
6.29 Written by Cygnus Support, 1993.
6.30
6.31 The opcode library (libopcodes.a) provides instruction decoders for
6.32 @@ -35,20 +35,21 @@
6.33 #include <stdio.h>
6.34 #include "xlat/disasm/bfd.h"
6.35
6.36 -typedef int (*fprintf_ftype) (void *, const char*, ...);
6.37 + typedef int (*fprintf_ftype) (void *, const char*, ...) /*ATTRIBUTE_FPTR_PRINTF_2*/;
6.38
6.39 -enum dis_insn_type {
6.40 - dis_noninsn, /* Not a valid instruction */
6.41 - dis_nonbranch, /* Not a branch instruction */
6.42 - dis_branch, /* Unconditional branch */
6.43 - dis_condbranch, /* Conditional branch */
6.44 - dis_jsr, /* Jump to subroutine */
6.45 - dis_condjsr, /* Conditional jump to subroutine */
6.46 - dis_dref, /* Data reference instruction */
6.47 - dis_dref2 /* Two data references in instruction */
6.48 +enum dis_insn_type
6.49 +{
6.50 + dis_noninsn, /* Not a valid instruction. */
6.51 + dis_nonbranch, /* Not a branch instruction. */
6.52 + dis_branch, /* Unconditional branch. */
6.53 + dis_condbranch, /* Conditional branch. */
6.54 + dis_jsr, /* Jump to subroutine. */
6.55 + dis_condjsr, /* Conditional jump to subroutine. */
6.56 + dis_dref, /* Data reference instruction. */
6.57 + dis_dref2 /* Two data references in instruction. */
6.58 };
6.59
6.60 -/* This struct is passed into the instruction decoding routine,
6.61 +/* This struct is passed into the instruction decoding routine,
6.62 and is passed back out into each callback. The various fields are used
6.63 for conveying information from your main routine into your callbacks,
6.64 for passing information into the instruction decoders (such as the
6.65 @@ -58,7 +59,8 @@
6.66 It must be initialized before it is first passed; this can be done
6.67 by hand, or using one of the initialization macros below. */
6.68
6.69 -typedef struct disassemble_info {
6.70 +typedef struct disassemble_info
6.71 +{
6.72 fprintf_ftype fprintf_func;
6.73 void *stream;
6.74 void *application_data;
6.75 @@ -74,11 +76,13 @@
6.76 unsigned long mach;
6.77 /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
6.78 enum bfd_endian endian;
6.79 + /* Endianness of code, for mixed-endian situations such as ARM BE8. */
6.80 + enum bfd_endian endian_code;
6.81 /* An arch/mach-specific bitmask of selected instruction subsets, mainly
6.82 for processors with run-time-switchable instruction sets. The default,
6.83 zero, means that there is no constraint. CGEN-based opcodes ports
6.84 may use ISA_foo masks. */
6.85 - unsigned long insn_sets;
6.86 + void *insn_sets;
6.87
6.88 /* Some targets need information about the current section to accurately
6.89 display insns. If this is NULL, the target disassembler function
6.90 @@ -94,11 +98,26 @@
6.91 /* Number of symbols in array. */
6.92 int num_symbols;
6.93
6.94 + /* Symbol table provided for targets that want to look at it. This is
6.95 + used on Arm to find mapping symbols and determine Arm/Thumb code. */
6.96 + asymbol **symtab;
6.97 + int symtab_pos;
6.98 + int symtab_size;
6.99 +
6.100 /* For use by the disassembler.
6.101 The top 16 bits are reserved for public use (and are documented here).
6.102 The bottom 16 bits are for the internal use of the disassembler. */
6.103 unsigned long flags;
6.104 -#define INSN_HAS_RELOC 0x80000000
6.105 + /* Set if the disassembler has determined that there are one or more
6.106 + relocations associated with the instruction being disassembled. */
6.107 +#define INSN_HAS_RELOC (1 << 31)
6.108 + /* Set if the user has requested the disassembly of data as well as code. */
6.109 +#define DISASSEMBLE_DATA (1 << 30)
6.110 + /* Set if the user has specifically set the machine type encoded in the
6.111 + mach field of this structure. */
6.112 +#define USER_SPECIFIED_MACHINE_TYPE (1 << 29)
6.113 +
6.114 + /* Use internally by the target specific disassembly code. */
6.115 void *private_data;
6.116
6.117 /* Function used to get bytes to disassemble. MEMADDR is the
6.118 @@ -108,18 +127,18 @@
6.119 Returns an errno value or 0 for success. */
6.120 int (*read_memory_func)
6.121 (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length,
6.122 - struct disassemble_info *info);
6.123 + struct disassemble_info *dinfo);
6.124
6.125 /* Function which should be called if we get an error that we can't
6.126 recover from. STATUS is the errno value from read_memory_func and
6.127 MEMADDR is the address that we were trying to read. INFO is a
6.128 pointer to this struct. */
6.129 void (*memory_error_func)
6.130 - (int status, bfd_vma memaddr, struct disassemble_info *info);
6.131 + (int status, bfd_vma memaddr, struct disassemble_info *dinfo);
6.132
6.133 /* Function called to print ADDR. */
6.134 void (*print_address_func)
6.135 - (bfd_vma addr, struct disassemble_info *info);
6.136 + (bfd_vma addr, struct disassemble_info *dinfo);
6.137
6.138 /* Function called to determine if there is a symbol at the given ADDR.
6.139 If there is, the function returns 1, otherwise it returns 0.
6.140 @@ -129,14 +148,14 @@
6.141 address, (normally because there is a symbol associated with
6.142 that address), but sometimes we want to mask out the overlay bits. */
6.143 int (* symbol_at_address_func)
6.144 - (bfd_vma addr, struct disassemble_info * info);
6.145 + (bfd_vma addr, struct disassemble_info *dinfo);
6.146
6.147 /* Function called to check if a SYMBOL is can be displayed to the user.
6.148 This is used by some ports that want to hide special symbols when
6.149 displaying debugging outout. */
6.150 bfd_boolean (* symbol_is_valid)
6.151 - (asymbol *, struct disassemble_info * info);
6.152 -
6.153 + (asymbol *, struct disassemble_info *dinfo);
6.154 +
6.155 /* These are for buffer_read_memory. */
6.156 bfd_byte *buffer;
6.157 bfd_vma buffer_vma;
6.158 @@ -156,7 +175,7 @@
6.159 int bytes_per_chunk;
6.160 enum bfd_endian display_endian;
6.161
6.162 - /* Number of octets per incremented target address
6.163 + /* Number of octets per incremented target address
6.164 Normally one, but some DSPs have byte sizes of 16 or 32 bits. */
6.165 unsigned int octets_per_byte;
6.166
6.167 @@ -172,6 +191,9 @@
6.168 alignment. */
6.169 unsigned int skip_zeroes_at_end;
6.170
6.171 + /* Whether the disassembler always needs the relocations. */
6.172 + bfd_boolean disassembler_needs_relocs;
6.173 +
6.174 /* Results from instruction decoders. Not all decoders yet support
6.175 this information. This info is set each time an instruction is
6.176 decoded, and is only valid for the last such instruction.
6.177 @@ -198,82 +220,97 @@
6.178 target address. Return number of octets processed. */
6.179 typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);
6.180
6.181 +extern int print_insn_alpha (bfd_vma, disassemble_info *);
6.182 +extern int print_insn_avr (bfd_vma, disassemble_info *);
6.183 +extern int print_insn_bfin (bfd_vma, disassemble_info *);
6.184 +extern int print_insn_big_arm (bfd_vma, disassemble_info *);
6.185 extern int print_insn_big_mips (bfd_vma, disassemble_info *);
6.186 -extern int print_insn_little_mips (bfd_vma, disassemble_info *);
6.187 -extern int print_insn_i386 (bfd_vma, disassemble_info *);
6.188 -extern int print_insn_i386_att (bfd_vma, disassemble_info *);
6.189 -extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
6.190 -extern int print_insn_ia64 (bfd_vma, disassemble_info *);
6.191 -extern int print_insn_i370 (bfd_vma, disassemble_info *);
6.192 -extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
6.193 -extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
6.194 -extern int print_insn_m68k (bfd_vma, disassemble_info *);
6.195 -extern int print_insn_z8001 (bfd_vma, disassemble_info *);
6.196 -extern int print_insn_z8002 (bfd_vma, disassemble_info *);
6.197 +extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
6.198 +extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
6.199 +extern int print_insn_big_score (bfd_vma, disassemble_info *);
6.200 +extern int print_insn_cr16 (bfd_vma, disassemble_info *);
6.201 +extern int print_insn_crx (bfd_vma, disassemble_info *);
6.202 +extern int print_insn_d10v (bfd_vma, disassemble_info *);
6.203 +extern int print_insn_d30v (bfd_vma, disassemble_info *);
6.204 +extern int print_insn_dlx (bfd_vma, disassemble_info *);
6.205 +extern int print_insn_fr30 (bfd_vma, disassemble_info *);
6.206 +extern int print_insn_frv (bfd_vma, disassemble_info *);
6.207 extern int print_insn_h8300 (bfd_vma, disassemble_info *);
6.208 extern int print_insn_h8300h (bfd_vma, disassemble_info *);
6.209 extern int print_insn_h8300s (bfd_vma, disassemble_info *);
6.210 extern int print_insn_h8500 (bfd_vma, disassemble_info *);
6.211 -extern int print_insn_alpha (bfd_vma, disassemble_info *);
6.212 -extern int print_insn_big_arm (bfd_vma, disassemble_info *);
6.213 -extern int print_insn_little_arm (bfd_vma, disassemble_info *);
6.214 -extern int print_insn_sparc (bfd_vma, disassemble_info *);
6.215 -extern int print_insn_big_a29k (bfd_vma, disassemble_info *);
6.216 -extern int print_insn_little_a29k (bfd_vma, disassemble_info *);
6.217 -extern int print_insn_avr (bfd_vma, disassemble_info *);
6.218 -extern int print_insn_d10v (bfd_vma, disassemble_info *);
6.219 -extern int print_insn_d30v (bfd_vma, disassemble_info *);
6.220 -extern int print_insn_dlx (bfd_vma, disassemble_info *);
6.221 -extern int print_insn_fr30 (bfd_vma, disassemble_info *);
6.222 extern int print_insn_hppa (bfd_vma, disassemble_info *);
6.223 +extern int print_insn_i370 (bfd_vma, disassemble_info *);
6.224 +extern int print_insn_i386 (bfd_vma, disassemble_info *);
6.225 +extern int print_insn_i386_att (bfd_vma, disassemble_info *);
6.226 +extern int print_insn_i386_intel (bfd_vma, disassemble_info *);
6.227 extern int print_insn_i860 (bfd_vma, disassemble_info *);
6.228 extern int print_insn_i960 (bfd_vma, disassemble_info *);
6.229 +extern int print_insn_ia64 (bfd_vma, disassemble_info *);
6.230 extern int print_insn_ip2k (bfd_vma, disassemble_info *);
6.231 +extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
6.232 +extern int print_insn_little_arm (bfd_vma, disassemble_info *);
6.233 +extern int print_insn_little_mips (bfd_vma, disassemble_info *);
6.234 +extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
6.235 +extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
6.236 +extern int print_insn_little_score (bfd_vma, disassemble_info *);
6.237 +extern int print_insn_lm32 (bfd_vma, disassemble_info *);
6.238 +extern int print_insn_m32c (bfd_vma, disassemble_info *);
6.239 extern int print_insn_m32r (bfd_vma, disassemble_info *);
6.240 +extern int print_insn_m68hc11 (bfd_vma, disassemble_info *);
6.241 +extern int print_insn_m68hc12 (bfd_vma, disassemble_info *);
6.242 +extern int print_insn_m68k (bfd_vma, disassemble_info *);
6.243 extern int print_insn_m88k (bfd_vma, disassemble_info *);
6.244 -extern int print_insn_maxq_little (bfd_vma, disassemble_info *);
6.245 -extern int print_insn_maxq_big (bfd_vma, disassemble_info *);
6.246 extern int print_insn_mcore (bfd_vma, disassemble_info *);
6.247 +extern int print_insn_mep (bfd_vma, disassemble_info *);
6.248 +extern int print_insn_microblaze (bfd_vma, disassemble_info *);
6.249 extern int print_insn_mmix (bfd_vma, disassemble_info *);
6.250 extern int print_insn_mn10200 (bfd_vma, disassemble_info *);
6.251 extern int print_insn_mn10300 (bfd_vma, disassemble_info *);
6.252 +extern int print_insn_moxie (bfd_vma, disassemble_info *);
6.253 extern int print_insn_msp430 (bfd_vma, disassemble_info *);
6.254 +extern int print_insn_mt (bfd_vma, disassemble_info *);
6.255 extern int print_insn_ns32k (bfd_vma, disassemble_info *);
6.256 -extern int print_insn_crx (bfd_vma, disassemble_info *);
6.257 extern int print_insn_openrisc (bfd_vma, disassemble_info *);
6.258 -extern int print_insn_big_or32 (bfd_vma, disassemble_info *);
6.259 -extern int print_insn_little_or32 (bfd_vma, disassemble_info *);
6.260 extern int print_insn_pdp11 (bfd_vma, disassemble_info *);
6.261 extern int print_insn_pj (bfd_vma, disassemble_info *);
6.262 -extern int print_insn_big_powerpc (bfd_vma, disassemble_info *);
6.263 -extern int print_insn_little_powerpc (bfd_vma, disassemble_info *);
6.264 extern int print_insn_rs6000 (bfd_vma, disassemble_info *);
6.265 -extern int print_insn_s390 (bfd_vma, disassemble_info *);
6.266 +extern int print_insn_s390 (bfd_vma, disassemble_info *);
6.267 extern int print_insn_sh (bfd_vma, disassemble_info *);
6.268 +extern int print_insn_sh64 (bfd_vma, disassemble_info *);
6.269 +extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
6.270 +extern int print_insn_sparc (bfd_vma, disassemble_info *);
6.271 +extern int print_insn_spu (bfd_vma, disassemble_info *);
6.272 extern int print_insn_tic30 (bfd_vma, disassemble_info *);
6.273 extern int print_insn_tic4x (bfd_vma, disassemble_info *);
6.274 extern int print_insn_tic54x (bfd_vma, disassemble_info *);
6.275 +extern int print_insn_tic6x (bfd_vma, disassemble_info *);
6.276 extern int print_insn_tic80 (bfd_vma, disassemble_info *);
6.277 +extern int print_insn_tilegx (bfd_vma, disassemble_info *);
6.278 +extern int print_insn_tilepro (bfd_vma, disassemble_info *);
6.279 extern int print_insn_v850 (bfd_vma, disassemble_info *);
6.280 extern int print_insn_vax (bfd_vma, disassemble_info *);
6.281 extern int print_insn_w65 (bfd_vma, disassemble_info *);
6.282 +extern int print_insn_xc16x (bfd_vma, disassemble_info *);
6.283 extern int print_insn_xstormy16 (bfd_vma, disassemble_info *);
6.284 extern int print_insn_xtensa (bfd_vma, disassemble_info *);
6.285 -extern int print_insn_sh64 (bfd_vma, disassemble_info *);
6.286 -extern int print_insn_sh64x_media (bfd_vma, disassemble_info *);
6.287 -extern int print_insn_frv (bfd_vma, disassemble_info *);
6.288 -extern int print_insn_iq2000 (bfd_vma, disassemble_info *);
6.289 +extern int print_insn_z80 (bfd_vma, disassemble_info *);
6.290 +extern int print_insn_z8001 (bfd_vma, disassemble_info *);
6.291 +extern int print_insn_z8002 (bfd_vma, disassemble_info *);
6.292 +extern int print_insn_rx (bfd_vma, disassemble_info *);
6.293
6.294 extern disassembler_ftype arc_get_disassembler (void *);
6.295 extern disassembler_ftype cris_get_disassembler (bfd *);
6.296
6.297 +extern void print_i386_disassembler_options (FILE *);
6.298 extern void print_mips_disassembler_options (FILE *);
6.299 extern void print_ppc_disassembler_options (FILE *);
6.300 extern void print_arm_disassembler_options (FILE *);
6.301 extern void parse_arm_disassembler_option (char *);
6.302 -extern int get_arm_regname_num_options (void);
6.303 -extern int set_arm_regname_option (int);
6.304 -extern int get_arm_regnames (int, const char **, const char **, const char ***);
6.305 +extern void print_s390_disassembler_options (FILE *);
6.306 +extern int get_arm_regname_num_options (void);
6.307 +extern int set_arm_regname_option (int);
6.308 +extern int get_arm_regnames (int, const char **, const char **, const char *const **);
6.309 extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *);
6.310
6.311 /* Fetch the disassembler for a given BFD, if that support is available. */
6.312 @@ -281,7 +318,7 @@
6.313
6.314 /* Amend the disassemble_info structure as necessary for the target architecture.
6.315 Should only be called after initialising the info->arch field. */
6.316 -extern void disassemble_init_for_target (struct disassemble_info * info);
6.317 +extern void disassemble_init_for_target (struct disassemble_info * dinfo);
6.318
6.319 /* Document any target specific options available from the disassembler. */
6.320 extern void disassembler_usage (FILE *);
6.321 @@ -310,13 +347,13 @@
6.322 extern int generic_symbol_at_address
6.323 (bfd_vma, struct disassemble_info *);
6.324
6.325 -/* Also always true. */
6.326 +/* Also always true. */
6.327 extern bfd_boolean generic_symbol_is_valid
6.328 (asymbol *, struct disassemble_info *);
6.329 -
6.330 +
6.331 /* Method to initialize a disassemble_info struct. This should be
6.332 called by all applications creating such a struct. */
6.333 -extern void init_disassemble_info (struct disassemble_info *info, void *stream,
6.334 +extern void init_disassemble_info (struct disassemble_info *dinfo, void *stream,
6.335 fprintf_ftype fprintf_func);
6.336
6.337 /* For compatibility with existing code. */
7.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
7.2 +++ b/src/xlat/disasm/floatformat.c Tue Mar 06 12:42:33 2012 +1000
7.3 @@ -0,0 +1,771 @@
7.4 +/* IEEE floating point support routines, for GDB, the GNU Debugger.
7.5 + Copyright 1991, 1994, 1999, 2000, 2003, 2005, 2006, 2010
7.6 + Free Software Foundation, Inc.
7.7 +
7.8 +This file is part of GDB.
7.9 +
7.10 +This program is free software; you can redistribute it and/or modify
7.11 +it under the terms of the GNU General Public License as published by
7.12 +the Free Software Foundation; either version 2 of the License, or
7.13 +(at your option) any later version.
7.14 +
7.15 +This program is distributed in the hope that it will be useful,
7.16 +but WITHOUT ANY WARRANTY; without even the implied warranty of
7.17 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
7.18 +GNU General Public License for more details.
7.19 +
7.20 +You should have received a copy of the GNU General Public License
7.21 +along with this program; if not, write to the Free Software
7.22 +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
7.23 +
7.24 +#ifdef HAVE_CONFIG_H
7.25 +#include "config.h"
7.26 +#endif
7.27 +
7.28 +#include <math.h>
7.29 +
7.30 +#ifdef HAVE_STRING_H
7.31 +#include <string.h>
7.32 +#endif
7.33 +
7.34 +/* On some platforms, <float.h> provides DBL_QNAN. */
7.35 +#ifdef STDC_HEADERS
7.36 +#include <float.h>
7.37 +#endif
7.38 +
7.39 +#include "ansidecl.h"
7.40 +#include "floatformat.h"
7.41 +
7.42 +#ifndef INFINITY
7.43 +#ifdef HUGE_VAL
7.44 +#define INFINITY HUGE_VAL
7.45 +#else
7.46 +#define INFINITY (1.0 / 0.0)
7.47 +#endif
7.48 +#endif
7.49 +
7.50 +#ifndef NAN
7.51 +#ifdef DBL_QNAN
7.52 +#define NAN DBL_QNAN
7.53 +#else
7.54 +#define NAN (0.0 / 0.0)
7.55 +#endif
7.56 +#endif
7.57 +
7.58 +static int mant_bits_set (const struct floatformat *, const unsigned char *);
7.59 +static unsigned long get_field (const unsigned char *,
7.60 + enum floatformat_byteorders,
7.61 + unsigned int,
7.62 + unsigned int,
7.63 + unsigned int);
7.64 +static int floatformat_always_valid (const struct floatformat *fmt,
7.65 + const void *from);
7.66 +
7.67 +static int
7.68 +floatformat_always_valid (const struct floatformat *fmt ATTRIBUTE_UNUSED,
7.69 + const void *from ATTRIBUTE_UNUSED)
7.70 +{
7.71 + return 1;
7.72 +}
7.73 +
7.74 +/* The odds that CHAR_BIT will be anything but 8 are low enough that I'm not
7.75 + going to bother with trying to muck around with whether it is defined in
7.76 + a system header, what we do if not, etc. */
7.77 +#define FLOATFORMAT_CHAR_BIT 8
7.78 +
7.79 +/* floatformats for IEEE half, single and double, big and little endian. */
7.80 +const struct floatformat floatformat_ieee_half_big =
7.81 +{
7.82 + floatformat_big, 16, 0, 1, 5, 15, 31, 6, 10,
7.83 + floatformat_intbit_no,
7.84 + "floatformat_ieee_half_big",
7.85 + floatformat_always_valid,
7.86 + NULL
7.87 +};
7.88 +const struct floatformat floatformat_ieee_half_little =
7.89 +{
7.90 + floatformat_little, 16, 0, 1, 5, 15, 31, 6, 10,
7.91 + floatformat_intbit_no,
7.92 + "floatformat_ieee_half_little",
7.93 + floatformat_always_valid,
7.94 + NULL
7.95 +};
7.96 +const struct floatformat floatformat_ieee_single_big =
7.97 +{
7.98 + floatformat_big, 32, 0, 1, 8, 127, 255, 9, 23,
7.99 + floatformat_intbit_no,
7.100 + "floatformat_ieee_single_big",
7.101 + floatformat_always_valid,
7.102 + NULL
7.103 +};
7.104 +const struct floatformat floatformat_ieee_single_little =
7.105 +{
7.106 + floatformat_little, 32, 0, 1, 8, 127, 255, 9, 23,
7.107 + floatformat_intbit_no,
7.108 + "floatformat_ieee_single_little",
7.109 + floatformat_always_valid,
7.110 + NULL
7.111 +};
7.112 +const struct floatformat floatformat_ieee_double_big =
7.113 +{
7.114 + floatformat_big, 64, 0, 1, 11, 1023, 2047, 12, 52,
7.115 + floatformat_intbit_no,
7.116 + "floatformat_ieee_double_big",
7.117 + floatformat_always_valid,
7.118 + NULL
7.119 +};
7.120 +const struct floatformat floatformat_ieee_double_little =
7.121 +{
7.122 + floatformat_little, 64, 0, 1, 11, 1023, 2047, 12, 52,
7.123 + floatformat_intbit_no,
7.124 + "floatformat_ieee_double_little",
7.125 + floatformat_always_valid,
7.126 + NULL
7.127 +};
7.128 +
7.129 +/* floatformat for IEEE double, little endian byte order, with big endian word
7.130 + ordering, as on the ARM. */
7.131 +
7.132 +const struct floatformat floatformat_ieee_double_littlebyte_bigword =
7.133 +{
7.134 + floatformat_littlebyte_bigword, 64, 0, 1, 11, 1023, 2047, 12, 52,
7.135 + floatformat_intbit_no,
7.136 + "floatformat_ieee_double_littlebyte_bigword",
7.137 + floatformat_always_valid,
7.138 + NULL
7.139 +};
7.140 +
7.141 +/* floatformat for VAX. Not quite IEEE, but close enough. */
7.142 +
7.143 +const struct floatformat floatformat_vax_f =
7.144 +{
7.145 + floatformat_vax, 32, 0, 1, 8, 129, 0, 9, 23,
7.146 + floatformat_intbit_no,
7.147 + "floatformat_vax_f",
7.148 + floatformat_always_valid,
7.149 + NULL
7.150 +};
7.151 +const struct floatformat floatformat_vax_d =
7.152 +{
7.153 + floatformat_vax, 64, 0, 1, 8, 129, 0, 9, 55,
7.154 + floatformat_intbit_no,
7.155 + "floatformat_vax_d",
7.156 + floatformat_always_valid,
7.157 + NULL
7.158 +};
7.159 +const struct floatformat floatformat_vax_g =
7.160 +{
7.161 + floatformat_vax, 64, 0, 1, 11, 1025, 0, 12, 52,
7.162 + floatformat_intbit_no,
7.163 + "floatformat_vax_g",
7.164 + floatformat_always_valid,
7.165 + NULL
7.166 +};
7.167 +
7.168 +static int floatformat_i387_ext_is_valid (const struct floatformat *fmt,
7.169 + const void *from);
7.170 +
7.171 +static int
7.172 +floatformat_i387_ext_is_valid (const struct floatformat *fmt, const void *from)
7.173 +{
7.174 + /* In the i387 double-extended format, if the exponent is all ones,
7.175 + then the integer bit must be set. If the exponent is neither 0
7.176 + nor ~0, the intbit must also be set. Only if the exponent is
7.177 + zero can it be zero, and then it must be zero. */
7.178 + unsigned long exponent, int_bit;
7.179 + const unsigned char *ufrom = (const unsigned char *) from;
7.180 +
7.181 + exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize,
7.182 + fmt->exp_start, fmt->exp_len);
7.183 + int_bit = get_field (ufrom, fmt->byteorder, fmt->totalsize,
7.184 + fmt->man_start, 1);
7.185 +
7.186 + if ((exponent == 0) != (int_bit == 0))
7.187 + return 0;
7.188 + else
7.189 + return 1;
7.190 +}
7.191 +
7.192 +const struct floatformat floatformat_i387_ext =
7.193 +{
7.194 + floatformat_little, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64,
7.195 + floatformat_intbit_yes,
7.196 + "floatformat_i387_ext",
7.197 + floatformat_i387_ext_is_valid,
7.198 + NULL
7.199 +};
7.200 +const struct floatformat floatformat_m68881_ext =
7.201 +{
7.202 + /* Note that the bits from 16 to 31 are unused. */
7.203 + floatformat_big, 96, 0, 1, 15, 0x3fff, 0x7fff, 32, 64,
7.204 + floatformat_intbit_yes,
7.205 + "floatformat_m68881_ext",
7.206 + floatformat_always_valid,
7.207 + NULL
7.208 +};
7.209 +const struct floatformat floatformat_i960_ext =
7.210 +{
7.211 + /* Note that the bits from 0 to 15 are unused. */
7.212 + floatformat_little, 96, 16, 17, 15, 0x3fff, 0x7fff, 32, 64,
7.213 + floatformat_intbit_yes,
7.214 + "floatformat_i960_ext",
7.215 + floatformat_always_valid,
7.216 + NULL
7.217 +};
7.218 +const struct floatformat floatformat_m88110_ext =
7.219 +{
7.220 + floatformat_big, 80, 0, 1, 15, 0x3fff, 0x7fff, 16, 64,
7.221 + floatformat_intbit_yes,
7.222 + "floatformat_m88110_ext",
7.223 + floatformat_always_valid,
7.224 + NULL
7.225 +};
7.226 +const struct floatformat floatformat_m88110_harris_ext =
7.227 +{
7.228 + /* Harris uses raw format 128 bytes long, but the number is just an ieee
7.229 + double, and the last 64 bits are wasted. */
7.230 + floatformat_big,128, 0, 1, 11, 0x3ff, 0x7ff, 12, 52,
7.231 + floatformat_intbit_no,
7.232 + "floatformat_m88110_ext_harris",
7.233 + floatformat_always_valid,
7.234 + NULL
7.235 +};
7.236 +const struct floatformat floatformat_arm_ext_big =
7.237 +{
7.238 + /* Bits 1 to 16 are unused. */
7.239 + floatformat_big, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64,
7.240 + floatformat_intbit_yes,
7.241 + "floatformat_arm_ext_big",
7.242 + floatformat_always_valid,
7.243 + NULL
7.244 +};
7.245 +const struct floatformat floatformat_arm_ext_littlebyte_bigword =
7.246 +{
7.247 + /* Bits 1 to 16 are unused. */
7.248 + floatformat_littlebyte_bigword, 96, 0, 17, 15, 0x3fff, 0x7fff, 32, 64,
7.249 + floatformat_intbit_yes,
7.250 + "floatformat_arm_ext_littlebyte_bigword",
7.251 + floatformat_always_valid,
7.252 + NULL
7.253 +};
7.254 +const struct floatformat floatformat_ia64_spill_big =
7.255 +{
7.256 + floatformat_big, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64,
7.257 + floatformat_intbit_yes,
7.258 + "floatformat_ia64_spill_big",
7.259 + floatformat_always_valid,
7.260 + NULL
7.261 +};
7.262 +const struct floatformat floatformat_ia64_spill_little =
7.263 +{
7.264 + floatformat_little, 128, 0, 1, 17, 65535, 0x1ffff, 18, 64,
7.265 + floatformat_intbit_yes,
7.266 + "floatformat_ia64_spill_little",
7.267 + floatformat_always_valid,
7.268 + NULL
7.269 +};
7.270 +const struct floatformat floatformat_ia64_quad_big =
7.271 +{
7.272 + floatformat_big, 128, 0, 1, 15, 16383, 0x7fff, 16, 112,
7.273 + floatformat_intbit_no,
7.274 + "floatformat_ia64_quad_big",
7.275 + floatformat_always_valid,
7.276 + NULL
7.277 +};
7.278 +const struct floatformat floatformat_ia64_quad_little =
7.279 +{
7.280 + floatformat_little, 128, 0, 1, 15, 16383, 0x7fff, 16, 112,
7.281 + floatformat_intbit_no,
7.282 + "floatformat_ia64_quad_little",
7.283 + floatformat_always_valid,
7.284 + NULL
7.285 +};
7.286 +
7.287 +static int
7.288 +floatformat_ibm_long_double_is_valid (const struct floatformat *fmt,
7.289 + const void *from)
7.290 +{
7.291 + const unsigned char *ufrom = (const unsigned char *) from;
7.292 + const struct floatformat *hfmt = fmt->split_half;
7.293 + long top_exp, bot_exp;
7.294 + int top_nan = 0;
7.295 +
7.296 + top_exp = get_field (ufrom, hfmt->byteorder, hfmt->totalsize,
7.297 + hfmt->exp_start, hfmt->exp_len);
7.298 + bot_exp = get_field (ufrom + 8, hfmt->byteorder, hfmt->totalsize,
7.299 + hfmt->exp_start, hfmt->exp_len);
7.300 +
7.301 + if ((unsigned long) top_exp == hfmt->exp_nan)
7.302 + top_nan = mant_bits_set (hfmt, ufrom);
7.303 +
7.304 + /* A NaN is valid with any low part. */
7.305 + if (top_nan)
7.306 + return 1;
7.307 +
7.308 + /* An infinity, zero or denormal requires low part 0 (positive or
7.309 + negative). */
7.310 + if ((unsigned long) top_exp == hfmt->exp_nan || top_exp == 0)
7.311 + {
7.312 + if (bot_exp != 0)
7.313 + return 0;
7.314 +
7.315 + return !mant_bits_set (hfmt, ufrom + 8);
7.316 + }
7.317 +
7.318 + /* The top part is now a finite normal value. The long double value
7.319 + is the sum of the two parts, and the top part must equal the
7.320 + result of rounding the long double value to nearest double. Thus
7.321 + the bottom part must be <= 0.5ulp of the top part in absolute
7.322 + value, and if it is < 0.5ulp then the long double is definitely
7.323 + valid. */
7.324 + if (bot_exp < top_exp - 53)
7.325 + return 1;
7.326 + if (bot_exp > top_exp - 53 && bot_exp != 0)
7.327 + return 0;
7.328 + if (bot_exp == 0)
7.329 + {
7.330 + /* The bottom part is 0 or denormal. Determine which, and if
7.331 + denormal the first two set bits. */
7.332 + int first_bit = -1, second_bit = -1, cur_bit;
7.333 + for (cur_bit = 0; (unsigned int) cur_bit < hfmt->man_len; cur_bit++)
7.334 + if (get_field (ufrom + 8, hfmt->byteorder, hfmt->totalsize,
7.335 + hfmt->man_start + cur_bit, 1))
7.336 + {
7.337 + if (first_bit == -1)
7.338 + first_bit = cur_bit;
7.339 + else
7.340 + {
7.341 + second_bit = cur_bit;
7.342 + break;
7.343 + }
7.344 + }
7.345 + /* Bottom part 0 is OK. */
7.346 + if (first_bit == -1)
7.347 + return 1;
7.348 + /* The real exponent of the bottom part is -first_bit. */
7.349 + if (-first_bit < top_exp - 53)
7.350 + return 1;
7.351 + if (-first_bit > top_exp - 53)
7.352 + return 0;
7.353 + /* The bottom part is at least 0.5ulp of the top part. For this
7.354 + to be OK, the bottom part must be exactly 0.5ulp (i.e. no
7.355 + more bits set) and the top part must have last bit 0. */
7.356 + if (second_bit != -1)
7.357 + return 0;
7.358 + return !get_field (ufrom, hfmt->byteorder, hfmt->totalsize,
7.359 + hfmt->man_start + hfmt->man_len - 1, 1);
7.360 + }
7.361 + else
7.362 + {
7.363 + /* The bottom part is at least 0.5ulp of the top part. For this
7.364 + to be OK, it must be exactly 0.5ulp (i.e. no explicit bits
7.365 + set) and the top part must have last bit 0. */
7.366 + if (get_field (ufrom, hfmt->byteorder, hfmt->totalsize,
7.367 + hfmt->man_start + hfmt->man_len - 1, 1))
7.368 + return 0;
7.369 + return !mant_bits_set (hfmt, ufrom + 8);
7.370 + }
7.371 +}
7.372 +
7.373 +const struct floatformat floatformat_ibm_long_double =
7.374 +{
7.375 + floatformat_big, 128, 0, 1, 11, 1023, 2047, 12, 52,
7.376 + floatformat_intbit_no,
7.377 + "floatformat_ibm_long_double",
7.378 + floatformat_ibm_long_double_is_valid,
7.379 + &floatformat_ieee_double_big
7.380 +};
7.381 +
7.382 +
7.383 +#ifndef min
7.384 +#define min(a, b) ((a) < (b) ? (a) : (b))
7.385 +#endif
7.386 +
7.387 +/* Return 1 if any bits are explicitly set in the mantissa of UFROM,
7.388 + format FMT, 0 otherwise. */
7.389 +static int
7.390 +mant_bits_set (const struct floatformat *fmt, const unsigned char *ufrom)
7.391 +{
7.392 + unsigned int mant_bits, mant_off;
7.393 + int mant_bits_left;
7.394 +
7.395 + mant_off = fmt->man_start;
7.396 + mant_bits_left = fmt->man_len;
7.397 + while (mant_bits_left > 0)
7.398 + {
7.399 + mant_bits = min (mant_bits_left, 32);
7.400 +
7.401 + if (get_field (ufrom, fmt->byteorder, fmt->totalsize,
7.402 + mant_off, mant_bits) != 0)
7.403 + return 1;
7.404 +
7.405 + mant_off += mant_bits;
7.406 + mant_bits_left -= mant_bits;
7.407 + }
7.408 + return 0;
7.409 +}
7.410 +
7.411 +/* Extract a field which starts at START and is LEN bits long. DATA and
7.412 + TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */
7.413 +static unsigned long
7.414 +get_field (const unsigned char *data, enum floatformat_byteorders order,
7.415 + unsigned int total_len, unsigned int start, unsigned int len)
7.416 +{
7.417 + unsigned long result = 0;
7.418 + unsigned int cur_byte;
7.419 + int lo_bit, hi_bit, cur_bitshift = 0;
7.420 + int nextbyte = (order == floatformat_little) ? 1 : -1;
7.421 +
7.422 + /* Start is in big-endian bit order! Fix that first. */
7.423 + start = total_len - (start + len);
7.424 +
7.425 + /* Start at the least significant part of the field. */
7.426 + if (order == floatformat_little)
7.427 + cur_byte = start / FLOATFORMAT_CHAR_BIT;
7.428 + else
7.429 + cur_byte = (total_len - start - 1) / FLOATFORMAT_CHAR_BIT;
7.430 +
7.431 + lo_bit = start % FLOATFORMAT_CHAR_BIT;
7.432 + hi_bit = min (lo_bit + len, FLOATFORMAT_CHAR_BIT);
7.433 +
7.434 + do
7.435 + {
7.436 + unsigned int shifted = *(data + cur_byte) >> lo_bit;
7.437 + unsigned int bits = hi_bit - lo_bit;
7.438 + unsigned int mask = (1 << bits) - 1;
7.439 + result |= (shifted & mask) << cur_bitshift;
7.440 + len -= bits;
7.441 + cur_bitshift += bits;
7.442 + cur_byte += nextbyte;
7.443 + lo_bit = 0;
7.444 + hi_bit = min (len, FLOATFORMAT_CHAR_BIT);
7.445 + }
7.446 + while (len != 0);
7.447 +
7.448 + return result;
7.449 +}
7.450 +
7.451 +/* Convert from FMT to a double.
7.452 + FROM is the address of the extended float.
7.453 + Store the double in *TO. */
7.454 +
7.455 +void
7.456 +floatformat_to_double (const struct floatformat *fmt,
7.457 + const void *from, double *to)
7.458 +{
7.459 + const unsigned char *ufrom = (const unsigned char *) from;
7.460 + double dto;
7.461 + long exponent;
7.462 + unsigned long mant;
7.463 + unsigned int mant_bits, mant_off;
7.464 + int mant_bits_left;
7.465 + int special_exponent; /* It's a NaN, denorm or zero */
7.466 +
7.467 + /* Split values are not handled specially, since the top half has
7.468 + the correctly rounded double value (in the only supported case of
7.469 + split values). */
7.470 +
7.471 + exponent = get_field (ufrom, fmt->byteorder, fmt->totalsize,
7.472 + fmt->exp_start, fmt->exp_len);
7.473 +
7.474 + /* If the exponent indicates a NaN, we don't have information to
7.475 + decide what to do. So we handle it like IEEE, except that we
7.476 + don't try to preserve the type of NaN. FIXME. */
7.477 + if ((unsigned long) exponent == fmt->exp_nan)
7.478 + {
7.479 + int nan = mant_bits_set (fmt, ufrom);
7.480 +
7.481 + /* On certain systems (such as GNU/Linux), the use of the
7.482 + INFINITY macro below may generate a warning that can not be
7.483 + silenced due to a bug in GCC (PR preprocessor/11931). The
7.484 + preprocessor fails to recognise the __extension__ keyword in
7.485 + conjunction with the GNU/C99 extension for hexadecimal
7.486 + floating point constants and will issue a warning when
7.487 + compiling with -pedantic. */
7.488 + if (nan)
7.489 + dto = NAN;
7.490 + else
7.491 + dto = INFINITY;
7.492 +
7.493 + if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1))
7.494 + dto = -dto;
7.495 +
7.496 + *to = dto;
7.497 +
7.498 + return;
7.499 + }
7.500 +
7.501 + mant_bits_left = fmt->man_len;
7.502 + mant_off = fmt->man_start;
7.503 + dto = 0.0;
7.504 +
7.505 + special_exponent = exponent == 0 || (unsigned long) exponent == fmt->exp_nan;
7.506 +
7.507 + /* Don't bias zero's, denorms or NaNs. */
7.508 + if (!special_exponent)
7.509 + exponent -= fmt->exp_bias;
7.510 +
7.511 + /* Build the result algebraically. Might go infinite, underflow, etc;
7.512 + who cares. */
7.513 +
7.514 + /* If this format uses a hidden bit, explicitly add it in now. Otherwise,
7.515 + increment the exponent by one to account for the integer bit. */
7.516 +
7.517 + if (!special_exponent)
7.518 + {
7.519 + if (fmt->intbit == floatformat_intbit_no)
7.520 + dto = ldexp (1.0, exponent);
7.521 + else
7.522 + exponent++;
7.523 + }
7.524 +
7.525 + while (mant_bits_left > 0)
7.526 + {
7.527 + mant_bits = min (mant_bits_left, 32);
7.528 +
7.529 + mant = get_field (ufrom, fmt->byteorder, fmt->totalsize,
7.530 + mant_off, mant_bits);
7.531 +
7.532 + /* Handle denormalized numbers. FIXME: What should we do for
7.533 + non-IEEE formats? */
7.534 + if (special_exponent && exponent == 0 && mant != 0)
7.535 + dto += ldexp ((double)mant,
7.536 + (- fmt->exp_bias
7.537 + - mant_bits
7.538 + - (mant_off - fmt->man_start)
7.539 + + 1));
7.540 + else
7.541 + dto += ldexp ((double)mant, exponent - mant_bits);
7.542 + if (exponent != 0)
7.543 + exponent -= mant_bits;
7.544 + mant_off += mant_bits;
7.545 + mant_bits_left -= mant_bits;
7.546 + }
7.547 +
7.548 + /* Negate it if negative. */
7.549 + if (get_field (ufrom, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1))
7.550 + dto = -dto;
7.551 + *to = dto;
7.552 +}
7.553 +
7.554 +static void put_field (unsigned char *, enum floatformat_byteorders,
7.555 + unsigned int,
7.556 + unsigned int,
7.557 + unsigned int,
7.558 + unsigned long);
7.559 +
7.560 +/* Set a field which starts at START and is LEN bits long. DATA and
7.561 + TOTAL_LEN are the thing we are extracting it from, in byteorder ORDER. */
7.562 +static void
7.563 +put_field (unsigned char *data, enum floatformat_byteorders order,
7.564 + unsigned int total_len, unsigned int start, unsigned int len,
7.565 + unsigned long stuff_to_put)
7.566 +{
7.567 + unsigned int cur_byte;
7.568 + int lo_bit, hi_bit;
7.569 + int nextbyte = (order == floatformat_little) ? 1 : -1;
7.570 +
7.571 + /* Start is in big-endian bit order! Fix that first. */
7.572 + start = total_len - (start + len);
7.573 +
7.574 + /* Start at the least significant part of the field. */
7.575 + if (order == floatformat_little)
7.576 + cur_byte = start / FLOATFORMAT_CHAR_BIT;
7.577 + else
7.578 + cur_byte = (total_len - start - 1) / FLOATFORMAT_CHAR_BIT;
7.579 +
7.580 + lo_bit = start % FLOATFORMAT_CHAR_BIT;
7.581 + hi_bit = min (lo_bit + len, FLOATFORMAT_CHAR_BIT);
7.582 +
7.583 + do
7.584 + {
7.585 + unsigned char *byte_ptr = data + cur_byte;
7.586 + unsigned int bits = hi_bit - lo_bit;
7.587 + unsigned int mask = ((1 << bits) - 1) << lo_bit;
7.588 + *byte_ptr = (*byte_ptr & ~mask) | ((stuff_to_put << lo_bit) & mask);
7.589 + stuff_to_put >>= bits;
7.590 + len -= bits;
7.591 + cur_byte += nextbyte;
7.592 + lo_bit = 0;
7.593 + hi_bit = min (len, FLOATFORMAT_CHAR_BIT);
7.594 + }
7.595 + while (len != 0);
7.596 +}
7.597 +
7.598 +/* The converse: convert the double *FROM to an extended float
7.599 + and store where TO points. Neither FROM nor TO have any alignment
7.600 + restrictions. */
7.601 +
7.602 +void
7.603 +floatformat_from_double (const struct floatformat *fmt,
7.604 + const double *from, void *to)
7.605 +{
7.606 + double dfrom;
7.607 + int exponent;
7.608 + double mant;
7.609 + unsigned int mant_bits, mant_off;
7.610 + int mant_bits_left;
7.611 + unsigned char *uto = (unsigned char *) to;
7.612 +
7.613 + dfrom = *from;
7.614 + memset (uto, 0, fmt->totalsize / FLOATFORMAT_CHAR_BIT);
7.615 +
7.616 + /* Split values are not handled specially, since a bottom half of
7.617 + zero is correct for any value representable as double (in the
7.618 + only supported case of split values). */
7.619 +
7.620 + /* If negative, set the sign bit. */
7.621 + if (dfrom < 0)
7.622 + {
7.623 + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->sign_start, 1, 1);
7.624 + dfrom = -dfrom;
7.625 + }
7.626 +
7.627 + if (dfrom == 0)
7.628 + {
7.629 + /* 0.0. */
7.630 + return;
7.631 + }
7.632 +
7.633 + if (dfrom != dfrom)
7.634 + {
7.635 + /* NaN. */
7.636 + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
7.637 + fmt->exp_len, fmt->exp_nan);
7.638 + /* Be sure it's not infinity, but NaN value is irrelevant. */
7.639 + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->man_start,
7.640 + 32, 1);
7.641 + return;
7.642 + }
7.643 +
7.644 + if (dfrom + dfrom == dfrom)
7.645 + {
7.646 + /* This can only happen for an infinite value (or zero, which we
7.647 + already handled above). */
7.648 + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
7.649 + fmt->exp_len, fmt->exp_nan);
7.650 + return;
7.651 + }
7.652 +
7.653 + mant = frexp (dfrom, &exponent);
7.654 + if (exponent + fmt->exp_bias - 1 > 0)
7.655 + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
7.656 + fmt->exp_len, exponent + fmt->exp_bias - 1);
7.657 + else
7.658 + {
7.659 + /* Handle a denormalized number. FIXME: What should we do for
7.660 + non-IEEE formats? */
7.661 + put_field (uto, fmt->byteorder, fmt->totalsize, fmt->exp_start,
7.662 + fmt->exp_len, 0);
7.663 + mant = ldexp (mant, exponent + fmt->exp_bias - 1);
7.664 + }
7.665 +
7.666 + mant_bits_left = fmt->man_len;
7.667 + mant_off = fmt->man_start;
7.668 + while (mant_bits_left > 0)
7.669 + {
7.670 + unsigned long mant_long;
7.671 + mant_bits = mant_bits_left < 32 ? mant_bits_left : 32;
7.672 +
7.673 + mant *= 4294967296.0;
7.674 + mant_long = (unsigned long)mant;
7.675 + mant -= mant_long;
7.676 +
7.677 + /* If the integer bit is implicit, and we are not creating a
7.678 + denormalized number, then we need to discard it. */
7.679 + if ((unsigned int) mant_bits_left == fmt->man_len
7.680 + && fmt->intbit == floatformat_intbit_no
7.681 + && exponent + fmt->exp_bias - 1 > 0)
7.682 + {
7.683 + mant_long &= 0x7fffffff;
7.684 + mant_bits -= 1;
7.685 + }
7.686 + else if (mant_bits < 32)
7.687 + {
7.688 + /* The bits we want are in the most significant MANT_BITS bits of
7.689 + mant_long. Move them to the least significant. */
7.690 + mant_long >>= 32 - mant_bits;
7.691 + }
7.692 +
7.693 + put_field (uto, fmt->byteorder, fmt->totalsize,
7.694 + mant_off, mant_bits, mant_long);
7.695 + mant_off += mant_bits;
7.696 + mant_bits_left -= mant_bits;
7.697 + }
7.698 +}
7.699 +
7.700 +/* Return non-zero iff the data at FROM is a valid number in format FMT. */
7.701 +
7.702 +int
7.703 +floatformat_is_valid (const struct floatformat *fmt, const void *from)
7.704 +{
7.705 + return fmt->is_valid (fmt, from);
7.706 +}
7.707 +
7.708 +
7.709 +#ifdef IEEE_DEBUG
7.710 +
7.711 +#include <stdio.h>
7.712 +
7.713 +/* This is to be run on a host which uses IEEE floating point. */
7.714 +
7.715 +void
7.716 +ieee_test (double n)
7.717 +{
7.718 + double result;
7.719 +
7.720 + floatformat_to_double (&floatformat_ieee_double_little, &n, &result);
7.721 + if ((n != result && (! isnan (n) || ! isnan (result)))
7.722 + || (n < 0 && result >= 0)
7.723 + || (n >= 0 && result < 0))
7.724 + printf ("Differ(to): %.20g -> %.20g\n", n, result);
7.725 +
7.726 + floatformat_from_double (&floatformat_ieee_double_little, &n, &result);
7.727 + if ((n != result && (! isnan (n) || ! isnan (result)))
7.728 + || (n < 0 && result >= 0)
7.729 + || (n >= 0 && result < 0))
7.730 + printf ("Differ(from): %.20g -> %.20g\n", n, result);
7.731 +
7.732 +#if 0
7.733 + {
7.734 + char exten[16];
7.735 +
7.736 + floatformat_from_double (&floatformat_m68881_ext, &n, exten);
7.737 + floatformat_to_double (&floatformat_m68881_ext, exten, &result);
7.738 + if (n != result)
7.739 + printf ("Differ(to+from): %.20g -> %.20g\n", n, result);
7.740 + }
7.741 +#endif
7.742 +
7.743 +#if IEEE_DEBUG > 1
7.744 + /* This is to be run on a host which uses 68881 format. */
7.745 + {
7.746 + long double ex = *(long double *)exten;
7.747 + if (ex != n)
7.748 + printf ("Differ(from vs. extended): %.20g\n", n);
7.749 + }
7.750 +#endif
7.751 +}
7.752 +
7.753 +int
7.754 +main (void)
7.755 +{
7.756 + ieee_test (0.0);
7.757 + ieee_test (0.5);
7.758 + ieee_test (256.0);
7.759 + ieee_test (0.12345);
7.760 + ieee_test (234235.78907234);
7.761 + ieee_test (-512.0);
7.762 + ieee_test (-0.004321);
7.763 + ieee_test (1.2E-70);
7.764 + ieee_test (1.2E-316);
7.765 + ieee_test (4.9406564584124654E-324);
7.766 + ieee_test (- 4.9406564584124654E-324);
7.767 + ieee_test (- 0.0);
7.768 + ieee_test (- INFINITY);
7.769 + ieee_test (- NAN);
7.770 + ieee_test (INFINITY);
7.771 + ieee_test (NAN);
7.772 + return 0;
7.773 +}
7.774 +#endif
8.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
8.2 +++ b/src/xlat/disasm/floatformat.h Tue Mar 06 12:42:33 2012 +1000
8.3 @@ -0,0 +1,151 @@
8.4 +/* IEEE floating point support declarations, for GDB, the GNU Debugger.
8.5 + Copyright 1991, 1994, 1995, 1997, 2000, 2003, 2005, 2010
8.6 + Free Software Foundation, Inc.
8.7 +
8.8 +This file is part of GDB.
8.9 +
8.10 +This program is free software; you can redistribute it and/or modify
8.11 +it under the terms of the GNU General Public License as published by
8.12 +the Free Software Foundation; either version 2 of the License, or
8.13 +(at your option) any later version.
8.14 +
8.15 +This program is distributed in the hope that it will be useful,
8.16 +but WITHOUT ANY WARRANTY; without even the implied warranty of
8.17 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8.18 +GNU General Public License for more details.
8.19 +
8.20 +You should have received a copy of the GNU General Public License
8.21 +along with this program; if not, write to the Free Software
8.22 +Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
8.23 +
8.24 +#if !defined (FLOATFORMAT_H)
8.25 +#define FLOATFORMAT_H 1
8.26 +
8.27 +#include "ansidecl.h"
8.28 +
8.29 +/* A floatformat consists of a sign bit, an exponent and a mantissa. Once the
8.30 + bytes are concatenated according to the byteorder flag, then each of those
8.31 + fields is contiguous. We number the bits with 0 being the most significant
8.32 + (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
8.33 + contains with the *_start and *_len fields. */
8.34 +
8.35 +/* What is the order of the bytes? */
8.36 +
8.37 +enum floatformat_byteorders {
8.38 + /* Standard little endian byte order.
8.39 + EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
8.40 + floatformat_little,
8.41 +
8.42 + /* Standard big endian byte order.
8.43 + EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
8.44 + floatformat_big,
8.45 +
8.46 + /* Little endian byte order but big endian word order.
8.47 + EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
8.48 + floatformat_littlebyte_bigword,
8.49 +
8.50 + /* VAX byte order. Little endian byte order with 16-bit words. The
8.51 + following example is an illustration of the byte order only; VAX
8.52 + doesn't have a fully IEEE compliant floating-point format.
8.53 + EX: 1.2345678e10 => 80 c5 00 00 06 42 e0 fe */
8.54 + floatformat_vax
8.55 +};
8.56 +
8.57 +enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
8.58 +
8.59 +struct floatformat
8.60 +{
8.61 + enum floatformat_byteorders byteorder;
8.62 + unsigned int totalsize; /* Total size of number in bits */
8.63 +
8.64 + /* Sign bit is always one bit long. 1 means negative, 0 means positive. */
8.65 + unsigned int sign_start;
8.66 +
8.67 + unsigned int exp_start;
8.68 + unsigned int exp_len;
8.69 + /* Bias added to a "true" exponent to form the biased exponent. It
8.70 + is intentionally signed as, otherwize, -exp_bias can turn into a
8.71 + very large number (e.g., given the exp_bias of 0x3fff and a 64
8.72 + bit long, the equation (long)(1 - exp_bias) evaluates to
8.73 + 4294950914) instead of -16382). */
8.74 + int exp_bias;
8.75 + /* Exponent value which indicates NaN. This is the actual value stored in
8.76 + the float, not adjusted by the exp_bias. This usually consists of all
8.77 + one bits. */
8.78 + unsigned int exp_nan;
8.79 +
8.80 + unsigned int man_start;
8.81 + unsigned int man_len;
8.82 +
8.83 + /* Is the integer bit explicit or implicit? */
8.84 + enum floatformat_intbit intbit;
8.85 +
8.86 + /* Internal name for debugging. */
8.87 + const char *name;
8.88 +
8.89 + /* Validator method. */
8.90 + int (*is_valid) (const struct floatformat *fmt, const void *from);
8.91 +
8.92 + /* Is the format actually the sum of two smaller floating point
8.93 + formats (IBM long double, as described in
8.94 + gcc/config/rs6000/darwin-ldouble-format)? If so, this is the
8.95 + smaller format in question, and the fields sign_start through
8.96 + intbit describe the first half. If not, this is NULL. */
8.97 + const struct floatformat *split_half;
8.98 +};
8.99 +
8.100 +/* floatformats for IEEE single and double, big and little endian. */
8.101 +
8.102 +extern const struct floatformat floatformat_ieee_half_big;
8.103 +extern const struct floatformat floatformat_ieee_half_little;
8.104 +extern const struct floatformat floatformat_ieee_single_big;
8.105 +extern const struct floatformat floatformat_ieee_single_little;
8.106 +extern const struct floatformat floatformat_ieee_double_big;
8.107 +extern const struct floatformat floatformat_ieee_double_little;
8.108 +
8.109 +/* floatformat for ARM IEEE double, little endian bytes and big endian words */
8.110 +
8.111 +extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
8.112 +
8.113 +/* floatformats for VAX. */
8.114 +
8.115 +extern const struct floatformat floatformat_vax_f;
8.116 +extern const struct floatformat floatformat_vax_d;
8.117 +extern const struct floatformat floatformat_vax_g;
8.118 +
8.119 +/* floatformats for various extendeds. */
8.120 +
8.121 +extern const struct floatformat floatformat_i387_ext;
8.122 +extern const struct floatformat floatformat_m68881_ext;
8.123 +extern const struct floatformat floatformat_i960_ext;
8.124 +extern const struct floatformat floatformat_m88110_ext;
8.125 +extern const struct floatformat floatformat_m88110_harris_ext;
8.126 +extern const struct floatformat floatformat_arm_ext_big;
8.127 +extern const struct floatformat floatformat_arm_ext_littlebyte_bigword;
8.128 +/* IA-64 Floating Point register spilt into memory. */
8.129 +extern const struct floatformat floatformat_ia64_spill_big;
8.130 +extern const struct floatformat floatformat_ia64_spill_little;
8.131 +extern const struct floatformat floatformat_ia64_quad_big;
8.132 +extern const struct floatformat floatformat_ia64_quad_little;
8.133 +/* IBM long double (double+double). */
8.134 +extern const struct floatformat floatformat_ibm_long_double;
8.135 +
8.136 +/* Convert from FMT to a double.
8.137 + FROM is the address of the extended float.
8.138 + Store the double in *TO. */
8.139 +
8.140 +extern void
8.141 +floatformat_to_double (const struct floatformat *, const void *, double *);
8.142 +
8.143 +/* The converse: convert the double *FROM to FMT
8.144 + and store where TO points. */
8.145 +
8.146 +extern void
8.147 +floatformat_from_double (const struct floatformat *, const double *, void *);
8.148 +
8.149 +/* Return non-zero iff the data at FROM is a valid number in format FMT. */
8.150 +
8.151 +extern int
8.152 +floatformat_is_valid (const struct floatformat *fmt, const void *from);
8.153 +
8.154 +#endif /* defined (FLOATFORMAT_H) */
9.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
9.2 +++ b/src/xlat/disasm/safe-ctype.c Tue Mar 06 12:42:33 2012 +1000
9.3 @@ -0,0 +1,255 @@
9.4 +/* <ctype.h> replacement macros.
9.5 +
9.6 + Copyright (C) 2000, 2001, 2002, 2003, 2004,
9.7 + 2005 Free Software Foundation, Inc.
9.8 + Contributed by Zack Weinberg <zackw@stanford.edu>.
9.9 +
9.10 +This file is part of the libiberty library.
9.11 +Libiberty is free software; you can redistribute it and/or
9.12 +modify it under the terms of the GNU Library General Public
9.13 +License as published by the Free Software Foundation; either
9.14 +version 2 of the License, or (at your option) any later version.
9.15 +
9.16 +Libiberty is distributed in the hope that it will be useful,
9.17 +but WITHOUT ANY WARRANTY; without even the implied warranty of
9.18 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
9.19 +Library General Public License for more details.
9.20 +
9.21 +You should have received a copy of the GNU Library General Public
9.22 +License along with libiberty; see the file COPYING.LIB. If
9.23 +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
9.24 +Boston, MA 02110-1301, USA. */
9.25 +
9.26 +/*
9.27 +
9.28 +@defvr Extension HOST_CHARSET
9.29 +This macro indicates the basic character set and encoding used by the
9.30 +host: more precisely, the encoding used for character constants in
9.31 +preprocessor @samp{#if} statements (the C "execution character set").
9.32 +It is defined by @file{safe-ctype.h}, and will be an integer constant
9.33 +with one of the following values:
9.34 +
9.35 +@ftable @code
9.36 +@item HOST_CHARSET_UNKNOWN
9.37 +The host character set is unknown - that is, not one of the next two
9.38 +possibilities.
9.39 +
9.40 +@item HOST_CHARSET_ASCII
9.41 +The host character set is ASCII.
9.42 +
9.43 +@item HOST_CHARSET_EBCDIC
9.44 +The host character set is some variant of EBCDIC. (Only one of the
9.45 +nineteen EBCDIC varying characters is tested; exercise caution.)
9.46 +@end ftable
9.47 +@end defvr
9.48 +
9.49 +@deffn Extension ISALPHA (@var{c})
9.50 +@deffnx Extension ISALNUM (@var{c})
9.51 +@deffnx Extension ISBLANK (@var{c})
9.52 +@deffnx Extension ISCNTRL (@var{c})
9.53 +@deffnx Extension ISDIGIT (@var{c})
9.54 +@deffnx Extension ISGRAPH (@var{c})
9.55 +@deffnx Extension ISLOWER (@var{c})
9.56 +@deffnx Extension ISPRINT (@var{c})
9.57 +@deffnx Extension ISPUNCT (@var{c})
9.58 +@deffnx Extension ISSPACE (@var{c})
9.59 +@deffnx Extension ISUPPER (@var{c})
9.60 +@deffnx Extension ISXDIGIT (@var{c})
9.61 +
9.62 +These twelve macros are defined by @file{safe-ctype.h}. Each has the
9.63 +same meaning as the corresponding macro (with name in lowercase)
9.64 +defined by the standard header @file{ctype.h}. For example,
9.65 +@code{ISALPHA} returns true for alphabetic characters and false for
9.66 +others. However, there are two differences between these macros and
9.67 +those provided by @file{ctype.h}:
9.68 +
9.69 +@itemize @bullet
9.70 +@item These macros are guaranteed to have well-defined behavior for all
9.71 +values representable by @code{signed char} and @code{unsigned char}, and
9.72 +for @code{EOF}.
9.73 +
9.74 +@item These macros ignore the current locale; they are true for these
9.75 +fixed sets of characters:
9.76 +@multitable {@code{XDIGIT}} {yada yada yada yada yada yada yada yada}
9.77 +@item @code{ALPHA} @tab @kbd{A-Za-z}
9.78 +@item @code{ALNUM} @tab @kbd{A-Za-z0-9}
9.79 +@item @code{BLANK} @tab @kbd{space tab}
9.80 +@item @code{CNTRL} @tab @code{!PRINT}
9.81 +@item @code{DIGIT} @tab @kbd{0-9}
9.82 +@item @code{GRAPH} @tab @code{ALNUM || PUNCT}
9.83 +@item @code{LOWER} @tab @kbd{a-z}
9.84 +@item @code{PRINT} @tab @code{GRAPH ||} @kbd{space}
9.85 +@item @code{PUNCT} @tab @kbd{`~!@@#$%^&*()_-=+[@{]@}\|;:'",<.>/?}
9.86 +@item @code{SPACE} @tab @kbd{space tab \n \r \f \v}
9.87 +@item @code{UPPER} @tab @kbd{A-Z}
9.88 +@item @code{XDIGIT} @tab @kbd{0-9A-Fa-f}
9.89 +@end multitable
9.90 +
9.91 +Note that, if the host character set is ASCII or a superset thereof,
9.92 +all these macros will return false for all values of @code{char} outside
9.93 +the range of 7-bit ASCII. In particular, both ISPRINT and ISCNTRL return
9.94 +false for characters with numeric values from 128 to 255.
9.95 +@end itemize
9.96 +@end deffn
9.97 +
9.98 +@deffn Extension ISIDNUM (@var{c})
9.99 +@deffnx Extension ISIDST (@var{c})
9.100 +@deffnx Extension IS_VSPACE (@var{c})
9.101 +@deffnx Extension IS_NVSPACE (@var{c})
9.102 +@deffnx Extension IS_SPACE_OR_NUL (@var{c})
9.103 +@deffnx Extension IS_ISOBASIC (@var{c})
9.104 +These six macros are defined by @file{safe-ctype.h} and provide
9.105 +additional character classes which are useful when doing lexical
9.106 +analysis of C or similar languages. They are true for the following
9.107 +sets of characters:
9.108 +
9.109 +@multitable {@code{SPACE_OR_NUL}} {yada yada yada yada yada yada yada yada}
9.110 +@item @code{IDNUM} @tab @kbd{A-Za-z0-9_}
9.111 +@item @code{IDST} @tab @kbd{A-Za-z_}
9.112 +@item @code{VSPACE} @tab @kbd{\r \n}
9.113 +@item @code{NVSPACE} @tab @kbd{space tab \f \v \0}
9.114 +@item @code{SPACE_OR_NUL} @tab @code{VSPACE || NVSPACE}
9.115 +@item @code{ISOBASIC} @tab @code{VSPACE || NVSPACE || PRINT}
9.116 +@end multitable
9.117 +@end deffn
9.118 +
9.119 +*/
9.120 +
9.121 +#include "ansidecl.h"
9.122 +#include "xlat/disasm/safe-ctype.h"
9.123 +#include <stdio.h> /* for EOF */
9.124 +
9.125 +#if EOF != -1
9.126 + #error "<safe-ctype.h> requires EOF == -1"
9.127 +#endif
9.128 +
9.129 +/* Shorthand */
9.130 +#define bl _sch_isblank
9.131 +#define cn _sch_iscntrl
9.132 +#define di _sch_isdigit
9.133 +#define is _sch_isidst
9.134 +#define lo _sch_islower
9.135 +#define nv _sch_isnvsp
9.136 +#define pn _sch_ispunct
9.137 +#define pr _sch_isprint
9.138 +#define sp _sch_isspace
9.139 +#define up _sch_isupper
9.140 +#define vs _sch_isvsp
9.141 +#define xd _sch_isxdigit
9.142 +
9.143 +/* Masks. */
9.144 +#define L (const unsigned short) (lo|is |pr) /* lower case letter */
9.145 +#define XL (const unsigned short) (lo|is|xd|pr) /* lowercase hex digit */
9.146 +#define U (const unsigned short) (up|is |pr) /* upper case letter */
9.147 +#define XU (const unsigned short) (up|is|xd|pr) /* uppercase hex digit */
9.148 +#define D (const unsigned short) (di |xd|pr) /* decimal digit */
9.149 +#define P (const unsigned short) (pn |pr) /* punctuation */
9.150 +#define _ (const unsigned short) (pn|is |pr) /* underscore */
9.151 +
9.152 +#define C (const unsigned short) ( cn) /* control character */
9.153 +#define Z (const unsigned short) (nv |cn) /* NUL */
9.154 +#define M (const unsigned short) (nv|sp |cn) /* cursor movement: \f \v */
9.155 +#define V (const unsigned short) (vs|sp |cn) /* vertical space: \r \n */
9.156 +#define T (const unsigned short) (nv|sp|bl|cn) /* tab */
9.157 +#define S (const unsigned short) (nv|sp|bl|pr) /* space */
9.158 +
9.159 +/* Are we ASCII? */
9.160 +#if HOST_CHARSET == HOST_CHARSET_ASCII
9.161 +
9.162 +const unsigned short _sch_istable[256] =
9.163 +{
9.164 + Z, C, C, C, C, C, C, C, /* NUL SOH STX ETX EOT ENQ ACK BEL */
9.165 + C, T, V, M, M, V, C, C, /* BS HT LF VT FF CR SO SI */
9.166 + C, C, C, C, C, C, C, C, /* DLE DC1 DC2 DC3 DC4 NAK SYN ETB */
9.167 + C, C, C, C, C, C, C, C, /* CAN EM SUB ESC FS GS RS US */
9.168 + S, P, P, P, P, P, P, P, /* SP ! " # $ % & ' */
9.169 + P, P, P, P, P, P, P, P, /* ( ) * + , - . / */
9.170 + D, D, D, D, D, D, D, D, /* 0 1 2 3 4 5 6 7 */
9.171 + D, D, P, P, P, P, P, P, /* 8 9 : ; < = > ? */
9.172 + P, XU, XU, XU, XU, XU, XU, U, /* @ A B C D E F G */
9.173 + U, U, U, U, U, U, U, U, /* H I J K L M N O */
9.174 + U, U, U, U, U, U, U, U, /* P Q R S T U V W */
9.175 + U, U, U, P, P, P, P, _, /* X Y Z [ \ ] ^ _ */
9.176 + P, XL, XL, XL, XL, XL, XL, L, /* ` a b c d e f g */
9.177 + L, L, L, L, L, L, L, L, /* h i j k l m n o */
9.178 + L, L, L, L, L, L, L, L, /* p q r s t u v w */
9.179 + L, L, L, P, P, P, P, C, /* x y z { | } ~ DEL */
9.180 +
9.181 + /* high half of unsigned char is locale-specific, so all tests are
9.182 + false in "C" locale */
9.183 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9.184 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9.185 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9.186 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9.187 +
9.188 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9.189 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9.190 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9.191 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9.192 +};
9.193 +
9.194 +const unsigned char _sch_tolower[256] =
9.195 +{
9.196 + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
9.197 + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
9.198 + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
9.199 + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
9.200 + 64,
9.201 +
9.202 + 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
9.203 + 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z',
9.204 +
9.205 + 91, 92, 93, 94, 95, 96,
9.206 +
9.207 + 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
9.208 + 'n', 'o', 'p', 'q', 'r', 's', 't', 'u', 'v', 'w', 'x', 'y', 'z',
9.209 +
9.210 + 123,124,125,126,127,
9.211 +
9.212 + 128,129,130,131, 132,133,134,135, 136,137,138,139, 140,141,142,143,
9.213 + 144,145,146,147, 148,149,150,151, 152,153,154,155, 156,157,158,159,
9.214 + 160,161,162,163, 164,165,166,167, 168,169,170,171, 172,173,174,175,
9.215 + 176,177,178,179, 180,181,182,183, 184,185,186,187, 188,189,190,191,
9.216 +
9.217 + 192,193,194,195, 196,197,198,199, 200,201,202,203, 204,205,206,207,
9.218 + 208,209,210,211, 212,213,214,215, 216,217,218,219, 220,221,222,223,
9.219 + 224,225,226,227, 228,229,230,231, 232,233,234,235, 236,237,238,239,
9.220 + 240,241,242,243, 244,245,246,247, 248,249,250,251, 252,253,254,255,
9.221 +};
9.222 +
9.223 +const unsigned char _sch_toupper[256] =
9.224 +{
9.225 + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
9.226 + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
9.227 + 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
9.228 + 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
9.229 + 64,
9.230 +
9.231 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
9.232 + 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z',
9.233 +
9.234 + 91, 92, 93, 94, 95, 96,
9.235 +
9.236 + 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
9.237 + 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X', 'Y', 'Z',
9.238 +
9.239 + 123,124,125,126,127,
9.240 +
9.241 + 128,129,130,131, 132,133,134,135, 136,137,138,139, 140,141,142,143,
9.242 + 144,145,146,147, 148,149,150,151, 152,153,154,155, 156,157,158,159,
9.243 + 160,161,162,163, 164,165,166,167, 168,169,170,171, 172,173,174,175,
9.244 + 176,177,178,179, 180,181,182,183, 184,185,186,187, 188,189,190,191,
9.245 +
9.246 + 192,193,194,195, 196,197,198,199, 200,201,202,203, 204,205,206,207,
9.247 + 208,209,210,211, 212,213,214,215, 216,217,218,219, 220,221,222,223,
9.248 + 224,225,226,227, 228,229,230,231, 232,233,234,235, 236,237,238,239,
9.249 + 240,241,242,243, 244,245,246,247, 248,249,250,251, 252,253,254,255,
9.250 +};
9.251 +
9.252 +#else
9.253 +# if HOST_CHARSET == HOST_CHARSET_EBCDIC
9.254 + #error "FIXME: write tables for EBCDIC"
9.255 +# else
9.256 + #error "Unrecognized host character set"
9.257 +# endif
9.258 +#endif
10.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000
10.2 +++ b/src/xlat/disasm/safe-ctype.h Tue Mar 06 12:42:33 2012 +1000
10.3 @@ -0,0 +1,150 @@
10.4 +/* <ctype.h> replacement macros.
10.5 +
10.6 + Copyright (C) 2000, 2001 Free Software Foundation, Inc.
10.7 + Contributed by Zack Weinberg <zackw@stanford.edu>.
10.8 +
10.9 +This file is part of the libiberty library.
10.10 +Libiberty is free software; you can redistribute it and/or
10.11 +modify it under the terms of the GNU Library General Public
10.12 +License as published by the Free Software Foundation; either
10.13 +version 2 of the License, or (at your option) any later version.
10.14 +
10.15 +Libiberty is distributed in the hope that it will be useful,
10.16 +but WITHOUT ANY WARRANTY; without even the implied warranty of
10.17 +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
10.18 +Library General Public License for more details.
10.19 +
10.20 +You should have received a copy of the GNU Library General Public
10.21 +License along with libiberty; see the file COPYING.LIB. If
10.22 +not, write to the Free Software Foundation, Inc., 51 Franklin Street - Fifth Floor,
10.23 +Boston, MA 02110-1301, USA. */
10.24 +
10.25 +/* This is a compatible replacement of the standard C library's <ctype.h>
10.26 + with the following properties:
10.27 +
10.28 + - Implements all isxxx() macros required by C99.
10.29 + - Also implements some character classes useful when
10.30 + parsing C-like languages.
10.31 + - Does not change behavior depending on the current locale.
10.32 + - Behaves properly for all values in the range of a signed or
10.33 + unsigned char.
10.34 +
10.35 + To avoid conflicts, this header defines the isxxx functions in upper
10.36 + case, e.g. ISALPHA not isalpha. */
10.37 +
10.38 +#ifndef SAFE_CTYPE_H
10.39 +#define SAFE_CTYPE_H
10.40 +
10.41 +/* Determine host character set. */
10.42 +#define HOST_CHARSET_UNKNOWN 0
10.43 +#define HOST_CHARSET_ASCII 1
10.44 +#define HOST_CHARSET_EBCDIC 2
10.45 +
10.46 +#if '\n' == 0x0A && ' ' == 0x20 && '0' == 0x30 \
10.47 + && 'A' == 0x41 && 'a' == 0x61 && '!' == 0x21
10.48 +# define HOST_CHARSET HOST_CHARSET_ASCII
10.49 +#else
10.50 +# if '\n' == 0x15 && ' ' == 0x40 && '0' == 0xF0 \
10.51 + && 'A' == 0xC1 && 'a' == 0x81 && '!' == 0x5A
10.52 +# define HOST_CHARSET HOST_CHARSET_EBCDIC
10.53 +# else
10.54 +# define HOST_CHARSET HOST_CHARSET_UNKNOWN
10.55 +# endif
10.56 +#endif
10.57 +
10.58 +/* Categories. */
10.59 +
10.60 +enum {
10.61 + /* In C99 */
10.62 + _sch_isblank = 0x0001, /* space \t */
10.63 + _sch_iscntrl = 0x0002, /* nonprinting characters */
10.64 + _sch_isdigit = 0x0004, /* 0-9 */
10.65 + _sch_islower = 0x0008, /* a-z */
10.66 + _sch_isprint = 0x0010, /* any printing character including ' ' */
10.67 + _sch_ispunct = 0x0020, /* all punctuation */
10.68 + _sch_isspace = 0x0040, /* space \t \n \r \f \v */
10.69 + _sch_isupper = 0x0080, /* A-Z */
10.70 + _sch_isxdigit = 0x0100, /* 0-9A-Fa-f */
10.71 +
10.72 + /* Extra categories useful to cpplib. */
10.73 + _sch_isidst = 0x0200, /* A-Za-z_ */
10.74 + _sch_isvsp = 0x0400, /* \n \r */
10.75 + _sch_isnvsp = 0x0800, /* space \t \f \v \0 */
10.76 +
10.77 + /* Combinations of the above. */
10.78 + _sch_isalpha = _sch_isupper|_sch_islower, /* A-Za-z */
10.79 + _sch_isalnum = _sch_isalpha|_sch_isdigit, /* A-Za-z0-9 */
10.80 + _sch_isidnum = _sch_isidst|_sch_isdigit, /* A-Za-z0-9_ */
10.81 + _sch_isgraph = _sch_isalnum|_sch_ispunct, /* isprint and not space */
10.82 + _sch_iscppsp = _sch_isvsp|_sch_isnvsp, /* isspace + \0 */
10.83 + _sch_isbasic = _sch_isprint|_sch_iscppsp /* basic charset of ISO C
10.84 + (plus ` and @) */
10.85 +};
10.86 +
10.87 +/* Character classification. */
10.88 +extern const unsigned short _sch_istable[256];
10.89 +
10.90 +#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (unsigned short)(bit))
10.91 +
10.92 +#define ISALPHA(c) _sch_test(c, _sch_isalpha)
10.93 +#define ISALNUM(c) _sch_test(c, _sch_isalnum)
10.94 +#define ISBLANK(c) _sch_test(c, _sch_isblank)
10.95 +#define ISCNTRL(c) _sch_test(c, _sch_iscntrl)
10.96 +#define ISDIGIT(c) _sch_test(c, _sch_isdigit)
10.97 +#define ISGRAPH(c) _sch_test(c, _sch_isgraph)
10.98 +#define ISLOWER(c) _sch_test(c, _sch_islower)
10.99 +#define ISPRINT(c) _sch_test(c, _sch_isprint)
10.100 +#define ISPUNCT(c) _sch_test(c, _sch_ispunct)
10.101 +#define ISSPACE(c) _sch_test(c, _sch_isspace)
10.102 +#define ISUPPER(c) _sch_test(c, _sch_isupper)
10.103 +#define ISXDIGIT(c) _sch_test(c, _sch_isxdigit)
10.104 +
10.105 +#define ISIDNUM(c) _sch_test(c, _sch_isidnum)
10.106 +#define ISIDST(c) _sch_test(c, _sch_isidst)
10.107 +#define IS_ISOBASIC(c) _sch_test(c, _sch_isbasic)
10.108 +#define IS_VSPACE(c) _sch_test(c, _sch_isvsp)
10.109 +#define IS_NVSPACE(c) _sch_test(c, _sch_isnvsp)
10.110 +#define IS_SPACE_OR_NUL(c) _sch_test(c, _sch_iscppsp)
10.111 +
10.112 +/* Character transformation. */
10.113 +extern const unsigned char _sch_toupper[256];
10.114 +extern const unsigned char _sch_tolower[256];
10.115 +#define TOUPPER(c) _sch_toupper[(c) & 0xff]
10.116 +#define TOLOWER(c) _sch_tolower[(c) & 0xff]
10.117 +
10.118 +/* Prevent the users of safe-ctype.h from accidently using the routines
10.119 + from ctype.h. Initially, the approach was to produce an error when
10.120 + detecting that ctype.h has been included. But this was causing
10.121 + trouble as ctype.h might get indirectly included as a result of
10.122 + including another system header (for instance gnulib's stdint.h).
10.123 + So we include ctype.h here and then immediately redefine its macros. */
10.124 +
10.125 +#include <ctype.h>
10.126 +#undef isalpha
10.127 +#define isalpha(c) do_not_use_isalpha_with_safe_ctype
10.128 +#undef isalnum
10.129 +#define isalnum(c) do_not_use_isalnum_with_safe_ctype
10.130 +#undef iscntrl
10.131 +#define iscntrl(c) do_not_use_iscntrl_with_safe_ctype
10.132 +#undef isdigit
10.133 +#define isdigit(c) do_not_use_isdigit_with_safe_ctype
10.134 +#undef isgraph
10.135 +#define isgraph(c) do_not_use_isgraph_with_safe_ctype
10.136 +#undef islower
10.137 +#define islower(c) do_not_use_islower_with_safe_ctype
10.138 +#undef isprint
10.139 +#define isprint(c) do_not_use_isprint_with_safe_ctype
10.140 +#undef ispunct
10.141 +#define ispunct(c) do_not_use_ispunct_with_safe_ctype
10.142 +#undef isspace
10.143 +#define isspace(c) do_not_use_isspace_with_safe_ctype
10.144 +#undef isupper
10.145 +#define isupper(c) do_not_use_isupper_with_safe_ctype
10.146 +#undef isxdigit
10.147 +#define isxdigit(c) do_not_use_isxdigit_with_safe_ctype
10.148 +#undef toupper
10.149 +#define toupper(c) do_not_use_toupper_with_safe_ctype
10.150 +#undef tolower
10.151 +#define tolower(c) do_not_use_tolower_with_safe_ctype
10.152 +
10.153 +#endif /* SAFE_CTYPE_H */
.