1.1 --- a/src/asic.c	Thu Dec 06 10:39:01 2007 +0000
     1.2 +++ b/src/asic.c	Thu Dec 06 10:40:27 2007 +0000
     1.3 @@ -374,6 +374,7 @@
     1.4  	    pvr_dma_transfer();
     1.5  	}
     1.6  	break;
     1.7 +	
     1.8      case MAPLE_DMA:
     1.9  	MMIO_WRITE( ASIC, reg, val );
    1.10  	break;
    1.11 @@ -463,6 +464,9 @@
    1.12      case IDEDMASIZ:
    1.13  	MMIO_WRITE( EXTDMA, reg, val & 0x01FFFFFE );
    1.14  	break;
    1.15 +    case IDEDMADIR:
    1.16 +	MMIO_WRITE( EXTDMA, reg, val & 1 );
    1.17 +	break;
    1.18      case IDEDMACTL1:
    1.19      case IDEDMACTL2:
    1.20  	MMIO_WRITE( EXTDMA, reg, val & 0x01 );
    1.21 @@ -478,34 +482,50 @@
    1.22  	    idereg.interface_enabled = FALSE;
    1.23  	}
    1.24  	break;
    1.25 +    case G2DMA0EXT: case G2DMA0SH4: case G2DMA0SIZ:
    1.26 +    case G2DMA1EXT: case G2DMA1SH4: case G2DMA1SIZ:
    1.27 +    case G2DMA2EXT: case G2DMA2SH4: case G2DMA2SIZ:
    1.28 +    case G2DMA3EXT: case G2DMA3SH4: case G2DMA3SIZ:
    1.29 +	MMIO_WRITE( EXTDMA, reg, val & 0x9FFFFFE0 );
    1.30 +	break;
    1.31 +    case G2DMA0MOD: case G2DMA1MOD: case G2DMA2MOD: case G2DMA3MOD:
    1.32 +	MMIO_WRITE( EXTDMA, reg, val & 0x07 );
    1.33 +	break;
    1.34 +    case G2DMA0DIR: case G2DMA1DIR: case G2DMA2DIR: case G2DMA3DIR:
    1.35 +	MMIO_WRITE( EXTDMA, reg, val & 0x01 );
    1.36 +	break;
    1.37      case G2DMA0CTL1:
    1.38      case G2DMA0CTL2:
    1.39 -	MMIO_WRITE( EXTDMA, reg, val );
    1.40 +	MMIO_WRITE( EXTDMA, reg, val & 1);
    1.41  	g2_dma_transfer( 0 );
    1.42  	break;
    1.43      case G2DMA0STOP:
    1.44 +	MMIO_WRITE( EXTDMA, reg, val & 0x37 );
    1.45  	break;
    1.46      case G2DMA1CTL1:
    1.47      case G2DMA1CTL2:
    1.48 -	MMIO_WRITE( EXTDMA, reg, val );
    1.49 +	MMIO_WRITE( EXTDMA, reg, val & 1);
    1.50  	g2_dma_transfer( 1 );
    1.51  	break;
    1.52  
    1.53      case G2DMA1STOP:
    1.54 +	MMIO_WRITE( EXTDMA, reg, val & 0x37 );
    1.55  	break;
    1.56      case G2DMA2CTL1:
    1.57      case G2DMA2CTL2:
    1.58 -	MMIO_WRITE( EXTDMA, reg, val );
    1.59 +	MMIO_WRITE( EXTDMA, reg, val &1 );
    1.60  	g2_dma_transfer( 2 );
    1.61  	break;
    1.62      case G2DMA2STOP:
    1.63 +	MMIO_WRITE( EXTDMA, reg, val & 0x37 );
    1.64  	break;
    1.65      case G2DMA3CTL1:
    1.66      case G2DMA3CTL2:
    1.67 -	MMIO_WRITE( EXTDMA, reg, val );
    1.68 +	MMIO_WRITE( EXTDMA, reg, val &1 );
    1.69  	g2_dma_transfer( 3 );
    1.70  	break;
    1.71      case G2DMA3STOP:
    1.72 +	MMIO_WRITE( EXTDMA, reg, val & 0x37 );
    1.73  	break;
    1.74      case PVRDMA2CTL1:
    1.75      case PVRDMA2CTL2:

     2.1 --- a/test/testregs.c	Thu Dec 06 10:39:01 2007 +0000
     2.2 +++ b/test/testregs.c	Thu Dec 06 10:40:27 2007 +0000
     2.3 @@ -37,26 +37,26 @@
     2.4      { 0xA05F6800, 0xFFFFFFFF, 0x13FFFFE0 },
     2.5      { 0xA05F6800, 0x00000000, 0x10000000 },
     2.6      { 0xA05F6804, 0xFFFFFFFF, 0x00FFFFE0 },
     2.7 -    { 0xA05F6808, 0xFFFFFFFF, 0x00000001 },
     2.8 -    { 0xA05F6808, 0x00000000, 0x00000000 },
     2.9 -    { 0xA05F680C, 0xFFFFFFFF, 0x00000000 },
    2.10 -    { 0xA05F7400, 0xFFFFFFFF, 0x00000000 },
    2.11 +//    { 0xA05F6808, 0xFFFFFFFF, 0x00000001 },
    2.12 +//    { 0xA05F6808, 0x00000000, 0x00000000 },  // DMA start
    2.13 +//    { 0xA05F680C, 0xFFFFFFFF, 0x00000000 },  // Not a register afaik
    2.14 +//    { 0xA05F7400, 0xFFFFFFFF, 0x00000000 },  // Not a register
    2.15      { 0xA05F7404, 0xFFFFFFFF, 0x1FFFFFE0 },
    2.16      { 0xA05F7404, 0x00000000, 0x00000000 },
    2.17      { 0xA05F7408, 0xFFFFFFFF, 0x01FFFFFE },
    2.18      { 0xA05F740C, 0xFFFFFFFF, 0x00000001 },
    2.19 -    { 0xA05F7410, 0xFFFFFFFF, 0x00000000 },
    2.20 +//    { 0xA05F7410, 0xFFFFFFFF, 0x00000000 },  // Not a register
    2.21      { 0xA05F7414, 0xFFFFFFFF, 0x00000001 },
    2.22 -    { 0xA05F7418, 0xFFFFFFFF, 0x00000001 },
    2.23 -    { 0xA05F741C, 0xFFFFFFFF, 0x00000000 },
    2.24 +//    { 0xA05F7418, 0xFFFFFFFF, 0x00000001 },  // DMA start
    2.25 +//    { 0xA05F741C, 0xFFFFFFFF, 0x00000000 },  // Not a register
    2.26      { 0xA05F7800, 0xFFFFFFFF, 0x9FFFFFE0 },
    2.27      { 0xA05F7800, 0x00000000, 0x00000000 },
    2.28      { 0xA05F7804, 0xFFFFFFFF, 0x9FFFFFE0 },
    2.29      { 0xA05F7808, 0xFFFFFFFF, 0x9FFFFFE0 },
    2.30 -    { 0xA05F780C, 0xFFFFFFFF, 0x00000001 },
    2.31 +    { 0xA05F780C, 0xFFFFFFFF, 0x00000001 }, 
    2.32      { 0xA05F7810, 0xFFFFFFFF, 0x00000007 },
    2.33      { 0xA05F7814, 0xFFFFFFFF, 0x00000001 },
    2.34 -    { 0xA05F7818, 0xFFFFFFFF, 0x00000000 },
    2.35 +//    { 0xA05F7818, 0xFFFFFFFF, 0x00000000 },  // DMA start
    2.36      { 0xA05F781C, 0xFFFFFFFF, 0x00000037 },
    2.37      { 0xA05F8000, 0xFFFFFFFF, 0x17FD11DB }, /* PVRID read-only */
    2.38      { 0xA05F8004, 0xFFFFFFFF, 0x00000011 }, /* PVRVER read-only */