Search
lxdream.org :: lxdream :: r40:852ee31ace0d
lxdream 0.9.1
released Jun 29
Download Now
changeset40:852ee31ace0d
parent39:3c35cb97b2ff
child41:e740565eb393
authornkeynes
dateMon Dec 26 10:48:20 2005 +0000 (14 years ago)
Fixup ARM memory to be a little more functional
src/aica/aica.h
src/aica/armmem.c
1.1 --- a/src/aica/aica.h Mon Dec 26 10:47:34 2005 +0000
1.2 +++ b/src/aica/aica.h Mon Dec 26 10:48:20 2005 +0000
1.3 @@ -1,5 +1,5 @@
1.4 /**
1.5 - * $Id: aica.h,v 1.1 2005-12-11 12:00:09 nkeynes Exp $
1.6 + * $Id: aica.h,v 1.2 2005-12-26 10:48:20 nkeynes Exp $
1.7 *
1.8 * MMIO definitions for the AICA sound chip. Note that the regions defined
1.9 * here are relative to the SH4 memory map (0x00700000 based), rather than
1.10 @@ -29,9 +29,10 @@
1.11 MMIO_REGION_END
1.12
1.13 MMIO_REGION_BEGIN( 0x00702000, AICA2, "AICA Sound System Control" )
1.14 -LONG_PORT( 0x040, VOLLEFT, PORT_MRW, 0, "Volume left" )
1.15 -LONG_PORT( 0x044, VOLRIGHT, PORT_MRW, 0, "Volume right" )
1.16 -LONG_PORT( 0x800, AICA_CTRL, PORT_MRW, UNDEFINED, "AICA control" )
1.17 +LONG_PORT( 0x040, CDDA_VOL_L, PORT_MRW, 0, "CDDA Volume left" )
1.18 +LONG_PORT( 0x044, CDDA_VOL_R, PORT_MRW, 0, "CDDA Volume right" )
1.19 +LONG_PORT( 0x800, VOL_MASTER, PORT_MRW, UNDEFINED, "Master volume" )
1.20 +LONG_PORT( 0x890, AICA_TIMER, PORT_MRW, 0, "IRQ Timer (?)" )
1.21 LONG_PORT( 0xC00, AICA_RESET,PORT_MRW, 0, "AICA reset" )
1.22 MMIO_REGION_END
1.23
2.1 --- a/src/aica/armmem.c Mon Dec 26 10:47:34 2005 +0000
2.2 +++ b/src/aica/armmem.c Mon Dec 26 10:48:20 2005 +0000
2.3 @@ -1,5 +1,5 @@
2.4 /**
2.5 - * $Id: armmem.c,v 1.5 2005-12-26 06:38:51 nkeynes Exp $
2.6 + * $Id: armmem.c,v 1.6 2005-12-26 10:48:20 nkeynes Exp $
2.7 *
2.8 * Implements the ARM's memory map.
2.9 *
2.10 @@ -21,10 +21,11 @@
2.11 #include "mem.h"
2.12
2.13 char *arm_mem = NULL;
2.14 +char *arm_mem_scratch = NULL;
2.15
2.16 void arm_mem_init() {
2.17 arm_mem = mem_get_region_by_name( MEM_REGION_AUDIO );
2.18 -
2.19 + arm_mem_scratch = mem_get_region_by_name( MEM_REGION_AUDIO_SCRATCH );
2.20 }
2.21
2.22 int arm_has_page( uint32_t addr ) {
2.23 @@ -40,17 +41,13 @@
2.24 switch( addr & 0xFFFFF000 ) {
2.25 case 0x00800000:
2.26 return mmio_region_AICA0_read(addr);
2.27 - break;
2.28 case 0x00801000:
2.29 return mmio_region_AICA1_read(addr);
2.30 - break;
2.31 case 0x00802000:
2.32 return mmio_region_AICA2_read(addr);
2.33 - break;
2.34 case 0x00803000:
2.35 - break;
2.36 case 0x00804000:
2.37 - break;
2.38 + return *(int32_t *)(arm_mem_scratch + addr - 0x00803000);
2.39 }
2.40 }
2.41 ERROR( "Attempted long read to undefined page: %08X",
2.42 @@ -60,44 +57,69 @@
2.43 }
2.44
2.45 uint32_t arm_read_word( uint32_t addr ) {
2.46 - if( addr < 0x00200000 ) {
2.47 - return *(int16_t *)(arm_mem + addr);
2.48 - /* Main sound ram */
2.49 - } else {
2.50 - /* Undefined memory */
2.51 - ERROR( "Attempted word read to undefined page: %08X",
2.52 - addr );
2.53 - return 0;
2.54 - }
2.55 -
2.56 + return (uint32_t)(uint16_t)arm_read_long( addr );
2.57 }
2.58
2.59 uint32_t arm_read_byte( uint32_t addr ) {
2.60 - if( addr < 0x00200000 ) {
2.61 - return (uint32_t)(*(uint8_t *)(arm_mem + addr));
2.62 - /* Main sound ram */
2.63 - } else {
2.64 - /* Undefined memory */
2.65 - ERROR( "Attempted byte read to undefined page: %08X",
2.66 - addr );
2.67 - return 0;
2.68 - }
2.69 + return (uint32_t)(uint8_t)arm_read_long( addr );
2.70 }
2.71
2.72 void arm_write_long( uint32_t addr, uint32_t value )
2.73 {
2.74 if( addr < 0x00200000 ) {
2.75 + /* Main sound ram */
2.76 *(uint32_t *)(arm_mem + addr) = value;
2.77 } else {
2.78 + switch( addr & 0xFFFFF000 ) {
2.79 + case 0x00800000:
2.80 + mmio_region_AICA0_write(addr, value);
2.81 + break;
2.82 + case 0x00801000:
2.83 + mmio_region_AICA1_write(addr, value);
2.84 + break;
2.85 + case 0x00802000:
2.86 + mmio_region_AICA2_write(addr, value);
2.87 + break;
2.88 + case 0x00803000:
2.89 + case 0x00804000:
2.90 + *(uint32_t *)(arm_mem_scratch + addr - 0x00803000) = value;
2.91 + break;
2.92 + default:
2.93 + ERROR( "Attempted long write to undefined address: %08X",
2.94 + addr );
2.95 + /* Undefined memory */
2.96 + }
2.97 }
2.98 + return 0;
2.99 }
2.100
2.101 void arm_write_byte( uint32_t addr, uint32_t value )
2.102 {
2.103 if( addr < 0x00200000 ) {
2.104 - *(uint8_t *)(arm_mem+addr) = (uint8_t)value;
2.105 + /* Main sound ram */
2.106 + *(uint8_t *)(arm_mem + addr) = (uint8_t)value;
2.107 } else {
2.108 + switch( addr & 0xFFFFF000 ) {
2.109 + case 0x00800000:
2.110 + mmio_region_AICA0_write(addr, value);
2.111 + break;
2.112 + case 0x00801000:
2.113 + mmio_region_AICA1_write(addr, value);
2.114 + break;
2.115 + case 0x00802000:
2.116 + mmio_region_AICA2_write(addr, value);
2.117 + break;
2.118 + case 0x00803000:
2.119 + case 0x00804000:
2.120 + *(uint8_t *)(arm_mem_scratch + addr - 0x00803000) = (uint8_t)value;
2.121 + break;
2.122 + default:
2.123 + ERROR( "Attempted byte write to undefined address: %08X",
2.124 + addr );
2.125 + /* Undefined memory */
2.126 + }
2.127 }
2.128 + return 0;
2.129 }
2.130
2.131 /* User translations - TODO */
.