1.1 --- a/test/Makefile.in	Mon Aug 18 12:18:10 2008 +0000
     1.2 +++ b/test/Makefile.in	Mon Aug 18 12:20:28 2008 +0000
     1.3 @@ -105,7 +105,7 @@
     1.4  	$(SH4CC) $(SH4LDFLAGS) $^  -o $@ $(SH4LIBS)
     1.5  	$(SH4OBJCOPY) testta testta.bin
     1.6  
     1.7 -testaica: lib/crt0.so $(SHARED_OBJECTS) testaica.so dmac.so asic.so lib.so
     1.8 +testaica: lib/crt0.so $(SHARED_OBJECTS) testaica.so dmac.so asic.so lib.so interrupt.so
     1.9  	$(SH4CC) $(SH4LDFLAGS) $^ -o $@ $(SH4LIBS)
    1.10  	$(SH4OBJCOPY) testaica testaica.bin
    1.11  

     2.1 --- a/test/asic.c	Mon Aug 18 12:18:10 2008 +0000
     2.2 +++ b/test/asic.c	Mon Aug 18 12:20:28 2008 +0000
     2.3 @@ -23,6 +23,7 @@
     2.4  #define ASIC_IRQA(n) (ASIC_BASE + 0x910 + (n<<2))
     2.5  #define ASIC_IRQB(n) (ASIC_BASE + 0x920 + (n<<2))
     2.6  #define ASIC_IRQC(n) (ASIC_BASE + 0x930 + (n<<2))
     2.7 +#define G2_FIFO  (ASIC_BASE + 0x88C)
     2.8  #define TIMEOUT 10000000
     2.9  
    2.10  /**
    2.11 @@ -111,3 +112,18 @@
    2.12      }
    2.13      fprintf( f, "\n" );
    2.14  }
    2.15 +
    2.16 +/**
    2.17 + * Wait until the g2 fifo is clear to write more data.
    2.18 + */
    2.19 +int g2_fifo_wait()
    2.20 +{
    2.21 +    int i;
    2.22 +    for (i=0; i<0x1800; i++) {
    2.23 +        if (!(long_read(G2_FIFO) & 0x11)) {
    2.24 +            return 0;
    2.25 +        }
    2.26 +
    2.27 +    }
    2.28 +    return -1;
    2.29 +}
    2.30 \ No newline at end of file

     3.1 --- a/test/asic.h	Mon Aug 18 12:18:10 2008 +0000
     3.2 +++ b/test/asic.h	Mon Aug 18 12:20:28 2008 +0000
     3.3 @@ -60,3 +60,8 @@
     3.4  void asic_dump( FILE *f );
     3.5  
     3.6  void asic_mask_all();
     3.7 +
     3.8 +/**
     3.9 + * Wait until the G2 FIFO buffer is clear to write
    3.10 + */
    3.11 +int g2_fifo_wait();

     4.1 --- a/test/dmac.c	Mon Aug 18 12:18:10 2008 +0000
     4.2 +++ b/test/dmac.c	Mon Aug 18 12:20:28 2008 +0000
     4.3 @@ -16,6 +16,7 @@
     4.4   * GNU General Public License for more details.
     4.5   */
     4.6  
     4.7 +#include <assert.h>
     4.8  #include "dma.h"
     4.9  #include "asic.h"
    4.10  
    4.11 @@ -40,7 +41,8 @@
    4.12  #define SORT_DMA_CTL   (ASIC_BASE+0x820)
    4.13  #define SORT_DMA_COUNT (ASIC_BASE+0x860)
    4.14  
    4.15 -#define G2BASERAM 0x00800000
    4.16 +#define AICA_RAM_BASE 0xA0800000
    4.17 +#define AICA_RAM_SIZE 0x00200000
    4.18  
    4.19  #define G2DMABASE 0xA05F7800
    4.20  #define G2DMATIMEOUT (G2DMABASE+0x90)
    4.21 @@ -203,3 +205,23 @@
    4.22  {
    4.23      return aica_dma_transfer( aica_addr, data, size, 0 );
    4.24  }
    4.25 +
    4.26 +int memcpy_to_aica( uint32_t aica_addr, void *data, size_t size )
    4.27 +{
    4.28 +    assert( (aica_addr & 0x03) == 0 );
    4.29 +    uint32_t *src = (uint32_t *)data;
    4.30 +    uint32_t *dest = (uint32_t *)aica_addr;
    4.31 +    while( size > 0 ) {
    4.32 +        int i;
    4.33 +        if( g2_fifo_wait() != 0 ) {
    4.34 +            return -1;
    4.35 +        }
    4.36 +        irq_disable();
    4.37 +        for( i=0; i<8 && size > 0; i++ ) {
    4.38 +            *dest++ = *src++;
    4.39 +            size -= 4;
    4.40 +        }
    4.41 +        irq_enable();
    4.42 +    }
    4.43 +    return 0;
    4.44 +}

     5.1 --- a/test/interrupt.s	Mon Aug 18 12:18:10 2008 +0000
     5.2 +++ b/test/interrupt.s	Mon Aug 18 12:20:28 2008 +0000
     5.3 @@ -265,3 +265,35 @@
     5.4  handler_stack:
     5.5  	.skip 0x200
     5.6  handler_stack_end:	
     5.7 +
     5.8 +
     5.9 +.globl  _irq_disable
    5.10 +_irq_disable:
    5.11 +        mov.l   _irqd_and,r1
    5.12 +        mov.l   _irqd_or,r2
    5.13 +        stc     sr,r0
    5.14 +        and     r0,r1
    5.15 +        or      r2,r1
    5.16 +        ldc     r1,sr
    5.17 +        rts
    5.18 +        nop
    5.19 +        
    5.20 +        .align 2
    5.21 +_irqd_and:
    5.22 +        .long   0xefffff0f
    5.23 +_irqd_or:
    5.24 +        .long   0x000000f0
    5.25 +
    5.26 +
    5.27 +.globl  _irq_enable
    5.28 +_irq_enable:
    5.29 +        mov.l   _irqe_and,r1
    5.30 +        stc     sr,r0
    5.31 +        and     r0,r1
    5.32 +        ldc     r1,sr
    5.33 +        rts
    5.34 +        nop
    5.35 +        
    5.36 +        .align 2
    5.37 +_irqe_and:
    5.38 +        .long   0xefffff0f

     6.1 --- a/test/lib.h	Mon Aug 18 12:18:10 2008 +0000
     6.2 +++ b/test/lib.h	Mon Aug 18 12:20:28 2008 +0000
     6.3 @@ -38,7 +38,6 @@
     6.4  void *align32(char *buf );
     6.5  void write_asic_status(void);
     6.6  void reset_asic_status(void);
     6.7 -void g2_fifo_wait( void );
     6.8  
     6.9  #define aica_enable() long_write( AICA_RESET, (long_read(AICA_RESET) & 0xFFFFFFFE) )
    6.10  #define aica_disable()  long_write( AICA_RESET, (long_read(AICA_RESET) | 1) )